Control method of memory system, memory system and electronic equipment

Abstract

The invention provides a control method of a memory system, the memory system and electronic equipment, when hard decoding of hard bit data read from a memory fails, the control method can read soft bit data in the memory, and soft decoding is carried out on the obtained soft bit data through an LLR value in an initial lookup table. And if the soft decoding fails, shifting the LLR value in the initial lookup table, and performing soft decoding according to the LLR value after each shifting, thereby improving the soft decoding efficiency.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a control method of a memory system, a memory system and an electronic device. Background Art

[0002] Memory and its system are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics. Among them, in order to improve the error correction capability of the memory, a combination of hard decoding and soft decoding is usually used to decode the data read from the memory. However, the current soft decoding method generally has the problem of low decoding efficiency. Summary of the invention

[0003] The embodiments of the present application provide a control method of a memory system, a memory system and an electronic device, aiming to solve the problem of low decoding efficiency caused by too high delay in the soft decoding process of the current memory.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, a control method for a memory system is provided. When the method is executed, first soft bit data corresponding to hard bit data read from the memory and a first lookup table are obtained. The first lookup table includes a first log-likelihood ratio value determined based on a first reference read voltage of the memory. Then, a first soft decoding operation is performed according to the first log-likelihood ratio value and the first soft bit data. Finally, when it is determined that the first soft decoding operation fails to decode, the first log-likelihood ratio value is shifted at least once, and a second soft decoding operation is performed according to the log-likelihood ratio value after each shift and the first soft bit data. In the above manner, when the first soft decoding operation fails, the log-likelihood ratio value can be directly shifted and then soft decoding is performed, instead of changing the lookup table or offsetting the reference read voltage during reading and then performing multiple soft decodings, thereby reducing the number of iterations of soft decoding, reducing the delay of soft decoding, and improving the efficiency of soft decoding.

[0006] In a possible implementation, when performing at least one shift on the first log-likelihood ratio value and performing the second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, the first log-likelihood ratio value may be positively shifted at least once, and soft decoding may be performed according to the log-likelihood ratio value after each shift and the first soft bit data. In the above manner, multiple positive shifts may be performed first on the basis of the first log-likelihood ratio value, thereby improving the efficiency of successful decoding.

[0007] In a possible implementation, when the first log-likelihood ratio value is positively shifted at least once and soft decoding fails according to the log-likelihood ratio value after each shift and the first soft bit data, the first log-likelihood ratio value may be negatively shifted at least once and soft decoding may be performed according to the log-likelihood ratio value after each shift and the first soft bit data. In the above manner, when the first log-likelihood ratio value cannot be successfully decoded by positive shift, the negative shift method is selected to further improve the efficiency of successful decoding.

[0008] In a possible implementation, when performing at least one shift on the first log-likelihood ratio value and performing the second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, the first log-likelihood ratio value may be negatively shifted at least once, and soft decoding may be performed according to the log-likelihood ratio value after each shift and the first soft bit data. In the above manner, multiple negative shifts may be performed on the basis of the first log-likelihood ratio value, thereby improving the efficiency of successful decoding.

[0009] In a possible implementation, the first log-likelihood ratio value is negatively shifted at least once, and when soft decoding fails according to the log-likelihood ratio value after each shift and the first soft bit data, the first log-likelihood ratio value may be positively shifted at least once, and soft decoding may be performed according to the log-likelihood ratio value after each shift and the first soft bit data. In the above manner, when the first log-likelihood ratio value cannot be successfully decoded by negative shift, the positive shift method is selected to further improve the efficiency of successful decoding.

[0010] In a possible implementation, when performing at least one shift on the first log-likelihood ratio value and performing the second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, the first log-likelihood ratio value may also be cross-shifted, and soft decoding may be performed according to the log-likelihood ratio value after each shift and the first soft bit data. By cross-shifting, the delay of soft decoding may be further reduced and the efficiency of successful soft decoding may be improved.

[0011] In a possible implementation manner, when the first log-likelihood ratio value is shifted at least once, the value of each shift is the same.

[0012] In a possible implementation manner, when the first log-likelihood ratio value is shifted at least once, the value of each shift is different.

[0013] In a possible implementation, after the second soft decoding operation is stopped when the number of shifts of the first log-likelihood ratio value reaches a preset value, the method further includes: acquiring a second lookup table; the second lookup table includes a second log-likelihood ratio value determined based on a second reference read voltage of the memory. Then, the first reference read voltage is shifted to the second reference read voltage. Finally, the second soft bit data of the memory is read according to the second reference read voltage, and a third soft decoding operation is performed according to the second soft bit data and the second log-likelihood ratio value.

[0014] In the above manner, when soft decoding fails using the first lookup table, the second lookup table may be replaced, and then soft decoding is performed by offsetting the reference read voltage, thereby improving the efficiency of successful decoding.

[0015] In a possible implementation, after the second soft decoding operation is stopped when the number of shifts of the first log-likelihood ratio value reaches a preset value, the method further includes: acquiring a third lookup table, the third lookup table including a third log-likelihood ratio value determined based on a third reference read voltage, and performing a fourth soft decoding operation according to the third log-likelihood ratio value and the first soft bit data.

[0016] By using the above method, when soft decoding fails using the first lookup table, the third lookup table can be replaced and soft decoding can be performed with reference to the first lookup table, thereby improving the efficiency of successful decoding.

[0017] In a possible implementation, the step of acquiring the first soft bit data and the first lookup table corresponding to the hard bit data read from the memory is performed after a hard decoding operation of the hard bit data fails.

[0018] In a second aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer program instructions. When the computer program instructions are executed by a processor, the method in any possible implementation manner of the first aspect is implemented.

[0019] In a third aspect, a memory system is provided. The memory system includes one or more memories; a memory controller coupled to the memory and configured to control the memory; and the memory controller includes a decoding circuit. The decoding circuit is configured to implement the method in any possible implementation of the first aspect.

[0020] In a fourth aspect, a memory controller is provided, the memory controller comprising a bus and a decoding circuit coupled to the bus, wherein the decoding circuit is configured to implement the method in any possible implementation manner of the first aspect.

[0021] According to a fifth aspect, an electronic device is provided, which includes an interface circuit and the above-mentioned memory system coupled to the interface circuit.

[0022] It can be understood that the beneficial effects that can be achieved by the above-mentioned second to fifth aspects of the present application can refer to the beneficial effects of the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0024] Figure 1 The following is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of the structure of a memory card provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the structure of a solid state hard disk provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the structure of a memory controller provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of a method for obtaining soft bit data and hard bit data provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of the confidence interval distribution when reading soft bit data provided by an embodiment of the present application;

[0031] Figure 8 A LLR value change trend diagram of a confidence interval provided in an embodiment of the present application;

[0032] Fig. 9 A schematic flow chart of a control method for a memory system provided in an embodiment of the present application;

[0033] Fig.10 A schematic diagram of a LLR value shift process provided in an embodiment of the present application;

[0034] Fig.11 A schematic diagram of another LLR value shifting process provided in an embodiment of the present application;

[0035] Fig.12 A schematic diagram of a process flow after a second soft decoding fails provided in an embodiment of the present application;

[0036] Fig.13 A schematic diagram of another process flow after the second soft decoding fails provided in an embodiment of the present application;

[0037] Fig.14 A schematic diagram of the structure of a soft decoding circuit provided in an embodiment of the present application;

[0038] Fig.15 A schematic diagram of the structure of a decoding circuit provided in an embodiment of the present application;

[0039] Fig.16 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the expressions "coupled", "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the terms "coupled" or "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the terms "coupled" and "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0044] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0045] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0046] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0047] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more conditions or values ​​may, in practice, be based on additional conditions or beyond values.

[0048] like Figure 1 As shown, a memory system 100 is provided in many electronic devices. The memory system 100 has one or more memories 120 and a memory controller 110 .

[0049] In some embodiments, the memory controller 110 is designed to operate in a low duty cycle environment, such as a secure digital memory card (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0050] In some embodiments, the memory controller 110 is designed to operate in a high duty cycle environment solid state disk (SSD) or embedded multi-media card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0051] The memory controller 110 may be configured to control operations of the memory 120, such as read, erase, and program operations. The memory controller 110 may also be configured to manage various functions regarding data stored or to be stored in the memory 120, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 110 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 120.

[0052] The memory controller 110 may also perform any other suitable functions, for example, formatting the memory 120. The memory controller 110 may communicate with an external device (e.g., the host 110) according to a specific communication protocol. For example, the memory controller 110 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, and the like.

[0053] The memory controller 110 and the one or more memories 120 may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package).

[0054] In such Figure 2 In one example shown in FIG. 1 , the memory controller 110 and the single memory 120 may be integrated into a memory card 200. The memory card 200 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), an SD card (SD, miniSD, microSD, SDHC), a universal flash storage (UFS), etc. The memory card 200 may also include a computer that connects the memory card 200 to a host (e.g., Figure 1 A memory card connector 210 coupled to a host 110 in the memory card module.

[0055] In such Figure 3 In another example shown in FIG. 1 , the memory controller 110 and the plurality of memories 120 may be integrated into a solid state drive (SSD) 300. The solid state drive 300 may also include a computer that connects the solid state drive 300 to a host (eg, Figure 1 In some embodiments, the storage capacity and / or operating speed of the solid-state drive 300 is greater than the storage capacity and / or operating speed of the memory card 200.

[0056] like Figure 4 As shown, the memory 120 includes a memory array 128 and peripheral circuits. The peripheral circuits include a connection terminal 121, a control logic circuit 122, a register 123, a voltage generator 124, a row driver 125, a column driver 126, and a page buffer 127. Among them, the connection terminal 121 is mainly used to receive a read instruction and a programming instruction sent by the memory controller 300 and to send the read data to the memory controller 300. The control logic circuit 122 is mainly used to control the row driver 125, the column driver 126, and the page buffer 127 to perform operations such as reading, programming, erasing, and verification according to the instructions sent by the memory controller 110. The register 123 can store the control instructions sent by the memory controller 110.

[0057] In one example, if Figure 5As shown, the memory controller 110 includes a bus 113; a host interface 115, a memory interface 116, a processor 111, an internal memory 112, and a check and error correction circuit 114 (also called an ECC circuit) coupled to the bus 113. Among them, the host interface 115 is used to connect to the host; the memory interface 116 is used to connect to one or more memories. The processor 111 can receive a request instruction sent by the host through the bus 113, and send a control instruction to the memory connected to the memory interface 116 according to the request instruction, thereby controlling the memory to perform a read / program operation. The internal memory 112 can include a read only memory (ROM) and a random access memory (RAM). The processor 111 can select a microcontroller unit (MCU). Among them, the ROM can store fixed instructions that the processor needs to execute, such as the initial log likelihood ratio (LLR) lookup table address and the fixed program address that needs to be run after the MCU is started. The RAM can store data for the MCU to interact with the host and the memory. The check and error correction circuit 114 includes a soft decoding circuit 1142 and a hard decoding circuit 1141. The hard decoding circuit 1141 is used to perform hard decoding on the hard bit data read from the memory. The soft decoding circuit 1142 is used to perform soft decoding on the soft bit data read from the memory. When performing hard decoding, a low density parity check (LDPC) code or the like can be used to perform it. For example, hard decoding may include a parity check operation for generating a check signature (syndrome) and a bit flipping algorithm, a min-sum algorithm and / or a sum-product algorithm for determining an error bit. When performing soft decoding, a low density parity check (LDPC) code or the like can also be used to perform it. For example, soft decoding may further include operations on information such as log likelihood ratio (LLR) values. In addition, soft decoding may include decoding operations that are the same as or different from at least a portion of hard decoding.

[0058] Next, refer to Figure 6 , specific examples of hard bit data (hard bit, HB) and soft bit data (soft bit, SB) are described. Figure 6 3 is a schematic diagram showing the relationship between the distribution of the threshold voltages of the memory cells in the “B” programming state and the “A” programming state and the hard bit data and the soft bit data.

[0059] like Figure 6 As shown in FIG. 1 , due to the influence of read disturbance or data retention, the width of the threshold voltage distribution of each programming state is sometimes expanded, and the lower ends of adjacent threshold voltage distributions overlap each other ( Figure 6 In this case, if a read operation is performed, the memory cell corresponding to the overlapped area at the lower end is more likely to become a failed bit. More specifically, for example, when the read voltage V A When performing a read operation corresponding to the "B" programming state, the read voltage V A A memory cell in the "A" programming state above the threshold voltage has a read voltage less than V A The memory cell in the "B" programming state with a threshold voltage of 0.00177 becomes a failure bit. If the number of failure bits generated exceeds the number of bits that the ECC circuit can correct errors, it is difficult to read the data correctly.

[0060] Therefore, in this embodiment, in the read operation of one programming state, two read voltages are set across the region where the lower ends of the threshold voltage distribution overlap. More specifically, for the "B" programming state, two read voltages V AL and V AH . Read the voltage V AL is less than the read voltage V A Read the voltage V AH is higher than the read voltage V A The area where the programming state "A" overlaps with the programming state "B" is located at the read voltage V AL With the read voltage V AH In addition, the voltage V AL With the read voltage V A The voltage difference can be read as V A With the read voltage V AH The voltage difference can be the same or different.

[0061] For example, when using the read voltage V AL In the read operation, the threshold voltage is less than the read voltage V AL The data of the memory cell is "1". The threshold voltage is the read voltage V AL The data of the above memory cells is "0".

[0062] In addition, when using the read voltage V AH In the read operation, the threshold voltage is less than the read voltage V AH The data of the memory cell is "1". The threshold voltage is the read voltage V AH The data of the above memory cells is "0".

[0063] In this embodiment, of the two read voltages corresponding to one programming state, data read out by a lower read voltage is defined as hard bit data.

[0064] The soft bit data is calculated by a logical operation (for example, an XOR operation) of two read data. Figure 6 In the example, the threshold voltage is less than the read voltage V AL The soft bit data of the storage cell is "0". The threshold voltage is the read voltage V AL Above and less than the read voltage V AH The soft bit data of the storage cell is "1". The threshold voltage is the read voltage V AH The soft bit data of the above storage unit is "0". In addition, the operation of the soft bit data is not limited to the XOR operation. The operation of the soft bit data can be set based on the definition of the soft bit data. For example, when the threshold voltage is set to the read voltage V AL Above and less than the read voltage V AH When the soft bit data of the storage cell is defined as "0", the soft bit data can also be calculated using an XNOR (exclusive NOT OR) operation.

[0065] Therefore, the soft bit data indicates whether the threshold voltage is located near the boundary of two adjacent threshold voltage distributions. By referring to the hard bit data and the soft bit data, information on whether the threshold voltage is located at the lower end of the threshold voltage distribution of the target programming state can be obtained.

[0066] Furthermore, during the soft decoding process, if the soft decoding fails, the common solutions mainly include the following three types:

[0067] 1) Perform more read offsets based on the reference read voltage to obtain more soft bit data for decoding.

[0068] 2) Shift the reference read voltage, and then obtain soft bit data based on the shifted reference level for soft decoding.

[0069] 3) Set up lookup tables for various scenarios. When soft decoding fails using a certain lookup table, use other LLR lookup tables for soft decoding.

[0070] However, adjusting the soft decoding strategy in the above manner will add a lot of decoding processes, thereby increasing the delay of soft decoding and reducing the efficiency of soft decoding.

[0071] like Figure 7As shown, when reading soft bit data from the overlapping area of ​​two adjacent programming states in the storage cell, the reference read voltage RV can be subjected to multiple positive and negative voltage offsets. To obtain multiple soft bit data. Exemplarily, taking 8 offset voltages such as ±0.07V, ±0.14V, ±0.21V and ±0.28V as an example, when reading soft bit data through 8 offset voltages, the overlapping area can be divided into 8 confidence intervals (Z1~Z8). Among them, when reading soft bit data with 4 offset voltages such as ±0.07V and ±0.14V, the changes in the LLR values ​​of the above 8 confidence intervals are shown in Table 1. Among them, when the LLR value is positive, the larger the value, the greater the probability that the data is 0. When the LLR value is negative, the smaller the value, the greater the probability that the data is 1.

[0072] Table 1

[0073] RV-0.14 63 63 57 39 23 10 -8 -59 RV-0.07 63 57 39 23 10 -8 -26 -63 RV 63 39 23 10 -8 -26 -49 -63 RV+0.07 63 23 10 -8 -26 -49 -53 -63 RV+0.14 54 10 -8 -26 -49 -53 -63 -63

[0074] It can be seen from Table 1 that when reading soft bit data with four offset voltages such as ±0.07V and ±0.14V, the LLR values ​​of the confidence intervals Z2-Z7 will change. In order to more intuitively see the change trend of the LLR value, a change trend graph of the LLR value of each confidence interval can be drawn based on Table 1. Among them, the change trend graph of the LLR value is as follows: Figure 8 As shown. Figure 8 It can be seen that there is a very good linear relationship between the LLR values ​​in the confidence interval Z2-Z7 and the positive and negative offset voltages when reading the soft bit data. Therefore, it is feasible to perform soft decoding by shifting the LLR values ​​according to this linear relationship.

[0075] Based on this, in order to solve the above problems, Fig. 9 As shown, an embodiment of the present application provides a control method for a memory system, which can be executed by a memory controller, and its specific implementation process is as follows.

[0076] S901. Read hard bit data from the memory and perform hard decoding operations.

[0077] Exemplarily, the memory controller may send a control instruction to the control logic circuit in the memory to instruct the control logic circuit to read the hard bit data of the corresponding programming state from the storage unit according to the first reference read voltage. The first reference read voltage may be the optimal read voltage of the memory (e.g., nand memory) in certain scenarios. The optimal read voltage may be obtained by testing the memory device under a set scenario. The set scenario may be set according to the actual use environment of the memory. Exemplarily, the set scenario may include the environmental factors of the memory and the parameters of the memory itself, such as the ambient temperature, ambient humidity, the power supply voltage of the memory, and the number of erase and write times. In the above implementation process, if the hard decoding operation is successfully performed to obtain the decoded data, the decoded data is output and the decoding is stopped, otherwise, S902 is continued.

[0078] S902. Repeatedly read the hard bit data for multiple times and perform a hard decoding operation on the hard bit data read each time.

[0079] In the process of executing the above method, if the first hard decoding fails, the memory controller can continue to send control instructions to the control logic circuit in the memory to repeatedly read the hard bit data of the corresponding programming state in the storage unit. When reading the hard bit data, the control logic circuit can use the reference read voltage in the same scenario for repeated reading, or can use the reference read voltage in different scenarios for repeated reading, and the embodiment of the present application does not impose specific restrictions on this.

[0080] In the above implementation process, if the hard decoding operation successfully obtains the decoded data, the decoded data is output and the decoding is stopped; otherwise, S903 is continued to be executed.

[0081] S903. Obtain first soft bit data and a first lookup table corresponding to the hard bit data read from the memory.

[0082] The first lookup table includes a first log-likelihood ratio value determined based on a first reference read voltage of the memory. The operating user can use the optimal read voltage in certain scenarios as the first reference read voltage, and then obtain the first log-likelihood ratio value after testing and calculation. The first soft bit data can be read by performing one or more positive and negative voltage offsets on the first reference read voltage. The first reference read voltage and each offset voltage value can be set according to actual scenario requirements, and the embodiments of the present application do not impose specific restrictions on this.

[0083] Exemplarily, after the hard decoding operation fails, the memory controller may send a control instruction to the logic control circuit in the memory to instruct the control logic circuit to read the first soft bit data in the storage unit.

[0084] In the above implementation process, the first lookup table can be stored in the internal memory of the memory controller, or in the memory coupled to the memory controller. When the first lookup table is stored in the internal memory of the memory controller, a ROM can be used for storage. After the memory controller fails to perform a hard decoding operation, the first lookup table can be read from the ROM. When the first lookup table is stored in the memory coupled to the memory controller, the address information of the first lookup table can be stored in the ROM so that the first lookup table can be read from the corresponding address of the memory when performing a soft decoding operation.

[0085] S904. Perform a first soft decoding operation according to the first log-likelihood ratio value and the first soft bit data.

[0086] Exemplarily, after the memory controller acquires the first soft bit data, the first soft bit data can be soft-decoded according to the first log-likelihood ratio value through a soft decoding circuit (which may include an LDPC decoder). If the decoding is successful, the decoded data is output. Otherwise, S905 is continued to be executed. Among them, the first soft bit data may include soft bit data read after the first reference read voltage is positively and negatively offset once or more. Correspondingly, the first soft decoding operation includes at least one soft decoding, that is, each soft bit data corresponds to one soft decoding. In addition, in the above implementation process, the process of soft decoding according to the log-likelihood ratio value is a process well known to those skilled in the art, and the embodiments of the present application are not described in detail here.

[0087] S905. When it is determined that the first soft decoding operation fails, perform at least one shift on the first log-likelihood ratio value, and perform a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data.

[0088] In a possible implementation, if the first soft decoding operation fails, the soft decoding circuit in the memory controller may perform at least one shift on the first log-likelihood ratio value, and perform a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data. The second soft decoding operation includes at least one soft decoding, that is, soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data each time the first log-likelihood ratio value is shifted.

[0089] Exemplarily, the first log-likelihood ratio value may be positively shifted at least once, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data. If decoding still fails, the first log-likelihood ratio value may be negatively shifted at least once, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data. The specific execution process is as follows: Fig.10 shown.

[0090] S1001. Determine that the first soft decoding operation fails.

[0091] If the soft decoding cannot obtain correct data by performing soft decoding according to the first log-likelihood ratio value and the first soft bit data, it means that the first soft decoding operation fails.

[0092] S1002. Perform a positive shift on the first log-likelihood ratio value.

[0093] In one example, as shown in Table 2, assuming that the overlapping area of ​​two adjacent programming states in a certain storage unit is divided into multiple confidence intervals (Z1, Z2, Z3, ...), and the initial LLR values ​​corresponding to each confidence interval are (a, b, c, ...), then when the first log-likelihood ratio value is positively shifted, the value of each positive shift can be the same value (that is, the value of each shift is a fixed value). In Table 2, m represents the value of the shift. This value can be set according to actual needs, and the embodiment of the present application does not impose specific restrictions on this.

[0094] Table 2

[0095] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift a+m b+m c+m ... Second shift a+2m b+2m c+2m ... ... ... ... ... ...

[0096] In another example, as shown in Table 3, when the first log-likelihood ratio value is positively shifted, the value of each positive shift can be a different value (that is, the value of each shift is a non-fixed value). In Table 3, m and n represent two values ​​of different sizes. These two values ​​can be set according to actual needs, and the embodiments of the present application do not impose specific restrictions on this.

[0097] Table 3

[0098] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift a+m b+m c+m ... Second shift a+m+n b+m+n c+m+n ... ... ... ... ... ...

[0099] S1003. Perform soft decoding according to the shifted log-likelihood ratio value and the first soft bit data.

[0100] The log-likelihood ratio value can be soft-decoded with the first soft bit data once each time it is shifted. If the decoding is successful, the decoded data is output. Otherwise, S1004 is continued.

[0101] S1004. Determine whether the number of positive shifts of the first log-likelihood ratio value reaches a set threshold.

[0102] If the number of positive shifts of the first log-likelihood ratio value reaches the set threshold, S1005 to S1007 are executed. If the number of positive shifts of the first log-likelihood ratio value does not reach the set threshold, S1002 to S1003 are continued.

[0103] S1005. Negatively shift the first log-likelihood ratio value.

[0104] In one example, as shown in Table 4, when the first log-likelihood ratio value is positively shifted, the value of each positive shift may be the same value (i.e., the value of each shift is a fixed value). In Table 4, m represents the value of each positive shift. The value may be set according to actual needs, and the embodiment of the present application does not impose any specific limitation on this.

[0105] Table 4

[0106] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift 2. bm cm ... Second shift a-2m b-2m c-2m ... ... ... ... ... ...

[0107] In another example, as shown in Table 5, when the first log-likelihood ratio value is negatively shifted, the value of each positive shift can be a different value (i.e., the value of each shift is a non-fixed value). In Table 5, m and n represent two values ​​of different sizes. These two values ​​can be set according to actual needs, and the embodiments of the present application do not impose specific restrictions on this.

[0108] Table 5

[0109] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift 2. bm cm ... Second shift amn bmn cmn ... ... ... ... ... ...

[0110] S1006. Perform soft decoding according to the shifted log-likelihood ratio value and the first soft bit data.

[0111] The log-likelihood ratio value can be soft-decoded with the first soft bit data once each time it is shifted. If the decoding is successful, the decoded data is output. Otherwise, S1007 is continued.

[0112] S1007. Determine whether the number of negative shifts of the first log-likelihood ratio value reaches a set threshold.

[0113] If the number of positive shifts of the first log-likelihood ratio value reaches the set threshold, the second soft decoding operation is terminated. If the number of positive shifts of the first log-likelihood ratio value does not reach the set threshold, S1005 to S1006 are continued.

[0114] In another possible implementation, the first log-likelihood ratio value may be negatively shifted at least once, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data. If the decoding still fails, the first log-likelihood ratio value may be positively shifted at least once, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data. The specific implementation process is as follows: Fig.11 shown.

[0115] S1101. Determine that the first soft decoding operation fails.

[0116] If the soft decoding cannot obtain correct data by performing soft decoding according to the first log-likelihood ratio value and the first soft bit data, it means that the first soft decoding operation fails.

[0117] S1102. Negatively shift the first log-likelihood ratio value.

[0118] Among them, the first log-likelihood ratio value may be negatively shifted in the manner of Table 4 or Table 5, and the embodiments of the present application are not described in detail here.

[0119] S1103. Perform soft decoding according to the shifted log-likelihood ratio value and the first soft bit data.

[0120] The log-likelihood ratio value can be soft-decoded with the first soft bit data once each time it is shifted. If the decoding is successful, the decoded data is output. Otherwise, S1104 is continued.

[0121] S1104. Determine whether the number of negative shifts of the first log-likelihood ratio value reaches a set threshold.

[0122] If the number of negative shifts of the first log-likelihood ratio value reaches the set threshold, S1105 to S1107 are executed. If the number of negative shifts of the first log-likelihood ratio value does not reach the set threshold, S1102 to S1103 are continued.

[0123] S1105. Perform a positive shift on the first log-likelihood ratio value.

[0124] Among them, the first log-likelihood ratio value may be positively shifted in the manner of Table 2 or Table 3, and the embodiments of the present application are not described in detail here.

[0125] S1106. Perform soft decoding according to the shifted log-likelihood ratio value and the first soft bit data.

[0126] The log-likelihood ratio value can be soft-decoded with the first soft bit data once each time it is shifted. If the decoding is successful, the decoded data is output. Otherwise, S1107 is continued.

[0127] S1107. Determine whether the number of negative shifts of the first log-likelihood ratio value reaches a set threshold.

[0128] If the number of positive shifts of the first log-likelihood ratio value reaches the set threshold, the second soft decoding operation is terminated. If the number of positive shifts of the first log-likelihood ratio value does not reach the set threshold, S1105 to S1106 are continued.

[0129] In another possible implementation, the first log-likelihood ratio value may be cross-shifted, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data, wherein the cross-shifting means that positive shift and negative shift are performed alternately, but the number of positive shifts or negative shifts after each crossover is not limited.

[0130] In one example, the first log-likelihood ratio value may be positively shifted at least once, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data. Next, the first log-likelihood ratio value may be negatively shifted at least once, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data. Then, the first log-likelihood ratio value may be positively shifted at least once again, and soft decoding may be performed based on the log-likelihood ratio value after each shift and the first soft bit data. This may be repeated until the decoding is successful or the number of shifts of the first log-likelihood ratio value reaches a set maximum value. The value of each shift may be the same or different.

[0131] Exemplarily, as shown in Table 6, it is assumed that the overlapping area of ​​two adjacent programming states in a certain storage unit is divided into multiple confidence intervals (Z1, Z2, Z3, ...), and the initial LLR values ​​corresponding to each confidence interval are (a, b, c, ...) in sequence. The first shift can first shift the first log-likelihood ratio value positively (i.e., add m). The second shift shifts the first log-likelihood ratio value negatively for the first time (i.e., subtract m). The third shift shifts the first log-likelihood ratio value positively for a second time (i.e., add m+n). The fourth shift shifts the first log-likelihood ratio value negatively for a second time (i.e., subtract 2m). Among them, the values ​​of m and n can be set according to actual needs, and the embodiments of the present application do not impose specific restrictions on this.

[0132] Table 6

[0133] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift a+m b+m c+m ... Second shift 2. bm cm ... The third shift a+m+n b+m+n c+m+n ... The fourth shift a-2m a-2m a-2m ... ... ... ... ... ...

[0134] In the above implementation process, when cross-shifting is performed, the value of each positive shift or negative shift can also be set according to actual needs and is not limited to the method in Table 6.

[0135] In one possible embodiment, Fig.12 As shown, when the number of shifts of the first log-likelihood ratio reaches a preset value, after the second soft decoding operation is finished, the soft decoding circuit can also replace the second lookup table to continue soft decoding the first soft bit data, as described below.

[0136] S1201. Obtain a second lookup table.

[0137] The second lookup table includes a second log-likelihood ratio value determined based on a second reference read voltage, and the second lookup table corresponds to a different scenario from the first lookup table.

[0138] Specifically, the reference read voltage in some scenarios may be offset, so the operating user can offset the reference read voltage in some scenarios to obtain a second reference read voltage, and obtain a second log-likelihood ratio value that can be decoded successfully after testing and calculation. The second lookup table can also be stored in the internal memory of the memory controller, or in a memory coupled to the memory controller.

[0139] S1202. Shift the first reference read voltage to a second reference read voltage.

[0140] Among them, when performing the offset of the read voltage, it can be set according to actual needs, and the embodiment of the present application does not impose specific limitations on this.

[0141] S1203. Read second soft bit data of the memory according to the second reference read voltage, and perform a third soft decoding operation according to the second soft bit data and the second log-likelihood ratio value.

[0142] The third soft decoding operation may be performed in a manner similar to the second soft decoding operation, and the embodiments of the present application will not be elaborated herein.

[0143] In the above manner, the reference read voltage may be offset first, and then the LLR value may be shifted based on the second lookup table, and soft decoding may be performed, thereby improving the efficiency of soft decoding.

[0144] In one possible embodiment, Fig.13 As shown, when the number of shifts of the first log-likelihood ratio reaches a preset value, after the second soft decoding operation is completed, the soft decoding circuit can also replace the third lookup table to continue soft decoding the first soft bit data, and the specific content is as follows.

[0145] S1301. Obtain a third lookup table.

[0146] The third lookup table includes a third log-likelihood ratio value determined based on a third reference read voltage, and the third lookup table corresponds to a different scenario than the first lookup table.

[0147] S1302. Perform a fourth soft decoding operation according to the third log-likelihood ratio value and the first soft bit data.

[0148] After the third lookup table is obtained, soft decoding can be performed directly according to the third lookup table, so that the soft decoding is performed by replacing the lookup table, thereby improving the efficiency of the soft decoding.

[0149] In the above implementation process, Fig.10 and Fig.11The corresponding soft decoding method can be selectively performed after the soft decoding fails by performing the shift of the LLR value based on the first lookup table. The embodiment of the present application does not impose any specific limitation on this.

[0150] In a possible implementation manner, the steps of shifting the log likelihood ratio value and soft decoding in the above various possible implementation manners can be implemented by a soft decoding circuit.

[0151] For example, Fig.14 As shown, the soft decoding circuit 1142 may include a register circuit 1410 coupled to the bus 113; and a decoding circuit 1420 coupled to the register circuit 1410. Fig.15 As shown, the decoding circuit 1420 may include a processor 1421 coupled to the register circuit 1410; a decoder 1422 coupled to the processor 1421, and a main controller 1423 coupled to the decoder 1422 and the processor 1421. Among them, the register circuit 1410 can store the lookup table read from the memory and the soft bit data read from the memory. The processor 1421 can send the LLR value and the soft bit data in the lookup table to the decoder 1422 for soft decoding. If the decoding is successful, the decoder 1422 sends the decoded data to the register circuit 1410 for caching. If the decoding fails, the decoder 1422 sends a flag signal to the main controller 1423. After receiving the flag signal, the main controller 1423 can send an indication signal to the processor 1421. The indication signal is used to instruct the processor 1421 to shift the LLR value in the lookup table and then transmit the LLR value to the decoder 1422 for soft decoding. Among them, the above-mentioned decoder 1422 can use an LDPC decoder. The main controller 1423 and processor 1422 mentioned above may include but are not limited to a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP) or a general-purpose processor, etc.

[0152] In the above implementation process, the main controller 1423 and the processor 1422 may also be the same device, and the embodiment of the present application does not impose any specific restrictions on this. In addition, the above soft decoding circuit 1142 may be disposed on a circuit board and sold or used as an independent chip, or may be sold or used as part of a memory controller.

[0153] In a possible implementation, the present application also provides a computer-readable storage medium. The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the steps corresponding to the method in any of the above possible implementations are implemented.

[0154] In some embodiments, the storage medium may be a ferromagnetic random access memory (FRAM), a read only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EPROM), a flash memory, a magnetic surface storage, an optical disc, or a compact disc read only memory (CD-ROM), UFS, a CF card, a memory stick, etc.

[0155] In one possible embodiment, Fig.16As shown, an embodiment of the present application further provides an electronic device 1600, which includes a host 1610 and a memory system 100 coupled to the host. Among them, the memory controller 110 in the memory system 100 is coupled to the host 1610. The memory controller 110 can manage the data stored in the memory 120 and communicate with the host 1610. The host 1610 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (System on Chip, SoC) (e.g., an application processor (AP)) of the electronic device 1600. The host 1610 can be configured to send data to the memory 120. Alternatively, the host 1610 can be configured to receive data from the memory 120. That is, the memory system 100 can be applied to and packaged into different types of electronic devices 1600, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0156] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A control method for a memory system, characterized in that: include: Acquire first soft bit data and a first lookup table corresponding to the hard bit data read from the memory; The first lookup table includes a first log-likelihood ratio value determined based on a first reference read voltage of the memory; performing a first soft decoding operation according to the first log-likelihood ratio value and the first soft bit data; When it is determined that the first soft decoding operation fails, the first log-likelihood ratio value is shifted at least once, and a second soft decoding operation is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

2. The method according to claim 1, characterized in that Shifting the first log-likelihood ratio value at least once, and performing a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, comprising: The first log-likelihood ratio value is positively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

3. The method according to claim 2, characterized in that The first log-likelihood ratio value is positively shifted at least once, and when soft decoding fails according to the log-likelihood ratio value after each shift and the first soft bit data, the method includes: The first log-likelihood ratio value is negatively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

4. The method according to claim 1, characterized in that: Shifting the first log-likelihood ratio value at least once, and performing a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, comprising: The first log-likelihood ratio value is negatively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

5. The method according to claim 4, characterized in that The first log-likelihood ratio value is negatively shifted at least once, and when soft decoding fails according to the log-likelihood ratio value after each shift and the first soft bit data, the method includes: The first log-likelihood ratio value is positively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

6. The method according to claim 1, characterized in that Shifting the first log-likelihood ratio value at least once, and performing a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, comprising: The first log-likelihood ratio value is cross-shifted, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

7. The method according to claim 1, characterized in that When the first log-likelihood ratio value is shifted at least once, the value of each shift is the same.

8. The method according to claim 1, characterized in that When the first log-likelihood ratio value is shifted at least once, the value of each shift is different.

9. The method according to claim 1, characterized in that: The method further comprises: When it is determined that the second soft decoding operation is successful, the corresponding decoded data is output; otherwise, when the number of shifts of the first log-likelihood ratio value reaches a preset value, the second soft decoding operation is stopped.

10. The method according to claim 9, characterized in that: When the number of shifts of the first log-likelihood ratio value reaches a preset value, after stopping the second soft decoding operation, the method further includes: Obtaining a second lookup table, the second lookup table including second log-likelihood ratio values ​​determined based on a second reference read voltage of the memory; shifting the first reference read voltage to the second reference read voltage; Second soft bit data of the memory is read according to the second reference read voltage, and a third soft decoding operation is performed according to the second soft bit data and the second log-likelihood ratio value.

11. The method according to claim 9, characterized in that: When the number of shifts of the first log-likelihood ratio value reaches a preset value, after stopping the second soft decoding operation, the method further includes: Obtaining a third lookup table, the third lookup table including third log-likelihood ratio values ​​determined based on a third reference read voltage of the memory; A fourth soft decoding operation is performed according to the third log-likelihood ratio value and the first soft bit data.

12. The method according to any one of claims 1 to 11, characterized in that: The step of acquiring first soft bit data and a first lookup table corresponding to the hard bit data read from the memory is performed after a hard decoding operation of the hard bit data fails.

13. A computer-readable storage medium, characterized in that: Computer program instructions are stored; when the computer program instructions are executed by a processor, the method described in any one of claims 1 to 12 is implemented.

14. A memory system, characterized in that: comprising one or more memories; a memory controller coupled to the memories and configured to control the memories; the memory controller comprising a decoding circuit; The decoding circuit is configured as follows: Acquire first soft bit data corresponding to hard bit data read from a memory and a first lookup table; the first lookup table includes a first log-likelihood ratio value determined based on a first reference read voltage of the memory; performing a first soft decoding operation according to the first log-likelihood ratio value and the first soft bit data; When it is determined that the first soft decoding operation fails, the first log-likelihood ratio value is shifted at least once, and a second soft decoding operation is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

15. The memory system according to claim 14, characterized in that: When performing at least one shift on the first log-likelihood ratio value and performing a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, the decoding circuit is configured as follows: The first log-likelihood ratio value is positively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

16. The memory system according to claim 15, characterized in that: The first log-likelihood ratio value is positively shifted at least once, and when soft decoding fails according to the log-likelihood ratio value after each shift and the first soft bit data, the decoding circuit is further configured to: The first log-likelihood ratio value is negatively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

17. The memory system according to claim 14, wherein: When performing at least one shift on the first log-likelihood ratio value and performing a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, the decoding circuit is configured as follows: The first log-likelihood ratio value is negatively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

18. The memory system according to claim 17, wherein: The first log-likelihood ratio value is negatively shifted at least once, and when soft decoding fails according to the log-likelihood ratio value after each shift and the first soft bit data, the decoding circuit is further configured to: The first log-likelihood ratio value is positively shifted at least once, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

19. The memory system according to claim 14, wherein: Shifting the first log-likelihood ratio value at least once, and performing a second soft decoding operation according to the log-likelihood ratio value after each shift and the first soft bit data, comprising: The first log-likelihood ratio value is cross-shifted, and soft decoding is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

20. The memory system according to claim 14, wherein: When the first log-likelihood ratio value is shifted at least once, the value of each shift is the same.

21. The memory system according to claim 14, wherein: When the first log-likelihood ratio value is shifted at least once, the value of each shift is different.

22. A memory controller, characterized in that: comprising a bus and a decoding circuit coupled to the bus; The decoding circuit is configured as follows: Acquire first soft bit data corresponding to hard bit data read from a memory and a first lookup table; the first lookup table includes a first log-likelihood ratio value determined based on a reference read voltage of the memory; performing a first soft decoding operation according to the first log-likelihood ratio value and the first soft bit data; When it is determined that the first soft decoding operation fails, the first log-likelihood ratio value is shifted at least once, and a second soft decoding operation is performed according to the log-likelihood ratio value after each shift and the first soft bit data.

23. An electronic device, characterized in that: An interface circuit is included, and a memory system as claimed in any one of claims 14 to 21 is coupled to the interface circuit.

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