Data writing method, storage control chip and flash memory device thereof

Abstract

The embodiment of the application relates to the application field of storage devices, and discloses a data writing method, a storage control chip and a flash memory device thereof, the data writing method comprises the following steps: obtaining a write command, sending a first programming instruction to a flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether a flow breakage mark exists; when the flow breakage mark is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation; and when the flow breakage mark is not detected after any data transmission operation is completed, sending a second programming instruction to the flash memory medium to write data into the flash memory medium. The application can process data flow breakage in the writing process, so that the data can be correctly and completely written into the flash memory medium, thereby reducing data writing errors caused by data flow breakage, improving the integrity and accuracy of data writing, and further improving the reliability and stability of the flash memory device.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a data writing method, a storage control chip, and a flash memory device thereof. Background Technology

[0002] Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium. During the data writing process, the storage controller chip of the flash memory device needs to transfer data to the flash memory medium. However, during high-speed data transfer, the storage controller chip is prone to processing bottlenecks, leading to data interruptions.

[0003] Data interruption refers to a temporary halt in data transmission when the processing speed of the flash memory device's controller chip is slower than the data transmission speed, until the controller chip completes processing the current data and then resumes transmission from the point of interruption. This can lead to errors during the data writing process, affecting data integrity and accuracy.

[0004] Currently, after a data interruption causes a data write error, the erroneous data is usually recovered. For example, for flash memory devices that use Redundant Arrays of Inexpensive Disks (RAID) technology, when a data interruption occurs in a data logical unit (Die), the redundancy characteristics of RAID are used to recover part of the erroneous data.

[0005] In the process of developing this application, the inventors discovered that the prior art has at least the following problems: existing solutions do not provide sufficient handling mechanisms for data interruptions during the writing process, and once a data interruption occurs, the written data is prone to errors. Furthermore, for flash memory devices using RAID technology, when a data interruption occurs across multiple dies, it exceeds the recovery capability of RAID technology, easily leading to permanent data loss. Summary of the Invention

[0006] This application provides a data writing method, a storage control chip, and a flash memory device to reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of the flash memory device.

[0007] The embodiments of this application provide the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a data writing method, which is applied to a flash memory device, the flash memory device including a flash memory medium, and the data writing method includes:

[0009] Obtain the write command, send the first programming instruction to the flash memory medium based on the write command, and perform data transmission operations;

[0010] After each data transmission operation is completed, check for the presence of a data interruption flag, which indicates that a data interruption occurred during the data transmission operation.

[0011] When a current interruption flag is detected, the first programming instruction is resent to the flash memory medium and the data transmission operation is restarted until no current interruption flag is detected after any data transmission operation is completed. Then, the second programming instruction is sent to the flash memory medium to write the data to the flash memory medium.

[0012] The first programming instruction includes the address information of the data, and the second programming instruction is used to instruct the flash memory medium to write data.

[0013] Secondly, embodiments of this application provide a storage control chip, comprising:

[0014] At least one processor; and,

[0015] A memory that is communicatively connected to at least one processor; wherein,

[0016] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform a data writing method as described in the first aspect.

[0017] Thirdly, embodiments of this application provide a flash memory device, including:

[0018] Such as the storage control chip in the second aspect;

[0019] At least one flash memory medium is communicatively connected to the storage controller chip.

[0020] Fourthly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions that enable a flash memory device to perform the data writing method as described in the first aspect.

[0021] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a data writing method applied to a flash memory device, which includes a flash memory medium. The data writing method includes: obtaining a write command; sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether a disconnection flag exists, wherein the disconnection flag indicates that a data interruption occurred during the data transmission operation; when a disconnection flag is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until no disconnection flag is detected after any data transmission operation is completed, sending a second programming instruction to the flash memory medium to write data into the flash memory medium; wherein the first programming instruction includes data address information, and the second programming instruction instructs the flash memory medium to write data.

[0022] By resending the first programming instruction and re-performing the data transmission operation when a data interruption flag is detected, and then sending the second programming instruction to the flash memory medium after any data transmission operation is completed without detecting a data interruption flag, the present application can handle data interruption during the writing process, enabling data to be written correctly and completely to the flash memory medium. This reduces data writing errors caused by data interruption, improves the integrity and accuracy of data writing, and thus improves the reliability and stability of the flash memory device. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 This is a schematic diagram of the structure of a main control system for a flash memory device provided in an embodiment of this application;

[0025] Figure 2 This is a flowchart illustrating a data writing method provided in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of a data writing process provided in an embodiment of this application;

[0027] Figure 4 yes Figure 3 A detailed flowchart of step S202 in the process;

[0028] Figure 5 This is a detailed flowchart illustrating the first data writing method provided in this application embodiment;

[0029] Figure 6 This is a detailed flowchart illustrating the second data writing method provided in the embodiments of this application;

[0030] Figure 7 This is a schematic diagram of a data writing process based on RAID technology provided in an embodiment of this application;

[0031] Figure 8 This is a detailed flowchart illustrating the third data writing method provided in the embodiments of this application;

[0032] Figure 9 This is a schematic diagram of a superblock provided in an embodiment of this application;

[0033] Figure 10 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0034] Figure 11 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0036] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0037] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0038] In this embodiment, the flash memory device includes a solid-state drive or other storage device that uses flash memory as the storage medium, and the storage control chip includes a controller for the solid-state drive or other storage device that uses flash memory as the storage medium.

[0039] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a main control system for a flash memory device provided in an embodiment of this application;

[0040] It is understandable that the storage control chip of a flash memory device includes a main control system, which is used to connect the host and the flash memory array to realize data input and output (I / O) processing.

[0041] like Figure 1 As shown, the main control system 100 includes:

[0042] The front end module 101 (FE) is used to obtain host commands to generate I / O operations. The front end module 101 is also responsible for the communication protocol with the host 200, parsing host commands and solid-state drive commands, etc.

[0043] The flash algorithm module 102, also known as the flash translation layer (FTL), is used to map IO operations to determine the flash array to be sent.

[0044] The flash memory algorithm module 102 sends I / O operations to the back end (BE) module 103 of the storage control chip so that the back end module 103 can receive the I / O operations sent by the flash memory algorithm module 102.

[0045] The back-end module 103 (BE) is connected to the flash memory algorithm module 102 and is used to receive IO operations sent by the flash memory algorithm module 102 to control the hardware module 104 to perform read / write / erase operations on the flash memory array.

[0046] Hardware module 104 (HW Op Nand Mode) refers to the module that operates the Flash memory. It is connected to the back-end module 103 and controlled by the back-end module 103. It is used to operate the Flash memory, such as performing operations on the corresponding flash array or flash medium according to the IO operation, that is, to complete the operation processing of data to the Flash memory. The operation includes read operation, write operation or erase operation.

[0047] In this system, after receiving a host command, the front-end module 101 processes it to generate an I / O operation, which is then sequentially routed through the flash memory algorithm module 102, the back-end module 103, and the hardware module 104 to operate the flash memory array. For example, when the host needs to read or write data, it sends a host command to the flash memory device. The front-end module 101 (FE) of the flash memory device receives the host command, processes it, and distributes it to the flash memory algorithm module 102 (FTL). Upon receiving the command, the flash memory algorithm module 102 performs a logical-to-physical conversion and then sends the NAND read or write operation request to the back-end module 103 (BE). After receiving the request, the back-end module 103 sends the hardware instructions to the hardware module 104, performing NAND processing in parallel.

[0048] During the writing process of data to a flash memory device, the storage controller chip needs to transfer data to the flash memory medium. With the advancement of flash memory technology, the transfer rate of the storage controller chip is becoming increasingly faster, and the requirements for signal quality are becoming increasingly stringent. However, during high-speed data transfer, the storage controller chip is prone to processing bottlenecks, leading to data interruptions. High-speed transfer refers to a data transfer rate greater than 1600 mega-transfers per second (MT / s).

[0049] Specifically, data interruption refers to the temporary halt in data transmission when the processing speed of the flash memory device's storage controller chip is lower than the data transmission speed, until the storage controller chip completes processing of the current data, and then data transmission resumes from the point of interruption. This can lead to errors during data writing or reading, affecting data integrity and accuracy.

[0050] Existing solutions do not provide sufficient handling mechanisms for data interruptions. When a data interruption occurs during a read operation, the read data is identified as containing Uncorrectable Errors (UNCs). Currently, a reread operation is typically used in the hope of obtaining the correct data in the next read.

[0051] Data interruptions during the write process are often not handled effectively, typically resulting in data corruption. Recovery is only possible after the write operation has failed. For example, in flash memory devices using Redundant Arrays of Inexpensive Disks (RAID) technology, when a data interruption occurs in a single data logical unit (die), the redundancy of RAID allows for partial data recovery.

[0052] Specifically, RAID technology is a data storage virtualization technology that combines multiple disk drives into a single logical unit, providing data redundancy and improving performance by distributing data across disks. For flash memory devices using RAID, the data logical unit is divided into a general data logical unit and a parity data logical unit (ParityDie). The flash media includes at least two general data logical units and one parity data logical unit. The general data logical units store general data, and the parity data logical unit stores parity data. During data writing, the flash memory device divides the data to be written into multiple general data units and performs an XOR operation on these general data units to obtain the parity data. Then, the flash memory device writes each general data unit to its corresponding general data logical unit and the parity data to its corresponding parity data logical unit.

[0053] If a data interruption occurs in a regular data logic unit during the write process, resulting in a data write error, the data can only be recovered after the write operation is completed. Specifically, if an uncorrectable error occurs when reading data from that regular data logic unit after the write operation is completed, but no errors occur when reading data from other regular data logic units and check data logic units, the data in that regular data logic unit can be recovered by performing an XOR operation on the data in the other regular data logic units and check data logic units.

[0054] For example, the check data D is obtained by XORing data A, data B, and data C. If an error occurs during the writing of data A to the flash memory medium, data A can be obtained by XORing the check data D, data B, and data C.

[0055] However, this method only allows data loss to occur in one die. When data loss occurs in multiple dies, it exceeds the recovery capability of RAID technology and can easily lead to permanent data loss.

[0056] Based on this, this application proposes a data writing method that can handle data interruption during the writing process, rather than recovering data after a write error occurs due to data interruption. This application can reduce data write errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of flash memory devices.

[0057] Please see Figure 2 , Figure 2 This is a flowchart illustrating a data writing method provided in an embodiment of this application;

[0058] This data writing method is applied to a flash memory device, such as a storage controller chip for the flash memory device, wherein the flash memory device includes a flash memory medium.

[0059] like Figure 2 As shown, the data writing method includes:

[0060] Step S201: Obtain the write command, send the first programming instruction to the flash memory medium based on the write command, and perform data transmission operation;

[0061] The write command includes the data to be written and corresponding data information, including the logical block address (LBA) of the data. The first programming instruction includes a first command and data address information. The first command instructs the flash memory medium to prepare for writing data, and the data address information includes the physical block address (PBA) of the data, which is the physical location in the flash memory medium where the data is written. The data transfer operation is used to transfer data to the flash memory medium. In this embodiment, the first command is an 80h command, which instructs the flash memory medium to prepare for writing data.

[0062] Specifically, the storage controller chip receives the write command sent by the host, performs address translation on the logical address of the data contained in the write command, determines the physical address corresponding to the data, and then sends the first programming instruction to the flash memory medium. Then, it performs a data transfer operation to transfer the data to the flash memory medium.

[0063] In this embodiment, the first programming instruction includes an 80h command and the physical address corresponding to the data. The storage control chip first sends an 80h command to the flash memory medium to instruct it to prepare to write data. The 80h command is followed by the physical address corresponding to the data, instructing the flash memory medium to write the data to that physical address. Then, the storage control chip sends the data to the flash memory medium. At this point, the data is only loaded into the page buffer of the flash memory medium and is not written to the cell. Only after the subsequent second programming instruction is sent will the flash memory medium perform the actual programming action, writing the data in the page buffer to the specified physical location. The second programming instruction is used to instruct the flash memory medium to write data.

[0064] Please see Figure 3 , Figure 3 This is a schematic diagram of a data writing process provided in an embodiment of this application;

[0065] like Figure 3As shown, the storage control chip first sends a first programming instruction to the flash memory medium, then performs data transmission, and finally sends a second programming instruction to the flash memory medium, thereby triggering the flash memory medium to perform a programming action to complete the write operation. Specifically, after receiving the second programming instruction, the memory cells in the flash memory medium undergo a charging process, changing the charge state of the floating gates to store data.

[0066] In this embodiment, the flash memory device further includes a front-end module, a flash memory algorithm module, a back-end module, and a hardware module. For details on the connection methods of the front-end module, flash memory algorithm module, back-end module, and hardware module, please refer to [link to relevant documentation]. Figure 1 .

[0067] In step S201, the front-end module receives the write command sent by the host, processes it, and distributes it to the flash memory algorithm module. The flash memory algorithm module performs address translation on the logical address of the data contained in the write command to determine the physical address corresponding to the data, and then sends the write operation request to the back-end module. After receiving the write operation request, the back-end module executes the write operation and sends the first programming instruction to the flash memory medium. Then the hardware module performs the data transmission operation to transmit the data to the flash memory medium.

[0068] Step S202: After each data transmission operation is completed, check if there is a disconnection flag;

[0069] The interruption flag indicates a data transmission interruption during the data transfer operation. The storage controller chip checks for the presence of the interruption flag after each data transfer operation. Specifically, the backend module within the storage controller chip checks for the presence of the interruption flag after each data transfer operation.

[0070] Please see Figure 4 , Figure 4 yes Figure 2 A detailed flowchart of step S202 in the process;

[0071] In this embodiment, the flash memory device further includes a register. The register records whether a data transfer interruption occurs during a data transfer operation. When a data transfer interruption occurs, the register value is set to a first value; when no data transfer interruption occurs, the register value is a second value. The register includes, but is not limited to, a Hardware Status Register (HSR). The first and second values ​​can be set by those skilled in the art according to actual conditions, and are not limited in this embodiment. For example, the first value is 1, and the second value is 0.

[0072] like Figure 4As shown, step S202: After each data transmission operation is completed, detect whether there is a disconnection flag, including:

[0073] Step S221: Perform data transmission operation;

[0074] Specifically, before each data transmission operation, the storage control chip initializes the register, setting the register value to a second value, for example, setting the register value to 0. Then, after each data transmission operation is completed, steps S222-S227 are executed to detect whether a current interruption flag exists.

[0075] Step S222: Based on the hardware module, determine whether a data interruption occurred during the data transmission operation;

[0076] Specifically, the hardware module determines whether a data interruption occurs during the data transmission operation.

[0077] In some embodiments, the hardware module determines whether a data transmission interruption has occurred during the data transmission operation by timeout detection. For example, if the hardware module does not receive data or detect any data transmission activity within a preset time during the data transmission operation, the hardware module determines that a data transmission interruption has occurred; otherwise, the hardware module determines that no data transmission interruption has occurred. The preset time can be set by those skilled in the art according to actual conditions, and is not limited in this embodiment.

[0078] In some embodiments, the hardware module determines whether a data interruption has occurred during the data transmission operation by error checking. For example, during the data transmission operation, a cyclic redundancy check (CRC) is used to calculate the verification result. If the verification result calculated by the hardware module for the received data does not match the expectation, the hardware module determines that a data interruption has occurred during the data transmission operation; otherwise, the hardware module determines that no data interruption has occurred during the data transmission operation.

[0079] Cyclic redundancy check (CRB) involves calculating a checksum using a specific polynomial and then appending this result to the end of the data. During data transmission, the receiver can recalculate the checksum of the received data using the same polynomial and compare it to the checksum provided by the sender.

[0080] Furthermore, if a data interruption occurs during the data transmission operation, proceed to step S223; if no data interruption occurs during the data transmission operation, proceed to step S224.

[0081] Understandably, if no data interruption occurs during the data transmission operation, the register value will remain the second value.

[0082] Step S223: Set the value of the register to the first value;

[0083] Specifically, if a data transmission interruption occurs during the data transmission operation, the hardware module will set the value of the register to the first value, for example, set it to 1.

[0084] Step S224: Based on the backend module, query the value of the register;

[0085] Specifically, the backend module determines whether a flow interruption flag exists by querying the value of the register.

[0086] Step S225: Determine whether the value is the first value;

[0087] Specifically, the backend module determines whether the value of the queried register is the first value. If the value of the register is the first value, proceed to step S226; if the value of the register is not the first value, that is, the value of the register is the second value, proceed to step S227.

[0088] Step S226: Determine that a flow interruption marker has been detected;

[0089] Specifically, when the value retrieved by the backend module is the first value, the backend module determines that a data interruption flag has been detected. For example, if the backend module finds that the value in the register is 1, it determines that a data interruption flag has been detected. In other words, when a data interruption flag is detected, it can be determined that a data interruption occurred during the current data transmission operation.

[0090] Step S227: Determine that no interruption marker is detected.

[0091] Specifically, when the value retrieved by the backend module is the second value, the backend module determines that no data interruption flag has been detected. For example, if the backend module finds that the value of the register is 0, it determines that no data interruption flag has been detected. It can be understood that if no data interruption flag is detected, it can be determined that no data interruption occurred during this data transmission operation.

[0092] Step S203: When a current interruption flag is detected, the first programming instruction is resent to the flash memory medium and the data transmission operation is performed again until no current interruption flag is detected after any data transmission operation is completed. Then, the second programming instruction is sent to the flash memory medium to write the data to the flash memory medium.

[0093] The second programming instruction is used to instruct the flash memory medium to write data, that is, to instruct the memory cells in the flash memory medium to perform a charging process, changing the charge state of the floating gate, thereby storing data. In this embodiment, the second programming instruction is the 10h command, which instructs the flash memory medium to perform the actual programming action, that is, to trigger the memory cells of the flash memory medium to start the charging process, and to realize the storage of data by changing the charge state of the floating gate in the memory cell, thereby ensuring that the data is successfully written to the memory cell and completing the write operation.

[0094] Specifically, after each data transfer operation, if the storage controller chip detects a disconnection flag, it resends the first programming instruction to the flash memory medium and restarts the data transfer operation. This process continues until no disconnection flag is detected after any data transfer operation. In this case, the storage controller chip sends a second programming instruction to the flash memory medium to write the data. Alternatively, after each data transfer operation, if the storage controller chip does not detect a disconnection flag, it sends a second programming instruction to the flash memory medium to write the data.

[0095] In some embodiments, for flash memory devices without RAID data protection, i.e. flash memory devices that do not use RAID technology, step S203 includes: after each data transmission operation is completed, if a disconnection flag is detected and the number of disconnections is less than or equal to a first threshold, then the value of the number of disconnections is incremented by one, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again.

[0096] The interruption count refers to the number of times data transmission is interrupted during a single write operation. After the storage controller chip sends the first programming instruction to the flash memory medium, if a data interruption occurs during the data transmission operation, the interruption count is incremented by one.

[0097] In some embodiments, for flash memory devices without RAID data protection, the data writing method further includes: after each data transmission operation is completed, if a disconnection flag is detected and the number of disconnections is greater than a first threshold, then a disconnection error is determined to have occurred, and the disconnection error is processed.

[0098] The first threshold is the maximum number of data interruptions allowed to occur in the flash memory device, and an interruption error is a data write error caused by a data interruption during data transmission. The first threshold can be set by those skilled in the art according to actual circumstances, and is not limited in this embodiment. For example, the first threshold is 3.

[0099] In some embodiments, for a flash memory device with RAID data protection function, i.e., a flash memory device using RAID technology, step S203 includes: after each data transmission operation is completed, if a disconnection flag is detected and the number of disconnections is less than or equal to a first threshold, then the value of the disconnection count is incremented by one, the value of the non-disconnection flag is set to a second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again. Here, the non-disconnection flag indicates that no data interruption occurred during the data transmission operation.

[0100] In some embodiments, for a flash memory device with RAID data protection, step S203 further includes: after each data transmission operation is completed, incrementing the transmission count by one; after each data transmission operation is completed, if a disconnection flag is detected, and the disconnection count is greater than a first threshold, and the transmission count is even, then incrementing the disconnection count by one, setting the value of the non-disconnection flag to a second value, resending the first programming instruction to the flash memory medium, and re-performing the data transmission operation. Here, the transmission count is the number of times the data transmission operation is completed during a single write operation.

[0101] In some embodiments, for a flash memory device with RAID data protection, step S203 further includes: after each data transmission operation is completed, if no interruption flag is detected and the number of transmissions is odd, sending a second programming instruction to the flash memory medium to write data to the flash memory medium.

[0102] In some embodiments, for a flash memory device with RAID data protection, the data writing method further includes: after each data transmission operation is completed, if no interruption flag is detected, setting the value of the non-interruption flag to a first value; after each data transmission operation is completed, if no interruption flag is detected and the number of transmissions is even, incrementing the number of interruptions by one, setting the value of the non-interruption flag to a second value, resending the first programming instruction to the flash memory medium, and re-performing the data transmission operation.

[0103] In some embodiments, for a flash memory device with RAID data protection, the data writing method further includes: after each data transmission operation is completed, if a disconnection flag is detected, and the number of disconnections is greater than a first threshold and the number of transmissions is odd, then a disconnection error is determined to have occurred, and the disconnection error is processed.

[0104] For details, please refer to Figure 5 , Figure 5 This is a detailed flowchart illustrating the first data writing method provided in this application embodiment;

[0105] In this embodiment, the first data writing method is applied to a flash memory device that does not have RAID data protection, i.e., a flash memory device that does not employ RAID technology. The flash memory device also includes a first counter for recording the number of data interruptions.

[0106] like Figure 5 As shown, the detailed process of the first data writing method includes:

[0107] Step S501: Obtain the write command, send the first programming instruction to the flash memory medium based on the write command, and perform data transmission operation;

[0108] Specifically, the front-end module receives the write command sent by the host, processes it, and distributes it to the flash memory algorithm module. The flash memory algorithm module performs address translation on the logical address of the data contained in the write command to determine the physical address corresponding to the data, and then sends the write operation request to the back-end module. After receiving the write operation request, the back-end module executes the write operation and sends the first programming instruction to the flash memory medium. The first programming instruction includes the 80h command and the physical address corresponding to the data. Then, the hardware module performs the data transmission operation to transfer the data to the flash memory medium.

[0109] Before performing data transmission operations, the storage control chip initializes the first counter and register, and clears the first counter and register to zero.

[0110] Step S502: Confirm that a data transmission operation has been completed;

[0111] Step S503: Detect whether a current interruption marker exists;

[0112] Specifically, after each data transmission operation is completed, the backend module checks for the presence of a disconnection flag. This step is the same as step S202 and will not be described again here.

[0113] Further, if a flow interruption marker is detected, proceed to step S504; if no flow interruption marker is detected, proceed to step S507.

[0114] Step S504: Determine whether the number of disconnections exceeds the first threshold;

[0115] Specifically, the backend module determines whether the number of interruptions exceeds a first threshold, for example, whether the number of interruptions exceeds 3. The number of interruptions refers to the number of times data transmission is interrupted during a single write operation, specifically the number of times data transmission is interrupted during steps S501 and S506.

[0116] Further, if the number of disconnections is greater than the first threshold, proceed to step S505; if the number of disconnections is less than or equal to the first threshold, proceed to step S506.

[0117] In this embodiment, by determining whether the number of interruptions exceeds a first threshold after detecting the interruption flag, this application can take into account the situation where data interruption occurs during each data transmission operation. In this case, this application will not perform data transmission in an infinite loop, but will report the interruption error to the flash memory algorithm module, which will then process the interruption error, thereby improving the stability and reliability of data transmission and reducing resource waste and performance degradation caused by frequent interruptions.

[0118] Step S505: Determine that a flow interruption error has occurred;

[0119] Specifically, after each data transmission operation is completed, if a disconnection flag is detected and the number of disconnections exceeds the first threshold, the backend module determines that a disconnection error has occurred and reports the disconnection error to the flash memory algorithm module, which then handles the disconnection error.

[0120] In some embodiments, the backend module reports a flow interruption error to the flash memory algorithm module by reporting an error code.

[0121] In some embodiments, the steps of the flash memory algorithm module in handling the interruption error include: selecting a physical block from the remaining dies and re-executing steps S501-S507 to write data to the newly selected physical block.

[0122] In some embodiments, the flash memory algorithm module may handle flow interruption errors in other ways, which are not limited in the embodiments of this application.

[0123] Step S506: Increment the number of interruptions by one, resend the first programming instruction to the flash memory medium, and re-perform the data transmission operation;

[0124] Specifically, after each data transmission operation is completed, if the backend module detects a disconnection flag and the number of disconnections is less than or equal to the first threshold, the backend module increments the number of disconnections by one, resends the first programming instruction to the flash memory medium, and performs the data transmission operation again.

[0125] Furthermore, after the backend module completes step S506, it returns to step S502 and repeats steps S503-S506 until the backend module no longer detects the disconnection flag or the number of disconnections exceeds the first threshold.

[0126] Step S507: Send a second programming instruction to the flash memory medium to write data into the flash memory medium.

[0127] Specifically, after each data transmission operation is completed, if the backend module does not detect a current interruption flag, it sends a second programming instruction to the flash memory medium to write the data into the flash memory medium. After receiving the second programming instruction, the storage cells in the flash memory medium undergo a charging process, changing the charge state of the floating gate, thereby storing the data. At this point, the data is completely written into the flash memory medium, and the write operation is complete.

[0128] In this embodiment, after each data transmission operation is completed, if a disconnection flag is detected and the number of disconnections is less than or equal to a first threshold, the number of disconnections is incremented by one, the first programming instruction is resent to the flash memory medium, and the data transmission operation is repeated until no disconnection flag is detected after any data transmission operation is completed. Then, a second programming instruction is sent to the flash memory medium to write the data. Compared to existing solutions that can only recover erroneous data after a data disconnection causes a data write error, this application can handle data disconnections during the writing process, enabling data to be written correctly and completely to the flash memory medium. This reduces data write errors caused by data disconnections, improves the integrity and accuracy of data writing, and ultimately improves the reliability and stability of the flash memory device.

[0129] Please see Figure 6 , Figure 6 This is a detailed flowchart illustrating the second data writing method provided in the embodiments of this application;

[0130] In this embodiment, the second data writing method is applied to a flash memory device with RAID data protection, i.e., a flash memory device employing RAID technology. The flash memory device also includes a second counter, which records the number of transmissions, representing the number of data transmission operations completed during a single write operation.

[0131] For flash memory devices employing RAID technology, the flash memory device also includes a cache space and a redundancy buffer. The cache space includes at least two data buffers, and the flash media includes at least two ordinary data logical units and one parity data logical unit, wherein each ordinary data logical unit corresponds to one data buffer, and the parity data logical unit corresponds to the redundancy buffer.

[0132] The system includes a data buffer for storing data to be written, a redundancy buffer for storing data from several data buffers after XOR processing (including parity data), and a regular data logic unit for storing data written to the corresponding data buffer in the cache space (i.e., data to be written). The parity data logic unit stores the parity data written to the redundant data buffer.

[0133] The cache space includes, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) and other similar storage devices. The redundant buffer includes, but is not limited to, Redundant Array of Independent Disks (RAID) and other similar disk arrays.

[0134] like Figure 6 As shown, the detailed process of the second data writing method includes:

[0135] Step S601: Obtain the write command, send the first programming instruction to the flash memory medium based on the write command, and perform data transmission operation;

[0136] Specifically, the front-end module receives the write command sent by the host, splits the data contained in the write command to obtain at least two data items to be written, and stores each data item to be written into the corresponding data buffer; the flash memory algorithm module determines the physical address corresponding to each data item to be written, and then sends the write operation request to the back-end module; after receiving the write operation request, the back-end module executes the write operation, sends the first programming instruction to the flash memory medium, the first programming instruction includes the 80h command and the physical address of the ordinary data logic unit corresponding to each data item to be written; then the hardware module performs the data transmission operation, transferring each data item to be written from the corresponding data buffer to the flash memory medium.

[0137] Before performing data transmission operations, the data writing method also includes: initializing the register; and setting the values ​​of the interruption count, transmission count, and non-interruption flag to the second value.

[0138] Specifically, the storage control chip initializes the first counter, the second counter, the register, and the non-disconnection flag, clears the first counter, the second counter, and the register to 0, and sets the value of the non-disconnection flag to the second value, for example, 0. It can be understood that when the first counter and the second counter are cleared to 0, it means that the values ​​of the disconnection count and the transmission count are set to 0.

[0139] The "No Disconnection" flag indicates that no data interruption occurred during the data transmission operation. After a data transmission operation is completed, if the storage controller chip does not detect the disconnection flag, it sets the value of the "No Disconnection" flag to the first value, for example, 1. In this case, the "No Disconnection" flag indicates that no data interruption occurred during the data transmission operation. However, if a data interruption occurs during the data transmission operation, the value of the "No Disconnection" flag remains the second value, i.e., 0.

[0140] Please see Figure 7, Figure 7 This is a schematic diagram of a data writing process based on RAID technology provided in an embodiment of this application;

[0141] like Figure 7 As shown, the cache space includes at least two data buffers. Figure 7 Taking the first, second, and third data buffers as examples, each data buffer is used to store data to be written. The flash memory medium includes at least two ordinary data logic units and one parity data logic unit. Figure 7 Taking the first and second ordinary data logic units as examples, each ordinary data logic unit is used to store the data to be written in the corresponding data buffer in the cache space, and the verification data logic unit is used to store the verification data written to the redundant data buffer.

[0142] by Figure 7 For example, the hardware module performs an XOR operation on the data to be written in the three data buffers to obtain the check data, and then saves the check data to the redundancy buffer. The hardware module writes the data to be written in the three data buffers into the corresponding ordinary data logic units, and after obtaining the check data, the hardware writes the check data in the redundancy buffer into the check data logic unit in the flash memory medium.

[0143] In this embodiment, step S601: obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command, and performing data transmission operations, includes steps S611-S614:

[0144] Step S611: Split the data contained in the write command to obtain at least two pieces of data to be written;

[0145] Specifically, the front-end module splits the data contained in the write command to obtain at least two data items to be written.

[0146] Step S612: Store each piece of data to be written into the corresponding data buffer;

[0147] Specifically, the front-end module stores each piece of data to be written into the corresponding data buffer.

[0148] Step S613: Send the first programming instruction to the flash memory medium;

[0149] Specifically, the flash memory algorithm module determines the physical address corresponding to each piece of data to be written, and then sends the write operation request to the backend module. After receiving the write operation request sent by the flash memory algorithm module, the backend module executes the write operation and sends the first programming instruction to the flash memory medium. The first programming instruction includes the 80h command and the physical address of the ordinary data logic unit corresponding to each piece of data to be written. Each piece of data to be written corresponds to a different ordinary data logic unit.

[0150] Step S614: Perform a data transfer operation to transfer each piece of data to be written from the corresponding data buffer to the flash memory medium.

[0151] Specifically, the hardware module performs data transmission operations, transferring each piece of data to be written from its corresponding data buffer to the flash memory medium.

[0152] The method also includes the following when performing data transfer operations:

[0153] When performing data transmission operations on the data to be written in the first data buffer, the data to be written is XORed to obtain a first XOR result, and the first XOR result is stored in the redundant buffer. When performing data transmission operations on the data to be written in the remaining data buffers, the data to be written currently being transmitted is XORed with the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and the first XOR result stored in the redundant buffer is updated with the second XOR result.

[0154] Specifically, the first data buffer is the first data buffer to be used for data transmission. Before transferring the data to be written from the first data buffer to the flash memory medium, the flash memory device controls the redundancy buffer to zero.

[0155] In this embodiment, the hardware module performs XOR processing on the data to be written in each data buffer sequentially. When data transmission is performed on the data to be written in the first data buffer, the hardware module performs XOR processing on the data to be written, obtains a first XOR result, and stores the first XOR result in a redundant buffer. When data transmission is performed on the data to be written in the remaining data buffers, the hardware module performs XOR processing on the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer, obtains a second XOR result, and updates the first XOR result stored in the redundant buffer with the second XOR result, i.e., assigns the second XOR result to the first XOR result, thereby updating the original first XOR result in the redundant buffer. This process continues until the last data buffer undergoes data transmission, and the first XOR processing on the last data to be written is performed on the last data buffer, obtaining a second XOR result. After updating the first XOR result stored in the redundant buffer with the second XOR result, the XOR processing stops. At this point, the first XOR result stored in the redundant buffer is the check data.

[0156] Among them, the remaining data buffers refer to the data buffers other than the first data buffer. The first XOR result is the XOR result stored in the redundant buffer. The first XOR result will be updated by the second XOR result. The second XOR result is the XOR result obtained by XORing the currently transmitted data to be written with the first XOR result currently stored in the redundant buffer.

[0157] The XOR processing includes the XOR operation or modulo-2 addition. XOR is a binary operation whose result is 1 only if the two input bits are different, otherwise 0. Modulo-2 addition is a binary operation equivalent to XOR; its rule is to add the two sequences bit-by-bit modulo 2, meaning corresponding bits in the two sequences are added without carry; the result is 0 if they are the same, and 1 if they are different. That is, 1 plus 1 equals 0, 0 plus 0 equals 0, 1 plus 0 equals 1, and 0 plus 1 equals 1. Because XOR processing is very fast, the hardware module can ensure that the checksum data in the redundant buffer is read only after the XOR processing of all data to be written in the data buffer has been completed.

[0158] Step S602: Confirm that a data transmission operation has been completed;

[0159] Specifically, after each data transmission operation is completed, the backend module increments the transmission count by one to indicate that a data transmission has been completed.

[0160] Step S603: Detect whether a current interruption marker exists;

[0161] Specifically, after each data transmission operation is completed, the backend module checks for the presence of a disconnection flag. This step is the same as step S202 and will not be described again here.

[0162] Further, if no interruption flag is detected, proceed to step S604; if an interruption flag is detected, proceed to step S605.

[0163] Step S604: Set the value of the "No Flow Interruption" flag to the first value;

[0164] Specifically, if no disconnection flag is detected, the backend module sets the value of the disconnection flag to the first value, for example, 1.

[0165] Step S605: Determine whether the number of disconnections exceeds the first threshold;

[0166] Specifically, the backend module determines whether the number of disconnections is greater than the first threshold. For example, it determines whether the number of data disconnections during data transmission operations in steps S601 and S607 is greater than 3.

[0167] Further, if the number of disconnections is greater than the first threshold, proceed to step S606; if the number of disconnections is less than or equal to the first threshold, proceed to step S607.

[0168] In this embodiment, by determining whether the number of interruptions exceeds a first threshold after detecting the interruption flag, this application can take into account extreme cases where data interruptions occur frequently, such as when data interruptions occur during every data transmission operation. In such cases, this application will not perform data transmission in an infinite loop, but will instead report the interruption error to the flash memory algorithm module, which will then process the error, thereby improving the stability and reliability of data transmission and reducing resource waste and performance degradation caused by frequent interruptions.

[0169] Step S606: Determine if the number of transmissions is odd;

[0170] Specifically, if a disconnection flag is detected and the number of disconnections is greater than the first threshold, the backend module determines whether the number of transmissions is odd.

[0171] Alternatively, if no interruption flag is detected, after setting the value of the interruption flag to the first value, the backend module determines whether the number of transmissions is odd.

[0172] In this embodiment, after each data transmission operation is completed, the transmission count is incremented by one. Before each data transmission operation in steps S601 and S607, each piece of data to be written is XORed. When the transmission count is odd, it means that the transmitted data to be written has already undergone RAID XOR operation, that is, the XOR result obtained by the XOR operation has not been canceled. At this time, the data to be written can be written to the ordinary data logic unit of the flash memory medium. When the transmission count is even, it means that the XOR result obtained by the XOR operation has been canceled. At this time, it is necessary to re-XOR each piece of data to be written and then re-perform the data transmission operation.

[0173] Further, if the number of transmissions is odd, proceed to step S608; if the number of transmissions is not odd, i.e., the number of transmissions is even, proceed to step S607.

[0174] Step S607: Increment the value of the number of interruptions by one, set the value of the non-interruption flag to the second value, resend the first programming instruction to the flash memory medium and re-perform the data transmission operation;

[0175] Specifically, if a disconnection flag is detected and the number of disconnections is less than or equal to the first threshold, the backend module increments the number of disconnections by one, sets the value of the non-disconnection flag to the second value, resends the first programming instruction to the flash memory medium, and performs the data transmission operation again.

[0176] For example, if a disconnection flag is detected and the number of disconnections is less than or equal to 3, the backend module increments the number of disconnections by one, sets the value of the non-disconnection flag to 0, resends the first programming instruction to the flash memory medium, and retransmits each piece of data to be written from the corresponding data buffer to the flash memory medium.

[0177] Alternatively, if the number of transmissions is even, the backend module increments the value of the interruption count by one, sets the value of the non-interruption flag to the second value, resends the first programming instruction to the flash memory medium, and performs the data transmission operation again.

[0178] For example, if the number of transmissions is even, the backend module will increment the value of the interruption count by one, set the value of the non-interruption flag to 0, resend the first programming instruction to the flash memory medium, and retransmit each piece of data to be written from the corresponding data buffer to the flash memory medium.

[0179] The first programming instruction includes the 80h command and the physical address of the ordinary data logic unit corresponding to each piece of data to be written. During each data transmission operation, the data writing method further includes: performing an XOR operation on the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and updating the first XOR result stored in the redundant buffer with the second XOR result.

[0180] Step S608: Determine whether the value of the uninterrupted flow marker is the first value;

[0181] Specifically, the backend module determines whether the value of the "not interrupted flow" flag is the first value, for example, whether the value of the "not interrupted flow" flag is 1.

[0182] Further, if the value of the "not interrupted flow" flag is the first value, then proceed to step S609; if the value of the "not interrupted flow" flag is not the first value, that is, the value of the "not interrupted flow" flag is the second value, then proceed to step S610.

[0183] Step S609: Send a second programming instruction to the flash memory medium to write data into the flash memory medium.

[0184] Specifically, if the number of transmissions is odd and the value of the non-disconnection flag is the first value, the backend module sends a second programming instruction to the flash memory medium to write each piece of data to be written into the corresponding ordinary data logic unit. The second programming instruction is the 10h command; upon receiving this instruction, the flash memory medium writes each piece of data to be written into the corresponding ordinary data logic unit.

[0185] In this embodiment of the application, the data writing method further includes: after the data to be written is written to the corresponding ordinary data logic unit, writing the first XOR result stored in the redundant buffer to the verification data logic unit.

[0186] Specifically, after the data to be written is written to the corresponding ordinary data logic unit, the backend module sends a third programming instruction to the flash memory medium. The third programming instruction includes the 80h command and the physical address of the verification data logic unit. Then, the hardware module performs a data transmission operation, transferring the first XOR result from the redundant buffer to the flash memory medium. Then, the backend module sends a second programming instruction to the flash memory medium, which is the 10h command. After receiving the second programming instruction, the flash memory medium writes the first XOR result to the verification data logic unit. At this point, the write operation is complete.

[0187] It is understood that in steps S601 and S607, the data transmission operation only transmits each piece of data to be written, and does not transmit the first XOR result stored in the redundant buffer. When the back-end module sends the second programming instruction to the flash memory medium, the first XOR result stored in the redundant buffer is the verification data that needs to be written to the flash memory medium.

[0188] Step S610: Determine that a flow interruption error has occurred.

[0189] Specifically, if the number of transmissions is odd and the value of the non-disconnection flag is the second value, the backend module determines that a disconnection error has occurred and reports the disconnection error to the flash algorithm module, which then performs a rollback operation or garbage collection operation.

[0190] In some embodiments, the backend module reports a flow interruption error to the flash memory algorithm module by reporting an error code.

[0191] In some embodiments, the flash memory algorithm module performs a rollback operation, including: the flash memory algorithm module sending a rollback command to the backend module; upon receiving the rollback command, the backend module instructs the hardware module to perform an XOR operation on each piece of data to be written and the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and then updates the first XOR result stored in the redundant buffer with the second XOR result, thereby canceling out the result of the XOR operation. The rollback command is used to instruct the backend module to perform the XOR operation again.

[0192] In some embodiments, the flash memory algorithm module performs garbage collection operations, including: performing garbage collection on the stripe where the data to be written is located, and moving each piece of data to be written to other free physical blocks.

[0193] Striping is a data organization method where data is divided into small blocks, which are then written to different physical locations on the flash memory medium, forming a stripe. The stripe containing the data to be written includes each piece of data to be written. Garbage collection (GC) refers to moving data to new physical blocks, thereby freeing up the original storage space.

[0194] In some embodiments, the flash memory algorithm module selects the remaining dies to re-execute steps S601-S610. The flash memory algorithm module may use other methods to handle the interruption error, which are not limited in the embodiments of this application.

[0195] In this embodiment, after each data transmission operation is completed, if a disconnection flag is detected, and the number of disconnections is less than or equal to a first threshold, or if the number of disconnections is greater than the first threshold and the number of transmissions is even, a first programming instruction is resent to the flash memory medium, and the data transmission operation is restarted. This continues until no disconnection flag is detected after any data transmission operation is completed, and the number of transmissions is odd. In this case, a second programming instruction is sent to the flash memory medium to write the data to the flash memory medium. On the one hand, compared to existing solutions that can only recover data after a write error caused by a data disconnection, this application, through a reasonable disconnection detection and retry mechanism, can handle data disconnection during the writing process, rather than recovering data after a write error caused by a data disconnection. This can improve the integrity and reliability of data during the writing process.

[0196] On the other hand, compared to existing solutions for flash memory devices using RAID technology, when data interruption occurs in multiple dies, it exceeds the recovery capability of RAID technology and can easily lead to permanent data loss. This application, for flash memory devices using RAID technology, can handle data interruption by re-transmitting data during the write process when data interruption occurs in one or more dies. This can reduce data write errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of flash memory devices.

[0197] In some embodiments, flash memory devices employing RAID technology still have a verification function, which can recover data damaged due to a data interruption. For example, when reading data in a certain ordinary data logic unit, if an uncorrectable error occurs, the erroneous data in the ordinary data logic unit can be recovered by performing an XOR operation between the data in other ordinary data logic units and the verification data in the verification data logic unit.

[0198] Please see Figure 8 , Figure 8 This is a detailed flowchart illustrating the third data writing method provided in the embodiments of this application;

[0199] In this application embodiment, the third data writing method is applied to any flash memory device, that is, the third data writing method can be applied to flash memory devices without RAID data protection function or to flash memory devices with RAID data protection function.

[0200] like Figure 8 As shown, the detailed process of the third data writing method includes:

[0201] Step S801: Obtain the write command, send the first programming instruction to the flash memory medium based on the write command, and perform data transmission operation;

[0202] Specifically, for flash memory devices without RAID data protection, this step is the same as step S501, and will not be repeated here; for flash memory devices with RAID data protection, this step is the same as step S601, and will not be repeated here.

[0203] Step S802: Confirm that the data transmission operation is complete;

[0204] Step S803: Send a second programming instruction to the flash memory medium to write data into the flash memory medium;

[0205] Specifically, after the backend module sends the first programming instruction to the flash memory medium, the hardware module performs data transfer operations. Then, the backend module sends a second programming instruction to the flash memory medium to write the data into the flash memory medium. The first programming instruction includes an 80h command and the physical address corresponding to the data, and the second programming instruction is a 10h command.

[0206] Step S804: Read the data;

[0207] Specifically, after the write operation is completed, the backend module sends a read command to the flash memory to read the data that was just written from the flash memory.

[0208] Furthermore, after reading the data, the backend module performs error checking based on the error correction code to obtain the number of error bits. The error correction code (ECC) is a technique used to detect and correct errors in data transmission or storage. The error bit count is the number of error bits in the data read after a single data read operation. For example, the error bit count is the number of error bits in the data read after completing a 4KB data read operation.

[0209] When data is written to flash memory, the ECC algorithm generates a checksum and stores it in an out-of-band (OOB) area or a specific ECC memory area. Read operations not only read the data but also the corresponding error checksum. After reading the data, the same ECC algorithm is used to recalculate the error checksum, resulting in a new error checksum. By analyzing the bits of the error checksum, the number of error bits can be determined. For example, when the error correction code is Hamming code, the difference between the received error checksum and the recalculated error checksum can be used to determine the Hamming weight, which refers to the number of error bits.

[0210] Step S805: Determine whether an uncorrectable error has occurred or whether the number of error bits is greater than the second threshold;

[0211] Specifically, the backend module determines whether an uncorrectable error has occurred based on the error check code: it compares the newly calculated error check code with the received error check code. If the two error check codes are the same, it means that the data is not corrupted and it is determined that no uncorrectable error has occurred; if the two error check codes are different, it can be determined whether the error is correctable or uncorrectable according to the rules of the ECC algorithm.

[0212] Correctable errors refer to errors whose patterns can be fixed by the ECC algorithm, such as a single bit error. Uncorrectable errors refer to errors whose patterns exceed the repair capabilities of the ECC algorithm, such as multiple bit errors.

[0213] The second threshold can be set by those skilled in the art based on the actual decoder used, and is not limited in this embodiment. For example, when the amount of data read in a single read operation is 4KB, the second threshold is 200 bits.

[0214] Furthermore, if an uncorrectable error occurs during the reading process, or if the number of error bits is greater than the second threshold, then proceed to step S806; if no uncorrectable error occurs during the reading process, and the number of error bits is less than or equal to the second threshold, then proceed to step S807.

[0215] Step S806: Determine that this write operation has failed;

[0216] Specifically, if an uncorrectable error occurs during the read process, or if the number of error bits exceeds the second threshold, the backend module determines that the write operation has failed. The backend module reports the write operation failure to the flash memory algorithm module, which then handles the issue.

[0217] In some embodiments, when the flash memory device is a flash memory device with RAID data protection function, the flash memory device further includes a cache space and a redundancy buffer. The cache space includes at least two data buffers, and the flash memory medium includes at least two ordinary data logic units and one parity data logic unit. Each ordinary data logic unit corresponds to one data buffer, and the parity data logic unit corresponds to the redundancy buffer.

[0218] In step S801, the front-end module divides the data contained in the write command to obtain at least two data to be written, and stores each data to be written into the corresponding data buffer; the flash memory algorithm module sends the first programming instruction to the flash memory medium; the hardware module performs data transmission operation, transferring each data to be written from the corresponding data buffer to the flash memory medium.

[0219] When performing data transfer operations on the data to be written in the first data buffer, the hardware module performs an XOR operation on the data to be written and stores the first XOR result in the redundant buffer. When performing data transfer operations on the data to be written in the remaining data buffers, the hardware module performs an XOR operation on the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer, and updates the first XOR result stored in the redundant buffer with the second XOR result obtained. This process continues until the last data to be written in the data buffer that is being transmitted is XORed with the first XOR result currently stored in the redundant buffer, and the first XOR result stored in the redundant buffer is updated.

[0220] The data writing method further includes: after determining that the write operation has failed, performing an XOR operation on the data and the first XOR result stored in the redundant buffer to obtain a third XOR result, and updating the first XOR result stored in the redundant buffer with the third XOR result. The data includes first data to be written, which is the data to be written in the data buffer corresponding to a certain ordinary data logic unit that encountered an error during the read operation.

[0221] Specifically, the flash memory algorithm module sends a rollback command to the backend module. Upon receiving the rollback command, the backend module instructs the hardware module to perform an XOR operation between the first XOR result stored in the redundant buffer and the first data to be written, obtaining a third XOR result. The third XOR result is then assigned to the first XOR result to update the first XOR result stored in the redundant buffer. The rollback command instructs the backend module to perform an XOR operation between the first XOR result and the first data to be written. The third XOR result is the XOR result obtained by performing an XOR operation between the first XOR result stored in the redundant buffer and the first data to be written in the third data writing method.

[0222] By performing an XOR operation between the first XOR result stored in the redundant buffer and the first data to be written, the XOR operation (or modulo-2 addition) performed on the first data to be written in the redundant buffer can be canceled out. This allows the redundant buffer to verify errors in other ordinary data logic units in the stripe, thus ensuring that the stripe containing the first data to be written still has a verification function.

[0223] In some embodiments, the data writing method further includes: re-performing the write operation to write the data to the flash memory medium, wherein the data is stored in different locations on the flash memory medium during the two write operations.

[0224] For example, a flash memory device writes the first piece of data to be written to other free ordinary data logic units or other free physical blocks within the same ordinary data logic unit.

[0225] Step S807: Confirm completion of this write operation;

[0226] If no uncorrectable errors occur during the read process, and the number of error bits is less than or equal to the second threshold, the backend module determines that the write operation is complete.

[0227] In this embodiment, after sending a first programming instruction to the flash memory medium and performing a data transmission operation, a second programming instruction is sent to the flash memory medium to write data to the flash memory medium. Then, data is read from the flash memory medium. If no uncorrectable error occurs during the reading process and the number of error bits is less than or equal to a second threshold, the write operation is determined to be completed. If an uncorrectable error occurs during the reading process, or if the number of error bits is greater than the second threshold, the write operation is determined to have failed. This application can immediately determine whether a data writing error caused by data interruption has occurred after the write operation is completed, thereby handling the write operation failure immediately.

[0228] In the embodiments of this application, the three data writing methods described above can be applied to flash memory devices without a superblock management concept, such as flash drives or flash memory cards (T cards), and can also be applied to flash memory devices with a superblock management concept.

[0229] Please see Figure 9 , Figure 9 This is a schematic diagram of a superblock provided in an embodiment of this application;

[0230] like Figure 9 As shown, a superblock consists of multiple physical blocks, each located in a different data logical unit (Die). Each physical block consists of multiple physical pages; for example, physical block A consists of physical page 0, physical page 1, ..., physical page P, ..., physical page M.

[0231] When performing a write operation, data can be written to these data logic units simultaneously. When performing a read operation, data can be read from different data logic units simultaneously, thereby accelerating read and write performance.

[0232] In this embodiment, each superblock contains physical blocks that must be in different data logic units, and the physical block numbers can be different. For example, physical block 2 in data logic unit 0, physical block 3 in data logic unit 1, and physical block 4 in data logic unit 2 can all belong to the same superblock.

[0233] For flash memory devices using RAID technology Figure 9 The data logic unit n in the code can be a verification data logic unit. Only one data logic unit is allowed to have an uncorrectable error during a read operation.

[0234] For flash memory devices with a superblock management concept, if the backend module determines in step S806 that the write operation has failed, the flash memory device can write the first data to be written to another free superblock or another free superpage in the same superblock.

[0235] In this embodiment, a data writing method is provided, which is applied to a flash memory device including a flash memory medium. The data writing method includes: obtaining a write command; sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether a disconnection flag exists, wherein the disconnection flag is used to indicate that a data disconnection occurred during the data transmission operation; when a disconnection flag is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until no disconnection flag is detected after any data transmission operation is completed, and then sending a second programming instruction to the flash memory medium to write data into the flash memory medium; wherein the first programming instruction includes data address information, and the second programming instruction is used to instruct the flash memory medium to write data.

[0236] By resending the first programming instruction to the flash memory medium and re-performing the data transmission operation when a data interruption flag is detected, and then sending the second programming instruction to the flash memory medium to write data after any data transmission operation is completed without a data interruption flag, this application can reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of flash memory devices.

[0237] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0238] like Figure 10 As shown, the storage control chip 1000 includes one or more processors 1001 and a memory 1002. Wherein, Figure 10 Take processor 1001 as an example.

[0239] Processor 1001 and memory 1002 can be connected via a bus or other means. Figure 10 Taking the example of a connection between China and Israel via a bus.

[0240] Processor 1001 provides computing and control capabilities to control flash memory device 1100 to perform corresponding tasks, such as controlling flash memory device 1100 to perform a data writing method in any of the above method embodiments. This data writing method is applied to the flash memory device, which includes a flash memory medium. The data writing method includes: acquiring a write command; sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether a data interruption flag exists, wherein the data interruption flag indicates that a data interruption occurred during the data transmission operation; when a data interruption flag is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until no data interruption flag is detected after any data transmission operation, and then sending a second programming instruction to the flash memory medium to write data into the flash memory medium; wherein the first programming instruction includes data address information, and the second programming instruction instructs the flash memory medium to write data.

[0241] By resending the first programming instruction to the flash memory medium and re-performing the data transmission operation when a data interruption flag is detected, and then sending the second programming instruction to the flash memory medium to write data after any data transmission operation is completed without a data interruption flag, this application can reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of flash memory devices.

[0242] Processor 1001 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0243] The memory 1002, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the data writing method in the embodiments of this application. The processor 1001 can implement the data writing method in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in the memory 1002. Specifically, the memory 1002 may include volatile memory (VM), such as random access memory (RAM); the memory 1002 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; the memory 1002 may also include combinations of the above types of memory.

[0244] Memory 1002 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 1002 may optionally include memory remotely located relative to processor 1001, and these remote memories may be connected to processor 1001 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0245] One or more modules are stored in memory 1002. When executed by one or more processors 1001, they perform the data writing method in any of the above method embodiments, for example, the method described above. Figure 2 The steps shown.

[0246] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0247] like Figure 11 As shown, the flash memory device 1100 includes a storage control chip 1000 and at least one flash memory medium 1101. Figure 11 Taking a flash memory medium 1101 as an example, the storage controller chip 1000 and the flash memory medium 1101 are connected in communication.

[0248] The storage control chip 1000 is used to execute the data writing method in any of the above embodiments. The data writing method includes: obtaining a write command; sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether a disconnection flag exists, wherein the disconnection flag is used to indicate that a data disconnection occurred during the data transmission operation; when the disconnection flag is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until no disconnection flag is detected after any data transmission operation is completed, and then sending a second programming instruction to the flash memory medium to write data into the flash memory medium; wherein the first programming instruction includes data address information, and the second programming instruction is used to instruct the flash memory medium to write data.

[0249] At least one flash memory medium 1101 is communicatively connected to the storage control chip 1000 for storing data.

[0250] By including a storage controller chip and at least one flash memory medium in the flash memory device, the storage controller chip is used to execute the data writing method in any of the above embodiments, and the flash memory medium is used to store data. This application can reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of the flash memory device.

[0251] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the data writing method in any of the above method embodiments, such as executing the data writing method in any of the above method embodiments, or executing the steps described above.

[0252] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0253] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0254] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data writing method, characterized in that, The method is applied to a flash memory device, the flash memory device including a flash memory medium, a cache space, and a redundant buffer, the cache space including at least two data buffers; the method includes: Obtain a write command, send a first programming instruction to the flash memory medium based on the write command, and perform data transmission operation; After each data transmission operation is completed, a disconnection flag is detected, wherein the disconnection flag is used to indicate that a data interruption occurred during the data transmission operation; When the interruption flag is detected, the first programming instruction is resent to the flash memory medium and the data transmission operation is performed again until the interruption flag is not detected after any data transmission operation is completed. Then, the second programming instruction is sent to the flash memory medium to write the data to the flash memory medium. Wherein, the first programming instruction includes the address information of the data, and the second programming instruction is used to instruct the flash memory medium to write the data; The step of sending a first programming instruction to the flash memory medium based on the write command and performing data transmission operations includes: The data contained in the write command is split to obtain at least two data to be written; each data to be written is stored in the corresponding data buffer; a first programming instruction is sent to the flash memory medium; and a data transfer operation is performed to transfer each data to be written from the corresponding data buffer to the flash memory medium. The method further includes: When performing data transmission operation on the data to be written in the first data buffer, the data to be written is XORed to obtain a first XOR result, and the first XOR result is stored in the redundant buffer, wherein the first data buffer is the first data buffer to be transmitted. When performing data transmission operations on the remaining data buffers, the currently transmitted data to be written is XORed with the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and the first XOR result stored in the redundant buffer is updated with the second XOR result.

2. The method according to claim 1, characterized in that, The data transmission operation is used to transmit the data to the flash memory medium, and the flash memory device further includes a back-end module, a hardware module, and registers; The detection of whether a flow interruption marker exists includes: Based on the hardware module, determine whether a data interruption occurs during the data transmission operation; If a data interruption occurs during the data transmission operation, the value of the register is set to the first value. Based on the backend module, query the value of the register; When the value retrieved by the backend module is the first value, it is determined that the disconnection flag has been detected; When the value retrieved by the backend module is the second value, it is determined that the disconnection flag has not been detected.

3. The method according to claim 1, characterized in that, The method further includes: After each data transmission operation is completed, if the interruption flag is detected and the number of interruptions is less than or equal to the first threshold, the number of interruptions is incremented by one, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again. After each data transmission operation is completed, if the interruption flag is detected and the number of interruptions is greater than the first threshold, an interruption error is determined to have occurred, and the interruption error is processed. After each data transmission operation is completed, if the interruption flag is not detected, a second programming instruction is sent to the flash memory medium to write the data into the flash memory medium.

4. The method according to claim 1, characterized in that, The method further includes: Set the values ​​of disconnection count, transmission count, and non-disconnection flag to the second value; After each data transmission operation is completed, the transmission count is incremented by one, and a disconnection flag is checked. If the interruption flag is detected and the number of interruptions is less than or equal to the first threshold, then the number of interruptions is incremented by one, the value of the non-interruption flag is set to the second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again. If the interruption flag is detected and the number of interruptions is greater than the first threshold, then it is determined whether the number of transmissions is odd. If the interruption flag is not detected, the value of the non-interruption flag is set to the first value, and it is determined whether the number of transmissions is odd.

5. The method according to claim 4, characterized in that, The method further includes: If the number of transmissions is odd and the value of the non-disconnection flag is the second value, then a disconnection error is determined, and a rollback operation or garbage collection operation is performed. If the number of transmissions is even, then the value of the number of interruptions is incremented by one, the value of the non-interruption flag is set to a second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again. Specifically, during each data transmission operation, the data to be written currently being transmitted is XORed with the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and the first XOR result stored in the redundant buffer is updated with the second XOR result.

6. The method according to claim 4, characterized in that, The flash memory medium includes at least two ordinary data logic units and one verification data logic unit, wherein each ordinary data logic unit corresponds to one of the data buffers, and the verification data logic unit corresponds to the redundant buffer. The method further includes: If the number of transmissions is odd and the value of the uninterrupted flow marker is a first value, then a second programming instruction is sent to the flash memory medium to write each piece of data to be written into the corresponding ordinary data logic unit. After the data to be written is written to the corresponding ordinary data logic unit, the first XOR result stored in the redundant buffer is written to the verification data logic unit.

7. The method according to claim 1, characterized in that, The method further includes: After sending a first programming instruction to the flash memory medium and performing a data transmission operation, a second programming instruction is sent to the flash memory medium to write data into the flash memory medium. The data is read from the flash memory medium, and error verification is performed based on the error check code to obtain the number of error bits; If no uncorrectable errors occur during the read process, and the number of error bits is less than or equal to the second threshold, then the write operation is considered complete. If an uncorrectable error occurs during the read process, or if the number of error bits exceeds the second threshold, the write operation is determined to have failed.

8. The method according to claim 7, characterized in that, The method further includes: After determining that the write operation has failed, the data is XORed with the first XOR result stored in the redundant buffer to obtain a third XOR result, and the first XOR result stored in the redundant buffer is updated with the third XOR result. The write operation is re-executed to write the data to the flash memory medium, wherein the data is stored in different locations on the flash memory medium during the two write operations.

9. A storage control chip, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the data writing method as described in any one of claims 1-8.

10. A flash memory device, characterized in that, include: The storage control chip as described in claim 9; At least one flash memory medium is communicatively connected to the storage control chip.

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