FPGA module-based ac108 audio chip control system and method

Abstract

The application discloses an AC108 audio chip control system and method based on an FPGA module, and comprises a clock and reset management module, an I2S / PCM drive control module, a register configuration module and a FIFO module, wherein the clock and reset management module is used for generating a stable clock signal and synchronizing a reset signal; the I2S / PCM drive control module is responsible for controlling a hardware reset signal of a chip and managing transmission and counting of audio data; the register configuration module is responsible for reading register data from a ROM and sending the register data to the I2S / PCM drive control module; the FIFO module is used for temporarily storing register configuration data; and the I2S / PCM protocol bottom layer drive is used for processing audio data and generating an effective signal. The system provides accurate clock and reset management, flexible register configuration capability and a function of supporting 4-channel data acquisition and analysis. Through self-defined parameter configuration and a soft reset function, the application significantly improves portability and applicability of a drive program, and meets efficient control and optimization requirements of the AC108 chip on an FPGA platform.

Description

Technical Field

[0001] This invention relates to the field of audio signal processing technology, and in particular to an AC108 audio chip control system and method based on an FPGA module. Background Technology

[0002] The existing AC108 chip is a highly integrated four-channel ADC that supports I2S / TDM output conversion and is widely used in intelligent voice assistants, recording equipment, digital cameras, camcorders, and voice conferencing systems. However, current drivers designed for the AC108 chip are typically developed in C and rely on the Advanced Linux Sound Architecture (ALSA) for function control. Although the ALSA architecture provides rich audio processing capabilities, its complexity and size make it difficult for drivers to run efficiently on embedded systems and resource-constrained platforms.

[0003] Furthermore, existing drivers suffer from poor portability, especially on specific hardware platforms such as FPGAs. Adapting drivers to different architectures requires significant time and effort. Due to the high level of encapsulation of ALSA, users face difficulties in further customizing and optimizing the underlying hardware for specific application requirements, limiting the flexibility and applicability of the drivers. Additionally, existing drivers may not fully meet stringent latency requirements when handling real-time audio applications, impacting audio data processing quality and system stability. These factors restrict the widespread application and performance optimization of the AC108 chip on FPGA platforms. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an AC108 audio chip control system and method based on an FPGA module.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows:

[0006] An AC108 audio chip control system based on an FPGA module includes the following modules:

[0007] Clock and Reset Management Module: This module generates a stable clock signal, locks the board-level crystal oscillator signal via a phase-locked loop (PLL), and obtains the required TWI protocol clock, AC108 chip operating clock, and system clock frequency. It also generates the corresponding reset signal to ensure the system operates synchronously within the same clock domain, reducing metastability.

[0008] The I2S / PCM driver control module controls the hardware reset signal RSTn of the AC108 chip and manages the transmission and parsing of audio data. It is responsible for counting audio sample points, receiving user-sent sample signals, initiating the sampling process, and sending configuration commands to the AC108 chip according to the TWI protocol.

[0009] Register configuration module: It is responsible for reading register data from ROM and temporarily storing it in FIFO, and then sending information such as operation address, operation length and read / write direction to I2S / PCM driver control module to complete the register configuration.

[0010] FIFO module: Used to temporarily store register configuration data read from ROM, ensuring correct data order and timing when transmitted to the I2S / PCM driver control module.

[0011] The I2S / PCM protocol underlying driver parses 4-channel audio data according to the configured audio mode through frame alignment clock, bit alignment clock and data lines, performs serial-to-parallel conversion, and generates corresponding valid signals to indicate that the data is valid.

[0012] This invention also discloses a control method based on the above-mentioned AC108 audio chip control system, comprising the following steps:

[0013] Step S1: After power-on, the board-level crystal oscillator signal is phase-locked through a phase-locked loop (PLL) to generate a stable clock signal.

[0014] By multiplying and dividing the frequency, the TWI protocol clock signal, the AC108 chip operating clock, and the main frequency suitable for the system are obtained.

[0015] Each clock signal independently generates a corresponding reset signal, ensuring that the clock and reset signal are synchronized within the same clock domain, thus reducing the occurrence of metastability.

[0016] Step S2: The I2S / PCM drive control module pulls the reset signal RSTn of the AC108 chip low to ensure that all registers in the chip are restored to their initial state.

[0017] The reset signal is held for 20ms, then released, and then waits for another 20ms to ensure that the chip enters a stable working state and is ready to receive the user's sampling signal.

[0018] Step S3: The user sends a sampling trigger signal. After the register configuration module detects the rising edge of the signal, it starts to read the register data from the ROM in sequence and temporarily stores it in the FIFO module of the I2S / PCM driver control module.

[0019] Step S4: After the register data stored in the FIFO is ready, the register configuration module sends the operation address, length, and read / write direction to the I2S / PCM driver control module according to the timing.

[0020] The configuration process is as follows: First, configure the initialization information, and then supplement the parameter information after an interval of 50ms to ensure that the configuration process is successful.

[0021] Step S5: The I2S / PCM driver control module parses the operation information sent in step S3 and sends configuration commands to the AC108 chip via the TWI protocol.

[0022] Step S6: After the register configuration is completed, the I2S / PCM protocol underlying driver parses the 4-channel audio data received through the frame alignment clock, bit alignment clock and data line according to the configured audio mode, performs serial-to-parallel conversion and counts the audio sampling points.

[0023] Generate a corresponding valid signal on each channel to indicate that the data is valid.

[0024] Step S7: Send a soft reset command to restore the AC108 chip's registers to their initial state to stop the sampling process.

[0025] Furthermore, the configuration process includes two phases:

[0026] Configuration phase 1 includes: power supply configuration, clock configuration, enable / reset configuration, frame alignment clock configuration, bit alignment clock configuration, I2S encoding configuration, sampling depth configuration, sampling order configuration, gain configuration, and analog channel configuration.

[0027] Configuration phase 2 includes: power supply configuration and sampling rate configuration.

[0028] Furthermore, the specific process of the soft reset command is as follows:

[0029] The transmit operation address is 0x30, the operation data is 0x10, and the corresponding register name is I2S_CTRL. Its function is to disable the frame alignment clock, bit alignment clock, and data lines.

[0030] The transmit operation address is 0x00, the operation data is 0x12, and the corresponding register name is CHIP_AU DIO_RST. Its function is to restore all registers to their initial values.

[0031] Compared with the prior art, the advantages of the present invention are as follows:

[0032] 1. High portability and applicability: Developed using the Verilog language, it can be easily deployed on FPGA platforms, offering higher portability and wider applicability compared to existing drivers that rely on ALSA.

[0033] 2. Precise clock and reset management: A stable clock signal is generated using phase-locked loop (PLL) technology, and the clock and reset signals are synchronized within the same clock domain, reducing metastability and ensuring system stability.

[0034] 3. Flexible register configuration: It provides two configuration stages, which can precisely control and adjust system parameters to ensure that all functions of the AC108 chip can be correctly configured and initialized, thereby improving the flexibility and reliability of the system.

[0035] 4. Multi-channel data acquisition capability: The system supports 4-channel data acquisition and parsing, which can meet the needs of multi-channel audio signal processing and is suitable for various application scenarios such as intelligent voice assistants, recorders, and cameras.

[0036] 5. Customizable parameter configuration and control: Allows users to customize sampling parameters and control the sampling process through a soft reset function, providing greater control flexibility and ease of system operation. Attached Figure Description

[0037] Figure 1 This is a structural block diagram of the FPGA driver module in an embodiment of the present invention.

[0038] Figure 2 This is a flowchart of the FPGA driver module in an embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of the four-channel data collected in the test mode according to an embodiment of the present invention.

[0040] Figure 4 This is a schematic diagram of data 5A5A collected from one channel in test mode according to an embodiment of the present invention.

[0041] Figure 5 The waveforms of frame alignment, bit alignment clock, and data lines observed using an oscilloscope in the test mode of this embodiment of the invention are shown.

[0042] Figure 6 This is a graph showing the 0.5V voltage value collected in the actual working mode of this embodiment of the invention.

[0043] Figure 7 This is a graph of 1V voltage values ​​collected in actual working mode according to an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0045] like Figure 1 and 2 As shown, this invention provides a control method for an AC108 audio chip based on an FPGA module, comprising the following steps:

[0046] Step S1: When the device is powered on, the clock and reset management module locks the board-level crystal oscillator signal through a phase-locked loop to obtain a more stable clock signal. It obtains a 400KHz TWI protocol clock signal, a 24.576MHz AC108 chip operating clock, and a system main frequency of arbitrary frequency through frequency multiplication and division. Each clock generates a corresponding reset signal separately to ensure that the clock and reset signal are in the same clock domain and reduce metastability.

[0047] Step S2: The I2S / PCM driver control module pulls the AC108 hardware reset signal (RSTn) low to ensure that all registers in the AC108 chip are restored to their initial state. This reset signal lasts for 20ms. After canceling the reset signal, wait for another 20ms to ensure that the chip is working stably. Then, it enters the normal working state and waits for the start sampling signal sent by the user.

[0048] Step S3: The user sends a sampling signal. After the register configuration module detects the rising edge of the sampling signal, it reads the register data stored in the ROM in sequence and sends it to the FIFO module in the I2S / PCM driver control module for temporary storage.

[0049] Step S4: After the register data in the ROM is successfully temporarily stored in the FIFO, the register configuration module sends information such as the operation address, operation length, and read / write direction to the I2S / PCM driver control module according to the timing sequence. The entire configuration phase is divided into two parts: first, initialization information is configured with a 50ms interval, and then configuration parameter information is supplemented to ensure successful configuration.

[0050] Step S5: The I2S / PCM drive control module parses the operation information issued in step S3 and sends configuration commands to the AC108 chip via the bus according to the TWI protocol.

[0051] Step S6: After the register configuration is completed, the I2S / PCM protocol underlying driver parses the 4-channel data according to the configured audio mode through frame alignment clock, bit alignment clock and data line, performs serial-to-parallel conversion, and generates a corresponding valid signal on each channel to indicate that the data is valid.

[0052] Step S7: Send a soft reset instruction to restore the AC108 register to stop sampling.

[0053] The constant acquisition function was tested. A Xilinx XC7S50FGGA484-1 chip was used as the experimental platform. The AC108 chip's built-in debug function was used. The test data was 5A5A, 96kHz sampling rate, 4-channel transmission, 16-bit slot depth, 16-bit data width, PCM TDM mode. LRCK changed on the falling edge of BCLK, and the data became valid on the second rising edge of BCLK after LRCK. The data was changed on the falling edge of BCLK and read on the rising edge. The results were as follows: Figure 3 , Figure 4 Figure 5 The results show that the driver correctly sampled to 5A5A.

[0054] like Figure 3 As shown, the 4 channels of data and their corresponding valid signals are:

[0055] In test mode, four channels of audio data were acquired, and corresponding valid signals were generated. This demonstrates that the driver can correctly acquire and process multi-channel data.

[0056] like Figure 4 As shown, the acquired single-channel data is "5A5A:".

[0057] The driver successfully acquired 5A5A data in test mode, verifying the correctness of data transmission and parsing. The sampling rate was 96kHz, the data bit width was 16bit, and PCM TDM mode was used.

[0058] like Figure 5 As shown, the waveforms of the frame alignment, bit alignment clock, and data lines are:

[0059] The waveforms observed using an oscilloscope show the timing relationship between the frame alignment clock (LRCK), bit alignment clock (BCLK), and data lines during transmission. This result verifies the synchronization and correctness of the clock signal and data line signals.

[0060] Test results under actual working conditions

[0061] like Figure 6 The data collected for a 0.5V voltage is shown below:

[0062] In actual operating mode, a 0.5V DC signal was output from a signal generator and connected to the analog input of the AC108 chip. The driver successfully acquired the data and obtained the hexadecimal value 1E8F (decimal 7823). The actual measured value was 0.501V, which, compared with the reference voltage of 2.1V, indicates that the sampling result is accurate.

[0063] like Figure 7 The data collected for 1V voltage is shown below:

[0064] Similarly, in actual operating mode, when outputting a 1V DC signal, the acquired data is a hexadecimal value of 3717 (decimal 14103). The actual measured value is 0.903V. Although there is a certain deviation from the expected value of 1V, it is still within the acceptable range, indicating that the driver's acquisition function is effective.

[0065] In another embodiment of the present invention, an AC108 audio chip control system based on an FPGA module is provided. This system can be used to implement the above-described AC108 audio chip control method based on an FPGA module, specifically including:

[0066] Clock and Reset Management Module: This module generates a stable clock signal, locks the board-level crystal oscillator signal via a phase-locked loop (PLL), and obtains the required TWI protocol clock, AC108 chip operating clock, and system clock frequency. It also generates the corresponding reset signal to ensure the system operates synchronously within the same clock domain, reducing metastability.

[0067] The I2S / PCM driver control module controls the hardware reset signal RSTn of the AC108 chip and manages the transmission and parsing of audio data. It is responsible for counting audio sample points, receiving user-sent sample signals, initiating the sampling process, and sending configuration commands to the AC108 chip according to the TWI protocol.

[0068] Register configuration module: It is responsible for reading register data from ROM and temporarily storing it in FIFO, and then sending information such as operation address, operation length and read / write direction to I2S / PCM driver control module to complete the register configuration.

[0069] FIFO module: Used to temporarily store register configuration data read from ROM, ensuring correct data order and timing when transmitted to the I2S / PCM driver control module.

[0070] The I2S / PCM protocol underlying driver parses 4-channel audio data according to the configured audio mode through frame alignment clock, bit alignment clock and data lines, performs serial-to-parallel conversion, and generates corresponding valid signals to indicate that the data is valid.

[0071] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0072] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0073] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0074] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0075] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the implementation methods of the present invention, and should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of the present invention.

Claims

1. A control system for an AC108 audio chip based on an FPGA module, characterized in that, Includes the following modules: Clock and Reset Management Module: This module generates a stable clock signal, locks the board-level crystal oscillator signal through a phase-locked loop (PLL), and obtains the required TWI protocol clock, AC108 chip operating clock, and system main frequency. It is also responsible for generating the corresponding reset signal to ensure that the system operates synchronously within the same clock domain and to reduce metastability. I2S / PCM driver control module: controls the hardware reset signal RSTn of AC108 chip and manages the transmission and parsing of audio data; responsible for counting audio sampling points, controlling the reception of sampling signals sent by users, starting the sampling process, and sending configuration instructions to AC108 chip according to TWI protocol; Register configuration module: responsible for reading register data from ROM and temporarily storing it in FIFO, and then sending information such as operation address, operation length and read / write direction to I2S / PCM driver control module to complete the register configuration; FIFO module: Used to temporarily store register configuration data read from ROM to ensure correct data order and timing when transmitted to the I2S / PCM driver control module; The I2S / PCM protocol underlying driver parses 4-channel audio data according to the configured audio mode through frame alignment clock, bit alignment clock and data lines, performs serial-to-parallel conversion, and generates corresponding valid signals to indicate that the data is valid.

2. A control method based on the AC108 audio chip control system according to claim 1, characterized in that, Includes the following steps: Step S1: After power-on, the board-level crystal oscillator signal is phase-locked through a phase-locked loop (PLL) to generate a stable clock signal; By multiplying and dividing the frequency, the TWI protocol clock signal, the AC108 chip operating clock, and the main frequency suitable for the system are obtained. Each clock signal independently generates a corresponding reset signal, ensuring that the clock and reset signal are synchronized within the same clock domain, thus reducing the occurrence of metastability. Step S2: The I2S / PCM driver control module pulls the reset signal RSTn of the AC108 chip low to ensure that all registers in the chip are restored to their initial state; The reset signal is held for 20ms, then released, and then waits for another 20ms to ensure that the chip enters a stable working state and is ready to receive the user's sampling signal. Step S3: The user sends a sampling trigger signal. After the register configuration module detects the rising edge of the signal, it starts to read the register data from the ROM in sequence and temporarily stores it in the FIFO module of the I2S / PCM driver control module. Step S4: After the register data stored in the FIFO is ready, the register configuration module sends the operation address, length, and read / write direction to the I2S / PCM driver control module according to the timing. The configuration process is as follows: First, configure the initialization information, and then supplement the parameter information after an interval of 50ms to ensure that the configuration process is successful; Step S5: The I2S / PCM drive control module parses the operation information sent in step S3 and sends configuration commands to the AC108 chip via the TWI protocol; Step S6: After the register configuration is completed, the I2S / PCM protocol underlying driver parses the 4-channel audio data received through the frame-aligned clock, bit-aligned clock, and data line according to the configured audio mode, and performs serial-to-parallel conversion. Generate a corresponding valid signal on each channel to indicate that the data is valid; Step S7: Send a soft reset command to restore the AC108 chip's registers to their initial state to stop the sampling process.

3. The control method according to claim 2, characterized in that: The configuration process includes two phases: Configuration phase 1 includes: power supply configuration, clock configuration, enable / reset configuration, frame alignment clock configuration, bit alignment clock configuration, I2S encoding configuration, sampling depth configuration, sampling order configuration, gain configuration, and analog channel configuration. Configuration phase 2 includes: power supply configuration and sampling rate configuration.

4. The control method according to claim 2, characterized in that: The specific process of the soft reset command is as follows: The transmit operation address is 0x30, the operation data is 0x10, and the corresponding register name is I2S_CTRL; its function is to disable the frame alignment clock, bit alignment clock, and data lines. The send operation address is 0x00, the operation data is 0x12, and the corresponding register name is CHIP_AUDIO_RST; its function is to restore all registers to their initial values.

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