Multiplier, convolution circuit, calculation method, chip and electronic equipment

Abstract

The embodiment of the invention provides a multiplier, a convolution circuit, a calculation method, a chip and electronic equipment, is applied to the technical field of chips, and aims to solve the problem of power consumption waste caused by quantization after convolution calculation through the convolution circuit. The convolution circuit comprises a plurality of multipliers; and an adder coupled with the plurality of multipliers. Wherein the multiplier comprises a plurality of precoders and a plurality of encoder groups. Wherein the precoders and the encoder groups are in one-to-one correspondence, and part of the encoders in the encoder groups are provided with control circuits and corresponding control lines. During operation, the output of the corresponding encoder can be controlled by inputting the set control signal into the control line of each multiplier, so that the power consumption of the encoder is static power consumption or dynamic power consumption, and the power consumption of the multiplier can be better controlled according to actual requirements.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a multiplier, a convolution circuit, a calculation method, a chip and an electronic device. Background Art

[0002] With the development of artificial intelligence (AI) technology, more and more AI products are entering people's daily lives. In the implementation process of AI technology, its core mainly includes two aspects: 1. Advanced neural network algorithms; 2. Processors that provide massive hardware computing power. Among them, the calculation of neural network algorithms is mainly convolution calculation type. Traditionally, there are two hardware solutions to implement convolution calculation: (1) converting convolution calculation into matrix operation, and integrating a large number of multiplier matrices to implement matrix multiplication calculation by designing a general neural network processing unit (NPU). (2) Designing a dedicated convolution device to directly implement convolution calculation. Among them, the first solution is the current mainstream solution. However, this solution requires a large number of repeated read and write operations on the data, which increases power consumption. The convolution device in the second solution is composed of multiple multipliers and adders. After multiple multipliers independently multiply the input feature map, they are accumulated through the adder to obtain the output feature map. However, all data in the input feature map needs to be calculated by the multiplier, and the power consumption of the multiplier cannot be controlled according to actual needs. Summary of the invention

[0003] The embodiments of the present application provide a multiplier, a convolution circuit, a calculation method, a chip and an electronic device to solve the problem that the current multiplier hardware circuit cannot control the power consumption.

[0004] In order to solve the above problems, the embodiments of the present application provide the following technical solutions:

[0005] In a first aspect, a multiplier is provided, which includes a first precoder, a first encoder group, and an addition tree circuit. The multiplier is coupled to a control line, a plurality of weight input lines, and a plurality of feature input lines. The first encoder group includes a control circuit and a first encoder. The control circuit is coupled to the control line, at least one feature input line among the plurality of feature input lines, and the first encoder. The first encoder is also coupled to a weight input line among the plurality of weight input lines and the first precoder, and the first encoder is also coupled to the addition tree circuit. Based on this, the control circuit can control the output of the first encoder through a control signal input by the control line and a signal input by at least one feature input line, thereby controlling the power consumption of the multiplier according to actual needs.

[0006] In a possible implementation, the multiplier can be coupled to multiple control lines; the first encoder group includes multiple control circuits and multiple first encoders; wherein the weight input lines of the multiple first encoders are the same, and each control circuit is coupled to a corresponding first encoder, a control line, and at least one characteristic input line. Based on this, when all first encoders are not required to perform dynamic operations, the corresponding first encoders can be controlled to continuously output constants through multiple control lines, so that the power consumption of the multiple first encoders is static power consumption, further reducing the total power consumption of the multiplier during the calculation process.

[0007] In a possible implementation, the multiplier includes a plurality of first precoders and a plurality of first encoder groups; each first precoder corresponds to a first encoder group, and the encoders of the same digit in the plurality of first encoder groups correspond to the same control line. Based on this, the first encoders of the same digit in different encoder groups can be controlled by the same control line, and the plurality of encoder groups can be controlled more conveniently while reducing the power consumption of the multiplier.

[0008] In a possible implementation, the control signal input to the control line is determined by the maximum allowable calculation error range of the multiplier. Based on this, the control signal can be transmitted to the control line according to the maximum allowable calculation error range to meet different quantization requirements.

[0009] In a possible implementation, the control circuit controls the first encoder to output a constant through a signal input through at least one characteristic input line and a control signal input through a control line. Based on this, the control signal input through the control line can control the first encoder to only output a constant, so that the power consumption of the first encoder is static power consumption, thereby reducing the total power consumption of the multiplier during the calculation process.

[0010] In a possible implementation, the first encoder includes a first input terminal and a second input terminal. The control circuit is coupled to the first characteristic input line and the second characteristic input line, and the control circuit includes a first AND gate and a second AND gate. The first input terminal of the first AND gate and the first input terminal of the second AND gate are both coupled to the control line. The second input terminal of the first AND gate is coupled to the first characteristic input line. The second input terminal of the second AND gate is coupled to the second characteristic input line. The output terminal of the first AND gate is coupled to the first input terminal of the first encoder. The output terminal of the second AND gate is coupled to the second input terminal of the first encoder. Based on this, the control circuit can perform AND logic operations on the control signal input to the control line and the signals input to the first characteristic input line and the second characteristic input line, thereby controlling the output of each first encoder.

[0011] In a possible implementation, the first encoder includes a first input terminal and a second input terminal. The control circuit is coupled to the first characteristic input line and the second characteristic input line, and the control circuit includes a first OR gate and a second OR gate. The first input terminal of the first OR gate and the first input terminal of the second OR gate are both coupled to the control line. The second input terminal of the first OR gate is coupled to the first characteristic input line. The second input terminal of the second OR gate is coupled to the second characteristic input line. The output terminal of the first OR gate is coupled to the first input terminal of the first encoder. The output terminal of the second OR gate is coupled to the second input terminal of the first encoder. Based on this, the control circuit can perform OR logic operations on the control signal input to the control line and the signals input to the first characteristic input line and the second characteristic input line, respectively, so as to control the output of each first encoder.

[0012] In a possible implementation, the first encoder includes a first input terminal and a second input terminal. The control circuit is coupled to the first characteristic input line and the second characteristic input line, and the control circuit includes a first switch and a second switch. The first characteristic input line is coupled to the first input terminal of the first encoder through the first switch. The second characteristic input line is coupled to the second input terminal of the first encoder through the second switch. The controlled end of the first switch and the controlled end of the second switch are also coupled to the control line. Based on this, the on-off state of the first switch and the second switch can be controlled by the control signal input by the control line, thereby controlling the output of the first encoder.

[0013] In a possible implementation, the first encoder includes a first input terminal and a second input terminal; the control circuit is coupled to the first characteristic input line, and the control circuit may include a third AND gate. The first input terminal of the third AND gate is coupled to the control line. The second input terminal of the third AND gate is coupled to the first characteristic input line. The first encoder includes a first input terminal and a second input terminal. The first input terminal and the second input terminal of the first encoder are both coupled to the output terminal of the third AND gate. Based on this, the control circuit may also perform an AND logic operation on the signal input by the control line and the signal input by the first characteristic input line, thereby controlling the output of the first encoder.

[0014] In a possible implementation, the first encoder includes a first input terminal and a second input terminal. The control circuit is coupled to the first characteristic input line, and the control circuit includes a third OR gate. The first input terminal of the third OR gate is coupled to the control line. The second input terminal of the third OR gate is coupled to the first characteristic input line. The first encoder includes a first input terminal and a second input terminal. The first input terminal and the second input terminal of the first encoder are both coupled to the output terminal of the third OR gate. Based on this, the control circuit can also perform an OR logic operation on the signal input by the control line and the signal input by the first characteristic input line, thereby controlling the output of the first encoder.

[0015] In a possible implementation, the first encoder includes a first input terminal and a second input terminal. The control circuit is coupled to the first characteristic input line, and the control circuit includes a third switch. The first input terminal and the second input terminal of the first encoder are both coupled to the first characteristic input line through the third switch. The controlled end of the third switch is also coupled to the control line. Based on this, the on-off state of the third switch can be controlled by the control signal input by the control line, thereby controlling the output of the first encoder.

[0016] In a possible implementation, the output end of the adder tree circuit may be further coupled to a compensation adder circuit, through which the error compensation may be performed on the data output by the adder tree circuit according to the received compensation data.

[0017] In a possible implementation, the multiplier further includes a register circuit. The register circuit includes a plurality of registers, and each of the plurality of weight input lines, each of the plurality of feature input lines, and the control line are coupled to a register in the register circuit, respectively. Based on this, the signals transmitted to the weight input line, the feature input line, and the control line can be cached and then transmitted through the register circuit, so as to better meet the requirements in a high-speed computing environment.

[0018] In a second aspect, a convolution circuit is provided, which includes a plurality of multipliers in any possible implementation of the first aspect, and a first adder coupled to the plurality of multipliers.

[0019] In a possible implementation, the convolution circuit further includes a second adder coupled to the first adder. The second adder is also coupled to a memory. The second adder can perform error compensation on the data output by the first adder according to the compensation data stored in the memory.

[0020] In a possible implementation manner, the control lines corresponding to the first encoders of the same digit in a plurality of multipliers are the same.

[0021] In a third aspect, a calculation method applied to the multiplier is provided. When executing the method, a control instruction may be received first; the control instruction is used to instruct the first encoder to output a constant. Then, a control signal is input to the control line according to the control instruction. Finally, in response to the control signal, the control circuit controls the first encoder to output a constant.

[0022] In a possible implementation, the method further includes: acquiring first compensation data. Then, sending the first compensation data to a compensation adding circuit, and performing error compensation on data output by the adding tree circuit through the compensation adding circuit.

[0023] In a possible implementation, the control signal may be determined by a maximum allowable calculation error range of the multiplier.

[0024] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer program instructions. When the computer program instructions are executed by a processor, the method in any possible implementation manner of the third aspect described above can be implemented.

[0025] In a fifth aspect, a chip is provided, comprising a circuit board and a convolution circuit arranged on the circuit board as in any possible implementation of the second aspect, or a multiplier as in any possible implementation of the first aspect.

[0026] In a sixth aspect, an electronic device is provided, comprising a memory, and the chip in the fifth aspect coupled to the memory.

[0027] In a seventh aspect, a computer program product is provided, which, when executed by a processor, can implement the method in any possible implementation manner of the third aspect above.

[0028] Among them, the technical effects that can be brought about by the above-mentioned second to seventh aspects can be referred to the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0030] Figure 2 It is a hardware structure block diagram for realizing multi-layer convolution calculation;

[0031] Figure 3 A schematic diagram of the structure of a chip system for implementing convolution calculation;

[0032] Figure 4 is a schematic diagram of a convolution circuit;

[0033] Figure 5 is a schematic diagram of a multiplier;

[0034] Figure 6 is a structural block diagram of a multiplier;

[0035] Figure 7 A schematic diagram of an adder tree circuit in each multiplier in a convolution circuit;

[0036] Figure 8 A schematic diagram of a quantization method in a convolution circuit;

[0037] Fig. 9A schematic diagram of the structure of a multiplier provided in an embodiment of the present application;

[0038] Fig.10 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0039] Fig.11 A schematic diagram of the structure of an encoder provided in an embodiment of the present application;

[0040] Fig.12 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0041] Fig.13 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0042] Fig.14 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0043] Fig.15 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0044] Fig.16 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0045] Fig.17 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0046] Fig.18 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0047] Fig.19 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0048] Fig. 20 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0049] Fig.21 A schematic diagram of the structure of another multiplier provided in an embodiment of the present application;

[0050] Fig. 22 A schematic diagram of the control principle of a multiplier provided in an embodiment of the present application;

[0051] Fig.23 A schematic diagram of the structure of a convolution circuit provided in an embodiment of the present application;

[0052] Fig.24 A flowchart of a calculation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0054] In order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0055] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical contact or point contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical contact or electrical contact with each other, or it may mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0056] The present application is described in detail below with reference to the accompanying drawings and embodiments:

[0057] Currently, AI technology is used in many electronic devices 100. The electronic device 100 may be a terminal or a server, or may be a chip, a chipset, a circuit board or a module in a terminal or a server. Figure 1 As shown, the electronic device 100 may include a memory 110, a processor 120, a communication interface 130 and a bus 140. The memory 110, the processor 120 and the communication interface 130 are interconnected via the bus 140. The memory 110 may be used to store data, software programs and modules, and mainly includes a program storage area and a data storage area. The program storage area may store an operating system, an application required for at least one function, etc., and the data storage area may store data created when the device is used, etc. The processor 120 is used to control and manage the actions of the communication device, such as executing various functions of the device and processing data by running or executing software programs and / or modules stored in the memory 110, and calling data stored in the memory 110. The communication interface 130 is used to support the device to communicate.

[0058] The processor 120 includes, but is not limited to, a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP) or a general-purpose processor. The processor 120 may include one or more multipliers, such as a multiplier array, which is a device for implementing multiplication operations in the processor. On the other hand, the multiplier may also be arranged in a convolution circuit. The convolution circuit may be arranged on a circuit board as an independent chip, and the received data may be subjected to convolution operations. In addition, the convolution circuit may also be arranged in the processor as a convolution calculation module in the processor.

[0059] The bus 140 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0060] The memory 110 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. The nonvolatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0061] In the above electronic devices, the core of AI technology is mainly reflected in two aspects: advanced neural network algorithms and processors that can provide massive hardware computing power. Among them, neural network algorithms usually include multiple layers of convolution calculations. Each layer of convolution calculation can output a high-bitwidth integer result. The integer result is then quantized to produce a low-bitwidth integer feature map, which is used as the input of the next layer of convolution operation. Figure 2As shown, taking the convolution calculation of two layers as an example, the two-layer convolution calculation usually includes a first convolution layer 210, a quantization layer 220 and a second convolution layer 230. Among them, the first convolution layer 210 can perform convolution calculation according to the input feature map F(k, j) and the weight parameter W(m, k, j) corresponding to the input feature map F(k, j) to obtain a high-bit width integer result. The integer result is quantized by the quantization layer 220 and then used as the input of the second convolution layer 230. The second convolution layer 230 finally performs convolution calculation again according to the quantized data and the corresponding weight parameter to obtain the output feature map. For example, the first convolution layer 210 can perform convolution calculation on the input feature map of 8-bit integer type (int8) and the weight parameter of int8, and then output 29-bit (bit) data. The quantization layer 220 quantizes the 29-bit data into data of int8 data type according to the input scale parameter (scale). Finally, the second convolution layer 230 performs convolution calculation based on the quantized data and the corresponding weight parameter to obtain the output feature map.

[0062] In order to realize the convolution calculation of each convolution layer mentioned above, the following two hardware solutions are usually adopted: one is to convert the convolution calculation into matrix operation, and integrate a large number of multiplier matrices to realize matrix multiplication calculation by designing a general neural network processing unit (NPU). The other is to design a dedicated convolution device to directly realize the convolution calculation.

[0063] Among them, the implementation method of convolution calculation through a dedicated convolution device is as follows Figure 3 As shown in the figure, the convolution unit can perform convolution calculation on the input feature map F(k,j) according to the weight parameter W(m,k,j) stored in the register group to obtain the corresponding output feature map Out(m). Figure 4 As shown, the convolution circuit inside the convolution device usually includes multiple multipliers 410 and adders 420 coupled to the multiple multipliers 410. Each multiplier 410 can independently operate on the input feature map according to the configured weight parameters. Then, the operation results of all multipliers in the convolution device are input to the adder 420 for accumulation to obtain the final output result. Among them, the above-mentioned multiplier 410 usually adopts a multiplying accumulator (MAC). Figure 5As shown, the multiplier 410 includes multiple precoders 411, multiple encoder groups 412 and an addition tree circuit 413. Among them, each precoder is coupled to an encoder group. In the process of performing the operation, multiple precoders 411 can be used to precode according to the values ​​of 3 bits in the configured weight parameters, and two-way coded data can be output. Then, multiple encoder groups output a partial product according to the two-way coded data output by the corresponding precoder and the value of each bit in the input feature map. Among them, the precoder and each encoder in the encoder group are prior art, and the specific principles can refer to the patent with application number PCT / CN2019 / 119993 and the patent with application number PCT / CN2020 / 082840, and the embodiments of this application are not repeated here.

[0064] The addition tree circuit 413 generally adopts a Wallace tree addition tree structure. The input of the addition tree circuit includes not only the partial products of the encoder outputs in each encoder group, but also the partial products S and constant 1 related to the weight parameters. Among them, the addition tree circuit 413 outputs multiple digits of data through multiple output lines. The output of the encoder corresponding to the odd digits of the data in each encoder group is added with the corresponding partial product S or constant 1. The digit can also be called a weight, which refers to the bits at different positions in the binary system, similar to the ones, tens and hundreds in the decimal system.

[0065] Among them, Figure 6As shown, a plurality of feature input lines (input is F[0]~F[Z-1]) and a plurality of weight input lines (input is odd bits in W[0]~W[R-1]) are provided in the multiplier 410. The input of each feature input line is the value of a bit in the input feature map. In the multiplier 410, the number of feature input lines and the number of encoders in each encoder group are the same as the number of bits of the input feature map, and the number of pre-encoders and the number of weight input lines are half the number of feature input lines. For example, if the input feature map is 8-bit integer (int8) data, the number of feature input lines is 8, the number of encoders is 8, and the number of pre-encoders and the number of weight input lines are both 4. Multiple encoder groups form a coding array. Among them, in each encoder group, except that the first encoder is only coupled with the feature input line corresponding to the 0th bit F[0], the remaining encoders are coupled with the feature input lines corresponding to two adjacent bits in turn. For example, the second encoder in the encoder group can be coupled with the feature input line corresponding to the 0th bit position F[0] and the feature input line corresponding to the 1st bit position F[1] (denoted as F[0]&F[1]). The third encoder in the encoder group can be coupled with the feature input line corresponding to the 1st bit position F[1] and the feature input line corresponding to the 2nd bit position F[2]. The same applies to other encoders, which are not described in detail in this application. In addition, each encoder group is also coupled with a corresponding weight input line. Each precoder can provide two precoded data (M1S and M2S) to the encoder according to the two bit values ​​set in the weight parameter. Among them, Figure 6 The two precoded data output by each precoder in are distinguished by an even number in the range of 0 to R-2 (R is an even number) as a subscript. Furthermore, each encoder in each encoder group operates on the two bit values ​​of the two feature input lines according to the corresponding two precoded data and the value of the corresponding weight input line input to obtain the corresponding partial product. The partial product is output after a carry addition operation through an adder tree circuit. Among them, the input of each weight input line is the value of the odd bit in the weight parameter corresponding to the input feature map. For example, if the weight parameter corresponding to the input feature map is R bits; then the values ​​output by each weight input line in the corresponding multiplier are the value of the 1st bit W[1], the value of the 3rd bit W[3], the value of the 5th bit W[5], ..., the value of the R-1th bit W[R-1].

[0066] When the adder tree circuit 413 performs calculations, each encoder group can be regarded as a row; each encoder in each encoder group can be regarded as a column. The column where each encoder in each encoder group is located corresponds to a weight (2 0 ~2 n), and the outputs of encoders with the same weights are added with carry. Starting from the second row, the output of the encoder of the kth column (k≥1) in each row and the output of the encoder of the k+2th column in the previous row are binary bits with the same weight. In addition, when adding the outputs of each encoder corresponding to the first column of the first row to the first column of the last row, it is also necessary to add a partial product S related to the weight parameter at the end of each odd column. The partial product S can be the value of the odd bit of the weight parameter. When adding the outputs of each encoder corresponding to the last column of the first row to the last column of the last row, it is also necessary to add a constant 1 to each odd column first.

[0067] Specifically, Figure 7 As shown, in each layer of the addition tree circuit of each multiplier (MUL0~MULn), binary bits with the same weight are added in parallel through multiple full adders. Each adder ( Figure 7 The rectangular box in the figure inputs a 3-bit binary number on the same weight position, outputs 1 sum bit and 1 carry bit, and the sum bits output by all adders and the remaining bits not added in the current layer are transmitted together to the arrangement column of the same weight position in the second layer of the adder tree circuit, and the carry bit of the adder is transmitted to the arrangement column of the adjacent high weight position in the second layer, thereby forming a second layer arrangement array, and the adders in the second layer perform parallel addition on the binary bits on the same weight position, and the sum bits output by all adders and the remaining bits not added in the current layer are transmitted together to the arrangement column of the same weight position in the third layer of the adder tree, and the carry bit of the adder in the second layer is transmitted to the arrangement column of the adjacent high weight position in the third layer, ..., and the parallel addition is performed until the last layer. When there are no more than 2 bits of data left in the arrangement column of each weight position, the parallel addition is completed. Finally, the adder can accumulate the outputs of all multipliers to obtain the corresponding output result. The output result can be quantized and then transmitted to the next level of convolution circuit. Further, as Figure 8 As shown in FIG. 1 , the quantization process of the output result is to select the value range of the quantized data through a slicing operation (clip), which is equivalent to adjusting the position of the decimal point in the output data according to the configured effective bits, and then discarding the decimal part. For example, when the effective bit number is 8 bits, the effective bits can be selected through quantization, and then the decimal part can be discarded.

[0068] In the above implementation process, although the convolution calculation can be realized by the above convolution device, the calculation result after the convolution operation still needs to be quantized, and the subsequent quantization process will discard some unnecessary data. This part of the data still requires the encoder group inside the multiplier to consume power for calculation, which increases the power consumption of the entire circuit.

[0069] To solve this problem, Fig. 9As shown, the embodiment of the present application provides a multiplier 900, which includes a first precoder 910, a first encoder group 920 and an adder tree circuit 930, and the multiplier 900 is coupled to multiple weight input lines, a control line C[1] and multiple feature input lines. Among them, the first encoder group 920 is coupled to one weight input line (input is W[1]) among the multiple weight input lines and the first precoder 910, and the first encoder group 920 is also coupled to the adder tree circuit 930 ( Fig. 9 The hollow circles represent the output terminals of the encoders in the encoder group. The first encoder group 920 includes a control circuit 921 and a first encoder 922. The control circuit 921 is coupled to the control line C[1], two feature input lines (the inputs are F[0] and F[1]) among the multiple feature input lines, and the first encoder 922.

[0070] In the above multiplier 900, the first encoder 922 can output a constant when the control line C[1] continuously inputs a set signal, so that the power consumption of the first encoder 922 can be maintained at a static power consumption. The other encoders inside the first encoder group 920 normally operate on the input data. Since the input data is constantly changing during the operation, the power consumption of the encoder during the calculation process is dynamic power consumption. However, the partial product output by some encoders has little effect on the quantization result, and the dynamic power consumption is much larger than the static power consumption. Therefore, by keeping some encoders at static power consumption according to actual quantization requirements, the power consumption of each multiplier during the operation process can be reduced, thereby reducing the total power consumption of the multiplier.

[0071] In one possible embodiment, Fig.10As shown, the control circuit 921 can adopt a logic circuit. The control circuit 921 includes a first AND gate U1 and a second AND gate U2; the first encoder 922 includes a first input terminal and a second input terminal. The first input terminal of the first AND gate U1 and the first input terminal of the second AND gate U2 are both coupled to the control line C[1]. The second input terminal of the first AND gate U1 is coupled to the first characteristic input line (the input is F[0]). The second input terminal of the second AND gate U2 is coupled to the second characteristic input line (the input is F[1]). The output terminal of the first AND gate U1 is coupled to the first input terminal of the first encoder 922. The output terminal of the second AND gate U2 is coupled to the second input terminal of the first encoder 922. The input of the first characteristic input line and the second characteristic input line is the data of two adjacent bits in the input characteristic map. The first input terminal of the first AND gate U1 and the first input terminal of the second AND gate U2 are used to input the same level signal. When the first input terminal of the first AND gate U1 and the first input terminal of the second AND gate U2 input a high level (the signal is 1), the first encoder 922 can dynamically operate on the continuously input data. When the first input terminal of the first AND gate U1 and the first input terminal of the second AND gate U2 continuously input a low level (the signal is 0), the first encoder 922 continuously outputs a constant.

[0072] Further, such as Fig.11 As shown, the first encoder 922 generally includes an AND gate AND2, an AND gate AND3, an OR gate OR1, and an XOR gate XOR2. The first input of the AND gate AND2 is inputted with the first coded data M1S outputted by the corresponding precoder. The second input of the AND gate AND2 is inputted with the value F[a] of the ath bit in the input feature map. The first input of the AND gate AND3 is inputted with the second coded data M2S outputted by the corresponding precoder. The second input of the AND gate AND3 is inputted with the value F[a-1] of the a-1th bit in the input feature map. Wherein, a is an integer not less than 1. In addition, if a=0, the second input of the AND gate AND2 and the second input of the AND gate AND3 are inputted with the value of the 0th bit in the input feature map. The first input of the OR gate OR1 is coupled with the output of the AND gate AND2; the second input of the OR gate OR1 is coupled with the output of the AND gate AND3. The first input of the XOR gate XOR2 is coupled with the output of the OR gate OR1. The input of the second input terminal of the XOR gate XOR2 is the value of the R-1th bit in the weight parameter corresponding to the input feature map. Wherein R is a positive even number. In addition, the structure of the encoder in each encoder group is the same as that of the first encoder 922, and the embodiment of the present application is not repeated here.

[0073] During the calculation process, the values ​​of the first characteristic input line and the second characteristic input line input dynamically change between 0 and 1. Therefore, the inputs of the second input end of the first AND gate U1 and the second input end of the second AND gate U2 also change dynamically. At this time, if the signal input by the control line C[1] is at a low level (the signal is 0), the outputs of the first AND gate U1 and the second AND gate U2 are both 0. Because the weight parameters input by the weight input line remain unchanged during the calculation process, the output of the first encoder 922 is a constant. The first encoder 922 only has static power consumption. If the signal input by the control line C[1] is at a high level (the signal is 1), the outputs of the first AND gate U1 and the second AND gate U2 will change dynamically with the input of the first characteristic input line and the input of the second characteristic input line. At this time, the first encoder 922 can perform dynamic operations normally according to the input data.

[0074] In one possible embodiment, Fig.12 As shown, the control circuit 921 may also include a first OR gate H1 and a second OR gate H2. The first input terminal of the first OR gate H1 and the first input terminal of the second OR gate H2 are both coupled to the control line C[1]. The second input terminal of the first OR gate H1 is coupled to the first characteristic input line. The second input terminal of the second OR gate H2 is coupled to the second characteristic input line. The output terminal of the first OR gate H1 is coupled to the first input terminal of the first encoder 922. The output terminal of the second OR gate H2 is coupled to the second input terminal of the first encoder 922. Fig.10 In comparison, the corresponding relationship between the signal input to the control line C[1] and the output of the first encoder 922 is opposite. Among them, when the first input end of the first OR gate H1 and the first input end of the second OR gate H2 input a low level (signal is 0), the first encoder 922 can dynamically operate on the data continuously input by the first characteristic input line and the second characteristic input line, and the output data is dynamically changing. When the first input end of the first OR gate H1 and the first input end of the second OR gate H2 continuously input a high level (signal is 1), the signal output by the control circuit 921 is unchanged, regardless of the value of the first characteristic input line and the second characteristic input line input, and the first encoder 922 continuously outputs a constant. Therefore, the power consumption of the first encoder 922 can be kept static by continuously inputting a high level (signal is 1) to the control line C[1], thereby reducing the power consumption of the multiplier.

[0075] In one possible embodiment, Fig.13As shown, the control circuit 921 may also use a switch circuit. The control circuit 921 may include a first switch K1 and a second switch K2. The first encoder 922 includes a first input terminal and a second input terminal. The first switch K1 is coupled between the first characteristic input line and the first input terminal of the first encoder 922. The second switch K2 is coupled between the second characteristic input line and the second input terminal of the first encoder 922. The controlled terminal of the first switch K1 and the controlled terminal of the second switch K2 are also coupled to the control line C[1]. The signal input by the control line C[1] can control the on-off state of the first switch K1 and the second switch K2, thereby controlling the first encoder 922 to output a constant or perform dynamic operations normally. Exemplarily, if the control line C[1] inputs a high level (the signal is 1), the first switch K1 and the second switch K2 are turned on, and the signals at the two input terminals of the first encoder 922 change with the signals input by the first characteristic input line and the second characteristic input line. At this time, the first encoder 922 can perform dynamic operations normally. If the control line C[1] inputs a low level (signal is 0), the first switch K1 and the second switch K2 are both disconnected, and the signals at the two input ends of the first encoder 922 are both 0. At this time, the output of the first encoder 922 is a constant. The first switch K1 and the second switch K2 may also be disconnected when the control line C[1] inputs a high level, and may be turned on when the control line C[1] inputs a low level, and the embodiment of the present application does not impose any specific restrictions on this. In addition, the control circuit 921 may also select other switch circuits with the same or similar functions, and the embodiment of the present application does not impose any specific restrictions on its structure.

[0076] In a possible implementation, when the first encoder 922 is the encoder of the first digit in each encoder group, the corresponding control circuit 921 can be coupled to a control line C[0], a feature input line (i.e., the first feature input line) among the plurality of feature input lines, and the corresponding first encoder 922. For example, Fig.14 As shown, the control circuit 921 may include a third AND gate U3. The first input terminal of the third AND gate U3 is coupled to the control line C[0]. The second input terminal of the third AND gate U3 is coupled to the first characteristic input line. The first input terminal and the second input terminal of the first encoder 922 are both coupled to the output terminal of the third AND gate U3. Fig.10Similarly, when performing calculations, if the control line C[0] inputs a high level, the signals at the two input terminals of the first encoder 922 change with the signals input by the first characteristic input line. At this time, the first encoder 922 can perform dynamic operations normally. If the signal input by the control line C[0] is a low level, the signals at the two input terminals of the first encoder 922 are both 0. At this time, the output of the first encoder 922 is a constant. By continuously inputting a low level to the control line C[0], the power consumption of the first encoder 922 can be kept at a static power consumption, thereby reducing the power consumption of the multiplier.

[0077] In another embodiment, Fig.15 As shown, the control circuit 921 may include a third OR gate H3. The first input terminal of the third OR gate H3 is coupled to the control line C[0]. The second input terminal of the third OR gate H3 is coupled to the first characteristic input line. The first input terminal and the second input terminal of the first encoder 922 are both coupled to the output terminal of the third OR gate H3. Fig.12 Similarly, when calculating, if the control line C[0] inputs a high level, the signals at the two input terminals of the first encoder 922 are both 1. At this time, the output of the first encoder 922 is a constant. If the signal input to the control line C[0] is a low level, the signals at the two input terminals of the first encoder 922 change with the signal input to the first characteristic input line. At this time, the output of the first encoder 922 changes dynamically. By continuously inputting a high level to the control line C[0], the power consumption of the first encoder 922 can be kept at a static power consumption, thereby reducing the power consumption of the multiplier.

[0078] In another embodiment, Fig.16 As shown, the control circuit 921 may also include a third switch K3. The first input terminal and the second input terminal of the first encoder 922 are both coupled to the first characteristic input line through the third switch K3. The controlled end of the third switch K3 is also coupled to the control line C[0]. The on-off state of the third switch K3 can be controlled by the signal input by the control line C[0], so as to control the first encoder 922 to output a constant or perform dynamic operations normally. Exemplarily, if the input signal of the control line C[0] is at a high level, the third switch K3 is turned on, and the signals at the two input terminals of the first encoder 922 change with the signals input by the first characteristic input line. At this time, the first encoder 922 can perform dynamic operations normally. If the signal input by the control line C[0] is at a low level, the third switch K3 is turned off, and the signals at the two input terminals of the first encoder 922 are both 0. At this time, the output of the first encoder 922 is a constant.

[0079] In a possible implementation, the multiplier 900 may be coupled to a plurality of control lines. The first encoder group 920 may include a plurality of control circuits and a plurality of first encoders. Each first encoder is coupled to a corresponding control circuit, a control line, and two characteristic input lines.

[0080] For example, Fig.17 As shown, the first encoder group 910 in the multiplier includes two control lines (C[0] and C[1]), two control circuits (921a and 921b), and two encoders (922a and 922b). The control circuit 921a can use Fig.10 The structure in the control circuit 921b uses Fig.14 The structure in. Encoder 922a and encoder 922b adopt the structure of the first encoder. Control circuit 921a corresponds to control line C[0], encoder 922a, first characteristic input line and second characteristic input line, and control circuit 921b corresponds to control line C[1], encoder 922b and first characteristic input line F[0]. In this way, encoder 922a and / or encoder 922b can be controlled to output constants according to the requirements of quantization error, thereby reducing power consumption according to actual requirements.

[0081] Further, such as Fig.18 and 19 As shown, the control circuit 921b can also be used Fig.15 or Fig.16 Similarly, the control circuit 921a can also be used Fig.12 or Fig.13 In the actual manufacturing process, the structures of the control circuit 921b and the control circuit 921a can be selected according to actual needs, and the embodiment of the present application does not make any specific limitation on this.

[0082] Further, such as Fig. 20 As shown, a third control line C[2] and a control circuit 921c can also be set in the first encoder group 920. The first encoder group 920 also includes an encoder 922c. Among them, the control circuit 921c corresponds to the encoder 922c, the second characteristic input line, the third characteristic input line F[3] and the control line C[2]. Based on this, more encoder output constants in the first encoder group 920 can be controlled, thereby reducing more power consumption for the multiplier.

[0083] Referring to the above method, the first encoder group 920 can continue to configure corresponding control lines and control circuits for each encoder according to actual needs, so as to better control the number of encoders that output constants according to actual needs.

[0084] In a possible implementation, the multiplier 900 may also include a plurality of first precoders and a plurality of first encoder groups. Each first precoder corresponds to a first encoder group, and encoders of the same digit in each first encoder group correspond to the same control line.

[0085] For example, Fig.21 As shown, the multiplier 900 may include two weight input lines (input is W[1] and W[3]), two pre-encoders (910a and 910b) and two encoder groups (920a and 920b). Encoder group 920a includes four encoders (A1 to A4), four control lines (C[0] to C[3]) and four control circuits (B1 to B4). Encoder group 920b includes two control lines, two control circuits (b1 and b2) and two encoders (a1 and a2). Among them, encoders A1 to A4 in encoder group 920a all adopt Fig.11 The control circuits B2 to B4 and the control circuit b2 all adopt Fig.10 The structure of the first control circuit in FIG. The control circuits B1 and b1 adopt Fig.14 The structure of the first control circuit in . Encoders A2 to A4 correspond to the characteristic input lines of two adjacent bits in F[0]~F[3] in turn, and each encoder corresponds to a control line in C[1]~C[3] and a control circuit in control circuits B2~B4. Among them, control circuit B1 corresponds to encoder A1, the first characteristic input line and control line C[0]. Control circuit B2 corresponds to encoder A2, the first characteristic input line, the second characteristic input line and control line C[1]. Control circuit B3 corresponds to encoder A3, the second characteristic input line, the third characteristic input line (input is F[2]) and control line C[2]. Control circuit B4 corresponds to encoder A4, the third characteristic input line, the fourth characteristic input line (input is F[3]) and control line C[3]. Because encoder a2 and encoder A4 are encoders on the same weight, and encoder a1 and encoder A3 are encoders on the same weight. So control circuit b1 corresponds to encoder a1, control line C[2] and the first characteristic input line. The control circuit b2 corresponds to the encoder a2, the control line C[3], the first characteristic input line, and the second characteristic input line.

[0086] Furthermore, in a possible implementation, Fig.21As shown, the output end of the adder tree circuit in the above-mentioned multiplier can also be coupled to a compensation adder circuit 940. The compensation adder circuit 940 can perform error compensation on the data output by the adder tree circuit according to the received compensation data D_comp. Among them, the compensation data D_comp received by the compensation adder circuit 940 can be error data obtained after inputting test data into the multiplier. In addition, the above-mentioned multiplier can also include a register circuit 950. The register circuit 950 includes a plurality of registers. Among them, a plurality of weight input lines, a plurality of feature input lines, a third feature input line and a control line in the multiplier are respectively coupled to a register in the register circuit. In addition, each precoder can also be coupled to a register in the register circuit 950. Based on this, the weight parameters of each precoder can be cached through the register, and the parameters required to be input by each input line can also be cached through the register to better meet the needs of the high-speed computing environment.

[0087] Further, see Figure 6 , the multiplier usually couples multiple feature input lines and multiple weight input lines, and the first encoder group and the second encoder group each include multiple encoders. Therefore, the remaining encoders in each encoder group can also set corresponding control circuits with reference to the structure of the first control circuit. In addition, the multiplier usually includes multiple precoders and encoder groups corresponding to each precoder. Therefore, the encoders in other encoder groups can also set corresponding control circuits in the same way, and the control circuits corresponding to the encoders with the same weights in multiple multipliers can be controlled through the same control line. For example, Fig. 22 As shown, the coding array can be divided into a left coding array and a right coding array according to the total number of weight bits of the data output by the multiplier. Among them, each encoder in the left coding array may not be provided with a control circuit and a control line. Each encoder in the right coding array is provided with a corresponding control circuit and a control line C[m:0] (i.e., C[0] to C[m]). The left coding array in all multipliers can perform addition operations by sharing a first addition tree circuit. The right coding array in all multipliers can perform addition operations by sharing a second addition tree circuit.

[0088] Exemplarily, in an 8bit*8bit multiplier, 4 precoders, 4 encoder groups, 8 feature input lines and 4 weight input lines are generally included. Each weight input line is coupled to a corresponding encoder group. Each encoder group includes 8 encoders, and the pth encoder in the i+1th encoder group and the p+2th encoder in the i-th encoder group are encoders with the same weight. Wherein, the value range of i is [1,4], and the value range of p is [1,6]. In this multiplier, each encoder in the first encoder group is provided with a corresponding control circuit and control line (C[0]~C[7]). In each of the other encoder groups, the encoders with the same weight as those in the first encoder group are also provided with corresponding control circuits; at the same time, the encoders with the same weight are controlled by the same control line. Wherein, the signal input to each control line can be determined by the maximum allowable calculation error range of the multiplier. When performing a convolution operation, the maximum allowable calculation error range can be configured according to actual needs (i.e., determining the weights that need to output constants), and a signal of 0 can be input to the corresponding control line to control the corresponding encoder to output constants. For example, if the encoders with weights 0 to 7 are required to output constants, a signal of 0 can be output to control lines C[0] to C[7]. If only the encoders with weights 0 to 4 are required to output constants, a signal of 0 can be output to control lines C[0] to C[4]. In a possible implementation, in an 8bit*8bit multiplier, corresponding control circuits and control lines can also be set for all encoders in a coding array composed of multiple encoder groups. Among them, encoders with the same weights are controlled by the same control line. When performing a convolution operation, more encoders can be controlled to output constants according to actual needs, thereby meeting different quantization requirements while reducing power consumption.

[0089] In the above implementation process, the control circuits and control lines in the encoding array can also be configured for encoders at different weights according to actual usage requirements, and the embodiments of the present application do not impose specific limitations on this.

[0090] In one possible embodiment, Fig.23 As shown, the embodiment of the present application also provides a convolution circuit 2100, which can be set on a circuit board and used as an independent chip. The convolution circuit 2100 includes a plurality of the above-mentioned multipliers 900, and a first adder 2110 coupled to the plurality of multipliers 900. A plurality of control lines C[m:0] are set in each multiplier to control part of the encoder, and the control lines corresponding to the encoders of the same digit in the plurality of multipliers 910 are the same. In the above manner, the power consumption of the convolution circuit can be reduced.

[0091] Further, the output end of the first adder 2110 can be selectively coupled to the second adder 2120, and the second adder 2120 can be coupled to the memory. The second adder 2120 can perform error compensation on the data output by the first adder according to the compensation data D_comp stored in the memory. In addition, when the second adder 2120 is set, the compensation adding circuit 940 in the multiplier can be selectively set according to actual needs.

[0092] In one possible embodiment, Fig.24 As shown, an embodiment of the present application also provides a calculation method applied to the above-mentioned multiplier, and the specific execution process of the calculation method is as follows.

[0093] S241. Receive a control instruction; the control instruction is used to instruct the first encoder to output a constant.

[0094] The control instruction may be an instruction preset according to actual needs, and the control instruction may include a control line address and a corresponding control signal corresponding to the first encoder in the first encoder group that needs to output a constant.

[0095] S242. Input a control signal to the control line according to the above control instruction.

[0096] Wherein, a control signal can be input to the corresponding control line according to the control line address corresponding to the first encoder included in the control instruction. The control signal can be 0 or 1, which is specifically selected according to the structure of the control circuit.

[0097] S243. In response to the above control signal, the control circuit controls the first encoder to output a constant.

[0098] S244. Receive first compensation data;

[0099] The first compensation data is used to reduce the error of the data output by the multiplier. The first compensation data may be pre-configured data at the factory, or may be error data obtained after testing the multiplier with test data.

[0100] S245. Send the first compensation data to the compensation adding circuit, and use the compensation adding circuit to perform error compensation on the data output by the adding tree circuit.

[0101] In the process of executing the calculation, the received first compensation data can be stored in the memory. When the calculation needs to be performed, the first compensation data can be read from the memory into the corresponding register, and then the output of the adder tree circuit is error compensated.

[0102] Furthermore, when the multiplier is used in a convolution circuit, the calculation method may further include the following steps:

[0103] S246. Obtain first data by accumulating outputs of multiple multipliers through a first adder.

[0104] S247. Receive second compensation data.

[0105] The second compensation data may be data pre-configured at the factory, or may be error data obtained after testing the convolution circuit using test data.

[0106] S248. Send the second compensated data to the second adder, perform error compensation on the first data, and obtain a corresponding output feature map.

[0107] Furthermore, in order to verify the reliability of the convolution circuit provided in the embodiment of the present application, the embodiment of the present application also tests the maximum quantization error of the convolution circuit corresponding to multiple input channels at different quantization scales, and the test results are shown in Table 1. Wherein, C[0] represents the digit 2 0 The corresponding encoder control line; C[1:0] represents digit 2 0 and 2 1 The corresponding encoder control line. C[2:0] represents the digit 2 0 ~2 2 The corresponding encoder control lines, and so on, are not described in detail in the embodiments of the present application.

[0108] Table 1

[0109]

[0110] In addition, the embodiment of the present application also tests the power consumption benefit (i.e., reduced power consumption) when the input signals of multiple control lines in each multiplier are 0, and the results are shown in Table 2.

[0111] Table 2

[0112]

[0113] In Table 1, each case where the maximum quantization error is less than 1 is within the maximum error constraint range, which shows that the convolution circuit reliability provided by the embodiment of the present application is good. In addition, it can be seen from Tables 1 and 2. The more input channels and the smaller the scale parameter, the smaller the quantization error, the more weights in the right encoding array, and the better the power consumption benefit. In the actual manufacturing and use process, the number of weights occupied by the right encoding array can be configured according to actual needs, and a corresponding control circuit can be set for each encoder.

[0114] In a possible implementation, the embodiment of the present application further provides a computer-readable storage medium, which stores computer program instructions, and when the computer program instructions are executed by a processor, the above-mentioned calculation method is implemented. The computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, a USB flash drive, an optical data storage device, etc.

[0115] In a possible implementation, the embodiment of the present application further provides a chip, which includes a circuit board and the above-mentioned convolution circuit or the above-mentioned multiplier arranged on the circuit board. In one example, the chip can be a processor. Among them, the convolution circuit can be used as a convolution operation unit in the processor. The multiplier can be used as a device in a computing unit in the processor that needs to perform multiplication operations. In another example, the chip can also be an independently set convolver chip or multiplier chip for sale and use, and coupled with an external device through a set interface. Among them, the specific coupling method of the interface and the external device is not specifically limited in the embodiment of the present application.

[0116] Those of ordinary skill in the art will appreciate that the functions of the circuits of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0117] In the several embodiments provided in the present application, it should be understood that the disclosed circuits and electronic devices can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0118] In addition, the chip in each embodiment of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0119] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A multiplier, characterized in that: It includes a first precoder, a first encoder group and an addition tree circuit; the multiplier is coupled to a control line, multiple weight input lines and multiple feature input lines; the first encoder group includes a control circuit and a first encoder; the control circuit is coupled to the control line, at least one feature input line among the multiple feature input lines and the first encoder; the first encoder is also coupled to a weight input line among the multiple weight input lines and the first precoder, and the first encoder is also coupled to the addition tree circuit.

2. The multiplier according to claim 1, characterized in that The multiplier is coupled to multiple control lines; the first encoder group includes multiple control circuits and multiple first encoders; wherein the weight input lines of multiple first encoders are the same, and each control circuit is coupled to a corresponding first encoder, a control line and at least one characteristic input line.

3. The multiplier according to claim 2, characterized in that The multiplier includes a plurality of the first precoders and a plurality of the first encoder groups; each of the first precoders corresponds to one of the first encoder groups, and encoders of the same digit in the plurality of the first encoder groups correspond to the same control lines.

4. The multiplier according to any one of claims 1 to 3, characterized in that: The control circuit controls the first encoder output constant through the signal input from the at least one characteristic input line and the control signal input from the control line.

5. The multiplier according to any one of claims 1 to 4, characterized in that: The control signal inputted by the control line is determined by the maximum allowable calculation error range of the multiplier.

6. The multiplier according to claim 1, characterized in that: The first encoder includes a first input terminal and a second input terminal; the control circuit is coupled to the first characteristic input line and the second characteristic input line, and the control circuit includes a first AND gate and a second AND gate; The first input terminal of the first AND gate and the first input terminal of the second AND gate are both coupled to the control line; the second input terminal of the first AND gate is coupled to the first characteristic input line; the second input terminal of the second AND gate is coupled to the second characteristic input line; the output terminal of the first AND gate is coupled to the first input terminal of the first encoder; and the output terminal of the second AND gate is coupled to the second input terminal of the first encoder.

7. The multiplier according to claim 1, characterized in that: The first encoder includes a first input terminal and a second input terminal; the control circuit is coupled to the first characteristic input line and the second characteristic input line, and the control circuit includes a first OR gate and a second OR gate; The first input terminal of the first OR gate and the first input terminal of the second OR gate are both coupled to the control line; the second input terminal of the first OR gate is coupled to the first characteristic input line; the second input terminal of the second OR gate is coupled to the second characteristic input line; the output terminal of the first OR gate is coupled to the first input terminal of the first encoder; and the output terminal of the second OR gate is coupled to the second input terminal of the first encoder.

8. The multiplier according to claim 1, characterized in that: The first encoder includes a first input terminal and a second input terminal; the control circuit is coupled to the first characteristic input line and the second characteristic input line, and the control circuit includes a first switch and a second switch; The first characteristic input line is coupled to the first input terminal of the first encoder through the first switch; the second characteristic input line is coupled to the second input terminal of the first encoder through the second switch; The controlled end of the first switch and the controlled end of the second switch are also coupled to the control line.

9. The multiplier according to claim 1, characterized in that: The first encoder includes a first input terminal and a second input terminal; the control circuit is coupled to the first characteristic input line, and the control circuit includes a third AND gate; The first input terminal of the third AND gate is coupled to the control line; the second input terminal of the third AND gate is coupled to the first characteristic input line; the first input terminal and the second input terminal of the first encoder are both coupled to the output terminal of the third AND gate.

10. The multiplier according to claim 1, characterized in that: The first encoder includes a first input terminal and a second input terminal; the control circuit is coupled to the first characteristic input line, and the control circuit includes a third OR gate; The first input terminal of the third OR gate is coupled to the control line; the second input terminal of the third OR gate is coupled to the first characteristic input line; the first input terminal and the second input terminal of the first encoder are both coupled to the output terminal of the third OR gate.

11. The multiplier according to claim 1, characterized in that: The first encoder includes a first input terminal and a second input terminal; the control circuit is coupled to the first characteristic input line, and the control circuit includes a third switch; The first input terminal and the second input terminal of the first encoder are both coupled to the first characteristic input line through the third switch; The controlled end of the third switch is also coupled to the control line.

12. The multiplier according to any one of claims 1 to 11, characterized in that: The output end of the adding tree circuit is also coupled to a compensating adding circuit; The compensation adding circuit is used to perform error compensation on the data output by the adding tree circuit according to the received compensation data.

13. The multiplier according to any one of claims 1 to 12, characterized in that: It also includes a register circuit; the register circuit includes multiple registers; each weight input line in the multiple weight input lines, each feature input line in the multiple feature input lines and the control line are respectively coupled to a register in the register circuit.

14. A convolution circuit, characterized in that: The method comprises a plurality of multipliers as claimed in any one of claims 1 to 13, and a first adder coupled to the plurality of multipliers.

15. The convolution circuit according to claim 14, characterized in that: Also includes a second adder coupled to the first adder; the second adder is also coupled to the memory; The second adder is used to perform error compensation on the data output by the first adder according to the compensation data stored in the memory.

16. The convolution circuit according to claim 14 or 15, characterized in that: The control lines corresponding to the first encoders of the same digit in the plurality of multipliers are the same.

17. A computing method, applied to a multiplier, the multiplier comprising a first precoder, a first encoder group and an adder tree circuit; and the multiplier is coupled to a plurality of weight input lines, a control line and a plurality of feature input lines; the first encoder group comprises a control circuit and a first encoder; the control circuit is coupled to the control line, at least one feature input line of the plurality of feature input lines and the first encoder; the first encoder is also coupled to a weight input line of the plurality of weight input lines and the first precoder, and the first encoder is also coupled to the adder tree circuit; characterized in that, The method comprises: Receiving a control instruction; the control instruction is used to instruct the first encoder to output a constant; inputting a control signal to the control line according to the control instruction; In response to the control signal, the control circuit controls the first encoder to output a constant.

18. The method according to claim 17, characterized in that The output end of the addition tree circuit is further coupled to a compensation addition circuit, and the method further comprises: receiving first compensation data; The first compensation data is sent to the compensation adding circuit, and the compensation adding circuit performs error compensation on the data output by the adding tree circuit.

19. The method according to claim 17 or 18, characterized in that The control signal is determined by a maximum allowable calculation error range of the multiplier.

20. A computer-readable storage medium, characterized in that: Computer program instructions are stored, and when the computer program instructions are executed by a processor, the method described in any one of claims 17-19 is implemented.

21. A chip, characterized in that: It comprises a circuit board and a convolution circuit as described in any one of claims 14 to 16, or a multiplier as described in any one of claims 1 to 13, arranged on the circuit board.

22. An electronic device, characterized in that: A device comprising a memory and a chip as claimed in claim 21 coupled to the memory.

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