Register mapping

Abstract

The mode change detection circuit detects a mode change when the processing circuit is switched between a first processing mode and a second processing mode in which a first set of architectural registers are designated to have different register lengths. Register mapping circuitry maps the architectural registers to corresponding physical registers. For an operation specifying a given architectural register of the first set of architectural registers: in response to determining that the operation is to be processed in the first processing mode, the register mapping circuitry maps the given architectural register to physical registers of a first physical register file, and in response to determining that the operation is to be processed in the second processing mode, the register mapping circuitry maps the given architectural register to a physical register of a second physical register file, the second physical register file is separate from the first physical register file and has a physical register of a different register length than a physical register of the first physical register file.

Description

Background Art Technical Field

[0001] The present technology relates to the field of data processing. Technical Background

[0003] An apparatus for data processing may have register mapping circuitry for mapping (or "renaming") architectural registers identified by instructions to physical registers provided in hardware. Register renaming may be used, for example, in an out-of-order processor to improve performance by removing some false register dependencies between instructions, thereby increasing the chance that newer instructions in program order bypass older instructions in program order. Summary of the invention

[0004] At least some examples of the present technology provide an apparatus comprising:

[0005] a mode change detection circuit for detecting a mode change when the processing circuit switches between a first processing mode in which a first set of architectural registers is designated as having a first register length and a second processing mode in which the first set of architectural registers is designated as having a second register length different from the first register length; and

[0006] A register mapping circuit, the register mapping circuit is used to map the architectural register to the corresponding physical register;

[0007] Wherein for an operation specifying a given architectural register in the first set of architectural registers:

[0008] In response to determining that the operation is to be processed in the first processing mode, the register mapping circuitry is configured to map the given architectural register to a physical register of a first physical register file; and

[0009] In response to determining that the operation is to be processed in the second processing mode, the register mapping circuitry is configured to map the given architectural register to a physical register of a second physical register file separate from the first physical register file, the second physical register file comprising physical registers having a different register length than the physical registers of the first physical register file.

[0010] At least some examples of the present technology provide a system comprising: the above-described apparatus implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.

[0011] At least some examples of the present technology provide a chip-containing product that includes the above-described system assembled on a separate board with at least one other product component.

[0012] At least some examples of the present technology provide a non-transitory computer-readable medium for storing a computer-readable code for manufacturing an apparatus, the apparatus comprising:

[0013] a mode change detection circuit for detecting a mode change when the processing circuit switches between a first processing mode in which a first set of architectural registers is designated as having a first register length and a second processing mode in which the first set of architectural registers is designated as having a second register length different from the first register length; and

[0014] A register mapping circuit, the register mapping circuit is used to map the architectural register to the corresponding physical register;

[0015] Wherein for an operation specifying a given architectural register in the first set of architectural registers:

[0016] In response to determining that the operation is to be processed in the first processing mode, the register mapping circuitry is configured to map the given architectural register to a physical register of a first physical register file; and

[0017] In response to determining that the operation is to be processed in the second processing mode, the register mapping circuitry is configured to map the given architectural register to a physical register of a second physical register file separate from the first physical register file, the second physical register file comprising physical registers having a different register length than the physical registers of the first physical register file.

[0018] At least some examples of the present technology provide a method comprising:

[0019] Mapping architectural registers to corresponding physical registers; and

[0020] detecting a mode change when the processing circuit switches between a first processing mode in which a first set of architectural registers is designated as having a first register length and a second processing mode in which the first set of architectural registers is designated as having a second register length different from the first register length;

[0021] Wherein for an operation specifying a given architectural register in the first set of architectural registers:

[0022] In response to determining that the operation is to be processed in the first processing mode, the given architectural register is mapped to a physical register of a first physical register file; and

[0023] In response to determining that the operation is to be processed in the second processing mode, the given architectural register is mapped to a physical register of a second physical register file separate from the first physical register file, the second physical register file including physical registers having a different register length than the physical registers of the first physical register file.

[0024] Further aspects, features and advantages of the present technology will be apparent from the following description of examples read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 An apparatus including a mode change detection circuit and a register mapping circuit is shown;

[0026] Figure 2 A processing device is shown;

[0027] Figure 3 The architectural register set is shown;

[0028] Figure 4A and Figure 4B An example of a stage of a processing pipeline that supports mapping a first set of architectural registers to a first physical register file for operations processed in a first mode and mapping the first set of architectural registers to a second physical register file for operations processed in a second mode is shown;

[0029] Figure 5 An example of a register commit queue for tracking a register map is shown;

[0030] Figure 6 An example of providing a register file selection indication in an entry of a rename table and a register commit queue for controlling whether a physical register corresponding to a first group of architectural registers is released from a first physical register file or a second physical register file is shown;

[0031] Figure 7 An example of using a mode change indication entry in a register commit queue to detect a transition between register map entries associated with a first mode and a second mode, respectively, is shown;

[0032] Figure 8 A method of mapping architectural registers to physical registers is shown;

[0033] Fig. 9 Mode change detection is shown;

[0034] Fig.10shows the renaming level predicate register allocation;

[0035] Fig.11 and Fig.12 Two alternative methods for controlling the recycling of predicate registers when flushing operations from a pipeline are shown;

[0036] Fig.13 and Fig.14 Two alternative methods for controlling predicate register recycling at commit operation are shown; and

[0037] Fig.15 The system and the chip-containing product are shown. DETAILED DESCRIPTION

[0038] An apparatus includes a mode change detection circuit for detecting a mode change when processing circuitry switches between a first processing mode in which a first set of architectural registers is specified as having a first register length and a second processing mode in which the first set of architectural registers is specified as having a second register length different from the first register length. Supporting processing modes associated with different architectural register lengths can be used to provide the ability to trade off processing throughput with energy efficiency.

[0039] A possible method for supporting such a first processing mode and a second processing mode in hardware may be to provide a physical register file of a size determined according to the maximum architectural register length supported in the first processing mode and the second processing mode, and to use the same physical register file for the first set of architectural registers in both the first processing mode and the second processing mode. In a processing mode requiring a smaller architectural register length, a smaller portion of each physical register of the physical register file will be accessed to provide data for the architectural register of the shorter architectural register length. In such an example, the physical registers used to provide data for the first set of architectural registers in the second mode share physical storage hardware with the physical registers used to provide data for the first set of architectural registers in the first mode. However, the disadvantage of this method is that the size of the shared physical register file is extended compared to a processor that does not support a processing mode with a maximum architectural register size, which results in additional costs in power and circuit area.

[0040] In the examples discussed below, register mapping circuitry is provided to map architectural registers to corresponding physical registers. For operations specifying a given architectural register in a first set of architectural registers:

[0041] In response to determining that the operation is to be processed in the first processing mode, the register mapping circuitry is configured to map the given architectural register to a physical register of a first physical register file; and

[0042] In response to determining that the operation is to be processed in the second processing mode, the register mapping circuitry is configured to map the given architectural register to a physical register of a second physical register file separate from the first physical register file, the second physical register file comprising physical registers having a different register length than the physical registers of the first physical register file.

[0043] Thus, the register mapping circuit changes which of the two physically distinct physical register files is selected for mapping the architectural registers in the first set of architectural registers. While one might think that selectively mapping the first set of architectural registers to either the first or second physically distinct physical register files would increase circuit area requirements, in practice there may already be an available second physical register file for the other set of architectural registers, and thus by mapping the first set of architectural registers to the second physical register file in the second mode but to the first physical register file in the first mode, this can typically avoid the need to increase the amount of register storage provided in total compared to a system supporting a shorter architectural register length for the first set of architectural registers. Thus, counter-intuitively, providing the register mapping circuit with the ability to change which physically separate physical register file is used to provide physical registers mapped to the first set of architectural registers can help save circuit area and reduce power consumption.

[0044] The register length of the physical registers of the second physical register file may be longer than the register length of the physical registers of the first physical register file. Furthermore, the maximum length supported by the device for the second register length may be greater than the maximum length supported by the device for the first register length.

[0045] For an operation that specifies a selected architectural register in the second set of architectural registers, the register mapping circuitry may map the selected architectural register to a physical register of the second physical register file, regardless of whether the operation is processed in the first processing mode or the second processing mode. For example, the second physical register file may be a register file that has been provided for mapping to the second set of architectural registers (which may have an architectural register length that is longer than the architectural register length required by the first set of architectural registers in the first mode). The second physical register file may provide the second register length required by the second processing mode. Therefore, by enabling the first set of architectural registers to be mapped to the second physical register file for operations processed in the second mode, there is no need to expand the first physical register file to support the second register length, thereby allowing a reduction in circuit area and power consumption.

[0046] The first set of architectural registers and the second set of architectural registers may be any two different sets of architectural registers defined in an instruction set architecture (ISA). The ISA may define different purposes for the first set of architectural registers compared to the second set of architectural registers.

[0047] In some examples, the second set of architectural registers includes general purpose scalar registers used to provide operands for scalar processing operations.

[0048] In some examples, the first set of architecture registers includes a predicate register for providing a predicate value for predicate SIMD (single instruction multiple data) operations. SIMD operations may include vector processing operations, matrix processing operations, or other operations performed on operands representing multiple independent data elements. Predicate values ​​can be used to indicate which channels of SIMD operands, SIMD operations, or SIMD results will be masked to prevent processing operations for those channels from affecting the results. Predicates for SIMD operations can be used to implement vectorized loops, in which the number of vector elements to be processed may be unknown at compile time but can be changed dynamically at runtime, or can be used to implement conditional operations, in which for each channel of SIMD processing, whether a corresponding operation is required depends on a test condition applied to a corresponding SIMD element in an operand or result value.

[0049] In the case where the first set of architectural registers includes predicate registers for SIMD operations, the technique of mapping the first set of architectural registers to a selectable physical register file in the first physical register file and the second physical register file is particularly useful. It may be useful to support a mode in which SIMD operations (e.g., vector operations with different vector lengths or matrix operations with different matrix sizes) are performed with different operand lengths, and therefore the predicate values ​​used to predicate those SIMD operations may also need to scale with the operand length being used. However, in a processor that does not support different processing modes associated with different predicate lengths, the physical predicate register file provided in the hardware may have registers of relatively small register lengths, and extending the predicate register file to accommodate the larger predicate register length for the second mode may result in significant area costs. There may already be a larger physical register file available for a different set of architectural registers (e.g., general scalar registers), and therefore in the second processing mode, it may be more efficient to map the architectural predicate registers to physical registers in the second physical register file, rather than providing longer physical registers in the first physical register file.

[0050] The second physical register file may have a different number of physical registers than the first physical register file. More specifically, in some examples, the second physical register file may have a greater number of physical registers than the first physical register file.

[0051] Where the second physical register file has a larger number of physical registers than the first physical register file, an additional benefit of using the second physical register file to support the second processing mode rather than extending the length of each register in the first physical register file may be that in the second processing mode there is less pressure to reclaim physical registers when they are no longer needed because there is a larger pool of registers available for reallocation when necessary.

[0052] In some examples, for an operation that specifies an identified architectural register in another set of architectural registers: determining that in response to the operation being processed in the first processing mode, the register mapping circuit is configured to map the identified architectural register to a physical register of a third physical register file that is separate from the first physical register file and the second physical register file. On the other hand, in the second processing mode, the register mapping circuit may not be responsible for mapping the identified architectural register to any corresponding physical register. The method can be used to support a specific implementation in which different execution circuits handle processing operations for at least some operation types in the first mode and the second mode, respectively.

[0053] For example, in a first processing mode, an operation specifying one of the additional set of architectural registers is to be performed by a first execution circuit, but in a second processing mode, the operation specifying one of the additional set of architectural registers is to be performed by a second execution circuit separate from the first execution circuit using a fourth physical register file separate from the first physical register file, the second physical register file, and the third physical register file.

[0054] The fourth physical register file may not require any register renaming at all (e.g. where the second execution circuitry executes operations in program order), or the second execution circuitry may be associated with its own dedicated register mapping circuitry for mapping the further set of architectural registers to the fourth physical register file, separate from the register mapping circuitry for performing register mapping of architectural registers to the first, second and third physical register files. In either case, it is not necessary for the register mapping circuitry handling the mapping for the first set of architectural registers to support any register mapping of the further set of architectural registers for operations executed in the second processing mode.

[0055] The additional set of architectural registers may be designated as having different register lengths in the first mode and the second mode, respectively. For example, the additional set of architectural registers may be SIMD registers (e.g., vector registers or registers providing matrix operands) for providing operands that may be predicated based on predicate values ​​associated with the first set of architectural registers.

[0056] The first processing mode and the second processing mode may be associated with separate first and second items of register length indication state information. For operations processed in the first processing mode, the first register length of the first set of architectural registers may depend on the first item of register length indication state information (and similarly, the register length of another set of architectural registers may also depend on the first item of register length indication state information). For operations processed in the second processing mode, the second register length of the first set of architectural registers may depend on the second item of register length indication state information (and similarly, the register length for another set of architectural registers in the second mode may also depend on the second item of register length indication state information). Therefore, the mode may be associated with different architectural state items that control or specify the register lengths in the two modes. Such an architectural separation that provides a state indicating the two modes can be used to achieve fast switching between different register lengths, and / or help support micro-architecture implementations that can use different processing hardware to process the same type of operations in the first mode and the second mode, respectively (this can be used to allow more customized hardware to be provided that targets longer register lengths to accelerate high throughput operations in the second mode and to provide simpler hardware that targets shorter register lengths in the first mode).

[0057] Although the mode switch between the first processing mode and the second processing mode may be associated with a change in register length, the register length used in the first processing mode may be changed or the register length used in the second processing mode may be changed. For example, the first / second item of the register length indication state information may be programmable to respectively set the effective register length in the first / second processing mode, which may respectively affect which parts of the physical register are used to provide operands or to be written with results in the first / second mode.

[0058] Mode change detection can detect a mode change between a first mode and a second mode in different ways. For example, the mode change detection circuit can detect a mode change in response to at least one of the following: processing of a mode change instruction; and a change in mode indication state information stored in a control register. The mode change instruction can be an instruction with a dedicated opcode identifying an instruction for changing between a first mode and a second mode, or can be a system register update instruction that specifies that an update of a mode indication state stored in a control register is required. The opcode of such a system register update instruction can be the same as the opcode of a system register update instruction for other kinds of system register state updates. Additional parameters of the instruction (e.g., specified as an immediate value in the instruction encoding or specified as a value in a register referenced by the instruction) can specify which item of the system register state will actually be updated. With this approach, a general system register update instruction is used as a mode change instruction when additional parameters are encoded to identify that the mode indication state information will be updated. In either case, the mode change can be triggered by the processing of instructions included in the executed program by a software developer or compiler at a point in the program flow that is processing the program flow to be switched between modes.

[0059] The register mapping circuitry may trigger a register reset operation in response to a mode change to ensure that for a given operation processed after the mode change, the given operation specifies a particular architectural register in the first set of architectural registers for providing a source operand in the absence of any intervening operation having written to the particular architectural register between the mode change and the given operation, the source operand being considered to have a predetermined value. For example, the predetermined value may be zero or a predetermined non-zero value. The register reset operation may help provide a consistent starting point for an architectural state associated with the first set of architectural registers immediately after a mode switch, so that values ​​associated with the first set of architectural registers do not need to be transferred between the first physical register file and the second physical register file when switching processing modes (and similarly, the earlier mentioned additional set of architectural registers may also be cleared to prevent the need to transfer data between the third physical register file and the fourth physical register file when the mode is switched). This may provide a more efficient processor implementation. The ISA may specify that software programmers cannot rely on values ​​from the first set of architectural registers (or the additional set of architectural registers) remaining available after a mode change, and therefore software should assume that if one of the first set (or the additional set) of architectural registers is read after a mode change without any intervening operations having written to that particular architectural register since the mode change, then the register read will return a predetermined value, regardless of the previous state associated with that architectural register before the mode change.

[0060] The register mapping circuitry may dispatch an operation specifying a given architectural register of the first set of architectural registers to a subsequent pipeline stage in association with a register file selection indication indicating whether a physical register mapped to the given architectural register is a physical register of the first physical register file or a physical register of the second physical register file. The register file selection indication allows a later pipeline stage to determine which physical register file should be accessed to obtain an operand for the operation or which physical register file should be written to a processing result for the operation.

[0061] Register reclamation circuitry may be provided to determine whether at least one physical register to be released for reallocation is to be released from the first physical register file or the second physical register file after an operation specifying one of the first set of architectural registers is committed or flushed. A given physical register identifier may correspond to a register in the first physical register file or the second physical register file, and thus the register reclamation circuitry may support a mechanism for tracking whether a physical register corresponding to one of the first set of architectural registers for a given operation is allocated in the first physical register file or the second physical register file.

[0062] For example, a register submission queue may be provided, the register submission queue including register mapping entries representing a queue of register mappings associated with corresponding points of program flow. The register recycling circuit may identify a given physical register to be released for reallocation based on a submitted or refreshed register mapping entry of the register submission queue. For a submitted register mapping entry (an entry that can be removed from the register submission queue or overwritten in the register submission queue once the operation has been submitted and will not need to be refreshed, given physical registers are identified based on a physical register indication specified in a corresponding rename table entry, the corresponding rename table entry corresponding to an architectural register specified by the submitted register mapping entry. For a refreshed register mapping entry (e.g., an entry that can be removed from or overwritten in the register submission queue after determining that the corresponding operation has been incorrectly processed due to a misprediction or other error), the register recycling circuit identifies a given physical register based on a physical register indication specified in the refreshed register mapping entry itself.

[0063] Determining whether a given physical register is to be released in the first physical register file or the second physical register file may be accomplished in a number of different ways.

[0064] In one example, in response to detecting a mode change, the mode change detection circuit may allocate a mode change indication entry indicating a mode change to the register submission queue. The register recycling circuit may detect a transition between a first set of register mapping entries corresponding to an operation processed in a first mode (for which physical registers are released from a first physical register file upon commit or flush of those register mapping entries) and a second set of register mapping entries corresponding to an operation processed in a second mode (for which physical registers are released from a second physical register file upon commit or flush of those register mapping entries) based on the mode change indication entry. For example, the register recycling circuit may maintain a "current mode" indication and may flip the state of the current mode indication in response to detecting the mode change indication entry. When a physical register mapped to one of the first set of architectural registers is to be released, the current mode indication may be used to determine whether to release a register in the first physical register file or a register in the second physical register file. The method may help save circuit area by avoiding the need to tag register mapping entries and rename table entries associated with the mapping with an indication of which physical register file to select for the mapping of the first set of architectural registers.

[0065] Another approach may be that register map tracking structures such as register commit queues and rename tables may have entries tagged with register file selection indications to indicate which physical register file is used for a physical register allocated for one of the first set of architectural registers. Thus, the register reclaim circuitry may detect whether a physical register indicated by a flushed register map entry or the corresponding rename table entry as being mapped to one of the first set of architectural registers should be released from the first physical register file or the second physical register file based on the register file selection indication specified by the flushed register map entry or the register file selection indication specified by the corresponding rename table entry corresponding to the architectural register specified by the committed register map entry.

[0066] Specific examples will now be described with reference to the accompanying drawings.

[0067] Figure 1 An example of an apparatus 2 having a mode change detection circuit 4 and a register mapping circuit 6 is schematically shown. Figure 1The mode change detection circuit 4 detects a mode change when switching between a first processing mode and a second processing mode (not shown in FIG). The first processing mode and the second processing mode are associated with different register lengths for the first set of architectural registers (e.g., the second mode may have a larger register length than the first mode). The mode change may be detected based on the execution of a mode change instruction by the processing circuit or based on a change in mode indication state information indicating the current mode. The register mapping circuit 6 is responsible for mapping the architectural registers specified by an operation (op) to be processed by the processing circuit to physical registers implemented in hardware. The register mapping circuit 6 may also be referred to as a register renaming circuit. The register mapping circuit 6 maintains a mapping table 8 that tracks the mapping from architectural registers to physical registers. As further explained below, for a first set of architectural registers (in the specific example below, the predicate register set), the register mapping circuit 6 selects whether to map one of the first set of architectural registers specified by the operation to a physical register in the first physical register file 10 or a physical register in the second physical register file 12 based on whether the operation requiring register mapping is processed in the first mode or in the second mode.

[0068] Figure 2 A more detailed example of a data processing device 15 that may use the register mapping techniques discussed herein is shown. The device 15 has one or more processors 20 that share access to a shared memory system 22. Figure 2 An example with two such processors 20 is shown, but it should be understood that there may be a different number of processors. The processors may be homogeneous or heterogeneous - in the case of a heterogeneous multi-processing system, different processors may have different micro-architectural features. For example, each processor may be a CPU (central processing unit), a GPU (graphics processing unit), an NPU (neural processing unit - a processor dedicated to the operation of neural networks or other machine learning workloads), or other types of processors. Each processor may have: one or more execution units 24 (an example of a processing circuit), which are used to perform different kinds of processing operations; one or more physical register files 28, which provide hardware registers for storing operands of processing operations performed by the execution unit 24 and the results of the processing operations; and one or more caches, which are used to cache data or instructions obtained from the memory system 22.

[0069] like Figure 2 As shown, at least one of the processors 20 has Figure 1The mode change detection circuit 4 and register mapping circuit 6 are described, and also have a register recycling circuit 70 (which will be described in more detail later). The processor 20 has a plurality of separate physically different physical register files 30, 32, 34 for its physical register files, each of which includes a specific number of hardware registers for a given physical register length (different register files may have different numbers of registers and registers of different register lengths). For example, Figure 2 The example of the processor 20 having a predicate register file (first physical register file) 30 for storing predicate values ​​for predicated vector operations or other SIMD operations, a general register file (second physical register file) 32 for storing scalar operands and results, and a vector register file (third physical register file) 34 for storing vector / SIMD operands and vector / SIMD results for vector operations or other SIMD operations is shown. The vector / SIMD operands and results include multiple independent data elements, each of which represents an independent value separate from other data elements of the operand / result. Although in Figure 2 In the case of a processor, only one of the processors has Figure 2 Mode change detection circuitry 4, register mapping / reclaim circuitry 6, 70 and first, second and third physical register files 30, 32, 34 are shown, but in other examples two or more of the processors may have these features.

[0070] The apparatus 15 also includes a coprocessor 40 that may be shared between the processors 20 (or dedicated for use by a particular processor 20) and has its own set of execution units 42 that are dedicated to performing a particular class of processing operations. The coprocessor 40 has its own physical register file 44 and may (optionally) have its own register mapping / reclaim circuitry 46 that is separate from the register mapping circuitry 6 provided in a given processor 20. By allowing a particular class of processing operations (e.g., vector, matrix, or other SIMD processing operations) to be offloaded to the coprocessor 40 (when processed in a particular processing mode (e.g., the second processing mode described earlier)), this may free up bandwidth on the processor 20 for other operations, allow the use of a more customized set of hardware (which may support functionality not available in the execution units 24 of the processor 20 and / or may process the class of operations more efficiently than the general purpose hardware in the processor 20 itself), and / or allow the customized hardware to be shared between the processors 20, thereby avoiding the need to replicate the hardware at each individual processor 20.

[0071] Figure 3A set of architectural registers are shown that are available for reference by instructions encoded according to an instruction set architecture (ISA) supported by processing system 15 . Figure 3 The physical register files provided in the hardware for implementing these architectural registers are not shown, only which registers are logically available for reference by instructions. In this example, the ISA supports:

[0072] A general register file 50 (a second set of architectural registers) comprising general registers for specifying scalar operands for scalar processing operations;

[0073] A vector register set 52 (a third set of architectural registers) comprising vector registers for specifying vector operands for vector processing operations, matrix operations or other SIMD operations;

[0074] A predicate register set 54 (a first set of architectural registers) comprising predicate registers for specifying predicate values ​​for predicated vector, matrix or other SIMD operations; and

[0075] A set of control registers 56 for storing control values ​​for controlling the operation of processor 20. The information stored in the control registers may be automatically set in response to certain events,

[0076] Or the execution of the instruction may be programmable based on the system register update.

[0077] The ISA supported by the processing device 15 is a scalable vector ISA (also referred to as a "vector length agnostic" vector ISA) that supports vector instructions that operate on vectors of scalable vector lengths so that the same instruction sequence can be executed on devices with hardware that supports different maximum vector lengths. This allows different hardware designers of processor implementations to select different maximum vector lengths based on whether their design priorities are high performance or reduced circuit area and power consumption, while software developers do not need to customize their software to a specific hardware platform, because software written in accordance with the scalable vector ISA can be executed across any hardware platform that supports the scalable vector ISA, regardless of the specific maximum vector length supported by the specific hardware platform. Therefore, the vector length of a specific vector instruction to be used for the scalable vector ISA (and therefore the assertion length of the corresponding assertion register 54) is unknown at compile time (neither defined as fixed in the ISA itself nor specified by parameters of the software itself). The operation performed in response to a given vector instruction of the scalable vector ISA may differ depending on the vector length selected for a specific hardware implementation (e.g., hardware that supports a larger maximum vector length may process a greater number of vector elements for a given vector instruction than hardware that supports a smaller maximum vector length). Therefore, an implementation with a shorter vector length may require a larger number of loop iterations to implement a particular function than an implementation with a longer vector length.

[0078] The vector length agnostic property of a scalable vector ISA is useful because within the fixed encoding space available for encoding instructions for the ISA, it is not feasible to create different instructions for each different vector length that a processor designer may need when considering the wide range of requirements from scaling from relatively small energy efficient microcontrollers to servers and other high performance computing systems. By not having a fixed vector length known at compile time, the same ISA can be used to address multiple markets without requiring the effort of software developers to customize the code for each performance / power / area point.

[0079] In order to implement the scalable properties of the scalable vector ISA, the functionality of the vector instructions of the scalable vector ISA is architecturally referenced to a parameter (e.g., such as _ ... Figure 3The predicate register 54 may be defined by a VL 60 or SVL 59 shown in the figure, described in more detail below), where the parameter VL or SVL is unknown at compile time. Therefore, executing the same vector instruction on different systems may produce different results (usually varying according to the number of vector elements generated, a subset of the vector elements may have the same result value on different platforms, but generally speaking, a platform implementing a larger vector length may generate additional vector elements compared to a platform implementing a smaller vector length). The predicate values ​​defined in the predicate register 54 may be used to control which elements are generated in a given instance of an instruction and may be set based on a vector length agnostic principle, such as by using a comparison instruction to automatically generate the value of the predicate for a particular loop iteration or applying a generally defined predicate mode that is scalable to different vector lengths. Certain instructions may update loop control parameters (such as an element count value) to track how many vector elements have been processed so far, so that on all iterations of the loop as a whole, both implementations with wider and narrower vector lengths may ultimately achieve the same result but with different performance levels, because the implementation with a wider vector length may require fewer loop iterations than the implementation with a narrower vector length.

[0080] This particular ISA also supports two different modes for performing vector operations: a non-streaming operation mode (a first operation mode) and a streaming operation mode (a second operation mode). The mode indication status information 58 stored in the control register 56 indicates whether the current mode is a non-streaming mode or a streaming mode, and can be set in response to the execution of a mode change instruction. Scalar operations using the general register 50 can be processed in the same manner regardless of whether the current mode is a non-streaming mode or a streaming mode, but operations using the vector register 52 and the predicate register 54 can be processed differently depending on whether the current mode is a streaming mode or a non-streaming mode.

[0081] In non-streaming mode, vector registers 52 are architecturally specified as having a vector register length VL identified by a non-streaming vector length designation 60 specified in control register 56, and predicate registers 54 are architecturally specified as having a register length VL / X, where X is a constant corresponding to the minimum vector element size supported (e.g., for an implementation in which the minimum vector element size is 8 bits, X may be equal to 8). In streaming mode, vector registers 52 are architecturally specified as having a streaming mode vector length SVL identified by a streaming vector length designation 59 specified in control register 56, and predicate registers 54 are architecturally specified as having a register length SVL / X. Thus, when there is a mode change between streaming mode and non-streaming mode, both vector registers 52 and predicate registers 54 may be logically considered to have changed register lengths.

[0082] The non-streaming vector length designation 60 and the streaming mode vector length designation 59 may be implemented in different ways. In some examples, these vector length designations 60, 59 may simply be hard-wired pieces of state information that are not programmable by software and simply indicate the maximum register length supported by the hardware for each mode. This can then be read by software to identify the specific vector length implemented on the hardware executing the program, so that the same software can be executed with different vector lengths on different hardware.

[0083] In other examples, the ISA may support higher privilege software that can limit the maximum vector length that can be used by software executing in a lower privilege state. For example, in order to save power, a given software fragment may be limited so that it cannot utilize the full vector length supported in the hardware. Therefore, the vector length specification value 60, 59 may include information that can be set by software to specify the vector length to be used in each mode 60, 59. However, even if the higher privilege software imposes restrictions on the vector length, the vector length used for the application software is still unknown at compile time because it will not be known whether the actual implemented vector length in a particular processor will be greater than or less than the limit defined in the length specification value 60, 59. For a specific implementation of hardware with support for a maximum vector length smaller than the limit defined in the length specification value 60, 59, a smaller vector length than indicated by the limit will actually be used. For example, the effective vector length seen by the software may correspond to the minimum of the maximum vector length supported in the hardware for the current mode and the vector length limit set by the software. The vector length designations 60, 59 may be grouped by exception level so that different limits on maximum supported vector lengths may be specified for software executing in different exception levels (e.g., software at one exception level may be allowed to use longer vector lengths than software at another exception level).

[0084] Thus, there may be a variety of ways in which the control state information stored in control registers 56 may affect the vector length used for vector operations, but in general some state information is available that may enable software to determine the effective vector length for each mode.

[0085] Supporting both non-streaming mode and streaming mode can be useful because it can provide hardware microarchitecture designers with greater flexibility to introduce features such as Figure 2The coprocessor 40 shown, because the architecturally defined processing modes and the separate vector length indication values ​​60, 59 for the respective modes make it easier for the hardware to determine when instructions requiring vector registers should be offloaded to the coprocessor 40 or executed within the local execution unit 24 of a given processor 20. It also allows software to explicitly specify whether a particular workload would be better suited to be executed on the general purpose execution unit 24 of the processor 20 or on the more customized hardware of the coprocessor 40. This may be useful because for vector processing routines requiring smaller vectors and / or workloads in which vector operations are interspersed with scalar operations, it may be more appropriate to process vector operations on the general purpose execution unit 24 local to the processor 20 itself, while the coprocessor 40 may be more suitable for processing "streaming" workloads that require high throughput of vector operations on large data sets with relatively little need for intermediate scalar operations (e.g., workloads associated with machine learning applications such as neural network processing). To simplify microarchitectural implementation, a register reset operation may be performed to ensure that reads of vector registers 52 and predicate registers 54 after a mode change between streaming / non-streaming modes return predetermined values ​​(e.g., zero) if they occur after the mode change without any intervening writes to the registers since the mode change. This avoids the need to transfer data between registers in processor 20 and registers in coprocessor 40 upon a mode change, since the ISA specifies that software should assume that the architectural state in vector registers 52 and predicate registers 54 is cleared upon a mode change.

[0086] For such streaming workloads, longer vector lengths may be used to reduce the instruction fetch / decode overhead associated with processing a given number of vector elements. Thus, although the ISA does not require it (the vector length for non-streaming mode may be selected from a particular set of supported vector lengths, and the streaming mode vector length may be selected from a second set of supported vector lengths, wherein there is no fixed relationship between the lengths selected for non-streaming mode and streaming mode), in a specific implementation that chooses to provide a coprocessor 40 for supporting streaming vector mode, it is relatively likely that the streaming mode vector length may be greater than the non-streaming mode vector length, in some cases many times greater. As just one example (other lengths may also be used), a specific implementation may choose to implement a maximum vector length of 128 bits in non-streaming mode and 512 bits in streaming mode, wherein the predicate registers thus have an architectural vector length of 16 bits in non-streaming mode and 64 bits in streaming mode. When a coprocessor is provided, vector instructions that execute streaming mode will be expected to run on the coprocessor 40, which may have physical registers of sufficient size within its physical register file 44 to handle the maximum streaming mode vector length. Therefore, the vector physical register file 34 in the processor 20 may not need to be extended beyond the maximum vector length supported for non-streaming mode.

[0087] However, for the predicate register file 54, it may still be necessary to perform predicate calculation operations within the execution unit 24 of the processor 20, even when the current mode is streaming mode. Allowing the processor 20 to calculate predicates for streaming mode can sometimes be more efficient than using a coprocessor to perform predicate calculations, because the predicate calculation instructions can rely on scalar operands generated by scalar instructions executed on the execution unit 24 of the processor 20. Therefore, it is expected that supporting streaming mode may require the physical predicate register file 30 to be expanded in size, so that each physical register in the predicate register file 30 is sized according to the maximum streaming mode vector length supported for streaming mode. However, this may require a significant amount of additional register storage circuitry compared to a processor that does not support streaming mode.

[0088] In the examples discussed below, the need to expand the size of each physical predicate register in the predicate register file 30 is avoided by instead mapping the architectural predicate register 54 to one of the other physical register files 32, 34 for operations processed in streaming mode. This recognizes that the general purpose scalar register file 32 and / or the vector register file 34 may already have registers of sufficient size to store predicate values ​​of the predicate register 54 corresponding to the length SVL / X in streaming mode, so when the current mode is streaming mode, the register mapping circuitry 6 in the processor 20 may map the architectural predicate register to one of these other register files 32, 34. In the following examples, the general purpose register file 32 is selected for mapping the architectural predicate register 54 during streaming mode, but in other examples, the architectural predicate register 54 may be mapped from the vector register file 34 to physical registers for operations processed in streaming mode. Another advantage of using a general register file 32 or a vector register file 34 for predicate operations in streaming mode is that these register files may have a larger number of physical registers than predicate register files, so there is a larger register pool available for allocation to predicate registers. This may be useful when operations are offloaded to a coprocessor 40, because the physical separation between the processor 20 and the coprocessor 40 may mean that there may be a longer delay between the predicate values ​​calculated at the processor 20 and those values ​​that are no longer needed, so that the physical registers corresponding to those predicates can be recycled for reallocation to other architectural registers. By using a register file with a larger pool of physical registers for predicates in streaming mode, the pressure to recycle registers for reallocation is reduced, making it less likely that delays in reclaiming physical registers will cause processing stalls because there are not enough physical registers available for allocation to another architectural register. Therefore, mapping architectural predicate registers to a general register file 32 or a vector register file 34 in streaming mode can also help improve performance.

[0089] Figure 4A and Figure 4B A more detailed example of a portion of a processing pipeline included in processor 20 is schematically shown, the processing pipeline including register mapping circuitry 6 and register recycling circuitry 70, the processing pipeline supporting the ability to variably map architectural predicate registers 54 to either physical predicate register file 30 or physical general purpose register file 32 depending on the mode of operation of processing specifying one of those predicate registers 54. Figure 4A and Figure 4BA rename stage 61, an issue stage 62, an execute stage 64, and a commit stage 66 of the processing pipeline are shown. It should be understood that these are not all the stages of the pipeline, and other stages may also be provided. For example, the pipeline may also include a fetch stage and a decode stage before the rename stage 61, the fetch stage being used to fetch instructions from an instruction cache or memory, and the decode stage being used to decode the instructions to generate decoded instructions representing operations to be processed by the remaining stages of the pipeline.

[0090] exist Figure 4A At the renaming stage 61 shown, the architectural register specified by the decoded instruction is mapped to a physical register identifier (tag) identifying a physical register within one of the physical register banks 30, 32, 34 provided in the hardware. The renaming stage 61 includes register mapping circuitry 6 that is responsible for providing register mappings for the architectural predicate registers 54, the architectural general registers 50, and, in the non-streaming mode (first processing mode), for the architectural vector registers 52. In the streaming mode, the register mapping circuitry 6 within the renaming stage 61 of the processing pipeline in the processor 20 is not responsible for providing any register mapping for the architectural vector registers 52, because in the streaming mode, the coprocessor 40 is responsible for performing vector operations using the architectural vector registers, and the coprocessor 40 may have its own register mapping circuitry 46 for providing architectural to physical register mappings for the vector registers in the streaming mode, or the coprocessor 40 may not have any register mapping circuitry at all and may perform operations in a fixed one-to-one mapping between the architectural vector registers 52 and the physical registers in the physical register file 44 of the coprocessor 40.

[0091] Register mapping circuit 6 includes general renaming circuit 68-G, predicate renaming circuit 68-P and vector renaming circuit 68-V for respectively providing register renaming functions for architectural general registers 50, architectural predicate registers 54 and architectural vector registers 52. When describing features common to the three instances of renaming circuits 68-G, 68-P and 68-V, general renaming circuit 68-G, predicate renaming circuit 68-P and vector renaming circuit 68-V are generally referred to as renaming circuit 68 below.

[0092] Each renaming circuit 68 controls register mapping based on a corresponding speculative rename table (SRT) 71-G, 71-P, 71-V (generally referred to as SRT 71 when referring to features common to the three instances) and a corresponding free register list 72-G, 72-P, 72-V (generally referred to as free register list 72 when referring to features common to the three instances). SRT 71 is a table indicating the latest mapping between architectural registers 50, 52, 54 and corresponding physical registers assigned by the renaming stage 6 (including mappings assigned to speculatively processed instructions whose results have not yet been resolved). There are separate SRTs 71-G, 71-P, 71-V for indicating mappings for general registers 50, predicate registers 54, and vector registers, respectively. The SRT 71 is distinct from an architectural rename table (ART) 75-G, 75-P, 75-V maintained at the commit stage 66 for each set of architectural registers 50, 54, 52, which tracks the committed architectural to physical register mappings that represent the architectural state at a commit point, which represents a point in program flow up to which processing is known to be correct (and does not yet include any mappings allocated in the SRT 71 for speculatively processed operations that have not yet been resolved). A free register list 72-G, 72-P, 72-V identifies which physical registers in the corresponding physical register bank 32, 30, 34 are available for allocation to different architectural registers. Maintenance of the free register list 72 is controlled by the register mapping circuitry 6 at the rename stage 61 (when new physical registers are allocated) and by the reclaim circuitry 70 at the commit stage 66 (when an operation is committed or flushed from the pipeline).

[0093] When a decoded instruction representing an operation to be performed is received at the renaming stage 61, the register mapping circuit 6 determines which types of architectural registers are required by the decoded instruction. If the decoded instruction requires one or more architectural general registers 50, the corresponding architectural general register identifiers are provided to the general renaming circuit 68-G. If the decoded instruction requires one or more architectural predicate registers 54, the corresponding architectural predicate register identifiers are provided to the predicate renaming circuit 68-P. If the decoded instruction requires one or more architectural vector registers 52 and the current mode is non-streaming mode, the corresponding architectural vector register identifiers are provided to the vector renaming circuit 68-V. The same decoded instruction may require more than one of the architectural register sets 50, 52, 54, so the same instruction may trigger processing by more than one of the renaming circuit engines 68-G, 68-P, 68-V.

[0094] When a given instance of renaming circuitry 68 associated with one of the architectural register files 50, 52, 54 receives a corresponding architectural register identifier, the mapping performed by the given renaming circuitry 68 depends on whether the architectural register identifier is provided for a source register (which provides a source operand for an operation to be processed) or a destination register (which is the register to which the result of the operation is to be written). It is possible for the same architectural register to serve as both the source register and the destination register for the same decoded instruction.

[0095] For a given architectural register used as a source register, renaming circuitry 68 looks up the current register map entry for that architectural register specified in SRT 71 and outputs the physical register tag specified in that entry of the SRT. The physical register tag is an identifier of the physical register from which the source operand for the corresponding processing operation is obtained, and the physical register tag is passed to the next pipeline stage along with an indication of the operation to be performed.

[0096] For a given architectural register used as a destination register, the renaming circuit 68 selects a free physical register indicated in the free register list 72 as available for allocation, updates the SRT 71 to designate the selected physical register as the mapped physical register in the entry corresponding to the given architectural register, and outputs a physical register tag identifying the newly allocated physical register to the next pipeline stage to indicate the physical register to which the result of the corresponding processing operation is to be written. Furthermore, the renaming circuit 68 updates the free register list to indicate that the selected physical register is no longer available for allocation. Furthermore, the renaming circuit 68 allocates an entry indicating the new mapping from the given architectural register to the selected physical register to the register commit queue (RCQ) 74. Figure 5An example of an RCQ 74 is shown in more detail. The RCQ 74 is managed as a circular buffer including a plurality of RCQ entries 80, each of which specifies at least an architectural register identifier 82 of an architectural register and a physical register identifier 84 that identifies a corresponding physical register mapped to the architectural register by the rename circuit 68. An allocation pointer 86 is used by the rename circuit 68 to identify a location in the buffer where the next RCQ entry should be inserted when a new register mapping is allocated by the rename circuit 68. A commit pointer 88 is used by the reclaim circuit 70 to identify a location in the buffer corresponding to the next RCQ entry to be committed when a corresponding operation is committed. Each time a new entry is inserted into the buffer, the allocation pointer 86 is advanced to the next entry (and wraps around from the end of the buffer to the beginning of the buffer when the end of the buffer has been reached). Similarly, each time an entry is committed, the commit pointer is advanced (and wraps around from the end of the buffer to the beginning of the buffer if necessary). As discussed in more detail below, the entries of RCQ 74 represent, in program order, a sequence of register maps allocated by register mapping circuitry 6 and are used by reclaim circuitry 75 to determine which physical registers may be freed for reallocation when a speculative operation is flushed or committed.

[0097] Back to Figure 4A and Figure 4B As discussed above, for general renaming circuit 68-G, reference is made to SRT 71-G and free register list 72-G to control register mapping to map architectural general registers 50 to physical registers in general register store 32. Similarly, vector renaming circuit 68-V references SRT 71-V and free register list 72-V to map architectural vector registers 52 to physical registers in vector register store 34 (in streaming mode (second mode), it is not expected that renaming circuit 68 within processor 20 will receive any such request to map architectural vector registers, as coprocessor 40 will handle the execution of vector instructions).

[0098] However, the assertion renaming circuit 68-P changes which free register list 72 is referenced when selecting a physical register to be mapped to an architectural predicate register, depending on whether the corresponding operation is to be processed in a non-streaming mode (a first mode) or a streaming mode (a second mode). For an operation to be processed in a non-streaming mode, any assertion register referenced by the operation is mapped to the assertion register store 30, and the assertion free register list 72-P is used (and maintained after a new allocation) to track which physical registers of the assertion register store 30 are available for allocation. For an operation to be processed in a streaming mode, any assertion register is mapped to the general register store 32, and the general free register list 72-G is used (and maintained after a new allocation) to track which physical registers of the general register store 30 are available for allocation. Therefore, a communication path may be provided between the assertion renaming circuit 68-P and the general renaming circuit 68-G to allow both the assertion renaming circuit 68-P and the general renaming circuit 68-G to reference the general free register list 72-G.

[0099] The issue stage 62 issues the operation for execution by the execute stage 64 when the operands for the operation are ready. The issue stage 62 is also responsible for reading the required operands from the corresponding physical register store 30, 32, 34. Therefore, the physical register identifier provided by the rename stage 61 for each register referenced by the decoded operation is used to identify which register of the corresponding register store 30, 32, 34 will be accessed to provide the operand. For some operations, which register store will be accessed may be implicit. However, for other operations, a register file indicator may be passed from the rename stage 61 to the issue stage 62 to identify the register file to be accessed for the instruction. Specifically, for operations that require predicate registers, the register file indicator may be set by the rename stage 61 to indicate whether the predicate register will be accessed in the predicate register store 30 or the general register store 32.

[0100] Once the required operands are available, the operation is issued to execute stage 64 which performs the processing operation using one of execution units 24 and writes the result to the corresponding physical register assigned to the destination register for the operation.

[0101] The reorder buffer 73 is used by the commit stage 66 to track the out-of-order execution and submission of processing operations. The reorder buffer 73 has a plurality of entries, each of which corresponds to a given operation to be processed and specifies whether the operation has been executed. When the operation to be processed is generated by the front-end stage of the pipeline (e.g., the decoding stage or the renaming stage 61), the entry is assigned to the reorder buffer 73. If the instructions of the corresponding program are executed in the original program order, the entries are arranged in the order in which the operation will logically appear. However, the execution stage 64 can perform operations out of order in an order different from the program order, so that the newer operation whose operands are already available can bypass the older operation that is still waiting for the operand, wherein the newer operation is independent of the older operation. Therefore, when a given operation is executed, the corresponding entry in the reorder buffer 73 is updated to indicate that the operation has been executed. When a given operation tracked by the reorder buffer 73 has been executed by the execution stage 64 and there is still no older operation waiting to be submitted, the given operation can be submitted. For example, the reorder buffer submission pointer can track the reorder buffer entry corresponding to the oldest remaining unsubmitted operation that has not yet been executed. Once the operation is performed, the reorder buffer commit pointer may be advanced to the next oldest unexecuted entry, and the operation corresponding to the entry previously pointed to by the reorder buffer commit pointer (and any intermediate entries between that entry and the most recent entry pointed to by the reorder buffer commit pointer) may be committed, causing the register reclamation operation to be performed by the reclamation circuitry 70 based on the corresponding entry of the RCQ 74.

[0102] In some cases, reorder buffer entry 73 may be shared between multiple separate micro-operations executed by execute stage 64 (e.g., micro-operations handled by different execution units corresponding to the same program instruction), and if so, the entry is committed once all of those micro-operations have been executed (reorder buffer entry 73 may track how many of the micro-operations have been executed to allow a determination of when the entry can be considered committed).

[0103] When a given entry of the reorder buffer 73 is committed, the entry specifies how many corresponding RCQ entries 80 are to be allocated to the RCQ 74 by the register mapping circuitry 6 when register renaming is performed for the corresponding operation. The number of RCQ entries 80 for the committed operation may correspond to the number of destination registers associated with the operation. Accordingly, the reclaim circuitry 70 reads the specified number of RCQ entries 80 from the RCQ 74 (from a position in the RCQ 74 determined relative to the RCQ commit pointer 88) and advances the RCQ commit pointer 88 corresponding to the number of RCQ entries read so that the RCQ commit pointer 88 now points to the next uncommitted RCQ entry.

[0104] The register reclamation circuit 70 has reclamation circuits 75-G, 75-P, 75-V (generally referred to as reclamation circuits 75) for respectively reclaiming registers from the general physical register file 32, the predicate physical register file 30, and the vector physical register file 34. Each reclamation circuit 75 maintains a corresponding architectural rename table (ART) 76-G, 76-P, 76-V (generally referred to as ART76), which indicates a committed register mapping, and for each architectural register in the corresponding group of architectural registers 50, 52, 54, the committed register mapping represents the physical register storing the most recently committed architectural state for the architectural register.

[0105] When a given RCQ entry 80 is committed, the entry identifies whether the entry relates to an architectural general register, an architectural predicate register, or an architectural vector register, and the committed RCQ entry is provided to the corresponding reclamation circuitry in the reclamation circuitry 75-G, 75-P, 75-V that handles register reclamation for architectural registers of that type. The associated reclamation circuitry 75 looks up the architectural register specified in the committed RCQ entry in the associated ART 76 associated with the architectural register of that type, obtains the physical register identifier that is specified as being mapped to the architectural register in the ART 76 (the physical register identifier identifying the physical register evicted from the ART), and updates the ART entry corresponding to the architectural register identifier specified by the committed RCQ entry to indicate the physical register identified by the committed RCQ entry as the mapped physical register. Thus, the committed RCQ entry has effectively overwritten the corresponding entry of the ART 76, causing the speculative mapping assigned for the committed operation to become committed to a state that is part of the mapping represented in the ART 76. The reclaim circuit 75 may also update the free register list 72 to mark the evicted physical register previously specified in the ART entry corresponding to the committed architectural register as freed for reallocation. In some examples, there may be at least one other condition (and evicting the physical register from the ART 76) that should be satisfied before updating the free register list 72 to mark the evicted physical register as freed.

[0106] Thus, for general registers, these ART and free register list updates occur in the general ART 76-G and general free register list 72-G. For vector registers, the structures to be updated are the vector ART 76-V and vector free register list 72-V.

[0107] For predicated registers, the predicate ART 76-P is updated, but for the release of physical registers, the predicate recycling circuit 75-P may choose whether to update the general free register list 72-G or the predicate register list 72-P, depending on whether the corresponding operation whose mapping is overwritten in the ART is processed in non-streaming mode or in streaming mode. As discussed further below Figure 6 and Figure 7 As shown, there may be a number of different ways in which the reclaim circuit 75 -P may be able to identify a mode of processing a corresponding operation to allow for a determination of whether to release the corresponding physical register from the general physical register file 32 or the predicate physical register file 30 .

[0108] If a branch misprediction, data value or address misprediction, or other form of incorrect speculation occurs, a pipeline flush may be performed to flush the pipeline of some incorrectly executed operations, and processing may be rewound to a previous point in the program flow (e.g., by restoring the register map shown in ART 76 to SRT 72 and restarting execution from the operation corresponding to the commit point of the program flow represented by ART 76). This may cause individual entries of reorder buffer 73 to be flushed, thereby causing the corresponding RCQ entry to be (logically) flushed (without having to physically remove the flushed entry from RCQ 74, since an equivalent operation may be to update allocation pointer 86 associated with RCQ 74 to point to the entry following the most recent non-flushed operation, so that subsequent allocations into RCQ 74 may overwrite the previous entry corresponding to the flushed operation). When an entry is flushed from the RCQ 74, the physical register identified by the entry may be released from the associated physical register file, and accordingly the corresponding reclaim circuit 75 associated with the type of architectural register specified by the flushed RCQ entry may update the associated free register list 72 to indicate that the physical register identified by the flushed entry may now be reallocated to other architectural registers. Similarly, for flushed RCQ entries corresponding to general purpose registers or vector registers, the corresponding free register lists 72-G, 72-V are updated to indicate that the register is free for reallocation in the general purpose register file 32 or vector register file 34, but for flushed RCQ entries corresponding to predicated registers, the selection of updating the general purpose free register list 72-G or the predicated free register list 72-P is made depending on whether the mode associated with the flushed operation is a streaming mode or a non-streaming mode.

[0109] Figure 6 and Figure 7 Two alternative techniques are shown for enabling the predicate register reclaim circuit 75-P to determine whether a physical register should be released from the general register file 32 or from the predicate register file 32 when a given RCQ entry is committed or flushed. Figure 6 and Figure 7 Two separate instances of RCQ 74 are shown in rename stage 61 and commit stage 66 respectively, but they represent the same physical data structure (so only one instance of the data structure itself may be provided in hardware). Figure 6 and Figure 7 The two instances of RCQ 74 shown represent different timings of references to RCQ 74 by rename stage 61 when allocating a new register mapping for an operation and by commit stage 66 when processing a commit / flush event.

[0110] exist Figure 6 In the example of , entries of predicate SRT 71-P, ART 76-P, and RCQ 74 are tagged with register file select indicators 94 which indicate, for a predicate register map, whether the physical registers used for the map have been allocated in predicate register file 30 or general register file 32. The corresponding register file select indicator 94 also progresses through the pipeline with the operation to indicate to issue stage 62 and execute stage 64 which register file is to be accessed for reading operands and writing results corresponding to the predicate registers.

[0111] The mode change detection circuit 4 may receive a signal indicating a detected streaming mode change (e.g., the signal may be triggered based on the execution of a mode change instruction or based on a state change of the mode indication state information 58), and when receiving the signal, the mode change detection circuit 4 converts the value of the current mode indication value 96.

[0112] The predicate renaming circuit 68-P determines how to set the register file selection indicator 94 based on the current mode indication value 96, which is written to the SRT 71-P for the newly generated destination register mapping and passed downstream with the corresponding operation. The register file selection indicator 94 is set to indicate the predicate register file 30 when the current mode indication value 96 corresponds to the non-streaming mode, and is set to indicate the general register file 32 when the current mode indication value 96 corresponds to the streaming mode.

[0113] At the commit stage 66, when an RCQ entry is logically removed from the RCQ 74 upon committing the corresponding operation, the predicate register reclaim circuit 75-P determines whether the physical register identified in the entry of the ART 76-P corresponding to the architectural register specified in the committed RCQ entry should be released from the predicate free register list 72-P or the general free register list 72-G based on the register file select indicator 94 specified in the entry of the ART 76-P. Also, when an RCQ entry is flushed from the RCQ 74, the predicate register reclaim circuit 75-P determines whether the physical register identified in the entry of the ART 76-P should be released from the predicate free register list 72-P or the general free register list 72-G based on the register file select indicator 94 specified in the flushed RCQ entry 74.

[0114] Figure 7 A second example is shown in which a mode change indication entry is allocated to RCQ 74 in response to the mode change detection circuit 4 detecting a streaming mode change. The mode change indication entry is used by the recycling circuit 75-P to determine the transition between RCQ entries associated with operations processed in non-streaming mode and RCQ entries associated with operations processed in streaming mode. This approach can save circuit area because it avoids the need to extend each entry in SRT 71-P, ART 76-P, and RCQ 74 to include a register file selection indicator 94.

[0115] Therefore, in Figure 7 In the embodiment of the present invention, the mode change detection circuit 4 again maintains the current mode indication value 96 and switches the state of the mode change indication value 96 in response to the signal indicating that a mode change has occurred. When such a mode change occurs, the mode change detection circuit 4 or the register mapping circuit 6 pushes a mode change indication entry to the RCQ 74, the mode change indication entry having an encoding different from any valid encoding representing the mapping between the architectural registers and the physical registers. For example, there may be a reserved encoding that may be assigned to represent the mode change indication entry.

[0116] The operation of specifying an architectural predicate register is performed by tagged pipelines using an indication of which register file 30, 32 is selected for allocation of the corresponding physical register, but in Figure 7 In the example of , there is no need to specify such a register file designation indication in the SRT 71 -P or an entry of the RCQ 74 allocated for specifying a register map.

[0117] At the commit stage, a further portion of the mode change detection circuitry 4 is provided which maintains a second mode indication value 98. When the mode change indication entry is logically removed from the RCQ 74 when bypassed by the commit pointer (because the commit point of the program flow has passed the point of the program flow where the mode change occurs), or is logically removed from the RCQ 74 when flushed (when the commit pointer is updated to point to an entry older than the mode change indication entry), the mode change detection circuitry 4 flips the state of the second mode indication value 98 to indicate that the current operating mode is the opposite of the non-streaming mode and the streaming mode compared to before the mode change indication entry was committed or flushed.

[0118] When an RCQ entry representing a register map is committed or flushed, the predicate register reclaim circuit 75-P determines, based on the second mode indication value 98, whether a physical register (specified by the flushed RCQ entry or specified in an entry of the ART 76-P to be overwritten with the committed RCQ entry) should be released (deallocated) from the predicate register file 30 or the general register file 32, and the corresponding free register lists 72-P, 72-G are updated accordingly.

[0119] Figures 8 to 14 A flow chart showing the method performed in the above example is shown. For each flow chart, although the steps are shown as a specific logical order for exemplary purposes, it should be understood that the same function can be performed using some steps that are reordered or at least partially performed in parallel.

[0120] Figure 8 A method for controlling register mapping is shown. At step 200, register mapping circuit 6 maps architectural registers to corresponding physical registers. At step 202, when the processing circuit switches between a first processing mode (e.g., non-streaming mode) and a second processing mode (e.g., streaming mode), mode change detection circuit 4 detects a mode change. At step 204, register mapping circuit determines whether an operation specifying a given architectural register (e.g., predicate register 54) in a first set of architectural registers will be processed in the first mode or the second mode. If the operation will be processed in the first mode, then at step 206, the given architectural register is mapped to a physical register of a first physical register file (e.g., predicate register file 30). If the operation will be processed in the second mode, then at step 208, the given architectural register is mapped to a physical register of a second physical register file (e.g., general register file 32).

[0121] Fig. 9A method for responding to a mode change is shown. At step 220, the mode change detection circuitry 4 detects a mode change, for example, based on the execution of a mode change instruction (which may be a dedicated opcode indicating a streaming mode change, or a general system register update instruction specifying a parameter identifying the mode indication state information 58 as a parameter to be updated by the instruction). In response to the mode change instruction, at step 222, the processor 20 updates the architecturally defined mode indication state information 58. The mode change detection circuitry 4 may also update any local microarchitectural mode indication value 96 used by the register mapping circuitry 6 at the renaming stage 61 to keep track of which mode is the current mode.

[0122] In response to the mode change, at step 224, register mapping circuit 6 triggers a register reset operation to ensure that for a given operation processed after the mode change, the given operation specifies a specific architecture register in the first group of architecture registers for providing a source operand when no intermediate operation has been written to the specific architecture register between the mode change and the given operation, and the source operand is considered to have a predetermined value. For example, each of the physical registers currently mapped to the architecture predicate register 54 can be cleared to a predetermined value. The predetermined value can be zero or can be a predetermined non-zero value. The architecture vector register 52 can also be architecturally reset to a predetermined value in response to the mode change. This ensures a consistent starting point for the architecture state associated with the predicate register 54 and the vector register 52 after the mode transition, which can reduce the need to transfer the architecture state between the coprocessor 40 and the processor 20 when the mode changes.

[0123] if Figure 7 The method shown is used to enable the commit stage to determine which register file is used to allocate the physical register corresponding to the predicate register, then in response to the mode change, at step 226, a mode change indication entry is also allocated into the RCQ entry 74. Figure 6 If the method shown in FIG. 1 is used, step 226 is not performed.

[0124] Fig.10 A method of controlling the allocation of physical registers corresponding to architectural predicate registers at the renaming stage is shown. At step 230, an operation is received by the renaming stage 61 to designate a given architectural predicate register as a destination register (as described above, for registers used as source registers, the current mapping may be simply read from the SRT - Fig.10 The predicate register mapping circuitry 68-P is provided with an identifier of a given architectural predicate register and checks the current processing mode associated with the operation at step 232 (e.g., determines the current mode based on the microarchitectural indication 96 of the current mode maintained by the mode change detection circuitry 4).

[0125] If the current mode is the first mode, then at step 234, the predicate register mapping circuitry 68-P selects a physical register of the predicate register file 30 that is identified as free (not yet allocated) in the predicate free register list 72-P. At step 236, the predicate register mapping circuitry 68-P updates the entry of the SRT 71-P corresponding to the given architectural predicate register to specify the selected physical register selected at step 234 so as to speculatively map the architectural predicate register to a physical register in the predicate register file 30. If the predicate register is used Figure 6 8. In the method shown, the SRT mapping assigned to SRT 71-P may also specify a register file select indication 94 that identifies the physical registers to be allocated in predicate register file 30 for the mapping. At step 238, a new RCQ entry specifying the mapping from the given architectural predicate register to the selected predicate register is allocated to RCQ 74 (at the entry determined by reference allocation pointer 86), and RCQ allocation pointer 86 is updated to advance to the next entry in the RCQ. If the mapping is used, Figure 6 The method shown, the new RCQ entry specifies a register file selection indication 94, which indicates that the physical register for the mapping is allocated in the predicate register file 30. Figure 7 According to the method shown, the register file selection indication 94 is omitted from the SRT entry updated at step 236 and the RCQ entry allocated at step 238 .

[0126] If the current mode is the second mode, then at step 240, the predicate register mapping circuitry 68-P selects a physical register of the general register file 32 that is identified as free in the general free register list 72-G. At step 242, the predicate register mapping circuitry 68-P updates the entry of the SRT 71-P corresponding to the given architectural predicate register to specify the selected physical register selected at step 240, so as to speculatively map the architectural predicate register to a physical register in the general register file 32. If the architectural predicate register is used Figure 6 8. In the method shown, the SRT mapping assigned to SRT 71-P also specifies register file select indication 94 that identifies the physical registers to be allocated in general register file 32 for the mapping. At step 244, a new RCQ entry specifying the mapping from the given architectural predicate register to the selected predicate register is allocated to RCQ 74 (at the entry determined by reference allocation pointer 86), and RCQ allocation pointer 86 is updated to advance to the next entry in the RCQ. Similarly, if the mapping is performed using Figure 6The method shown, the new RCQ entry specifies a register file selection indication 94, which specifies that the physical register for this mapping has been allocated in the general register file 32. Figure 7 According to the method shown, the register file selection indication 94 is omitted from the SRT entry and the RCQ entry.

[0127] Regardless of which mode is the current mode, at step 246, operations requiring predicate registers are dispatched to a downstream pipeline stage (e.g., issue stage 62), which specifies a register file select indication indicating which register file to use to allocate the physical register corresponding to the architectural predicate register.

[0128] Fig.11 Shown in use Figure 6 In a specific implementation of the method shown, the method of asserting register recycling is performed when the RCQ entry is refreshed. At step 250, the recycling circuit 70 detects that the RCQ entry has been refreshed. The RCQ entry is detected as being refreshed when a refresh event occurs, which causes the commit pointer to be rewound to point to an entry older than the refreshed RCQ entry. In response to the RCQ entry being refreshed, at step 252, the recycling circuit 70 determines the type of the architectural register specified by the refreshed RCQ entry. If the refreshed entry specifies a general architectural register, then at step 254, the general recycling circuit 75-G updates the general free register list 72-G to mark the physical register specified in the refreshed RCQ entry as free to be reallocated. If the refreshed entry specifies a vector architectural register, then at step 256, the vector recycling circuit 75-V updates the vector free register list 72-V to mark the physical register specified in the refreshed RCQ entry as free to be reallocated.

[0129] If the flushed entry specifies an asserted architectural register, then at step 258, the assertion recycling circuit 75-P determines which register file is specified by the register file selection indicator 94 of the flushed RCQ entry. If the register file selection indicator 94 specifies an asserted register file, then at step 260, the assertion recycling circuit 75-P updates the assertion free register list 72-P to mark the physical register specified in the flushed RCQ entry as free to be reallocated. If the register file selection indicator 94 specifies a general register file, then at step 262, the assertion recycling circuit 75-P updates the general free register list 72-G to mark the physical register specified in the flushed RCQ entry as free to be reallocated.

[0130] Fig.12 Shown in use Figure 7In the specific implementation of the method shown, the method of asserting register recycling is performed when refreshing the RCQ entry. Steps 250, 252, 254, 256 and Fig.11 and therefore if the flushed RCQ entry specifies an architectural general or vector register, the physical register is released from the general physical register file 32 or the vector physical register file 34, as described above for Fig.11 However, in Fig.12 In response to the RCQ entry being flushed, if it is detected at step 270 that the flushed RCQ entry is a mode change indication entry, then at step 272, the current mode indication 98 (for tracking the register file from which the predicate register should be reclaimed) is updated to switch states and indicate a mode opposite to the mode indicated before the mode change indication entry was flushed. Moreover, if it is detected at step 252 that the flushed RCQ entry is a designated predicated architectural register, then at step 274, the predicate register reclaim circuit 75-P determines whether the current mode indication 98 indicates the first mode (non-streaming mode) or the second mode (streaming mode). If the current mode indication 98 indicates the first mode, step 260 is executed (for updating the predicate free register list 72-P to mark the physical predicate register specified in the flushed RCQ entry as free), and if the current mode indication 98 indicates the second mode, step 262 is executed (for updating the general register list 72-G to mark the physical general register specified in the flushed RCQ entry as free).

[0131] Fig.13 Shown in use Figure 6 In a specific implementation of the method shown, the method of asserting register reclamation is performed when an RCQ entry is committed. At step 280, the reclamation circuit 70 detects that the RCQ entry has been committed (when the commit pointer advances (based on the commit of the corresponding operation in the reorder buffer) to point to an entry that is newer than the committed RCQ entry). In response to detecting that the RCQ entry is committed, at step 282, the reclamation circuit 70 determines the type of architectural register specified by the committed RCQ entry. If the committed entry specifies a general architectural register, then at step 284, the general reclamation circuit 75-G updates the general free register list 72-G to mark the physical register specified in the overwritten ART entry of the ART 75-G corresponding to the architectural register specified by the committed RCQ entry as free to be reallocated. If the committed entry specifies a vector architectural register, then at step 286, the vector reclamation circuit 75-V updates the vector free register list 72-V to mark the physical register specified in the overwritten ART entry of the ART 75-V corresponding to the architectural register specified by the committed RCQ as free to be reallocated.

[0132] If the committed entry specifies an asserted architectural register, then at step 288, the assertion reclamation circuitry 75-P determines which register file is specified by the register file selection indicator 94 of the overwritten ART entry of the ART 75-P corresponding to the same architectural register as the committed RCQ entry. If the register file selection indicator 94 of the overwritten ART entry specifies an assertion register file, then at step 290, the assertion reclamation circuitry 75-P updates the assertion free register list 72-P to mark the physical register specified in the overwritten ART entry as free to be reallocated in the assertion register file 30. If the register file selection indicator 94 specifies a general register file, then at step 292, the assertion reclamation circuitry 75-P updates the general free register list 72-G to mark the physical register specified in the overwritten ART entry as free to be reallocated in the general register file 32.

[0133] Regardless of the type of architectural register specified by the submitted RCQ entry, at step 294, the reclaim circuit 70 updates the overwritten ART entry (selected from the relevant ARTs in the ARTs 75-G, 75-P, 75-V corresponding to the type of architectural register specified by the submitted RCQ entry) so that the overwritten ART entry now specifies the physical register identifier identified in the submitted RCQ entry.

[0134] Fig.14 Shown in use Figure 7 In the specific implementation of the method shown, the method of asserting register recycling is performed when the RCQ entry is submitted. Steps 280, 282, 286 and Fig.11 and therefore if the submitted RCQ entry specifies an architectural general or vector register, the physical register is released from the general physical register file 32 or the vector physical register file 34, as described above for Fig.13 Furthermore, step 294 of updating the overwritten ART entry based on the submitted RCQ entry is the same as Fig.13 The same as in.

[0135] However, in Fig.14 In response to the RCQ entry being committed, if it is detected at step 296 that the committed RCQ entry is a mode change indication entry, then at step 298, the current mode indication 98 (used to track the register file from which the predicate register should be reclaimed, the current mode indication being updated) is converted to switch states and indicate a mode opposite to the mode indicated before the mode change indication entry was committed.

[0136] Furthermore, if it is detected at step 282 that the submitted RCQ entry is a designated predicated architectural register, then at step 289, the predicate register recycling circuit 75-P determines whether the current mode indication 98 indicates the first mode (non-streaming mode) or the second mode (streaming mode). If the current mode indication 98 indicates the first mode, step 290 is executed (for updating the predicated free register list 72-P to mark the physical predicated register designated in the overwritten ART entry of the ART 75-P as free), and if the current mode indication 98 indicates the second mode, step 292 is executed (for updating the general register list 72-G to mark the physical general register designated in the overwritten ART of the ART 75-P as free).

[0137] Although for simplicity, Fig.13 and Fig.14 One approach is shown in which, upon submission of an RCQ entry specifying an architectural register corresponding to an overwritten ART entry, the physical register specified in the overwritten ART entry may be freed for reallocation, but other examples may also impose at least one other condition (in addition to evicting the physical register from the ART) that should be satisfied before the physical register may be marked as free in a free register list.

[0138] The concepts described herein may be embodied in a system including at least one packaged chip. The previously described apparatus is implemented in at least one packaged chip (or implemented in one specific chip of the system, or distributed over more than one packaged chip). At least one packaged chip is assembled on a board with at least one system component. A chip-containing product may include a system assembled on another board with at least one other product component. The system or chip-containing product may be assembled into a housing or assembled onto a structural support such as a frame or blade.

[0139] like Fig.15 As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, wherein the above-mentioned devices are implemented on one chip or distributed over two or more of the chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer can be provided as a semiconductor package, which includes a protective housing (e.g., made of metal, plastic, glass, or ceramic) that accommodates a semiconductor device that implements the above-mentioned devices and a connector such as a pad, a ball, or a pin for connecting the semiconductor device to the external environment. In the case of providing more than one chip 400, these chips can be provided as separate integrated circuits (provided as separate packages), or can be packaged into a multi-chip semiconductor package by a semiconductor provider (e.g., using an interposer, or by using three-dimensional integration to provide a multi-layer chip product including two or more vertically stacked integrated circuit layers).

[0140] In some examples, a collection of chiplets (i.e., small modular chips with specific functions) may themselves be referred to as a chip. A chiplet may be packaged individually in a semiconductor package and / or with other chiplets in a multi-chiplet semiconductor package (e.g., using an interposer, or by using three-dimensional integration to provide a multi-layer chiplet product including two or more vertically stacked integrated circuit layers).

[0141] One or more packaged chips 400 are assembled on board 402 together with at least one system component 404. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials (e.g., plastic, glass, ceramic, or a flexible substrate material such as paper, plastic, or textile material). At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include, for example, any one or more of the following: another packaged chip (e.g., provided by a different manufacturer or produced at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0142] A chip-containing product 416 is manufactured, which includes a system 406 (including board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product component 412 includes one or more additional components that are not part of system 406. As a non-exhaustive list of examples, one or more product components 412 may include: user input / output devices such as keyboards, touch screens, microphones, speakers, display screens, tactile devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical movements; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled onto additional board 414.

[0143] Plate 402 or additional plates 414 may be disposed on or within a device housing or other structural support (eg, a frame or blade) to provide a product that is user-disposable and / or intended for operational use by a person or company.

[0144] System 406 or chip-containing product 416 may be at least one of the following: an end-user product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automatic control system. For example, as a non-exhaustive list of examples, the chip-containing product may be any of the following: telecommunications equipment, a mobile phone, a tablet, a laptop, a computer, a server (e.g., a rack server or a blade server), infrastructure equipment, networking equipment, a vehicle or other automotive product, an industrial machine, a consumer device, a smart card, a credit card, smart glasses, avionics equipment, a robotic device, a camera, a television, a smart TV, a DVD player, a set-top box, a wearable device, a home appliance, a smart meter, a medical device, a heating / lighting control device, a sensor, and / or a control system for controlling public infrastructure equipment (such as a smart highway or a traffic light).

[0145] The concepts described herein may be embodied in computer readable code for fabricating devices embodying the described concepts. For example, the computer readable code may be used at one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate integrated circuits including devices embodying the concepts. The above computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0146] For example, computer readable code for making an apparatus embodying the concepts described herein may be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register transfer level (RTL) abstraction for defining one or more logic circuits of an apparatus embodying the concepts. The code may define an HDL representation of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer readable code may provide definitions embodying concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of concepts that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0147] Additionally or alternatively, the computer readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representation to generate definitions for manufacturing devices embodying the present invention. Alternatively or additionally, one or more logic synthesis processes may generate from the computer readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing the integrated circuit, or the FPGA may be deployed directly in a product.

[0148] The computer readable code may include a mixture of code representations for making a device, such as a mixture including one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and manufacturing process to make a device embodying the invention. Alternatively or additionally, concepts may be defined in a combination of a computer readable definition used in a semiconductor design and manufacturing process to make a device and computer readable code defining instructions to be executed by the defined device once manufactured.

[0149] Such computer readable code may be provided in any known transient computer readable medium (such as wired or wireless code transmission over a network) or non-transitory computer readable medium such as a semiconductor, a magnetic disk, or an optical disk. An integrated circuit manufactured using the computer readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concepts alone or collectively.

[0150] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0151] In the present application, a feature list beginning with the phrase "at least one of..." means that any one or more of those features can be provided individually or in combination. For example, "at least one of the following: [A], [B], and [C]" covers any of the following options: only A (without B or C), only B (without A or C), only C (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0152] Although exemplary embodiments of the present invention have been described in detail herein in conjunction with the accompanying drawings, it will be appreciated that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. A device, comprising: a mode change detection circuit for detecting a mode change when the processing circuit switches between a first processing mode in which a first set of architectural registers is designated as having a first register length and a second processing mode in which the first set of architectural registers is designated as having a second register length different from the first register length; and A register mapping circuit, the register mapping circuit is used to map the architectural registers to corresponding physical registers; Wherein for an operation specifying a given architectural register in the first set of architectural registers: In response to determining that the operation is to be processed in the first processing mode, the register mapping circuit is configured to map the given architectural register to a physical register of a first physical register file; and In response to determining that the operation is to be processed in the second processing mode, the register mapping circuit is configured to map the given architectural register to a physical register of a second physical register file separate from the first physical register file, the second physical register file including physical registers having a different register length than the physical registers of the first physical register file.

2. The apparatus of claim 1 , wherein for an operation specifying a selected architectural register of a second set of architectural registers, the register mapping circuit is configured to map the selected architectural register to a physical register of the second physical register file regardless of whether the operation is to be processed in the first processing mode or the second processing mode.

3. The apparatus of claim 2, wherein the second set of architectural registers comprises general purpose scalar registers for providing operands for scalar processing operations.

4. The apparatus according to any one of claims 1 to 3, wherein the first set of architectural registers comprises a predicate register for providing predicate values ​​for predicate SIMD (Single Instruction Multiple Data) operations.

5. The apparatus according to any one of claims 1 to 4, wherein the second physical register file has a different number of physical registers than the first physical register file.

6. The apparatus of any one of claims 1 to 5, wherein for an operation specifying an identified architectural register in another set of architectural registers: In response to determining that the operation is to be processed in the first processing mode, the register mapping circuit is configured to map the identified architectural register to a physical register of a third physical register file separate from the first physical register file and the second physical register file.

7. The device according to claim 6, wherein: In the second processing mode, the register mapping circuitry is not responsible for mapping the identified architectural registers to corresponding physical registers.

8. The device according to any one of claims 6 and 7, wherein: in said first processing mode, specifying that an operation of one of said further set of architectural registers is to be performed by a first execution circuit; and In the second processing mode, operations specifying one of the additional set of architectural registers are performed by second execution circuitry separate from the first execution circuitry using a fourth physical register file separate from the first physical register file, the second physical register file, and the third physical register file.

9. The apparatus of any one of claims 6 to 8, wherein the further set of architectural registers are designated to have different register lengths in the first mode and the second mode, respectively.

10. The apparatus of any one of claims 1 to 9, wherein the mode change detection circuit is configured to detect the mode change in response to at least one of: Processing of mode change instructions; and The mode stored in the control register indicates a change in state information.

11. An apparatus according to any one of claims 1 to 10, wherein the register mapping circuit is configured to trigger a register reset operation in response to the mode change to ensure that, for a given operation processed after the mode change, the given operation specifies a particular architectural register in the first set of architectural registers for providing a source operand, the source operand being deemed to have a predetermined value if no intervening operation between the mode change and the given operation has written to the particular architectural register.

12. An apparatus according to any one of claims 1 to 11, wherein the register mapping circuit is configured to dispatch the operation specifying the given architectural register in the first set of architectural registers to a subsequent pipeline stage in association with a register file selection indication, the register file selection indication indicating whether the physical register mapped to the given architectural register is a physical register of the first physical register file or a physical register of the second physical register file.

13. An apparatus according to any one of claims 1 to 12, comprising register reclamation circuitry to determine whether at least one physical register to be freed for reallocation is to be released from the first physical register file or the second physical register file after an operation specifying one of the first set of architectural registers is committed or flushed.

14. The apparatus of claim 13, the apparatus comprising a register commit queue comprising a plurality of register map entries representing a queue of register maps associated with respective points of program flow; Wherein the register reclamation circuit is configured to identify a given physical register to be freed for reallocation based on a committed or flushed register map entry of the register commit queue.

15. The device according to claim 14, wherein: In response to detecting the mode change, the mode change detection circuit is configured to allocate a mode change indication entry indicating the mode change to the register submission queue; and The register recycling circuit is configured to detect, based on the mode change indication entry, a transition between a first set of register map entries corresponding to operations processed in the first mode and a second set of register map entries corresponding to operations processed in the second mode.

16. The apparatus of claim 14 , wherein the register reclaim circuit is configured to detect whether a physical register indicated by the flushed register map entry or the corresponding rename table entry as mapping to one of the first set of architectural registers should be released from the first physical register file or the second physical register file based on a register file selection indication specified by the flushed register map entry or a register file selection indication specified by a corresponding rename table entry corresponding to the architectural register specified by the committed register map entry.

17. A system, comprising: An apparatus according to any preceding claim implemented in at least one packaged chip; at least one system component; and plate, The at least one packaged chip and the at least one system component are assembled on the board.

18. A chip-containing product, comprising the system according to claim 17, the system being assembled on a separate board with at least one other product component.

19. A non-transitory computer readable medium storing a computer readable code for manufacturing an apparatus, the apparatus comprising: a mode change detection circuit for detecting a mode change when the processing circuit switches between a first processing mode in which a first set of architectural registers is designated as having a first register length and a second processing mode in which the first set of architectural registers is designated as having a second register length different from the first register length; and A register mapping circuit, the register mapping circuit is used to map the architectural registers to corresponding physical registers; Wherein for an operation specifying a given architectural register in the first set of architectural registers: In response to determining that the operation is to be processed in the first processing mode, the register mapping circuit is configured to map the given architectural register to a physical register of a first physical register file; and In response to determining that the operation is to be processed in the second processing mode, the register mapping circuit is configured to map the given architectural register to a physical register of a second physical register file separate from the first physical register file, the second physical register file including physical registers having a different register length than the physical registers of the first physical register file.

20. A method comprising: Map architectural registers to corresponding physical registers; as well as detecting a mode change when the processing circuit switches between a first processing mode in which a first set of architectural registers is designated as having a first register length and a second processing mode in which the first set of architectural registers is designated as having a second register length different from the first register length; Wherein for an operation specifying a given architectural register in the first set of architectural registers: In response to determining that the operation is to be processed in the first processing mode, the given architectural register is mapped to a physical register of a first physical register file; and In response to determining that the operation is to be processed in the second processing mode, the given architectural register is mapped to a physical register of a second physical register file separate from the first physical register file, the second physical register file including physical registers having a different register length than the physical registers of the first physical register file.

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