Data operation method, electronic device and chip system

Abstract

The present application discloses a data operation method, electronic device, and chip system. The method may include: receiving a data operation instruction from a memory controller DDRC, the data operation instruction including a target data address; determining a target memory space from a normal data memory space and a near memory calculation PIM data memory space of the memory based on the target data address, wherein the normal data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset partition unit; and responding to the data operation instruction, performing a data operation on the target memory space based on the target data address. It can be seen that by dividing the memory into mutually independent normal data memory space and PIM data memory space, the operation instructions for normal data and the operation instructions for PIM data can be accurately distinguished, the corresponding operation instructions can be accurately executed in the memory space, and the effectiveness of data operations can be improved.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a data operation method, electronic equipment, and chip system. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the application of large language models on devices (such as mobile phones, tablets, laptops, PDAs, and wearable devices) is becoming increasingly common. In practical applications, the deployment of large language models on devices poses significant challenges to memory bandwidth. For example, with dynamic random access memory (DRAM), each time a large language model generates a token (the basic unit for model processing and understanding text), all of the model's weights must be read from DRAM. Therefore, even using the full bandwidth of DRAM, achieving ideal inference speeds is difficult.

[0003] To increase AI inference bandwidth, DRAM-based processor in memory (PIM) computing is an effective technical solution. Compared to methods that require the processor to read large model weight data from memory and perform data operations, PIM technology directly performs data operations on large model weights in the processing unit (PU) of DRAM memory. However, because the double data rate controller (DDRC) of current system-on-chip (SoC) memory controllers does not support PIM data operation instructions (such as read and write instructions), PIM functions must reuse standard memory read and write instructions. When DRAM is used for PIM data operations, it also needs to process the system's normal read and write instructions. However, the DDRC's disassembly and reordering of read and write instructions can cause conflicts between normal instructions and PIM instructions, resulting in failures of data read and write operations.

[0004] It can be seen that how to improve the effectiveness of data operations in PIM solutions is an urgent problem to be solved. Summary of the Invention

[0005] Embodiments of the present application provide a data operation method, electronic device, and chip system that can divide memory into mutually independent normal data memory space and PIM data memory space. This allows accurate distinction between normal operation instructions and PIM operation instructions based on the memory space corresponding to the target data address, and accurately executes the corresponding operation instructions in the memory space, thereby improving the effectiveness of data operations in the PIM solution.

[0006] In a first aspect, an embodiment of the present application provides a data operation method, comprising: receiving a data operation instruction from a memory controller DDRC, the data operation instruction including a target data address, the data operation instruction being sent by the DDRC based on the target data address; determining a target memory space from a normal data memory space and a near memory calculation PIM data memory space of the memory based on the target data address, wherein the normal data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset partitioning unit; and responding to the data operation instruction, performing a data operation on the target memory space based on the target data address. It can be seen that in this technical solution, by dividing the memory into mutually independent normal data memory space and PIM data memory space, operation instructions for normal data and operation instructions for PIM data can be accurately distinguished, and corresponding operation instructions can be accurately executed in the memory space, thereby improving the effectiveness of data operations in the PIM solution.

[0007] In conjunction with the first aspect, in one possible approach, determining a target memory space in a memory based on a target data address includes: obtaining memory space configuration information, the memory space configuration information including address information of a normal data memory space and address information of a PIM data memory space; and determining, based on the memory space configuration information and the target data address, the normal data memory space or the PIM data memory space in the memory as the target memory space. This indicates that using the memory space configuration information can accurately identify the target memory space corresponding to the current data operation instruction, allowing the data operation instruction to be accurately and efficiently executed in the target memory space.

[0008] In conjunction with the first aspect, in one possible approach, determining whether the normal data memory space or the PIM data memory space in the memory is the target memory space based on the memory space configuration information and the target data address includes: if the target data address matches the address information of the PIM data memory space, that is, the target data address falls within the address range indicated by the address information of the PIM data memory space, determining the PIM data memory space in the memory as the target memory space; and if the target data address matches the address information of the normal data memory space, that is, the target data address falls within the address range indicated by the address information of the normal data memory space, determining the normal data memory space in the memory as the target memory space. Thus, when determining the target memory space, by matching the target data address with the address information of the normal data memory space and the address information of the PIM data memory space included in the memory space configuration information, the target memory space corresponding to the current data operation instruction can be accurately identified.

[0009] In conjunction with the first aspect, in one possible embodiment, the method further includes: receiving a memory space configuration instruction issued by a processor, the memory space configuration instruction including memory space configuration information; and, in response to the memory space configuration instruction, saving the memory space configuration information. Thus, based on the memory space configuration information issued by the processor, the memory can accurately divide the memory into mutually independent normal data memory space and PIM data memory space, thereby facilitating isolation and mutual interference between different types of data operation instructions.

[0010] In conjunction with the first aspect, in one possible embodiment, the preset partitioning unit includes ranks, and the memory is partitioned according to the rank granularity. Assuming that the memory of the electronic device is dual-rank, the first rank of the dual rank is divided into normal data memory space, and the second rank is divided into PIM data memory space. In this case, all banks in all memory granules included in the first rank are used as normal data memory space, and all banks in all memory granules included in the second rank are used as PIM data memory space. In this case, performing data operations on the target memory space based on the target data address includes:

[0011] When the target memory space is a normal data memory space, for each memory particle included in the first rank, the target bank is determined from each memory particle according to the target data address, and data operations are performed on the target bank according to the target data address. It can be seen that at this time the data operation instruction is recognized by the memory as a normal data operation instruction, and it is only necessary to execute the data operation instruction on the specific bank (such as the target bank mentioned above) indicated by the target data address in the relevant memory particles (that is, each memory particle included in the first rank) to complete operations such as reading or writing normal data.

[0012] When the target memory space is the PIM data memory space, for each memory particle included in the second rank, data operations are performed on all banks of each memory particle according to the target data address. It can be seen that at this time, the data operation instruction is recognized by the memory as a PIM data operation instruction, and the data operation instruction needs to be executed on all banks of the relevant memory particles (that is, each memory particle included in the second rank) to complete operations such as reading or writing PIM data.

[0013] The first rank is different from the second rank. This shows that by dividing the memory into normal data memory space and PIM data memory space based on rank, physical isolation between the normal data memory space and the PIM data memory space can be ensured. Furthermore, data operation instructions are independently executed within the corresponding ranks, avoiding conflicts between different types of data operation instructions. This prevents data read / write failures and improves the effectiveness of data operations in the PIM solution.

[0014] In conjunction with the first aspect, in one possible embodiment, the preset partitioning unit includes a bank, and the memory is partitioned according to the granularity of the physical bank. Assuming that the memory of the electronic device is dual-rank, for any rank, denoted as the third rank, the multiple first banks of each memory cell included in the third rank are divided into normal data memory space, and the multiple second banks are divided into PIM data memory space. For example, each memory cell includes 16 banks, specifically bank 0-bank 15. The first bank can refer to bank 0-bank 7 in the memory cell, and the second bank can refer to bank 8-bank 15 in the memory cell. That is, a portion of the banks (such as the multiple first banks mentioned above) of each memory cell included in the third rank are divided into normal data memory space, and another portion of the banks (such as the multiple second banks mentioned above) are divided into PIM data memory space. In this case, performing data operations on the target memory space based on the target data address includes:

[0015] In the case where the target memory space is the normal data memory space, for each memory particle included in the third rank, the target bank corresponding to the target data address is determined from the multiple first banks allocated to the normal data memory space, and data operations are performed on the target bank according to the target data address. It can be seen that at this time, the data operation instruction is recognized by the memory as a normal data operation instruction, and it is only necessary to execute the data operation instruction on the specific bank (such as the above-mentioned target bank) indicated by the target data address in the bank allocated to the normal data memory space of the relevant memory particles (such as each memory particle included in the third rank) to complete operations such as reading or writing normal data.

[0016] When the target memory space is the PIM data memory space, for each memory particle included in the third rank, all banks allocated to the PIM data memory space (i.e., the second bank mentioned above) are determined, and data operations are performed on all second banks according to the target data address. It can be seen that at this time, the data operation instruction is recognized by the memory as a PIM data operation instruction, and the data operation instruction needs to be executed on all banks (such as the second bank mentioned above) allocated to the PIM data memory space of the relevant memory particles (such as each memory particle included in the third rank) to complete operations such as reading or writing PIM data.

[0017] The first bank is different from the second bank. This shows that by dividing the memory into normal data memory space and PIM data memory space by bank, physical isolation between the normal data memory space and the PIM data memory space is ensured. Data operation instructions are independently executed in the corresponding banks, avoiding conflicts between different types of data operation instructions. This prevents data read / write failures and improves the efficiency of data operations in the PIM solution.

[0018] In conjunction with the first aspect, in one possible manner, performing a data operation on a target memory space based on a target data address includes:

[0019] When the target memory space is the PIM data memory space, obtain the working mode of the PIM data memory space.

[0020] When the operating mode of the PIM data memory space is the PIM mode, a data operation corresponding to the PIM data operation instruction is performed on the PIM data memory space based on the target data address.

[0021] When the working mode of the PIM data memory space is not the PIM mode, a data operation corresponding to the normal data operation instruction is performed on the PIM data memory space based on the target data address.

[0022] As can be seen, when the PIM data memory space operates in PIM mode, it can execute PIM data operation instructions to read and write PIM data. When the PIM data memory space operates in a non-PIM mode (for example, normal mode), it can execute normal data operation instructions to read and write normal data. By identifying the operating mode of the PIM data memory space, PIM data memory space can be reused, thereby improving memory resource utilization.

[0023] In combination with the first aspect, in one possible embodiment, the method further includes:

[0024] Obtain a PIM mode configuration instruction issued by the processor for the PIM data memory space. In response to the PIM mode configuration instruction, set the operating mode of the PIM data memory space to PIM mode. For example, the processor may send the PIM mode configuration instruction to the memory after the electronic device is powered on, or during operation of the electronic device, after the PIM data memory space and the general data memory space are configured. This shows that the memory can flexibly set the operating mode of the PIM data memory space based on the processor configuration, helping to improve memory resource utilization.

[0025] In combination with the first aspect, in one possible embodiment, the method further includes:

[0026] When a data operation corresponding to a PIM data operation instruction is performed on the PIM data memory space based on the target data address, a normal mode configuration instruction issued by the processor for the PIM data memory space can be obtained. In response to the normal mode configuration instruction, the operating mode of the PIM data memory space is set to normal mode. Therefore, after the PIM data operation is performed on the PIM data memory space, the memory can configure the operating mode of the PIM data memory space to normal mode based on the processor configuration, thereby enabling reuse of the PIM data memory space and improving memory resource utilization.

[0027] In a second aspect, an embodiment of the present application provides another data operation method, the method comprising:

[0028] Generate a data operation instruction based on the target data address; send the data operation instruction to the memory controller DDRC, the data operation instruction is used to trigger the DDRC to send the data operation instruction to the target memory particle of the memory based on the target data address; wherein the data operation instruction is used to trigger the target memory particle to determine the target memory space of the memory based on the target data address, and perform data operations on the target memory space based on the target data address, the target memory space is the ordinary data memory space or the near memory computing PIM data memory space, the ordinary data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to the preset division unit.

[0029] It can be seen that in this technical solution, by dividing the memory into mutually independent normal data memory space and PIM data memory space, when the processor sends data operation instructions to the memory, the memory can accurately distinguish between operation instructions for normal data and operation instructions for PIM data, and accurately execute the corresponding operation instructions in the memory space, which can improve the effectiveness of data operations in the PIM solution.

[0030] In conjunction with the second aspect, in one possible implementation, the preset partitioning unit includes a rank or a bank. This division of memory into a normal data memory space and a PIM data memory space based on rank or bank granularity ensures physical isolation between the normal data memory space and the PIM data memory space. Furthermore, data operation instructions are independently executed within corresponding ranks, thereby avoiding data read / write failures and improving the effectiveness of data operations in the PIM solution.

[0031] In conjunction with the second aspect, in one possible approach, a memory space configuration instruction is sent to each memory granule included in each rank of memory. The memory space configuration instruction includes memory space configuration information, and the memory space configuration information includes address information of the normal data memory space and address information of the PIM data memory space. The memory space configuration instruction is used to trigger each memory granule to save the memory space configuration information. This shows that the processor can send memory space configuration information to the memory based on actual needs, allowing the memory to be accurately divided into mutually independent normal data memory space and PIM data memory space, which helps to isolate different types of data operation instructions from interfering with each other.

[0032] In conjunction with the second aspect, in one possible approach, a PIM mode configuration instruction is sent to a memory cell allocated to the PIM data memory space in the memory. The PIM mode configuration instruction is used to trigger the memory cell allocated to the PIM data memory space to set the operating mode of the PIM data memory space to PIM mode. For example, the processor may send the PIM mode configuration instruction to the memory after the electronic device is powered on, or during operation of the electronic device, after the configuration of the PIM data memory space and the normal data memory space is complete. This shows that the processor can flexibly control the memory to set the operating mode of the PIM data memory space as needed, thereby helping to improve memory resource utilization.

[0033] In conjunction with the second aspect, in one possible approach, when the target memory space is the PIM data memory space, a normal mode configuration instruction is sent to a memory cell allocated to the PIM data memory space. The normal mode configuration instruction triggers the memory cell allocated to the PIM data memory space to set the operating mode of the PIM data memory space to normal mode. As can be seen, after the PIM data memory space completes the PIM data operation, the processor can control the memory to set the operating mode of the PIM data memory space to normal mode, thereby enabling reuse of the PIM data memory space and improving memory resource utilization.

[0034] In a third aspect, the present application provides an electronic device comprising: one or more processors, memory and storage; the storage is coupled to the memory and the one or more processors, the storage is used to store computer program code, the computer program code includes computer instructions, and the memory calls the computer instructions to execute the method as described in any one of the first aspects above.

[0035] In a fourth aspect, the present application provides an electronic device comprising: one or more processors, memory and storage; the storage is coupled to the memory and the one or more processors, the storage is used to store computer program code, the computer program code includes computer instructions, and the one or more processors call the computer instructions to execute any method described in any one of the second aspects above.

[0036] In a fifth aspect, the present application provides a chip system, which includes a processor, a memory controller DDRC, and a memory, wherein:

[0037] a processor, configured to generate a data operation instruction based on a target data address, and send the data operation instruction to the DDRC;

[0038] DDRC, used to receive data operation instructions sent by the processor and send data operation instructions to the memory particles of the memory based on the target data address;

[0039] The memory granule of the memory is used to receive data operation instructions sent by the DDRC and determine the target memory space of the memory based on the target data address. The target memory space is the normal data memory space or the near memory computing PIM data memory space. The normal data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to the preset division unit;

[0040] The memory granules are also used to respond to data operation instructions and perform data operations on the target memory space based on the target data address. This allows the processor to divide the memory into independent normal data memory space and PIM data memory space. When the memory receives a data operation instruction, it can accurately distinguish between operations targeting normal data and operations targeting PIM data and accurately execute the corresponding operations in the memory space, thereby improving the effectiveness of data operations in the PIM solution.

[0041] In conjunction with the fifth aspect, in one possible embodiment, the memory granules include processing units (PUs) corresponding to the PIM data memory space, but do not include PUs corresponding to the normal data memory space. This technical solution configures processing units (PUs) only for the PIM data memory space. For example, a PU is configured only for each bank allocated to the PIM data memory space, while no PU is configured for each bank allocated to the normal data memory space. This improves the efficiency of data operations in the PIM solution while reducing memory costs and memory size, thereby facilitating the miniaturization and lightweight design of electronic devices.

[0042] In a sixth aspect, the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed by memory particles of a memory, the method described in any one of the first aspects above is implemented.

[0043] In a seventh aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the method described in any one of the second aspects above.

[0044] In an eighth aspect, the present application provides a computer program product comprising instructions, which, when executed on an electronic device, enables the memory particles of the memory of the electronic device to execute the method as described in any one of the above-mentioned first aspects.

[0045] In a ninth aspect, the present application provides a computer program product comprising instructions, which, when executed on an electronic device, enables a processor of the electronic device to execute any of the methods described in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1a A schematic diagram illustrating the splitting and reordering of instructions in a PIM solution provided in an embodiment of the present application;

[0047] Figure 1b A schematic diagram of a data read operation in a PIM solution provided in an embodiment of the present application;

[0048] Figure 2 A flowchart of a data operation method provided in an embodiment of the present application;

[0049] Figure 3 A flowchart of another data operation method provided in an embodiment of the present application;

[0050] Figure 4a A schematic diagram of data operation for memory partitioning according to rank provided in an embodiment of the present application;

[0051] Figure 4b A schematic diagram of a memory structure provided in an embodiment of the present application;

[0052] Figure 5a A schematic diagram of data operation for performing memory division according to banks provided in an embodiment of the present application;

[0053] Figure 5b A schematic diagram of data operations within a memory cell provided in an embodiment of the present application;

[0054] Figure 6 A flowchart of another data operation method provided in an embodiment of the present application;

[0055] Figure 7 A schematic diagram of a large model reasoning calculation process provided in an embodiment of the present application;

[0056] Figure 8 A schematic diagram of the software structure of an electronic device provided in an embodiment of the present application;

[0057] Figure 9 A schematic diagram of the hardware structure of a chip system provided in an embodiment of the present application;

[0058] Figure 10 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] The terms "first", "second", "third", etc. in the embodiments of the present application are distinguished from different objects, rather than being used to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a series of steps or units are included, or optionally, steps or units that are not listed are also included, or optionally, other steps or units inherent to these processes, methods, products or devices are also included. The terms "one embodiment" or "some embodiments" etc. mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in the differences in the embodiments of the present application are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way.

[0061] In the embodiments of this application, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0062] In addition, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or plural.

[0063] In the current PIM solution, since the SoC's DDRC does not support PIM instructions, PIM instructions can be understood as read / write operations on data stored in memory in the PIM format. Data stored in the PIM format can be understood as PIM data, such as the weight data of a large language model. This requires the PIM function to reuse standard read and write instructions. In the PIM solution, there are requirements for the placement format of PIM data, such as the weight data of a large language model. PIM data must be distributed within the same physical address range of the DRAM bank. One current approach is to designate the same memory area in each bank of the DRAM memory chip to store the large model's weight data. For example, the 3rd row and 5th column of each bank are used to store PIM data, and the remaining memory area is used to store other normal data.

[0064] If a standard read or write instruction falls within a pre-defined memory area (such as the memory area within a bank where PIM data resides), the DRAM will recognize it as a PIM operation and process it for all banks. If it falls elsewhere, it will be recognized as a normal operation, valid only for the designated bank. However, since the DDRC does not support PIM instructions, processing these instructions can be challenging. For example, when a read instruction is issued by the CPU, the DDRC breaks it down into a series of instructions, including an activate instruction ("Activate") and a read instruction ("Read"). An activate instruction can activate a row in a bank, while a read instruction can read data from a column in the activated row. Furthermore, to improve efficiency, the DDRC reorders activate instructions for different banks.

[0065] The splitting and rearrangement of instructions can be as follows: Figure 1aAs shown in the figure. The CPU sends the normal read operation instruction and the PIM read operation instruction to the DDRC in sequence. After the DDRC splits and rearranges the instructions, it obtains a total of 4 instructions: normal activation instruction, PIM activation instruction, normal read instruction, and PIM read instruction. After the memory DRAM receives the above instructions, the process of executing the data read operation can be as follows Figure 1b As shown, Figure 1b The figure shows the state changes of any DRAM memory chip when executing the above four instructions, including state ① corresponding to executing a normal activation instruction, state ② corresponding to executing a PIM activation instruction, state ③ corresponding to executing a normal read instruction, and state ④ corresponding to executing a PIM read instruction.

[0066] Assume that the memory chip includes 16 banks, specifically bank 0-bank 15. The xth row, nth column of each bank is used as the memory area for storing PIM data. A normal read operation instruction targets the xth row, mth column of bank 0, which means that data needs to be read from the xth row, mth column of bank 0. A PIM read operation instruction targets the yth row, nth column of bank 15. Since it is a read operation instruction targeting the memory area storing PIM data, it will be recognized by the DRAM as a PIM read operation instruction. Therefore, it is effective for all banks, which means that data needs to be read from the yth row, nth column of all banks.

[0067] First, the internal controller of the memory chip executes the normal activation instruction to activate the xth row of bank 0, such as Figure 1b Then, the internal controller of the memory particle executes the PIM activation instruction to activate the yth row of all banks (bank 0-bank 15), as shown in Figure 1b As shown in the status ②.

[0068] Next, the internal controller of the memory chip executes a normal read instruction and needs to read data from bank 0. However, since two rows (row x and row y) of bank 0 are both active at this time, the data cannot be read correctly, resulting in a failure to read normal data. Figure 1b As shown in the status ③.

[0069] Similarly, the internal controller of the memory chip executes the PIM read instruction and needs to read data from all banks. However, since two rows (row x and row y) of bank 0 are both active at this time, data cannot be read correctly from bank 0, which ultimately leads to the failure of PIM data reading. Figure 1b As shown in the status ④.

[0070] As can be seen, DDRC is not compatible with the current PIM solution, making it impossible to correctly and efficiently read and write data without modifying the DDRC. Related technologies have attempted to adapt the DDRC to ensure correct and efficient data reading and writing in PIM solutions, by modifying the DDRC hardware design. However, this approach requires extensive DDRC adaptation, making implementation complex and costly.

[0071] Based on this, the data operation method provided in the embodiment of the present application can be applied to scenarios where an electronic device is deployed with a large end-side language model and needs to perform PIM operations on data stored in PIM format, such as the weight data of the large language model. The data operation method provided in the embodiment of the present application can divide the memory into mutually independent normal data memory space and PIM data memory space, thereby accurately distinguishing normal operation instructions from PIM operation instructions based on the memory space corresponding to the target data address, and accurately executing the corresponding operation instructions in the memory space. This can improve the effectiveness of data operations in the PIM solution, and can achieve compatibility between DDRC and PIM solutions without changing the design of DDRC, thereby reducing the implementation cost of data operations in the PIM solution.

[0072] Based on the PIM solution described above, the data operation method provided by the embodiment of this application is described below. Figure 2 , Figure 2 A flowchart of a data operation method provided in an embodiment of the present application is provided. The method may include but is not limited to the following steps:

[0073] 201. Receive a memory space configuration instruction sent by a processor, where the memory space configuration instruction includes memory space configuration information.

[0074] The memory space configuration information includes address information for the normal data memory space and address information for the near-memory computing PIM data memory space. The normal data memory space address information indicates the location of the memory area allocated to the normal data memory space, while the PIM data memory space address information indicates the location of the memory area allocated to the PIM data memory space.

[0075] Specifically, the processor of the electronic device may send a memory space configuration instruction to the DDRC of the electronic device, the DDRC forwards the memory space configuration instruction to each memory cell of the memory of the electronic device, and the memory cell receives the memory space configuration instruction.

[0076] In one embodiment, the processor may send a memory space configuration instruction to the memory cell after the electronic device is powered on, or during the operation of the electronic device.

[0077] In one embodiment, the DDRC may also save memory space configuration information, so that when the processor performs memory data operations, it can determine whether the data is located in the normal data memory space or the PIM data memory space based on the data address and the memory space configuration information, and thus forward data operation instructions to the corresponding data memory space to achieve separation of different types of operation instructions.

[0078] In one embodiment, a memory particle may also be referred to as a memory chip or Die.

[0079] 202. In response to the memory space configuration instruction, save memory space configuration information.

[0080] Specifically, the memory particles save the memory space configuration information in response to the memory space configuration instruction, that is, record the memory space configuration information. Since the memory space configuration information indicates the address information of the ordinary data memory space and the address information of the near-memory computing PIM data memory space, by saving the memory space configuration information, the memory particles can know the memory division situation, that is, the memory area corresponding to the ordinary data memory space and the memory area corresponding to the PIM data memory space in the memory.

[0081] In one embodiment, the memory space configuration information may be saved by an internal controller of the memory particle. For example, the memory space configuration information may be recorded in a mode register, or the memory space configuration information may be recorded using a designated memory space of the memory particle, thereby achieving accurate and complete recording of the memory space configuration information.

[0082] In one embodiment, the memory particles divide the memory into a normal data memory space and a PIM data memory space according to a preset partitioning unit based on the address information of the normal data memory space and the address information of the PIM data memory space included in the memory space configuration information. The normal data memory space and the PIM data memory space are different memory spaces. The memory can be divided into mutually independent normal data memory space and PIM data memory space according to the preset partitioning unit.

[0083] In one embodiment, the preset division unit may be a rank or a bank.

[0084] In one embodiment, when the address information included in the memory space configuration information is a rank identifier, the preset division unit is a rank, that is, the first rank corresponding to the rank identifier in the address information of the ordinary data memory space is used as the ordinary data memory space. At this time, all banks of the memory particles included in the first rank are divided into the ordinary data memory space. Similarly, the second rank corresponding to the rank identifier in the address information of the PIM data memory space is used as the PIM data memory space. At this time, all banks of the memory particles included in the second rank are divided into the PIM data memory space. The first rank is different from the second rank, so that the memory is divided into two independent memory spaces according to the granularity of the rank, realizing physical isolation of the ordinary data memory space and the PIM data memory space at the rank level. At this time, all memory spaces of a rank (specifically, all banks included in each memory particle in the rank) belong to the ordinary data memory space or the PIM data memory space.

[0085] In one embodiment, when the address information included in the memory space configuration information is a bank identifier, the preset division unit is a bank. That is, the first bank corresponding to the bank identifier in the address information of the normal data memory space is used as the normal data memory space. In this case, the first bank in each memory cell is divided into the normal data memory space. Similarly, the second bank corresponding to the bank identifier in the address information of the PIM data memory space is used as the PIM data memory space. In this case, the second bank in each memory cell is divided into the PIM data memory space. The first bank and the second bank are different, thereby dividing the memory into two independent memory spaces at the bank granularity, thereby achieving physical isolation between the normal data memory space and the PIM data memory space at the bank level. In this case, a portion of the memory space of each memory cell (specifically, a portion of the banks included in the memory cell) belongs to the normal data memory space, and another portion of the memory space (specifically, another portion of the banks included in the memory cell) belongs to the PIM data memory space.

[0086] 203. Obtain a PIM mode configuration instruction issued by the processor for the PIM data memory space.

[0087] Among them, the processor can perform mode management on the PIM data memory space. The working mode of the PIM data memory space can be divided into PIM mode and normal mode. In PIM mode, the PIM data memory space is used to store PIM data and can execute operation instructions of PIM data; in normal mode, the PIM data memory space is used to store normal data and can execute operation instructions of normal data.

[0088] Specifically, when the memory space configuration is completed, the processor can send a PIM mode configuration instruction for the PIM data memory space to the DDRC. The DDRC forwards the PIM mode configuration instruction to the memory particles allocated to the PIM data memory space in the memory, and the memory particles receive the PIM mode configuration instruction for the PIM data memory space.

[0089] 204. In response to the PIM mode configuration instruction, configure the operating mode of the PIM data memory space to the PIM mode.

[0090] Specifically, in response to the PIM mode configuration instruction, the memory cell configures the operating mode of the PIM data memory space to PIM mode. For example, the memory cell can use a reserved bit in a mode register to record the operating mode of the PIM data memory space and modify the value of the reserved bit to configure the operating mode of the PIM data memory space to PIM mode. Alternatively, the memory cell can use a designated memory space to record whether the current operating mode of the PIM data memory space is PIM mode or normal mode, thereby achieving effective management of the operating mode of the PIM data memory space.

[0091] In one embodiment, the reserved bit value can be 0, indicating that the operating mode of the PIM data memory space is normal mode; the reserved bit value can be 1, indicating that the operating mode of the PIM data memory space is PIM mode. The reserved bit value can be 1, indicating that the operating mode of the PIM data memory space is normal mode; the reserved bit value can be 0, indicating that the operating mode of the PIM data memory space is PIM mode. This embodiment of the application is not limited to this.

[0092] 205. Receive a data operation instruction from a memory controller DDRC, where the data operation instruction includes a target data address.

[0093] The data operation instruction is sent by the DDRC based on the target data address.

[0094] Among them, the data operation instruction can be a data read instruction or a data write instruction, which is not limited in the embodiment of the present application.

[0095] The target data address indicates the corresponding location of the data operation in the memory.

[0096] In one embodiment, the target data address includes rank information (such as rank identification), bank information (such as bank identification) and row and column information (such as row and column identification), that is, the target data address indicates the target rank targeted by this data operation, the target bank within the target rank, and the specific row and column positions within the target bank.

[0097] Specifically, the processor sends a data operation instruction to the DDRC, the DDRC determines the corresponding rank based on the target data address, and sends the data operation instruction to each memory particle included in the corresponding rank. For example, if the target data address indicates rank 0, the DDRC sends a data operation instruction to each memory particle included in rank 0, and each memory particle receives the data operation instruction from the DDRC.

[0098] In one embodiment, the DDRC can split the data operation instruction sent by the processor to obtain the split operation instructions. The DDRC sends the split operation instructions to the corresponding memory particles based on the target data address. For example, the data operation instruction sent by the processor is a read operation instruction. The operation instructions obtained after the DDRC splits the read operation instruction may include a read activation instruction and a read instruction.

[0099] 206. Determine the target memory space of the memory by matching the target data address with the memory space configuration information.

[0100] The target memory space is a common data memory space or a PIM data memory space. The common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit.

[0101] Specifically, the memory particle can obtain the saved memory space configuration information, match the target data address and the memory space configuration information to obtain a matching result, and determine the target memory space targeted by the data operation instruction based on the matching result. The target memory space is one of the ordinary data memory space and the PIM data memory space.

[0102] In one embodiment, a specific implementation of the memory granule determining the target memory space may include:

[0103] If the target data address matches the address information of the PIM data memory space, the memory chip determines the PIM data memory space in the memory as the target memory space. If the target data address matches the address information of the normal data memory space, the memory chip determines the normal data memory space in the memory as the target memory space. Thus, by matching the target data address with the address information of the normal data memory space and the address information of the PIM data memory space included in the memory space configuration information, the target memory space corresponding to the current data operation instruction can be accurately identified.

[0104] In one embodiment, when the target memory space is a normal data memory space, the memory cell identifies the data operation instruction as a normal data operation instruction and performs the corresponding data operation on the normal data memory space based on the target data address. When the target memory space is a PIM data memory space, the memory cell identifies the data operation instruction as a PIM data operation instruction and performs the corresponding data operation on the PIM data memory space based on the target data address. This eliminates the need for the DDRC to identify the type of data operation instruction. The memory cell accurately distinguishes between normal and PIM operation instructions based on the memory space corresponding to the target data address and accurately executes the corresponding operation instruction in the memory space. This improves the effectiveness of data operations in the PIM solution and enables compatibility between the DDRC and the PIM solution without changing the DDRC design.

[0105] 207. When the target memory space is a normal data memory space, perform a data operation corresponding to the normal data operation instruction on the normal data memory space based on the target data address.

[0106] Specifically, when the target memory space is a normal data memory space, the memory particle recognizes the data operation instruction as a normal data operation instruction, and performs the data operation corresponding to the normal data operation instruction on the normal data memory space based on the target data address.

[0107] 208. When the target memory space is the PIM data memory space, obtain the operating mode of the PIM data memory space.

[0108] 209. When the working mode of the PIM data memory space is the PIM mode, perform a data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address.

[0109] 210. When the working mode of the PIM data memory space is not the PIM mode, perform a data operation corresponding to a normal data operation instruction on the PIM data memory space based on the target data address.

[0110] Specifically, when the target memory space is the PIM data memory space, the memory particle may obtain the working mode of the PIM data memory space.

[0111] When the working mode of the PIM data memory space is the PIM mode, the memory chip determines that the data operation instruction is a PIM data operation instruction, and performs the data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address.

[0112] When the working mode of the PIM data memory space is not the PIM mode, the memory chip determines that the data operation instruction is a common data operation instruction, and performs a data operation corresponding to the common data operation instruction on the PIM data memory space based on the target data address.

[0113] Therefore, by identifying the working mode of the PIM data memory space, it is possible to determine whether the current data operation instruction for the PIM data memory space is a common data operation instruction or a PIM data operation instruction, thereby realizing the reuse of the PIM data memory space and helping to improve the utilization of memory resources.

[0114] In one embodiment, a memory chip includes a processing unit (PU) corresponding to the PIM data memory space and does not include a PU corresponding to the normal data memory space. The data operation instruction may be a PIM data read instruction. When the data operation corresponding to the PIM data operation instruction is performed on the PIM data memory space based on the target data address, the memory chip sends the data operation result to the PU. The data operation result may be the read PIM data (e.g., weight data of a large language model). The PU then performs arithmetic processing on the read PIM data to complete the PIM operation. Therefore, the memory chip only needs to configure a PU for the PIM data memory space. While ensuring accurate and efficient operations on PIM data, it can also reduce memory costs and size, facilitating the miniaturization and lightweight design of electronic devices.

[0115] In one embodiment, when a data operation corresponding to a PIM data operation instruction is executed on the PIM data memory space based on a target data address, i.e., when the PIM operation is completed, the processor can adjust the operating mode of the PIM data memory space so that the PIM data memory space can be used to execute normal data operation instructions. Specifically, the memory chip obtains a normal mode configuration instruction issued by the processor for the PIM data memory space and, in response to the normal mode configuration instruction, clears data from the PIM data memory space and sets the operating mode of the PIM data memory space to normal mode. Thus, when the PIM operation is completed, the data in the PIM data memory space can be cleared and the operating mode can be set to normal mode, allowing the PIM data memory space to be used for normal data read and write operations, thereby achieving memory space reuse and improving memory resource utilization.

[0116] In one embodiment, the preset partitioning unit includes ranks, the first rank of the memory is divided into a normal data memory space, and the second rank of the memory is divided into a PIM data memory space, and the first rank and the second rank are different. In this case, the specific implementation method of performing a data operation on the target memory space based on the target data address may include:

[0117] When the target memory space is a normal data memory space, the memory particle that receives the data operation instruction is the first memory particle, and the first memory particle is any memory particle included in the first rank. The first memory particle identifies the data operation instruction as a normal data operation instruction, determines the target bank from the first memory particle according to the bank information included in the target data address, and performs normal data operations on the corresponding row and column positions in the target bank according to the row and column information included in the target data address.

[0118] When the target memory space is the PIM data memory space, the memory particle that receives the data operation instruction is the second memory particle, and the second memory particle is any memory particle included in the second rank. The second memory particle identifies the data operation instruction as a PIM data operation instruction. The target data address includes certain bank information, such as the identifier of a certain bank. Since the data operation instruction is identified as a PIM data operation instruction at this time, the second memory particle performs the PIM data operation on the corresponding row and column positions in all banks of the second memory particle according to the row and column information included in the target data address.

[0119] It can be seen that by dividing the memory into ordinary data memory space and PIM data memory space according to rank, the physical isolation between the ordinary data memory space and the PIM data memory space can be guaranteed, and data operation instructions are executed independently in the corresponding rank, avoiding conflicts between different types of data operation instructions, thereby avoiding data read / write failures and improving the effectiveness of data operations in the PIM solution.

[0120] In one embodiment, a preset partitioning unit includes a bank, and memory is partitioned according to the granularity of a physical bank. Assuming that the memory of the electronic device is dual-rank, for any rank, denoted as the third rank, multiple first banks of each memory cell included in the third rank are divided into normal data memory space, and multiple second banks are divided into PIM data memory space. For example, each memory cell includes 16 banks, specifically bank 0-bank 15. The first bank may refer to bank 0-bank 7 in the memory cell, and the second bank may refer to bank 8-bank 15 in the memory cell. In other words, a portion of the banks (such as the multiple first banks described above) of each memory cell included in the third rank are divided into normal data memory space, and another portion of the banks (such as the multiple second banks described above) are divided into PIM data memory space, and the first bank and the second bank are different. In this case, a specific implementation method for performing a data operation on the target memory space based on the target data address may include:

[0121] When the target memory space is a normal data memory space, the memory particle that receives the data operation instruction is a third memory particle, and the third memory particle is any memory particle included in the third rank of the memory, that is, each third memory particle will receive the data operation instruction, and each third memory particle will identify the data operation instruction as a normal data operation instruction, and determine the target bank, such as bank 0, from the multiple first banks divided into the normal data memory space according to the bank information included in the target data address, and perform normal data operations on the corresponding row and column positions in the target bank according to the row and column information included in the target data address.

[0122] When the target memory space is the PIM data memory space, the memory particle that receives the data operation instruction is the third memory particle, and the third memory particle is any memory particle included in the third rank of the memory, that is, each third memory particle will receive the data operation instruction, and each third memory particle will identify the data operation instruction as a PIM data operation instruction. The target data address includes certain bank information, such as the identifier of a certain bank. Since the data operation instruction is identified as a PIM data operation instruction at this time, the third memory particle performs PIM data operations on the corresponding row and column positions in all banks (such as all the second banks mentioned above) divided into the PIM data memory space according to the row and column information included in the target data address.

[0123] It can be seen that by dividing the memory into normal data memory space and PIM data memory space according to banks, physical isolation between the normal data memory space and the PIM data memory space can be guaranteed, and data operation instructions are independently executed in the corresponding banks, avoiding conflicts between different types of data operation instructions, thereby preventing data read / write failures and improving the effectiveness of data operations in the PIM solution.

[0124] Based on the PIM solution described above, the data operation method provided by the embodiment of this application is described below. Figure 3 , Figure 3 A flowchart of another data operation method provided in an embodiment of the present application is provided. The method may include but is not limited to the following steps:

[0125] 301. Send a memory space configuration instruction to each memory particle included in each rank of the memory, where the memory space configuration instruction includes memory space configuration information.

[0126] The memory space configuration information includes address information of the common data memory space and address information of the PIM data memory space.

[0127] The memory space configuration instruction is used to trigger each memory particle to save the memory space configuration information to complete the configuration of the memory space.

[0128] In one embodiment, the processor of the electronic device can send a memory space configuration instruction to the DDRC after the electronic device is powered on, or during the operation of the electronic device, and the DDRC then forwards the memory space configuration instruction to each memory particle included in each rank.

[0129] 302. Send a PIM mode configuration instruction to a memory cell allocated to the PIM data memory space in the memory.

[0130] The PIM mode configuration instruction is used to trigger the memory particles allocated to the PIM data memory space to set the working mode of the PIM data memory space to the PIM mode.

[0131] Specifically, when the memory space configuration is completed, the processor can configure the working mode of the PIM data memory space. In the initial state, the working mode of the PIM data memory space can be a normal mode. When it is necessary to use the PIM data memory space to perform PIM data operations, the working mode of the PIM data memory space can be switched, and a PIM mode configuration instruction can be sent to the DDRC. Then, the DDRC sends the PIM mode configuration instruction to the memory particles allocated to the PIM data memory space in the memory.

[0132] Correspondingly, the memory cell receives the PIM mode configuration instruction and sets the working mode of the PIM data memory space to the PIM mode.

[0133] In one embodiment, the DDRC stores memory space configuration information. The DDRC can determine memory cells allocated to the PIM data memory space based on the memory space configuration information and send a PIM mode configuration instruction to the memory cells allocated to the PIM data memory space.

[0134] In one embodiment, the DDRC may send a PIM mode configuration instruction to all memory cells in the memory. Each memory cell receives the PIM mode configuration instruction and, if it determines based on the stored memory space configuration information that it is a memory cell allocated to the PIM data memory space, executes the PIM mode configuration instruction and sets the operating mode of the PIM data memory space to PIM mode. If it determines based on the stored memory space configuration information that it is not a memory cell allocated to the PIM data memory space, the PIM mode configuration instruction is not executed. For example, when the memory is divided by rank, the PIM mode configuration instruction may be executed by all memory cells included in the rank allocated to the PIM data memory space. When the memory is divided by bank, the PIM mode configuration instruction may be executed by all memory cells included in the memory.

[0135] 303. Generate a data operation instruction based on the target data address.

[0136] The target data address indicates the corresponding location of the data operation in the memory.

[0137] In one embodiment, the target data address includes rank information (such as rank identification), bank information (such as bank identification) and row and column information (such as row and column identification), that is, the target data address indicates the target rank targeted by this data operation, the target bank within the target rank, and the specific row and column positions within the target bank.

[0138] Specifically, for the processor, the storage location of the data to be read in the memory is known, including the storage location of the ordinary data in the memory and the storage location of the PIM data in the memory, or the specific location of the data to be written in the memory is known, including the memory location to be written to the ordinary data and the memory location to be written to the PIM data. According to the memory space configuration information, the target data address targeted by the data operation instruction can be determined, and the data operation instruction can be generated according to the target data address.

[0139] 304. Send a data operation instruction to the memory controller DDRC, where the data operation instruction is used to trigger the DDRC to send the data operation instruction to a target memory cell in the memory based on the target data address.

[0140] The data operation instruction is used to trigger the target memory granule to determine the target memory space of the memory based on the target data address and perform the data operation on the target memory space based on the target data address. The target memory space is the normal data memory space or the near memory computing PIM data memory space. The normal data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to the preset partition unit. The preset partition unit includes a rank or a bank.

[0141] Specifically, the processor sends a data operation instruction to the memory controller DDRC. The DDRC does not need to identify the data operation instruction, and sends the data operation instruction to the corresponding target memory particle in the memory according to the target data address. The data operation instruction is used to trigger the target memory particle to determine the target memory space of the memory based on the target data address, and perform data operations on the target memory space based on the target data address.

[0142] In one embodiment, the data operation instruction sent by the DDRC to the target memory cell may be a split operation instruction, such as an activation instruction and a specific operation instruction arranged in sequence. For a read operation, the specific instructions may be a read activation instruction and a read instruction. For a write operation, the specific instructions may be a write activation instruction and a write instruction.

[0143] Accordingly, the target memory cell receives the split operation instructions and executes them within the target memory space. For example, the target memory cell executes an activate instruction within the target memory space and then executes a specific operation instruction within the activation area. For a PIM read operation, the target memory cell can execute an activate instruction on all banks corresponding to the target memory space (in this case, the PIM data memory space) based on the target data address, and then execute the PIM read operation instruction within the activation area of ​​each bank. For a normal read operation, the target memory cell can execute an activate instruction on the corresponding bank of the target memory space (in this case, the normal data memory space) based on the target data address, and then execute a normal read operation instruction within the activation area of ​​that bank.

[0144] The specific implementation of the target memory particle determining the target memory space of the memory based on the target data address and performing data operations on the target memory space can be found in the relevant description of steps 206-210 in the above embodiment, which will not be repeated here.

[0145] It can be seen that by dividing the memory into independent normal data memory space and PIM data memory space, when the processor sends data operation instructions to the memory, the memory particles can accurately distinguish between operation instructions for normal data and operation instructions for PIM data, and accurately execute the corresponding operation instructions in the memory space, which can improve the effectiveness of data operations in the PIM solution.

[0146] 305. When the target memory space is the PIM data memory space, send a common mode configuration instruction to a memory cell allocated to the PIM data memory space in the memory.

[0147] The normal mode configuration instruction is used to trigger the memory granules allocated to the PIM data memory space to set the working mode of the PIM data memory space to the normal mode.

[0148] Specifically, if the target memory space is the PIM data memory space, the processor can, after completing a data operation on the PIM data memory space, send a normal mode configuration instruction to the memory granules allocated to the PIM data memory space. The normal mode configuration instruction triggers the memory granules allocated to the PIM data memory space to set the operating mode of the PIM data memory space to normal mode. Thus, after completing a PIM data operation on the PIM data memory space, the processor can control the memory to set the operating mode of the PIM data memory space to normal mode, thereby enabling reuse of the PIM data memory space and improving memory resource utilization.

[0149] In one embodiment, the processor can obtain memory utilization. When the memory utilization reaches a preset threshold, for example, when the memory utilization is greater than or equal to 80%, the processor sends a normal mode configuration instruction to the memory granules allocated to the PIM data memory space. Specifically, if the remaining memory is insufficient, the processor considers releasing the PIM data memory space. For example, if the memory utilization does not reach the preset threshold, the operating mode of the PIM data memory space does not need to be reconfigured during the next PIM operation, thereby ensuring efficient PIM operations. Thus, by adjusting the operating mode of the PIM data memory space based on memory usage, the normal operation of various services, including normal services and PIM services, can be ensured, thereby improving service execution efficiency.

[0150] In one embodiment, Figure 4a As shown, it is a schematic diagram of data operation for memory partitioning according to rank provided in an embodiment of the present application.

[0151] Among them, the memory rank 0 is divided into the normal data memory space (ie, normal DRAM), and the memory rank 1 is divided into the PIM data memory space (ie, PIM DRAM). The corresponding memory structure can be as follows Figure 4bIn this case, taking a data read operation as an example, the CPU sends a normal read operation instruction and a PIM read operation instruction to the DDRC. The DDRC splits the normal read operation instruction into corresponding normal activation instructions and normal read instructions. The DDRC splits the PIM read operation instruction into corresponding PIM activation instructions and PIM read instructions. The DDRC sends the normal activation instruction and normal read instruction to the normal data memory space based on the rank information (i.e., rank 0) indicated by the data address included in the normal read operation instruction. Specifically, the DDRC sends the normal activation instruction and normal read instruction to each memory chip included in rank 0. Each memory chip included in rank 0 executes the normal activation instruction and normal read instruction on the corresponding bank based on the bank information indicated by the data address. The DDRC sends the PIM activation instruction and PIM read instruction to the PIM data memory space based on the rank information (i.e., rank 1) indicated by the data address included in the PIM read operation instruction. Specifically, the DDRC sends the PIM activation instruction and PIM read instruction to each memory chip included in rank 1. Each memory chip included in rank 1 executes the PIM activation instruction and PIM read instruction on all banks.

[0152] In one embodiment, Figure 4b As shown, PIM DRAM (i.e., rank 1) uses PIM DRAM Die (including PIM DRAM Die 0, PIM DRAM Die 1, PIM DRAM Die 2, and PIM DRAM Die 3), and ordinary DRAM (i.e., rank 0) uses ordinary DRAM Die (including ordinary DRAM Die 0, ordinary DRAM Die 1, ordinary DRAM Die 2, and ordinary DRAM Die 3). Among them, each bank in the PIM DRAM Die is configured with a corresponding processing unit PU, while each bank in the ordinary DRAM Die is not configured with a corresponding PU. This can improve the effectiveness of data operations in the PIM solution while reducing memory costs and memory size, which is conducive to the miniaturization and lightweight design of electronic devices.

[0153] In one embodiment, Figure 5a , which is a schematic diagram of data operation for performing memory division according to banks provided in an embodiment of the present application.

[0154] Among them, bank 0-bank 7 of each memory chip is divided into normal data memory space (that is, normal DRAM), and bank 8-bank 15 of each memory chip is divided into PIM data memory space (that is, PIM DRAM).

[0155] In this case, taking data read operation as an example, the data operation process in each memory particle can be as follows: Figure 5b As shown. The CPU sends a normal read operation instruction and a PIM read operation instruction to the DDRC. The DDRC splits the normal read operation instruction into the corresponding normal activation instruction and normal read instruction. The DDRC splits the PIM read operation instruction into the corresponding PIM activation instruction and PIM read instruction. The DDRC sends the split and rearranged operation instructions, including the normal activation instruction, PIM activation instruction, normal read instruction, and PIM read instruction, to all memory cells in the same rank. The memory cells identify the normal activation instruction and normal read instruction as normal instructions, and the PIM activation instruction and PIM read instruction as PIM instructions based on the data addresses included in each operation instruction. They execute the normal instruction for the normal data memory space (i.e., bank 0-bank 7) within the memory cell, and execute the PIM instruction for the PIM data memory space (i.e., bank 8-bank 15) within the memory cell.

[0156] Assume that a normal instruction targets row x, column m of bank 0, meaning data needs to be read from row x, column m of bank 0. A PIM instruction targets row y, column n of bank 15. Since it is a read instruction targeting the PIM data memory space, it will be recognized by the DRAM as a PIM read instruction. Therefore, it is effective for all banks corresponding to the PIM data memory space, meaning data needs to be read from row y, column n of all banks corresponding to the PIM data memory space. The specific execution process of the instruction can be as follows:

[0157] The internal controller of the memory particle activates the xth row of bank 0 of the normal data memory space according to the data address included in the normal activation instruction (such as the xth row of bank 0), corresponding to Figure 5b Status ① in .

[0158] The internal controller of the memory chip activates the yth row of all banks (i.e. bank 8-bank 15) of the PIM data memory space according to the data address included in the PIM activation instruction (such as the yth row of bank 15), corresponding to Figure 5b Status ② in .

[0159] When executing a normal read instruction, since only the xth row of bank 0 is activated, the internal controller of the memory chip successfully reads data from the mth column of the xth row of bank 0 activated according to the data address included in the normal read instruction (such as the mth column of bank 0), corresponding to Figure 5b Status ③.

[0160] When executing the PIM read instruction, since only the yth row of banks 8-bank 15 is activated, the internal controller of the memory chip can successfully read data from the nth column of the yth row activated from banks 8-bank 15 according to the data address included in the PIM read instruction (such as the nth column of bank 15), corresponding to Figure 5b Status ④.

[0161] In one embodiment, Figure 5b As shown, only the banks corresponding to the PIM data memory space (e.g., bank 8-bank 15) can be configured with corresponding processing units (PUs), while the banks corresponding to the normal data memory space (e.g., bank 0-bank 7) are not configured with PUs. This can improve the effectiveness of data operations in the PIM solution while reducing memory costs and memory size, which is conducive to the miniaturization and lightweight design of electronic devices.

[0162] As can be seen, by dividing the memory into normal data memory space and PIM data memory space by rank or bank, physical isolation between the normal data memory space and the PIM data memory space is ensured. Data operation instructions are executed independently in the corresponding memory space, avoiding conflicts between different types of data operation instructions, thereby preventing data read / write failures and improving the effectiveness of data operations in the PIM solution. Furthermore, the DDRC does not need to be involved in instruction type identification, which means that compatibility between the DDRC and the PIM solution can be achieved without changing the DDRC design.

[0163] Based on the PIM solution described above, the data operation method provided by the embodiment of this application is described below. Figure 6 , Figure 6 A flowchart of another data operation method provided in an embodiment of the present application is provided. The method may include but is not limited to the following steps:

[0164] 601. The processor sends memory space configuration information to the DDRC.

[0165] The memory space configuration information includes address information of the common data memory space and address information of the PIM data memory space.

[0166] 602. The DDRC sends memory space configuration information to the memory cell.

[0167] Specifically, the DDRC receives the memory space configuration information sent by the processor, and sends the memory space configuration information to each memory cell of the memory.

[0168] 603. The memory granule stores memory space configuration information.

[0169] 604. The processor sends a PIM mode configuration instruction to the DDRC.

[0170] 605. The DDRC sends a PIM mode configuration instruction to the memory chip.

[0171] Specifically, the DDRC sends a PIM mode configuration instruction to a memory cell in the memory allocated to the PIM data memory space.

[0172] 606. The memory particle configures the working mode of the PIM data memory space to the PIM mode.

[0173] 607. The processor sends a data operation instruction to the DDRC.

[0174] 608. DDRC sends a data operation instruction to the memory chip.

[0175] 609. The memory particle determines the target memory space of the memory by matching the target data address included in the data operation instruction with the memory space configuration information.

[0176] 610. When the target memory space is a normal data memory space, the memory particle performs a data operation corresponding to the normal data operation instruction on the normal data memory space based on the target data address.

[0177] 611. The memory chip sends the first data operation result to the DDRC.

[0178] 612. The DDRC sends the first data operation result to the processor.

[0179] 613. When the target memory space is the PIM data memory space and the working mode of the PIM data memory space is the PIM mode, the memory particle performs a data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address.

[0180] 614. The memory chip sends the second data operation result to the PU.

[0181] The second data operation result may refer to PIM data obtained by performing a data operation corresponding to a PIM data operation instruction on a PIM data memory space, such as weight data of a large language model.

[0182] 615. The PU performs a data operation based on the second data operation result.

[0183] 616. The processor obtains the data operation result from the PU.

[0184] 617. When the target memory space is the PIM data memory space and the working mode of the PIM data memory space is not the PIM mode, the memory particle performs a data operation corresponding to the normal data operation instruction on the PIM data memory space based on the target data address.

[0185] 618. The memory chip sends the third data operation result to the DDRC.

[0186] 619. The DDRC sends the third data operation result to the processor.

[0187] The specific implementation of steps 601-619 can be found in the relevant description in the above embodiments and will not be repeated here.

[0188] Based on the PIM solution described above, the following describes the large model reasoning and calculation method provided by the embodiment of this application. Figure 7 , Figure 7 A flowchart of a large model inference calculation provided in an embodiment of the present application is provided. The method may include but is not limited to the following steps:

[0189] 701. Configure the physical address information corresponding to the PIM, with the minimum unit being bank.

[0190] The physical address information corresponding to the PIM may correspond to the address information of the PIM data memory space mentioned above.

[0191] 702. Clear or move data in the PIM DRAM and allocate the PIM DRAM to the PIM process.

[0192] 703. Load the large model weight data into the PIM DRAM.

[0193] The PIM DRAM may be a type of memory in the aforementioned PIM data memory space.

[0194] Specifically, after configuring the PIM DRAM, the processor can clear the data in the PIM DRAM or move the data to other storage spaces, such as local disk space or cloud storage. Local disk space may include universal flash storage (UFS). The processor then allocates the cleared PIM DRAM to the PIM process and loads PIM data, such as large model weights, from the current disk space into the PIM DRAM.

[0195] Among them, before the PIM DRAM is configured to PIM mode, the PIM DRAM is used as a storage space for ordinary data and can execute ordinary read and write instructions. The processor can use the write instructions of ordinary data to load large model weight data into the PIM DRAM.

[0196] 704. Configure the PIM DRAM to PIM mode.

[0197] 705. Use the PIM mode to perform large model inference calculations.

[0198] Specifically, the processor uses PIM instructions to perform inference calculations on large models. It can convert the instructions required for the calculation into read instructions for a specific PIM DRAM bank, which are then split and rearranged by the DDRC and sent to the PIM DRAM. The PIM DRAM recognizes the instructions as PIM instructions, executes the reading of the large model weight data, and uses the PU to perform arithmetic processing on the large model weight data.

[0199] It can be seen that by dividing the memory into independent normal data memory space and PIM data memory space, when executing PIM operations (such as large model inference business), normal operation instructions and PIM operation instructions are accurately distinguished according to the memory space corresponding to the data address (such as the specific PIM DRAM bank mentioned above), and the corresponding operation instructions are accurately executed in the memory space. This can improve the effectiveness of data operations in the PIM solution, thereby efficiently completing the inference calculation of large models.

[0200] 706. Configure the PIM DRAM to a normal mode to release PIM DRAM space.

[0201] Specifically, when the PIM DRAM operation processing is completed, the processor can configure the PIM DRAM to normal mode and release the PIM DRAM space. For example, the PIM DRAM space is cleared and the PIM DRAM is allocated to other processes. This can realize the reuse of the PIM data memory space and help improve the utilization of memory resources.

[0202] An embodiment of the present application also provides a software architecture for an electronic device.

[0203] In one embodiment, the software structure of the electronic device can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a microservice architecture, or a cloud architecture. The following uses the layered architecture of the Android system as an example to introduce a software structure of an electronic device.

[0204] like Figure 8As shown, the layered architecture of electronic devices can be divided into several software layers, each with clear roles and divisions of labor. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into the application layer, application framework layer, and kernel layer from top to bottom.

[0205] The application layer can include a series of application packages, including camera, gallery, video playback, map, calendar, music, call, and other applications. In the embodiment of this application, the application layer can also include an AI assistant. The AI ​​assistant can provide a variety of services such as image processing, translation, writing, shopping, etc. by leveraging the capabilities of the large language model on the terminal.

[0206] The application framework layer provides an application programming interface (API) and programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0207] The application framework layer may include a window manager. The window manager is used to manage window programs. The window manager can obtain the display size, determine whether there is a status bar, lock the screen, take screenshots, and more.

[0208] The application framework layer can also include a view system, a notification manager, and so on.

[0209] The view system includes visual controls, such as those for displaying text and images. The view system is used to build applications. A display interface can consist of one or more views. For example, a display interface containing a text notification icon might include a view for displaying text and a view for displaying images.

[0210] The notification manager enables applications to display notification information in the status bar, which can be used to convey informational messages and disappear automatically after a short stay without user interaction.

[0211] The kernel layer is the layer between hardware and software. The kernel layer includes at least display driver, camera driver, audio driver, memory driver, processor driver, etc.

[0212] It should be noted that the various functional modules included in the above software structure are merely exemplary and do not constitute a specific limitation on the software architecture of the mobile phone of this application. In other embodiments, the various functional modules included in the above software structure may be more or less, and this application does not impose any limitation on this. Although the embodiments of this application are described using the Android system as an example, the basic principles are also applicable to electronic devices based on operating systems such as iOS or Windows.

[0213] In the embodiments of the present application, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a personal digital assistant (PDA), etc., and the embodiments of the present application are not limited to this.

[0214] See Figure 9 , Figure 9 This is a hardware structure diagram of a chip system provided in an embodiment of the present application. The chip system may include but is not limited to: a processor, DDRC, and memory, wherein:

[0215] The processor is configured to generate a data operation instruction based on a target data address and send the data operation instruction to the DDRC.

[0216] DDRC is used to receive data operation instructions sent by the processor and send data operation instructions to the memory particles of the memory based on the target data address.

[0217] The memory particles of the memory are used to receive data operation instructions sent by the DDRC and determine the target memory space of the memory based on the target data address. The target memory space is the ordinary data memory space or the near memory computing PIM data memory space. The ordinary data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to the preset division unit.

[0218] The memory particles of the memory are further used to respond to data operation instructions and perform data operations on the target memory space based on the target data address.

[0219] In one embodiment, the memory granules of the memory include processing units PU corresponding to the PIM data memory space, and do not include PUs corresponding to the common data memory space.

[0220] For example, the hardware structure of the electronic device in the embodiment of the present application is introduced below.

[0221] like Figure 10 As shown, the electronic device may include: a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. Among them, the sensor module 180 can include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0222] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0223] The NPU is a neural network computing processor. Drawing on the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it rapidly processes input information and can continuously self-learn. The NPU enables intelligent cognitive applications in electronic devices, such as image recognition, face recognition, speech recognition, and text comprehension.

[0224] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0225] The internal memory 121 may be the aforementioned memory, such as a dynamic random access memory (DRAM), which is used to provide general data memory space and PIM data memory space. The electronic device may also include a DDRC, through which the processor 110 sends data operation instructions to the memory to perform read / write operations on the memory.

[0226] The electronic device implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0227] The wireless communication function of the electronic device can be implemented through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor.

[0228] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in an electronic device can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0229] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied in electronic devices. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0230] The wireless communication module 160 can provide wireless communication solutions for electronic devices, including wireless local area networks (WLAN) (such as WiFi networks), Bluetooth (Blue Tooth, BT), BLE broadcasting, global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared technology (IR), etc. The wireless communication module 160 can be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0231] The electronic device implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0232] Display screen 194 is used to display images, videos, and the like. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light emitting diode (OLED), an active matrix organic light emitting diode (AMOLED), a flexible light emitting diode (FLED), a MiniLED, a MicroLED, a MicrooLED, or a quantum dot light emitting diode (QLED). In some embodiments, the electronic device can include one or N display screens 194, where N is a positive integer greater than one.

[0233] The touch sensor 180K is also called a "touch panel." The touch sensor 180K can be disposed on the display screen 194. The touch sensor 180K and the display screen 194 form a touch screen, also called a "touch screen." The touch sensor 180K is used to detect touch operations applied thereto or in the vicinity thereof. The touch sensor 180K can transmit the detected touch operations to the application processor to determine the type of touch event. Visual output related to the touch operations can be provided via the display screen 194. In other embodiments, the touch sensor 180K can also be disposed on the surface of the electronic device, at a location different from that of the display screen 194.

[0234] It should be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than shown, or may combine or separate certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0235] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive).

[0236] It should be noted that for the aforementioned various method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0237] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0238] The modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0239] A person skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which may include: a flash drive, ROM, RAM, a magnetic disk or an optical disk, etc.

[0240] The above disclosure is only a preferred embodiment of the present application and is only a part of the embodiments of the present application. It cannot be used to limit the scope of rights of the present application.

Claims

1. A data operation method, characterized in that: Applied to memory particles, the method includes: receiving a data operation instruction from a memory controller DDRC, wherein the data operation instruction includes a target data address, and the data operation instruction is sent by the DDRC based on the target data address; Determining a target memory space of the memory based on the target data address, wherein the target memory space is a common data memory space or a near memory computing PIM data memory space, and the common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit; In response to the data operation instruction, a data operation is performed on the target memory space based on the target data address, where the data operation includes a data operation corresponding to a common data operation instruction or a data operation corresponding to a PIM data operation instruction.

2. The method according to claim 1, wherein The determining a target memory space of a memory based on the target data address includes: Obtaining memory space configuration information, where the memory space configuration information includes address information of a normal data memory space and address information of a PIM data memory space; Based on the memory space configuration information and the target data address, a normal data memory space or a PIM data memory space in the memory is determined as the target memory space.

3. The method according to claim 2, wherein The determining, based on the memory space configuration information and the target data address, the normal data memory space or the PIM data memory space in the memory as the target memory space includes: If the target data address matches the address information of the PIM data memory space, determining the PIM data memory space in the memory as the target memory space; In a case where the target data address matches the address information of the normal data memory space, the normal data memory space in the memory is determined to be the target memory space.

4. The method according to claim 2 or 3, wherein: The method further comprises: receiving a memory space configuration instruction issued by a processor, wherein the memory space configuration instruction includes memory space configuration information; In response to the memory space configuration instruction, the memory space configuration information is saved.

5. The method according to any one of claims 1 to 3, wherein The preset partitioning unit includes a rank, and performing a data operation on the target memory space based on the target data address includes: In a case where the target memory space is the normal data memory space, determining a target bank from a first memory particle according to the target data address, and performing a data operation on the target bank according to the target data address, the first memory particle being any memory particle included in a first rank allocated to the normal data memory space in the memory; When the target memory space is the PIM data memory space, performing a data operation on all banks of a second memory cell according to the target data address, where the second memory cell is any memory cell included in a second rank of the memory allocated to the PIM data memory space; The first rank is different from the second rank.

6. The method according to any one of claims 1 to 3, wherein: The preset partitioning unit includes a bank, and performing a data operation on the target memory space based on the target data address includes: In a case where the target memory space is the normal data memory space, determining a plurality of first banks included in a third memory particle and allocated to the normal data memory space, determining a target bank from the plurality of first banks according to the target data address, and performing a data operation on the target bank according to the target data address; When the target memory space is the PIM data memory space, determining all second banks allocated to the PIM data memory space from the third memory cell, and performing data operations on all the second banks according to the target data address; The third memory particle is any memory particle included in the third rank of the memory, and the first bank is different from the second bank.

7. The method according to any one of claims 1 to 3, wherein: The performing a data operation on the target memory space based on the target data address includes: When the target memory space is the PIM data memory space, obtaining an operating mode of the PIM data memory space; When the operating mode of the PIM data memory space is the PIM mode, performing a data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address; When the operating mode of the PIM data memory space is not the PIM mode, a data operation corresponding to a common data operation instruction is performed on the PIM data memory space based on the target data address.

8. The method according to claim 7, wherein The method further comprises: Obtaining a PIM mode configuration instruction issued by the processor for the PIM data memory space; In response to the PIM mode configuration instruction, the operating mode of the PIM data memory space is set to PIM mode.

9. The method according to claim 7, wherein The method further comprises: When a data operation corresponding to the PIM data operation instruction is performed on the PIM data memory space based on the target data address, obtaining a common mode configuration instruction issued by the processor for the PIM data memory space; In response to the normal mode configuration instruction, the operating mode of the PIM data memory space is set to the normal mode.

10. A data operation method, characterized in that: Applied to a processor, the method includes: generating a data operation instruction based on a target data address; Sending the data operation instruction to a memory controller DDRC, where the data operation instruction is used to trigger the DDRC to send the data operation instruction to a target memory cell of the memory based on the target data address; Among them, the data operation instruction is used to trigger the target memory particle to determine the target memory space of the memory based on the target data address, and perform data operations on the target memory space based on the target data address. The target memory space is a normal data memory space or a near memory computing PIM data memory space. The normal data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit. The data operation includes a data operation corresponding to a normal data operation instruction or a data operation corresponding to a PIM data operation instruction.

11. The method according to claim 10, wherein The preset division unit includes a rank or a bank.

12. The method according to claim 10 or 11, wherein: The method further comprises: Sending a memory space configuration instruction to each memory granule included in each rank of the memory, wherein the memory space configuration instruction includes memory space configuration information, and the memory space configuration information includes address information of the normal data memory space and address information of the PIM data memory space; The memory space configuration instruction is used to trigger each memory cell to save the memory space configuration information.

13. The method according to claim 12, wherein: The method further comprises: A PIM mode configuration instruction is sent to a memory cell allocated to the PIM data memory space in a memory, where the PIM mode configuration instruction is used to trigger the memory cell allocated to the PIM data memory space to set the working mode of the PIM data memory space to the PIM mode.

14. The method according to claim 13, wherein The method further comprises: When the target memory space is the PIM data memory space, a normal mode configuration instruction is sent to a memory cell allocated to the PIM data memory space in the memory. The normal mode configuration instruction is used to trigger the memory cell allocated to the PIM data memory space to set the operating mode of the PIM data memory space to normal mode.

15. An electronic device, characterized in that: The electronic device includes: one or more processors, storage and memory; the memory is used to store a first program code; the memory particles included in the memory are used to run the first program code to implement the method according to any one of claims 1-9.

16. An electronic device, characterized in that: The electronic device includes: one or more processors, storage and memory; the storage is used to store a second program code; the processor is used to run the second program code to implement the method according to any one of claims 10-14.

17. A chip system, characterized in that: The chip system includes a processor, a memory controller DDRC and a memory, wherein: The processor is configured to generate a data operation instruction based on a target data address and send the data operation instruction to the DDRC; The DDRC is configured to receive the data operation instruction sent by the processor, and send the data operation instruction to the memory cell of the memory based on the target data address; The memory granule of the memory is configured to receive the data operation instruction sent by the DDRC, and determine a target memory space of the memory based on the target data address, wherein the target memory space is a normal data memory space or a near memory computing (PIM) data memory space, and the normal data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit; The memory particles of the memory are further used to respond to the data operation instruction and perform data operation on the target memory space based on the target data address. The data operation includes a data operation corresponding to a normal data operation instruction or a data operation corresponding to a PIM data operation instruction.

18. The chip system according to claim 17, wherein: The memory particles of the memory include the processing units PU corresponding to the PIM data memory space, and do not include the PU corresponding to the common data memory space.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by the memory particles of the memory, implements the method according to any one of claims 1 to 9.

20. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 10 to 14 is implemented.

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