Data processing method and device

Abstract

The invention discloses a data processing method and device. In order to solve the problem that the data transmission rate of a current host and PCIe equipment is restricted by the version and channel number of a PCIe controller, the invention provides a data processing method, device and system in order to meet the service requirements. According to the data transmission method and device, the host and the different interfaces of the PCIe device are connected through the different PCIe links, and data transmission is carried out in parallel through the different PCIe links, so that the rate of data transmission through the PCIe links is increased.

Description

[0001] This application is a divisional application. The application number of the original application is 202011620686.6, and the original application date is December 30, 2020. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computing, and in particular to a method and device for data processing. Background Art

[0003] A bus is a standardized way of exchanging data between computer components, that is, providing data transmission and control logic for each component in a common way. A bus usually transmits bits between different components according to preset lines. These lines can only be responsible for transmitting one bit at a time. Therefore, multiple lines must be used at the same time to send more data, and the size of the data that the bus can transmit at the same time is called width, which is measured in bits. The larger the bus width, the better the transmission performance. The bandwidth of the bus (that is, the total data size that can be transmitted per unit time) can be calculated by multiplying the frequency by the width.

[0004] Peripheral Component Interconnect Express (PCIe) is a type of computer bus that builds a higher-speed serial communication system standard based on the programming concept and signal standard of Peripheral Component Interconnect (PCI). PCIe buses of different versions and different numbers of channels can support different maximum bandwidths. Generally speaking, the higher the version of the PCIe controller chip, the more corresponding channel data, the larger the maximum bandwidth that can be supported, and the more it can meet the real-time transmission of large amounts of data. For example, the common v3.x version has a single-channel rate of 985MB / s and 16 channels of 15.75GB / s; the current latest v5.x version has a single-channel rate of 3.938GB / s and 16 channels of 63.01GB / s.

[0005] In actual system design, the PCIe controller version is subject to a variety of physical and economic factors; and the number of PCIe channels is also affected by factors such as the module selection, computing unit density, and hardware wiring in the computer, especially as computers are becoming increasingly thinner and lighter. Therefore, how to effectively expand the bandwidth through innovations in transmission models and link connection methods while maintaining a certain PCIe version and number of channels, so as to make the system design more flexible, is an urgent problem to be solved. Summary of the invention

[0006] In view of the problem that the data transmission rate between the current host and the PCIe device is restricted by the version and number of channels of the PCIe controller, in order to meet business needs, the present application provides a data processing method, device and system, which can improve the rate at which data is transmitted through the PCIe link while keeping the version and number of channels of the PCIe controller unchanged.

[0007] In a first aspect, the present application provides a data processing system, which includes a host and a PCIe device, wherein the PCIe device includes a first interface and a second interface, wherein the PCIe device establishes a first PCIe link with the host through the first interface, and establishes a second PCIe link with the host through the second interface. The host is used to send first data to the PCIe device through the first PCIe link, and send second data to the PCIe device through the second PCIe link; the PCIe device is used to receive the first data through the first PCIe link and receive the second data through the second PCIe link, wherein the first PCIe link and the second PCIe link are both in an active state during data transmission.

[0008] In the existing practice, although the PCIe device itself can have multiple interfaces, only one interface is connected to the host through the PCIe link during operation. In the data processing system provided in the present application, the host is connected to at least two interfaces of the PCIe device through at least two independent PCIe links respectively, and can use these PCIe links to send data, and these independent PCIe links are in an active state during data transmission, so as to improve the data transmission rate through the PCIe link between the host and the PCIe device while keeping the version and number of channels of the PCIe controller unchanged.

[0009] According to the first aspect, in a possible implementation of the present application, the host is further used to determine data to be transmitted that needs to be sent to the PCIe device, and split the data to be transmitted into first data and second data.

[0010] In the above implementation, the host can, when executing a data transmission task, actively split the data to be transmitted corresponding to the data transmission task into multiple copies of data, and transmit the multiple copies of data simultaneously through multiple links, so that the method of the present application can, when receiving multiple data transmission tasks, transmit the data to be transmitted corresponding to a part of the multiple data transmission tasks through the first link, and transmit the data to be transmitted corresponding to another part of the data transmission tasks through the second link; it can also, when receiving a data transmission task, actively split the data to be transmitted corresponding to the data transmission task, and transmit it through different links, so that the present solution can be used in more scenarios.

[0011] According to the first aspect, in another possible implementation of the present application, the PCIe device is also used to determine the data to be transmitted that needs to be requested from the host, divide the data to be transmitted into first data and second data, and request the first data and the second data from the host respectively.

[0012] In the above implementation, the operation of determining the data to be transmitted, the first data, and the second data can be performed by a PCIe device, so that the solution can be used in more scenarios.

[0013] According to the first aspect, in another possible implementation of the present application, splitting the data to be transmitted into the first data and the second data is performed according to the link state of the first PCIe link and the link state of the second PCIe link.

[0014] According to the first aspect, in another possible implementation of the present application, the link status of the first PCIe link and the second PCIe link includes the bandwidth or usage rate of the first PCIe link and the second PCIe link.

[0015] In the above implementation, by determining the splitting method of the data to be transmitted according to the link status of different links, different sizes of data to be transmitted can be more reasonably allocated to different links. For example, more data to be transmitted can be allocated to links with larger bandwidth, thereby improving the efficiency of the data processing system as a whole.

[0016] According to the first aspect, in another possible implementation of the present application, the data to be transmitted may be evenly split into multiple pieces of data, that is, the sizes of the first data and the second data after the splitting are the same.

[0017] In the above implementation, the data splitting method is relatively simple, and usually the properties of multiple links of the host and PCIe link are the same. Therefore, the average splitting method can reduce the overhead caused by splitting data and achieve better results in most cases.

[0018] According to the first aspect, in another possible implementation of the present application, the host is also used to send first data to the PCIe device through the first link using direct memory access, and can also send second data to the PCIe device through the second link using direct memory access.

[0019] In the above implementation, since the data transmission can be completed without occupying a large amount of CPU resources when using direct memory access, the CPU can perform other tasks during data transmission. Therefore, the implementation can improve the efficiency of the data processing system.

[0020] According to the first aspect, in another possible implementation of the present application, the host is further configured to, before splitting the data to be transmitted into the first data and the second data, determine that the size of the data to be transmitted exceeds a preset value.

[0021] In the above implementation, before the data to be transmitted is split, the data to be transmitted is first compared with a preset value, and the splitting operation is performed only when the size of the data to be transmitted exceeds the preset value. Since the operation of splitting data will bring certain overhead, the data splitting and transmission through different links are performed only for the data to be transmitted that exceeds a certain size, which is conducive to improving the efficiency of the data processing system.

[0022] According to the first aspect, in another possible implementation of the present application, the host is further used to, when it is determined that both the first data and the second data have been sent to the PCIe device, send a synchronization signal to the PCIe device, where the synchronization signal is used to indicate that the data transmission is completed.

[0023] In the above implementation, since the PCIe device does not necessarily know the size of the data to be transmitted, nor the size of the first data and the second data, when the host determines that the first data and the second data have been transmitted, a synchronization signal is sent to the PCIe device so that the PCIe device can determine that the data transmission is completed, thereby increasing the stability of the data processing system.

[0024] According to the first aspect, in another possible implementation of the present application, the PCIe device is also used to, after determining that the first data is written, adjust the pointer to the end of the storage space, which is the space in the PCIe device for storing the received first data.

[0025] In the above implementation, the pointer is used to indicate the first address of the space for next data writing. Therefore, after the first data is written, the pointer can be adjusted to the end of the storage space for storing the first data, thereby indicating that the next received data will continue to be stored after the storage space.

[0026] According to the first aspect, in another possible implementation of the present application, the host is connected to the first interface and the second interface in the PCIe device respectively through a PCIe switch.

[0027] In the above implementation, the PCIe switch increases the number of PCIe devices or interfaces in PCIe devices to which the host can be connected, thereby increasing the scalability of the data processing system.

[0028] According to the first aspect, in another possible implementation of the present application, the data processing system can be applied to a cloud phone scenario, wherein the host is also used to receive a data processing task sent by a user before sending the first data to the PCIe device through the first PCIe link, and the data processing task corresponds to the data to be transmitted including the first data and the second data.

[0029] In the above implementation, the data processing system is applied to the cloud phone scenario, and the cloud phone scenario often requires a host to support dozens of cloud phones to run games or video rendering tasks at the same time, which requires a large amount of data transmission between the host and the PCIe device, and has high requirements for the real-time performance of data transmission. Therefore, by splitting the data to be transmitted and sending it through different links, it is beneficial to improve the processing efficiency of data processing tasks sent by users in the cloud phone scenario, and thus improve the user experience.

[0030] According to the first aspect, in another possible implementation of the present application, the data processing system can be applied to an artificial intelligence scenario, wherein the host is also used to receive an artificial intelligence task before sending first data to the PCIe device through the first PCIe link, and the artificial intelligence task corresponds to data to be transmitted including the first data and the second data.

[0031] In the above implementation, the data processing system is applied to artificial intelligence scenarios, and artificial intelligence tasks, including training tasks or reasoning tasks, involve a large amount of data transmission between the host and the PCIe device. Therefore, by adopting the method of splitting the data to be transmitted and sending it through different links, it is beneficial to improve the efficiency of the data processing system in performing artificial intelligence tasks in artificial intelligence scenarios.

[0032] In a second aspect, the present application provides a data processing method, which is applied to a host, a PCIe device establishes a first PCIe link with the host through a first interface, and establishes a second PCIe link with the host through a second interface, the data processing method includes: sending first data to the PCIe device through the first PCIe link, and sending second data to the PCIe device through the second PCIe link, wherein the first PCIe link and the second PCIe link are both in an activated state during data transmission.

[0033] According to the second aspect, in a possible implementation of the present application, the method further includes: the host determines data to be transmitted that needs to be sent to the PCIe device, and splits the data to be transmitted into first data and second data.

[0034] According to the second aspect, in another possible implementation of the present application, splitting the data to be transmitted into first data and second data includes: splitting the data to be transmitted into first data and second data according to the link status of the first PCIe link and the link status of the second PCIe link.

[0035] According to the second aspect, in another possible implementation of the present application, the link status of the first PCIe link and the second PCIe link includes the bandwidth or usage rate of the first PCIe link and the second PCIe link.

[0036] According to the second aspect, in another possible implementation of the present application, the sizes of the first data and the second data obtained by splitting are the same.

[0037] According to the second aspect, in another possible implementation of the present application, sending first data to a PCIe device via a first PCIe link includes: sending the first data to the PCIe device via the first PCIe link using direct memory access; and sending second data to the PCIe device via a second PCIe link includes: sending the second data to the PCIe device via the second PCIe link using direct memory access.

[0038] According to the second aspect, in another possible implementation of the present application, before splitting the data to be transmitted into the first data and the second data, the method further includes: the host determines that the size of the data to be transmitted exceeds a preset value.

[0039] According to the second aspect, in another possible implementation of the present application, the method further includes: after the host determines that the first data and the second data have been sent to the PCIe device, sending a synchronization signal to the PCIe device, wherein the synchronization signal is used to indicate that the data transmission is completed.

[0040] According to the second aspect, in another possible implementation of the present application, the host is connected to the first interface and the second interface respectively through a PCIe switch.

[0041] According to the second aspect, in another possible implementation of the present application, the method further includes: receiving a data transmission request from a PCIe device, wherein the data transmission request is used to instruct the host to transmit first data through the first link and transmit second data through the second link.

[0042] According to the second aspect, in another possible implementation of the present application, the data processing method is applied to a cloud phone scenario, wherein, before sending the first data to the PCIe device through the first PCIe link, the method also includes: receiving a data processing task sent by a user, and the data processing task corresponds to the data to be transmitted including the first data and the second data.

[0043] According to the second aspect, in another possible implementation of the present application, the data processing method is applied to an artificial intelligence scenario, wherein, before sending the first data to the PCIe device through the first PCIe link, the method also includes: receiving an artificial intelligence task, which corresponds to the data to be transmitted including the first data and the second data.

[0044] In a third aspect, the present application provides a data processing device, wherein a PCIe device establishes a first PCIe link with the data processing device through a first interface, and establishes a second PCIe link with the data processing device through a second interface, and the data processing device includes a transmission module for sending first data to the PCIe device through the first PCIe link, and sending second data to the PCIe device through the second PCIe link, wherein the first PCIe link and the second PCIe link are both in an activated state during data transmission.

[0045] According to the third aspect, in a possible implementation of the present application, the data processing device also includes: a determination module, used to determine the data to be transmitted that needs to be sent to the PCIe device; and a splitting module, used to split the data to be transmitted into first data and second data.

[0046] According to the third aspect, in another possible implementation of the present application, the splitting module is used to split the data to be transmitted into first data and second data according to the link status of the first PCIe link and the link status of the second PCIe link.

[0047] According to the third aspect, in another possible implementation of the present application, the link status of the first PCIe link and the second PCIe link includes the bandwidth or usage rate of the first PCIe link and the second PCIe link.

[0048] According to the third aspect, in another possible implementation of the present application, the first data and the second data are the same size.

[0049] According to the third aspect, in another possible implementation of the present application, the transmission module is used to send first data to the PCIe device through a first PCIe link using direct memory access, and to send second data to the PCIe device through a second PCIe link using direct memory access.

[0050] According to the third aspect, in another possible implementation of the present application, the determination module is further used to determine that the first data and the second data have been sent to the PCIe device, and to send a synchronization signal to the PCIe device.

[0051] According to the third aspect, in another possible implementation of the present application, the data processing device is connected to the first interface and the second interface respectively through a PCIe switch.

[0052] According to the third aspect, in another possible implementation of the present application, the transmission module is also used to receive a data transmission request from a PCIe device, wherein the data transmission request instructs the data processing device to transmit first data through a first PCIe link and transmit second data through a second PCIe link.

[0053] According to the third aspect, in another possible implementation of the present application, the data processing device is applied to a cloud phone scenario, wherein the transmission module is also used to receive a data processing task sent by a user, and the data corresponding to the data processing task includes first data and second data.

[0054] According to the third aspect, in another possible implementation of the present application, the data processing device is applied to an artificial intelligence scenario, wherein the transmission module is also used to receive an artificial intelligence task, and the data corresponding to the artificial intelligence task includes first data and second data.

[0055] In a fourth aspect, the present application provides a data processing method, which is applied to a PCIe device, wherein the PCIe device includes a first interface and a second interface, and the PCIe device establishes a first PCIe link with a host through the first interface, and establishes a second PCIe link with the host through the second interface. The data processing method includes: receiving first data sent by the host through the first PCIe link, and receiving second data sent by the host through the second PCIe link, wherein the first PCIe link and the second PCIe link are both in an activated state during data transmission.

[0056] According to the fourth aspect, in a possible implementation of the present application, the method further includes: determining data to be transmitted that needs to be requested from the host, and requesting first data and second data from the host respectively according to the data to be transmitted.

[0057] According to the fourth aspect, in another possible implementation of the present application, first data and second data are respectively requested from the host according to the data to be transmitted, including: first data and second data are respectively requested from the host according to the data to be transmitted and the link status of the first PCIe link and the link status of the second PCIe link.

[0058] According to the fourth aspect, in another possible implementation of the present application, the link status of the first PCIe link and the second PCIe link includes the bandwidth or usage rate of the first PCIe link and the second PCIe link.

[0059] According to the fourth aspect, in another possible implementation of the present application, the first data and the second data are the same size.

[0060] According to the fourth aspect, in another possible implementation of the present application, receiving first data sent by the host through the first PCIe link includes: receiving the first data sent by the host through the first PCIe link using direct memory access; and receiving second data sent by the host through the second PCIe link includes: receiving the second data sent by the host through the second PCIe link using direct memory access.

[0061] According to the fourth aspect, in another possible implementation of the present application, the method further includes: before requesting the first data and the second data from the host respectively according to the data to be transmitted, determining that the size of the data to be transmitted exceeds a preset value.

[0062] According to the fourth aspect, in another possible implementation of the present application, the method further includes: receiving a synchronization signal sent by a host, where the synchronization signal indicates that the first data and the second data have been transmitted.

[0063] According to the fourth aspect, in another possible implementation of the present application, the method further includes: after determining that the first data is written, adjusting the pointer to the end of the storage space, wherein the storage space is the space for storing the first data in the PCIe device.

[0064] According to the fourth aspect, in another possible implementation of the present application, the first interface and the second interface are connected to the host through a PCIe switch.

[0065] According to the fourth aspect, in another possible implementation of the present application, the data processing method is applied to a cloud phone scenario, wherein the first data and the second data correspond to a data processing task sent by a user to a host.

[0066] According to the fourth aspect, in another possible implementation of the present application, the data processing method is applied to an artificial intelligence scenario, wherein the first data and the second data correspond to an AI task received by the host.

[0067] In a fifth aspect, the present application provides a data processing device, which includes a first interface and a second interface. The data processing device establishes a first PCIe link with a host through the first interface, and establishes a second PCIe link with the host through the second interface. The data processing device includes: a transmission module, used to receive first data sent by the host through the first PCIe link, and receive second data sent by the host through the second PCIe link, wherein the first PCIe link and the second PCIe link are both in an activated state during data transmission.

[0068] According to the fifth aspect, in a possible implementation of the present application, the data processing device also includes: a determination module, used to determine the data to be transmitted that needs to be requested from the host; and a request module, used to request the first data and the second data from the host respectively according to the data to be transmitted.

[0069] According to the fifth aspect, in a possible implementation of the present application, the request module is used to request the first data and the second data from the host respectively according to the data to be transmitted and the link status of the first PCIe link and the link status of the second PCIe link.

[0070] According to the fifth aspect, in another possible implementation of the present application, the link status of the first PCIe link and the second PCIe link includes the bandwidth or usage rate of the first PCIe link and the second PCIe link.

[0071] According to the fifth aspect, in a possible implementation of the present application, the first data and the second data are the same size.

[0072] According to the fifth aspect, in a possible implementation of the present application, the transmission module is used to receive first data sent by the host through the first PCIe link using direct memory access.

[0073] According to the fifth aspect, in a possible implementation of the present application, the transmission module is further used to: receive a synchronization signal sent by a host, wherein the synchronization signal indicates that the first data and the second data have been transmitted.

[0074] According to the fifth aspect, in a possible implementation of the present application, the data processing device also includes: an adjustment module, which is used to adjust the pointer to the end of the storage space after determining that the first data is written, wherein the storage space is the space for storing the first data in the PCIe device.

[0075] According to the fifth aspect, in a possible implementation of the present application, the first interface and the second interface are connected to the host through a PCIe switch.

[0076] According to the fifth aspect, in a possible implementation of the present application, the data processing device is applied to a cloud phone scenario, wherein the first data and the second data correspond to a data processing task sent by a user to a host.

[0077] According to the fifth aspect, in a possible implementation of the present application, the data processing device is applied to an artificial intelligence scenario, wherein the first data and the second data correspond to an artificial intelligence task received by the host.

[0078] In a sixth aspect, the present application provides a computer device, comprising a processor and a memory, wherein the memory is used to store program code, and the processor is used to execute the program code to implement the data processing method provided in the second aspect or the fourth aspect.

[0079] In a seventh aspect, the present application provides a computer-readable storage medium, which includes instructions. When the instructions are executed on a computer, the computer executes the data processing method provided in the second aspect or the fourth aspect.

[0080] In an eighth aspect, the present application provides a computer program, which, when executed on a computer, enables the computer to execute the data processing method provided in the second aspect or the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 An architectural diagram of a data processing system that includes a PCIe link.

[0082] Figure 2 It is an architectural diagram of a data processing system provided in this application.

[0083] Figure 3 It is a schematic diagram of the process of a data processing embodiment provided by the present application.

[0084] Figure 4 The present invention is a schematic diagram of a scheme for splitting the data to be transmitted and transmitting them separately.

[0085] Figure 5 The diagram is a schematic diagram of the mapping relationship between the memory domain and the PCIe bus domain.

[0086] Figure 6 It is a schematic diagram of the process of another data processing embodiment provided by the present application.

[0087] Figure 7 It is a schematic diagram of the architecture of another data processing system provided by the present application.

[0088] Figure 8 It is a schematic diagram of the process of another data processing embodiment provided by the present application.

[0089] Fig. 9 It is a schematic diagram of an artificial intelligence application scenario provided by this application.

[0090] Fig.10 It is a schematic diagram of a cloud phone application scenario provided in this application.

[0091] Fig.11 It is a schematic diagram of a data processing device provided by the present application.

[0092] Fig.12 It is a schematic diagram of a data processing device provided by the present application.

[0093] Fig.13 This is a schematic diagram of the structure of the computer device provided in this application. DETAILED DESCRIPTION

[0094] In order to increase the data transmission rate without changing the PCIe version and number of channels, Figure 1 The architecture diagram of a data processing system that can expand bandwidth is given. The system compresses the data to be transmitted at the sending end and transmits the compressed data through the PCIe link. When the PCIe version and the number of channels remain unchanged, more data to be transmitted per unit time is transmitted to the receiving end, thereby actually increasing the data transmission rate.

[0095] Specifically, if Figure 1 As shown, the data processing system includes two computer devices, which are connected via a PCIe bus and both run software that can realize data compression and data decompression functions. These two functions can be realized by two softwares respectively or integrated into one software. When the computer device A of the two computer devices sends data to the computer device B, the software is first used to compress the data to be transmitted, thereby reducing the size of the data actually transmitted subsequently. For example, the size of the data to be transmitted is 2 Gigabytes (GB), and the compressed data to be transmitted is 1GB in size, and the 1GB compressed data is transmitted to the computer device B via the PCIe bus. When the computer device B receives the compressed data, it restores the compressed data to the original data to be transmitted. If the data transmission rate of the PCIe bus between the computer device A and the computer device B is 50 megabytes (MB) per second, the time required to transmit the 1GB compressed data is 20 seconds. These 20 seconds actually transfer 2GB of data from computer device A to computer device B, so it can be considered that a bandwidth of 100MB / s is actually achieved, thereby actually increasing the data transmission rate while keeping the PCIe version and number of channels unchanged.

[0096] However, using Figure 1The data processing system shown in the figure will bring some problems when transmitting data. First, the bandwidth improvement capability brought by this solution is limited, and the bandwidth capability is limited by the compression ratio of the compression algorithm used by the software, the algorithm load, and the computing power of the receiving and sending ends; second, since the sending and receiving ends need to perform data compression and decompression operations respectively, this will occupy additional processor resources at the sending and receiving ends, thereby causing additional overhead for system computing power and power consumption; third, it will introduce the development and use costs of compression software, and if third-party software or open source software is selected, it may also cause quality risks in the system and make software management more complicated.

[0097] Based on the above problems, the present application provides a method and device for improving bandwidth, which can overcome the constraints of the physical bandwidth upper limit on system design while keeping the bus version and number of channels of PCIe constant, and achieve an increase in the actual data transmission rate through the collaborative support of multi-channel hardware connection and software that realizes synchronous transmission function, thereby meeting the bandwidth requirements of large data stream transmission without incurring too much computing resource overhead and introducing too much additional cost.

[0098] Figure 2 This is an architecture diagram of a data processing system provided by this application. Figure 2 As shown, the data processing system includes a host and several subsystem devices. The host can be a computer device such as a server or a personal computer (PC). The subsystem device is connected to the host through a PCIe bus and can transmit data to and from the host. Among them, the subsystem device can be an external device connected to the host, or it can be an independent computer device. Among them, when the subsystem device is an external device connected to the host, it can be directly inserted into a card slot on the mainboard of the host, or it can be connected to the host through a cable; it can be located inside the host or outside the host. This application does not limit the connection method and position relationship between the subsystem device and the host.

[0099] like Figure 2 As shown, the host 200 includes a processor 210, a root complex (RC) 220, a PCIe switch 230, and a memory (not shown in the figure). The processor 210 is used to interpret computer instructions and process data in computer software, and the root complex 220 connects the processor 210 and the memory to a PCIe switching structure composed of one or more switching devices. Similar to the host bridge in the PCI system, the root complex 220 generates transaction requests on behalf of the processor 210. The root complex 220 can be a component independent of the processor 210 or integrated in the processor 210. Figure 2 The root complex 220 is shown separately as a component independent of the processor 210 , but the present application does not limit the actual form of the root complex 220 .

[0100] From the perspective of system software, each PCIe link occupies a PCI bus number, and the PCIe bus uses an end-to-end connection method. In theory, a PCIe link can only connect to one device. For example, each PCIe link can only connect to one PCIe device, PCIe switch, endpoint device (endpoint, EP) or PCIe bridge. When multiple EPs need to be mounted on a PCIe link, a PCIe switch needs to be used to use link extension. A standard PCIe switch has an upstream port (upstream port) and multiple downstream ports (downstream ports), where the upstream port can be connected to the downstream port of the root complex or other PCIe switches, and the downstream port can be connected to the upstream port of the EP, PCIe bridge or downstream PCIe switch.

[0101] PCIe switches extend links through multiple ports. Figure 2 As shown, the four ports of the PCIe switch 230 are connected to different PCIe controllers respectively. Among them, the four PCIe controllers belong to two different subsystem devices respectively, that is, each subsystem device may include multiple PCIe controllers, such as a main PCIe controller and a backup PCIe controller. The present application does not limit the number and type of PCIe controllers included in each subsystem device. Among them, the PCIe controller is usually integrated in the processor chip and supports the high-speed bus transceiver of the PCIe protocol, which can be regarded as the interface of the PCIe device. The number of PCIe controllers integrated in the processor chip can be set according to the specifications of the chip. When the processor chip integrates multiple PCIe controllers, each PCIe controller can occupy a pin of the processor chip, and can establish a link with the host through the pin as a main link or an alternative link.

[0102] For the host (or the processor in the host), each different PCIe controller on the other end will be identified as an independent device connected through different links, and these PCIe controllers have independent bus numbers, device numbers or function numbers (bus number / device number / function number, BDF). The independent BDF will cause different PCIe controllers to be assigned different space addresses.

[0103] It should be noted that, although the PCIe controller itself has an independent BDF and is recognized by the host as an independent device, in this application, the host can still identify the subsystem devices to which these PCIe controllers belong. For example, the host can recognize that PCIe controller 241 and PCIe controller 242 both belong to subsystem device 240, so when data needs to be sent to subsystem device 240, the data is sent through the first PCIe link (hereinafter referred to as the first link) connecting the host 200 and PCIe controller 241 and the second PCIe link (hereinafter referred to as the second link) connecting the host 200 and PCIe controller 242.

[0104] Figure 3 A schematic diagram of the process of a data processing embodiment provided in the present application.

[0105] The data processing process is based on Figure 2 The architecture shown is carried out when Figure 2 When data is transmitted between the host and a subsystem device, the following Figure 3 For the convenience of explanation, this application takes the example of the host sending data to the subsystem device, but the subsystem device can also use the host to send data Figure 3 The method flow shown in this application does not limit the direction of data transmission.

[0106] In general, Figure 3 The method flow shown utilizes multiple controllers of each subsystem device to split the data to be transmitted into multiple parts, which are transmitted through the links between the host and each controller respectively, thereby increasing the data transmission rate while keeping the version and number of channels of the PCIe bus unchanged.

[0107] S301: Determine whether the size of the data to be transmitted exceeds a splitting threshold.

[0108] In this embodiment, the data to be transmitted can be split into multiple parts and transmitted through different links. Before data splitting, it can be determined whether the data to be transmitted exceeds a preset splitting threshold. When the size of the data to be transmitted exceeds the splitting threshold, the data to be transmitted is split into multiple parts according to the number of available links between the host and the subsystem device. For example, Figure 2 As shown, when there is a first link between the host and the main PCIe controller and a second link between the host and the standby PCIe controller between the host and the subsystem device, the data to be transmitted can be divided into two parts and transmitted through the first link and the second link respectively. When the size of the data to be transmitted does not exceed the splitting threshold, the unsplit data to be transmitted is directly transmitted through the first link or the second link.

[0109] The reason for setting the split threshold is that when the host performs a split operation on the data, or when the subsystem device confirms whether the data to be transmitted has been transmitted, a certain amount of overhead may be generated. Therefore, for relatively small data to be transmitted, the benefits brought by the data processing method provided by this embodiment may not make up for the generated overhead, so the traditional method can be selected to transmit all the data to be transmitted through one link; while for relatively large data to be transmitted, the benefits brought by the data processing method provided by this embodiment often exceed the generated overhead, so the data is first split, and then the split data is transmitted through different data links.

[0110] For setting the split threshold, in a possible implementation of the present application, it can be set according to the properties of the data transmission of the first link and / or the second link. For example, when the host and the main PCIe controller transmit data through the first link, the data can be encapsulated into a transaction layer packet (TLP) and then transmitted. A complete TLP includes elements such as a TLP header and a data payload. In the PCIe bus, the maximum value of the data load of the TLP message is 4 kilobytes (KB), but the PCIe device may not be able to send a TLP of 4KB in size, and the TLP that can be sent is affected by the two parameters "Max_Payload_Size_Supported" and "Max_Payload_Size", wherein the "Max_Payload_Size_Supported parameter is used to indicate the maximum value of the TLP effective load in a PCIe device, which is determined by the hardware logic of the PCIe device and cannot be rewritten by the system software; and the "Max_Payload_Size" parameter is used to indicate the maximum value of the data load in the TLP actually used by the PCIe device, which is determined by the negotiation of the devices at both ends of the PCIe link and is the parameter actually used by the PCIe device when performing data transmission. In this embodiment, the split threshold can be set to the size of the "Max_Payload_Size_Supported" parameter or several times the size of the "Max_Payload_Size" parameter as a dividing line for determining whether to split the data.

[0111] In another possible implementation of the present application, the size of the split threshold can also be set by the user of the host. Since the overhead and benefits generated by splitting data transmission are affected by many factors, if it is set only by the attributes of the link itself, it may not necessarily obtain the best effect. Therefore, in actual use, the user can select a suitable split threshold according to the rate of transmitting data of different sizes in different ways.

[0112] In addition, the user or the host itself may choose not to perform the above judgment, and directly split all the data to be transmitted, and transmit them through different links respectively. This application does not limit whether to pre-execute the operation of judging whether the size of the data to be transmitted exceeds the splitting threshold.

[0113] S302: Split the data to be transmitted into first data and second data.

[0114] Figure 4 The present invention is a schematic diagram of a scheme for splitting the data to be transmitted and transmitting them separately.

[0115] like Figure 4 As shown, when it is determined that the size of the data to be transmitted exceeds the splitting threshold, it is determined to split the data to be transmitted, and the data to be transmitted is split into first data transmitted through the first link and second data transmitted through the second link by a certain method.

[0116] There are many methods for data splitting, and several of them are illustrated below. It should be noted that this application does not limit the method of data splitting.

[0117] In a possible implementation of the present application, the data to be transmitted can be equally divided. For example, if the size of the data to be transmitted is 1MB, and the links available for data transmission are the first link and the second link, the data to be transmitted is divided into two 0.5MB data, and the split data is transmitted through the first link and the second link respectively.

[0118] The method of evenly dividing the data to be transmitted is simple and easy to perform data splitting, and the properties of multiple PCIe links between the host and subsystem devices are often the same or similar, so this method can usually achieve good results.

[0119] In another possible implementation of the present application, the splitting method of the data to be transmitted can also be determined according to the link status of the first link and the second link. Wherein, the link status refers to the attributes of the link related to data transmission, such as link bandwidth, link utilization rate, etc. Since for a transmission task, when the data to be sent corresponding to the transmission task is transmitted through multiple links, only when the data corresponding to all links are transmitted, can the transmission task be considered to have been completed, and on this basis, the receiver can use the complete data. Therefore, it is beneficial to increase the efficiency of data transmission by making different links complete data transmission at the same time as much as possible. When the link status refers to the link bandwidth, and the bandwidth of the first link and the bandwidth of the second link are different, in order to make the first link and the second link complete data transmission at the same time or at a relatively similar time, the data to be transmitted can be proportionally allocated according to the bandwidth of the first link and the bandwidth of the second link. For example, if the size of the data to be transmitted is 3MB, and the bandwidth of the first link is twice the bandwidth of the second link, the data of 2MB in the data to be transmitted is allocated to the first link, and the remaining 1MB of data is allocated to the second link. Similarly, when the link status refers to the link utilization rate, less data to be transmitted will be allocated to a link whose current link utilization rate is already high, and more data to be transmitted will be allocated to a link whose current link utilization rate is low.

[0120] In order to determine the bandwidth of the first link and the second link respectively, or to determine the ratio of the bandwidth of the first link to the bandwidth of the second link, the host may obtain the attribute information of the two links, thereby obtaining the bandwidth data of the two links. For example, the host may obtain the specifications of the slots occupied by the ports of the first link and the second link. For the same PCIe version, the bandwidth of the X4 slot may be considered to be twice the bandwidth of the X2 slot. Then, when the first link uses the X4 slot and the second link uses the X2 slot, the bandwidth of the first link may be considered to be twice the bandwidth of the second link.

[0121] In addition, the bandwidth data of the first link and the bandwidth data of the second link can also be obtained by sending test messages. For example, the host first uses the first link to send a small test message, and determines the bandwidth of the first link based on the time required for the message to be transmitted through the first link and the size of the message; then uses the second link to send the test message, and determines the bandwidth of the second link based on the time required for the message to be transmitted through the second link and the size of the message. Since the bandwidth of the link often does not change significantly, the data obtained through the test can be used for a long period of time without the need to test every time data is transmitted.

[0122] In another possible implementation of the present application, the first data transmitted through the first link and the second data transmitted through the second link can also be determined according to the address alignment parameter (addressalignment attribute). When the host and subsystem devices transmit data, it is often necessary to pad the transmitted data according to the address alignment parameter. The alignment parameter is related to the PAGE_SIZE (usually 4K, up to 2M) parameter of the host operating system. If the byte length of the transmitted data is not an integer multiple of PAGE_SIZE, the operating system cannot guarantee that the data is allocated to continuous physical addresses. When data is transmitted according to continuous physical addresses, data mistransmission is likely to occur. In this case, it is possible to first ensure that the first data meets the requirements of the address alignment parameter, and then pad the second data according to the address alignment parameter.

[0123] S303: Send the first data and the second data to the subsystem device through the first link and the second link respectively.

[0124] like Figure 4 As shown, after the data to be transmitted is split, the first data and the second data are sent to the first PCIe controller and the second PCIe controller in the subsystem device through the first link and the second link respectively. In order to speed up the data transmission rate, direct memory access (DMA) can be selected to perform data transmission.

[0125] DMA is a technology for fast data transmission, which allows hardware devices of different speeds to communicate without relying on a large interrupt load of the processor. Otherwise, the processor needs to copy the data of each slice from the sending end to the register, and then write the data to the new place. During this period of time, the processor cannot perform other operations. Using DMA for data transmission is to copy data directly from one address space to another address space. When the processor initializes the data transmission action, the data transmission action itself is implemented and completed by the DMA controller. For example, when moving a block of memory outside the chip to the storage area inside the chip, the data transmission operation does not occupy the processing power of the processor, and the processor can continue to handle other business.

[0126] When implementing DMA transfer, the DMA controller directly controls the bus, so there is a problem of bus control transfer. That is, before DMA transfer, the processor hands over the bus control to the DMA controller, and after the DMA transfer ends, the DMA controller hands over the bus control to the processor. A complete DMA transfer process requires four steps: DMA request, DMA response, DMA transfer, and DMA end.

[0127] In the present application, according to the data splitting method in S302 and the first address of the data to be transmitted, the address information corresponding to the first data and the second data is determined. The address information of the first data or the second data can be represented by an address interval composed of a first address and a last address, or can be represented by the first address and the length information of the data, which is not limited in the present application.

[0128] The host transmits the split first data and second data by submitting different DMA descriptors (Descriptor) and using different DMA channels for data transmission. Among them, the DMA descriptor, also commonly known as the DMA descriptor array, is a pointer array in the form of unsigned long*hw_desc[DESC_NUM], and each pointer (hw_desc[i]) points to a descriptor. This descriptor is defined by the hardware, and its data structure is generally defined by the datasheet or SDK. DMA descriptors can be divided into hardware descriptors and software descriptors, among which the hardware descriptor usually includes control bits, data packet addresses, data packet lengths, ring tails, and ring links. The software descriptor usually includes information such as horizontal intra-packet fragmentation and vertical multi-packet chaining required to maintain the completed data link information in order to perform link tracking.

[0129] Since the processor in the host can only directly access the host's memory space, it cannot directly operate the subsystem device. Therefore, the storage space open to the host in the sub-device system needs to be mapped to the memory space. When the processor needs to access the storage space of the sub-device system, it only needs to access the corresponding memory space. As a PCIe device, the subsystem device may have several storage spaces that need to be mapped to the memory space. When the subsystem device leaves the factory, the size and attributes of these storage spaces are written in the base address register (BAR). The system software in the host reads the information in the BAR, allocates the corresponding system memory space to the storage space in the subsystem device, and writes the base address of the allocated system memory space to the BAR. In other words, the address of the BAR is the address of the PCIe bus domain, and the processor accesses the address of the memory domain. When the processor accesses the PCIe device, the address of the bus domain needs to be converted to the address of the memory domain.

[0130] Figure 5 The diagram is a schematic diagram of the mapping relationship between the memory domain and the PCIe bus domain.

[0131] When a PCIe device uses the DMA mechanism to access the address space of the memory domain, the processor system also needs to reversely map the address space of the memory domain to the PCIe bus address space. Assume that in a processor system, the main memory size is 2GB, and its address space in the memory domain is 0x0000-0000~0x7FFF-FFFF, and the "PCIe bus address space" corresponding to this address in the PCIe bus domain is 0x8000-0000~0xFFFF-FFFF. Therefore, when a PCIe device performs a DMA operation, it must use the address of the PCIe bus domain of 0x8000-0000~0xFFFF-FFFF, so that the HOST main bridge can claim this PCIe bus transaction, convert the PCIe bus address used by this bus transaction into a memory address, and transfer data with the memory area of ​​0x0000-0000~0x7FFF-FFFF.

[0132] It should be pointed out that the above-mentioned mapping method between the memory domain and the PCIe bus domain is only an example for the convenience of illustrating the embodiment of the present application, and does not limit the protection scope of the present application.

[0133] In this solution, when the host performs data transmission, both the first link and the second link are in an active state. The link being in an active state means that not only the interface between the host and the subsystem device forms a link through a physical connection, but also the link itself has completed the preparation for data transmission and is in a state of transmitting data or ready to transmit data at any time.

[0134] Furthermore, in order to speed up the data transmission rate, in one possible implementation, the transmission of the first data through the first link and the transmission of the second data through the second link can be performed in parallel. In this way, multiple links are used for data transmission at the same time, thereby increasing the bandwidth between the host and the subsystem device.

[0135] S304: Determine that data transmission is completed.

[0136] When the host sends the first data and the second data obtained by splitting the data to be transmitted to the subsystem device through the first link and the second link respectively, the subsystem device does not necessarily know the size of the data to be transmitted, nor does it necessarily know the size of the first data and the second data. Therefore, when the host determines that the data transmission of the first link and the data transmission of the second link have been completed, it is necessary to send a synchronization signal to the sub-device system, and the synchronization signal is used to inform the sub-system device that the data to be transmitted has been transmitted. When the sub-system device receives the synchronization signal, it determines that the data transmission has been completed.

[0137] In another possible implementation of the present application, when the first data transmitted through the first link has been transmitted, the host may send a first synchronization signal to the subsystem device; and when the second data transmitted through the second link has been transmitted, the host may send a second synchronization signal to the subsystem device.

[0138] The present application also does not limit the form of the synchronization signal and the method by which the host sends the synchronization signal to the subsystem device. In a possible implementation of the present application, the host and the subsystem device are also connected via a signal link independent of the data link, and the signal link is used to transmit data with high immediacy requirements, and the host can send the above synchronization signal via the signal link.

[0139] In addition, every time data is sent to a subsystem device, a certain amount of storage space is required. The storage space of the PCIe domain has a destination cache pointer, which is used to indicate the first address of the next data write. Therefore, when it is determined that the data transmission is completed, the destination cache pointer of the storage space of the PCIe domain needs to be updated, and the updated pointer points to the tail address of the data written this time in the storage space as the first address of the next data write.

[0140] S305: Subsystem device usage data.

[0141] When the subsystem device receives data to be transmitted, the data is written into the shared data buffer in the sub-operating system. The shared data buffer is a data storage area for producers to write and consumers to read. The producer refers to the provider of data, such as the process in the subsystem device responsible for receiving data to be transmitted. The producer generates data and writes the data into the shared data buffer after the consumer reads the data. The consumer refers to the user of the data, such as the process in the subsystem device that uses the data to be transmitted. The consumer obtains the data after the producer writes the data into the shared data cache.

[0142] The producer / consumer model completes the data exchange through the two status bits of Flag and Status, where the Flag status bit is used by the producer to inform the consumer whether the data has been written, and the Status status bit is used by the consumer to inform the producer whether the data has been read out. As shown in Table 1, specifically, when the producer has written the data into the shared data buffer, the Flag bit is set to 1. The consumer confirms that the producer has written the data into the shared data buffer by identifying the Flag bit as 1, and after reading the data, the Flag bit is set to 0. Correspondingly, when the consumer has read the data from the shared data buffer, the Status bit is set to 1. The producer confirms that the generator has read the data from the shared data buffer by identifying the Status bit as 1. When the producer subsequently writes data to the data buffer, the Status bit is set to 0.

[0143] Table 1 Flag and Status bits

[0144] Flag Status describe 0 0 Idle state, when the shared data buffer is empty 1 0 The producer writes data, but the consumer does not use it 0 1 The consumer has finished using the data 1 1 Error Status

[0145] The producer / consumer model is a method for a process on a subsystem device to use data from a host. This application does not limit how the subsystem device uses the data to be transmitted.

[0146] Figure 6 It is a schematic diagram of the process of another data processing embodiment provided by the present application.

[0147] Figure 3 The data processing method shown is that the host actively sends the data to be transmitted to the subsystem device. In practice, it is also possible that the subsystem device requests data from the host, and the host then sends the data to be transmitted to the subsystem device according to the data request of the subsystem device. Figure 6 As shown in the figure, when the subsystem device sends data to the host, the data processing flow includes the following steps:

[0148] S601: The subsystem device obtains information about data to be transmitted.

[0149] Since in this embodiment, the subsystem device requests the host for the data to be transmitted, and the requested data to be transmitted is stored in the host, the subsystem device needs to first obtain the information of the data to be transmitted.

[0150] In a possible implementation, the host has determined the data to be transmitted that needs to be sent to the subsystem device next based on the business between the host and the subsystem device. In this case, the host can send the information of the data to be transmitted to the subsystem device, so that the subsystem device obtains the information of the data to be transmitted.

[0151] In another possible implementation, the subsystem device may obtain information about part or all of the data in the host, for example, information about data in the host related to the subsystem device. In this case, the subsystem device determines information about the data to be transmitted from the known information about the data in the host according to the needs of subsequent services.

[0152] S602: The subsystem device determines whether the size of the data to be transmitted exceeds a split threshold.

[0153] Referring to step S301, after the subsystem device determines the information of the data to be transmitted, it can first determine whether the size of the data to be transmitted exceeds the split threshold. When the data to be transmitted is larger than the split threshold, step S603 is executed, that is, the data to be transmitted is split into multiple parts according to the data of the available link between the subsystem device and the host, and the split data is requested respectively; and when the size of the data to be transmitted does not exceed the split threshold, step S606 is executed, that is, the unsplit data to be transmitted is directly requested from the host.

[0154] S603: The subsystem device splits the data to be transmitted into first data and second data, and sends a first request for the first data and a second request for the second data to the host.

[0155] Referring to step S302, when the subsystem device determines that the size of the data to be transmitted exceeds the splitting threshold, it determines to split the data to be transmitted, and splits the data to be transmitted into first data transmitted through the first link and second data transmitted through the second link by a certain method. The data splitting method has been illustrated in step S302 and will not be repeated here.

[0156] It should be noted that in step S302, the host that performs the operation of splitting the data to be transmitted owns the data to be transmitted, while in step S603, the subsystem device that performs the operation of splitting the data to be transmitted actually only has information about the data to be transmitted. Therefore, the operation of splitting the data to be transmitted in step S603 includes the subsystem device sending information about the first data and the second data to the host, instructing the host to specifically perform the operation of splitting the data to be transmitted into the first data and the second data. The information about the first data and the second data may include the size of the data, the storage address in the host, the name of the corresponding file, etc., which is not limited in this application. For example, when the data to be transmitted is 10MB in size, the subsystem operation instructs the host to split the data to be transmitted into 6MB of first data and 4MB of second data.

[0157] S604: The subsystem device receives the first data and the second data.

[0158] After receiving the first request and the second request sent by the subsystem device, the host sends the first data and the second data to the subsystem device through the first link and the second link respectively. Referring to step S303, the host can send the first data and the second data to the subsystem device respectively through DMA, and the sending of the first data and the sending of the second data can be performed simultaneously.

[0159] Since the first data and the second data are both requested by the subsystem device to the host, in this case, the subsystem device has obtained information about the first data and the second data, for example, the sizes of the first data and the second data. Therefore, the subsystem device can determine by itself whether the data to be transmitted has been transmitted, and can also determine whether the first data transmitted through the first link or the second data transmitted through the second link has been transmitted, without the need for the host to send a synchronization signal.

[0160] S605: Subsystem device usage data.

[0161] The method for the subsystem device to use data is described in step S305 and will not be described in detail here.

[0162] Figure 7 It is a schematic diagram of the architecture of another data processing system provided by the present application.

[0163] like Figure 7 As shown, the data processing system includes a first device and a second device, wherein the first device and the second device are both electronic devices that can perform data processing, such as a host, a mobile phone, a mobile internet device (MID) wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. In one possible implementation, the first device and the second device are both hosts; and in another possible implementation, the first device is a host, and the second device is an external device. The second device includes at least two interfaces, and the first interface and the second interface are connected to the first device through the first link and the second link respectively, wherein at least two interfaces of the second device are components that can process data, such as a PCIe controller, a network interface card, etc., and the link between the interface and the first device is used to transmit data. For the first device, although the interfaces of the second device are identified as independent devices, the first device can recognize that these interfaces belong to the second device. Therefore, when the first device needs to send data to the second device, the data can be sent through the first link connected to the first interface and / or the second link connected to the second interface.

[0164] In a possible implementation of the present application, the link between the interface of the second device and the first device is a wired link, that is, the interface and the first device are connected through a physical cable or card slot such as a bus or a network cable.

[0165] In a possible implementation of the present application, data is sent between the interface of the second device and the first device through a preset protocol, such as the PCIe protocol, the compute express link (CXL) protocol, the Universal Serial Bus (USB) protocol, etc. The present application does not limit the type of protocol used for data transmission between the interface and the first device.

[0166] Figure 8 It is a schematic diagram of the process of another data processing embodiment provided by the present application.

[0167] The data processing process is based on Figure 7 The architecture shown is carried out. Figure 7 When data is transmitted between the first device and the second device, the following Figure 7 In the steps of the process shown in the figure, for the convenience of explanation, this application takes the first device sending data to the second device as an example for explanation, but the second device sending data to the first device can also use Figure 8 The method flow shown in this application does not limit the direction of data transmission.

[0168] in addition, Figure 8 The process shown includes both the case where the first device actively sends the data to be transmitted to the second device, and the case where the second device requests data from the first device, and the first device sends the data to be transmitted to the second device according to the data request of the second device.

[0169] S801: Determine whether the size of the data to be transmitted exceeds a split threshold.

[0170] Referring to steps S301 and S602, when the first device needs to transmit data to the second device, it can first determine whether the size of the data to be transmitted exceeds the splitting threshold. When the data to be transmitted exceeds the splitting threshold, step S802 is executed, that is, the data to be transmitted is split into the first data and the second data; and when the size of the data to be transmitted does not exceed the splitting threshold, step S806 is executed, that is, the unsplit data to be transmitted is directly transmitted through the first link or the second link.

[0171] Step S801 can be performed by the first device or the second device. Generally speaking, when the first device actively sends the data to be transmitted to the second device, the first device performs the above judgment operation; and when the first device sends the data to be transmitted to the second device according to the data request of the second device, the second device performs the above judgment operation.

[0172] S802: Split the data to be transmitted into first data and second data.

[0173] Referring to steps S302 and S603, when it is determined that the size of the data to be transmitted exceeds the splitting threshold, it is determined to split the data to be transmitted, and the data to be transmitted is split into first data transmitted through the first link and second data transmitted through the second link by a certain method. The data splitting method has been illustrated in step S302 and will not be repeated here.

[0174] Step S802 may be that the first device splits the data to be transmitted into the first data and the second data, or that after the second device obtains information about the data to be transmitted, it requests the first data and the second data from the first device through the first interface and the second interface respectively, so that the first device splits the data to be transmitted before data transmission.

[0175] S803: The first device sends the first data and the second data to the second device through the first link and the second link respectively.

[0176] Referring to steps S303 and S604, when the data to be transmitted is split, the first device sends the first data and the second data to the second device through the first link and the second link respectively. The first device can send the first data and the second data to the second device respectively through DMA, and the sending of the first data and the sending of the second data can be performed simultaneously.

[0177] S804: Determine that data transmission is completed.

[0178] Referring to steps S304 and S604, when the first device actively sends the data to be transmitted to the second device, since the second device does not obtain information such as the size of the data to be transmitted, it is unable to determine by itself whether the data transmission has been completed, and usually needs to determine the completion of the data transmission by receiving a synchronization signal sent by the first device; and when the first device sends the data to be transmitted to the second device according to the data request of the second device, the second device has obtained information about the data to be transmitted, the first data, and the second data, and can determine by itself whether the data to be transmitted has been transmitted without the need for the first device to send a synchronization signal again.

[0179] S805: The second device uses the received data.

[0180] Referring to steps S305 and S605, when the second device receives the data to be transmitted, the corresponding process in the second device will read and use the data.

[0181] Fig. 9 It is a schematic diagram of an artificial intelligence (AI) application scenario provided in this application.

[0182] like Fig. 9 As shown, the inference node includes a host and several inference cards. Among them, the inference card is used to provide artificial intelligence reasoning capabilities, usually including processing units such as a graphics processing unit (GPU), a network processor (NPU) or a central processing unit (CPU) with a certain computing power. The inference card can support artificial intelligence functions such as real-time analysis of high-definition video and image recognition, and is widely used in scenarios such as smart cities, smart transportation, and smart finance. Correspondingly, the host includes an artificial intelligence inference service (AI Inference Service) module for scheduling and management of AI reasoning tasks. Specifically, the AI ​​reasoning service module can receive AI reasoning tasks from the client through the network, and assign the received AI reasoning tasks to one or several reasoning cards through a certain scheduling method, and receive the results obtained by the reasoning card after the reasoning card completes the AI ​​reasoning task. In another possible implementation, the host can also instruct the reasoning card to process the AI ​​training task, that is, the host provides the model and training data to the reasoning card, and the reasoning card uses the model to process the training data, and compares the processing results with the actual results, thereby realizing functions such as model tuning.

[0183] In the process of processing AI inference tasks or AI training by the inference node, a large amount of data is transferred between the AI ​​inference service module in the host and the inference card, such as the feature data involved in the AI ​​inference task or the model and training data involved in the AI ​​training task. In order to increase the working efficiency of the inference node, Fig. 9 As shown, the host is connected to multiple interfaces on the inference card through multiple links. Fig. 9 The two interfaces of the host and each inference card are connected through different links, but this application does not limit the number of interfaces of each inference card and the number of interfaces between the inference card and the host.

[0184] When the host sends data to the inference card, you can refer to the following Figure 3 , Figure 6 and Figure 8 The method flow shown is to divide the sent data into multiple parts, and transmit each part of the data simultaneously through different links, so as to increase the bandwidth of data transmission between the host and the inference card while keeping the bus version and the number of channels constant.

[0185] Fig.10 It is a schematic diagram of a cloud phone application scenario provided in this application.

[0186] like Fig.10 As shown, the cloud phone system includes a user part, a network part and a data center part. Among them, the user's computer device or smart terminal device is connected to the host of the data center part through the network. Among them, the computer device can be a server, a personal computer (PC), a laptop, a tablet computer and other devices, and the smart terminal device can be a mobile phone, a smart head-mounted device, a smart watch and other devices. This application does not limit the types of computer devices and smart terminal devices.

[0187] In the data center, the host receives the user's service request and passes the task corresponding to the service request to the media card connected to the host for processing. After the media card completes the task, it feeds back the processing result of the task to the server, which then sends the result to the user's computer device or smart terminal device. The media card can be a processing unit that usually includes a graphics processor, a network processor or a central processing unit with a certain computing power.

[0188] In a cloud phone system, a host often needs to support dozens of cloud phones running applications at the same time. For example, when 30 cloud phones run large games at the same time, a large amount of image rendering data and data that needs to be calculated will often be generated, and all or part of this data needs to be interacted between the server and the media card. In addition, the cloud phone application scenario and user experience have high requirements for the real-time processing of cloud phone system tasks, and data transmission and processing need to be completed as quickly as possible.

[0189] Therefore, in the data center part, such as Fig.10 As shown, the host is connected to multiple interfaces on the media card through multiple links. The data transmission method between the server and the media card can refer to Figure 3 , Figure 6 and Figure 8Specifically, the server is connected to multiple interfaces on the media card through multiple links. When the server needs to send data to the media card, the data to be sent can be divided into multiple parts and transmitted simultaneously through different links, thereby increasing the bandwidth of data transmission between the server and the media card while keeping the bus version and the number of channels constant.

[0190] Fig.11 is a schematic diagram of a data processing device provided in the present application. The data processing device can be Figure 2 , Fig. 9 , Fig.10 Host or Figure 7 The first device in the PCIe device may also be a host or a part of the first device. The data processing device is connected to the first interface and the second interface in the PCIe device through the first PCIe link and the second PCIe link respectively.

[0191] like Fig.11 As shown, the data processing device 1100 includes a transmission module 1110, a determination module 1120 and a splitting module 1130. The functions of each module are as follows:

[0192] The transmission module 1110 is used to: send first data to the PCIe device through the first PCIe link; and send second data to the PCIe device through the second PCIe link while sending the first data.

[0193] The determination module 1120 is used to determine the data to be transmitted that needs to be sent to the PCIe device.

[0194] The splitting module 1130 is used to split the data to be transmitted into first data and second data.

[0195] The transmission module 1110, the determination module 1120 and the splitting module 1130 can also be used to perform the following steps: Figure 3 and Figure 8 Specifically, the transmission module 1110 may execute Figure 3 Steps 303 and S306 in Figure 8 Steps S803 and S806 in the determination module 1120 can be executed Figure 3 Steps S301 and S304 in Figure 8 Steps S801 and S804 in the above embodiment; the splitting module 1130 may perform Figure 3 Step S302 and Figure 8 The step S802 in the present application will not be described in detail here.

[0196] Fig.12is a schematic diagram of a data processing device provided in the present application. The data processing device can be Figure 2 Subsystem devices in Figure 7 The first device in Fig. 9 Accelerator card in Fig.10 The media card in the device may also be a part of the above device. The data processing device includes two interfaces, which are connected to the host through a first PCIe link and a second PCIe link respectively.

[0197] like Fig.12 As shown, the data processing device 1200 includes a transmission module 1210, a determination module 1220, a request module 1230 and an adjustment module 1240. The functions of each module are as follows:

[0198] The transmission module 1210 is used to: receive first data sent by the host through the first PCIe link, and receive second data sent by the host through the second PCIe link while receiving the first data.

[0199] The determination module 1220 is used to determine the data to be transmitted that needs to be requested from the host.

[0200] The request module 1230 is used to request the first data and the second data from the host according to the data to be transmitted.

[0201] The adjustment module 1240 is used to: when it is determined that the first data is written, adjust the pointer to the end of the storage space, where the storage space is the space in the data processing device 1200 for storing the first data.

[0202] The transmission module 1210, the determination module 1220, the request module 1230 and the adjustment module 1240 can be used to perform the following steps: Figure 6 and Figure 8 Specifically, the transmission module 1210 may execute Figure 6 Step S604 in Figure 8 Steps S803 and S806 in the determination module 1220 can be executed Figure 6 Steps S601 and S602 in Figure 8 Steps S801 and S804 in the request module 1230 can execute Figure 6 The present application will not repeat the steps in step S603.

[0203] Fig.13 1 is a schematic diagram of the structure of a computer device 1300 provided in an embodiment of the present application. The computer device 1100 in this embodiment can be one of the specific implementations of the computer devices in the above embodiments, that is, Figure 2 , Fig. 9 , Fig.10Host in Figure 7 The first device in the Figure 2 Subsystem device 240 in Figure 7 The second device in Fig. 9 Inference cards in or Fig.10 PCIe devices such as media cards in the

[0204] like Fig.13 As shown, the computer device 1300 includes a processor 1301, and the processor 1301 is connected to a memory 1305. The processor 1301 can be a field programmable gate array (Full name: Field Programmable Gate Array, abbreviated: FPGA), or a digital signal processor (Full name: Digital Signal Processor, abbreviated: DSP) or other computing logic or a combination of any of the above computing logics. The processor 1101 can also be a single-core processor or a multi-core processor.

[0205] The memory 1305 can be a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register or any other form of storage medium known in the art. The memory can be used to store program instructions. When the program instructions are executed by the processor 1301, the processor 1301 executes the method described in the above embodiment.

[0206] The connection line 1309 is used to transmit information between the components of the communication device. The connection line 1309 can use a wired connection method or a wireless connection method, which is not limited in this application. The connection line 1309 is also connected to the network interface 1304.

[0207] The network interface 1304 uses a connection device such as, but not limited to, a cable or twisted wire to achieve communication with other devices or the network 1311. The network interface 1304 can also be interconnected with the network 1311 in a wireless manner.

[0208] Some features of the embodiments of the present application may be completed / supported by the processor 1301 executing program instructions or software codes in the memory 1305. The software components loaded on the memory 1305 may be summarized in terms of function or logic, for example, Fig.11 The transmission module 1110, the determination module 1120 and the splitting module 1130 shown in FIG. Fig.12 The transmission module 1210, the determination module 1220, the request module 1230 and the adjustment module 1240 are shown.

[0209] In one embodiment of the present application, after the memory 1305 is loaded with program instructions, the processor 1301 executes transactions related to the above-mentioned functional / logical modules in the memory 1305 .

[0210] also, Fig.13 is merely an example of a computer device 1300 that may include a computer system 1300 that is different from the computer system 1300 described above. Fig.13 More or fewer components may be displayed, or components may be configured differently. Fig.13 The various components shown in the embodiment may be implemented in hardware, software, or a combination of hardware and software. For example, the memory and the processor may be implemented in one module, and the instructions in the memory may be pre-written into the memory or loaded by the subsequent processor during execution, which is not limited in this application.

Claims

1. A data processing system, characterized in that: The data processing system comprises: Host; A peripheral device high-speed interconnection PCIe device, the PCIe device includes a first interface and a second interface, the PCIe device establishes a first PCIe link with the host through the first interface, and the PCIe device establishes a second PCIe link with the host through the second interface; wherein, The host is used to send first data to the PCIe device through the first PCIe link, and send second data to the PCIe device through the second PCIe link; The PCIe device is used to receive the first data through the first PCIe link, and receive the second data through the second PCIe link; The first PCIe link and the second PCIe link are both in an activated state during data transmission.

2. The data processing system according to claim 1, characterized in that: The host is also used to determine the data to be transmitted that needs to be sent to the PCIe device; The data to be transmitted is divided into the first data and the second data.

3. The data processing system according to claim 1, characterized in that: The PCIe device is also used to determine the data to be transmitted that needs to be requested from the host; The first data and the second data are respectively requested from the host according to the data to be transmitted.

4. The data processing system according to claim 2, characterized in that: The host splits the data to be transmitted into the first data and the second data according to the link status of the first PCIe link and the second PCIe link.

5. The data processing system according to claim 2 or 3, characterized in that: The first data and the second data have the same size.

6. The data processing system according to any one of claims 1 to 5, characterized in that: The host is used to send the first data to the PCIe device through the first PCIe link by using direct memory access (DMA), and to send the second data to the PCIe device through the second PCIe link by using DMA.

7. The data processing system according to any one of claims 2 and 4-6, characterized in that: The host is further configured to: before splitting the data to be transmitted into the first data and the second data, determine that the size of the data to be transmitted exceeds a preset value.

8. The data processing system according to any one of claims 1 to 7, characterized in that: The host is also used to: Determining that the first data and the second data have been sent to the PCIe device; A synchronization signal is sent to the PCIe device.

9. The data processing system according to any one of claims 1 to 8, characterized in that: The PCIe device is further used for: after determining that the first data is written, adjusting the pointer to the end of the storage space, wherein the storage space is the space in the PCIe device for storing the first data.

10. The data processing system according to any one of claims 1 to 9, characterized in that: The data processing system is applied to cloud phone scenarios, where: The host is also used to: before sending the first data to the PCIe device through the first PCIe link, receive a data processing task sent by a user, and the data corresponding to the data processing task includes the first data and the second data.

11. The data processing system according to any one of claims 1 to 9, characterized in that: The data processing system is applied to artificial intelligence (AI) scenarios, where: The host is further used to receive an AI task before sending first data to the PCIe device through the first PCIe link, where the data corresponding to the AI ​​task includes the first data and the second data.

12. A data processing method, characterized in that: The method comprises: The host sends first data to the peripheral device high-speed interconnection PCIe device through a first PCIe link; the first PCIe link is a link established between the PCIe device and the host through a first interface of the PCIe device; The host sends second data to the PCIe device through a second PCIe link, where the second PCIe link is a link established between the PCIe device and the host through a second interface of the PCIe device; The first PCIe link and the second PCIe link are both in an activated state during data transmission.

13. The data processing method according to claim 12, characterized in that: The method further comprises: Determining data to be transmitted that needs to be sent to the PCIe device; The data to be transmitted is divided into the first data and the second data.

14. The data processing method according to claim 13, characterized in that: The step of splitting the data to be transmitted into the first data and the second data includes: The data to be transmitted is split into the first data and the second data according to the link status of the first PCIe link and the link status of the second PCIe link.

15. The data processing method according to any one of claims 12 to 14, characterized in that: Before splitting the data to be transmitted into the first data and the second data, the method further includes: It is determined that the size of the data to be transmitted exceeds a preset value.

16. The data processing method according to any one of claims 12 to 15, characterized in that: The data processing method is applied to a cloud phone scenario, wherein before sending the first data to the PCIe device through the first PCIe link, the method further includes: A data processing task sent by a user is received, where data corresponding to the data processing task includes the first data and the second data.

17. A data processing device, characterized in that: The device comprises: A transmission module, used to: send first data to a peripheral device high-speed interconnection PCIe device through a first PCIe link, and send second data to the PCIe device through a second PCIe link; The first PCIe link is a link established between the PCIe device and the data processing apparatus through a first interface of the PCIe device, and the second PCIe link is a link established between the PCIe device and the data processing apparatus through a second interface of the PCIe device; The first PCIe link and the second PCIe link are both in an activated state during data transmission.

18. The data processing device according to claim 17, characterized in that: The data transmission device also includes: A determination module, used to determine the data to be transmitted that needs to be sent to the PCIe device; A splitting module is used to split the data to be transmitted into the first data and the second data.

19. The data processing device according to claim 18, characterized in that: The splitting module is used to split the data to be transmitted into the first data and the second data according to the link status of the first PCIe link and the link status of the second PCIe link.

20. The data processing device according to any one of claims 17 to 19, characterized in that: The determination module is further used to determine whether the size of the data to be transmitted exceeds a preset value.

21. The data processing device according to any one of claims 17 to 20, characterized in that: The data processing device is applied to a cloud phone scenario, wherein: The transmission module is further used to: receive a data processing task sent by a user, and the data corresponding to the data processing task includes the first data and the second data.

22. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein the memory is used to store program codes, and the processor is used to execute the program codes to implement the data processing method according to any one of claims 12 to 16.

23. A data processing method, characterized in that: The method comprises: The peripheral device high-speed interconnection PCIe device receives the first data sent by the host through the first PCIe link; the first PCIe link is a link established between the PCIe device and the host through the first interface of the PCIe device; The PCIe device receives the second data sent by the host through a second PCIe link; the second PCIe link is a link established between the PCIe device and the host through a second interface of the PCIe device; The first PCIe link and the second PCIe link are both in an activated state during data transmission.

24. The data processing method according to claim 23, characterized in that: The method further comprises: Determining data to be transmitted that needs to be requested from the host; The first data and the second data are respectively requested from the host according to the data to be transmitted.

25. The data processing method according to claim 24, characterized in that: The requesting the first data and the second data from the host respectively according to the data to be transmitted comprises: The first data and the second data are respectively requested from the host according to the data to be transmitted and the link status of the first PCIe link and the link status of the second PCIe link.

26. The data processing method according to any one of claims 23 to 25, characterized in that: The method further comprises: Before respectively requesting the first data and the second data from the host according to the data to be transmitted, It is determined that the size of the data to be transmitted exceeds a preset value.

27. The data processing method according to any one of claims 23 to 26, characterized in that: The method further comprises: When it is determined that the first data is written, the pointer is adjusted to the end of the storage space, wherein the storage space is the space in the PCIe device for storing the first data.

28. The data processing method according to any one of claims 23 to 27, characterized in that: The data processing method is applied to a cloud phone scenario, wherein the first data and the second data correspond to a data processing task sent by a user to the host.

29. A data processing device, characterized in that: The device comprises: A transmission module, used to: receive first data sent by a host through a first PCIe link, and receive second data sent by the host through a second PCIe link; The first PCIe link is a link established between the data processing device and the host through the first interface of the data processing device, and the second PCIe link is a link established between the data processing device and the host through the second interface of the data processing device; The first PCIe link and the second PCIe link are both in an activated state during data transmission.

30. The data processing device according to claim 29, characterized in that: The data processing device further comprises: A determination module, used to: determine the data to be transmitted that needs to be requested from the host; The request module is used to respectively request the first data and the second data from the host according to the data to be transmitted.

31. The data processing device according to claim 30, characterized in that: The request module is used to: The first data and the second data are respectively requested from the host according to the data to be transmitted and the link status of the first PCIe link and the link status of the second PCIe link.

32. The data processing device according to any one of claims 29 to 31, characterized in that: The data processing device further comprises: The adjustment module is used to: when it is determined that the first data is written, adjust the pointer to the end of the storage space, wherein the storage space is the space in the PCIe device for storing the first data.

33. The data processing device according to any one of claims 29 to 32, characterized in that: The data processing device is applied to a cloud phone scenario, wherein the first data and the second data correspond to a data processing task sent by a user to a host.

34. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store program codes, and the processor is used to execute the program codes to implement the data processing method according to any one of claims 23 to 28.

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