Vector packed matrix multiplication and accumulation processors, methods, systems, and instructions

Abstract

Vector packed matrix multiplication and accumulation processors, methods, systems, and instructions are disclosed. Decoder circuitry decodes an instruction that indicates: a first vector register having a 128-bit channel storing a first matrix having 2 rows by K columns of data elements, the data elements having a number of bits; a storage location having 128 bits storing a second matrix having K rows multiplied by 2 columns of data elements, the data elements having the number of bits; and a second vector register having a 128-bit channel storing a third matrix having 2 rows by 2 columns of data elements, the data elements having a larger number of bits. Execution circuitry performs operations of the instruction, including generating and storing a result matrix in a 128-bit channel of the second vector register, the result matrix having 2 rows by 2 columns of result data elements, the result data elements having the larger number of bits. The result matrix represents an accumulation of the third matrix with a product matrix generated from matrix multiplication using the first and second matrices.

Description

background Technical Field

[0001] Embodiments generally relate to processors. Specifically, embodiments described herein generally relate to processors and instructions for processing matrices. Background Art

[0002] A matrix is ​​typically considered a two-dimensional square or rectangular array or arrangement of numbers into rows and columns of the matrix. For example, a 4×4 matrix may have 16 numbers arranged into 4 rows and 4 columns.

[0003] Matrices can be used in a wide variety of applications and for a wide variety of different purposes (e.g., graphics processing, signal processing, seismology, etc.) Recently, matrices are widely used to process data for artificial intelligence, machine learning, deep learning, neural networks, general graphics processing, and more. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various examples according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of an embodiment of a processor that operates to execute an embodiment of an instruction, such as a vector packed matrix multiply and accumulate instruction.

[0006] Figure 2 is a block diagram of an embodiment of a processor for performing vector packed matrix multiply and accumulate instructions using first and second matrices each having 32-bit data elements.

[0007] Figure 3 is a block diagram of an embodiment of a processor for performing a vector packed matrix multiply and accumulate instruction using a first matrix and a second matrix each having 16-bit data elements.

[0008] Figure 4 is a block diagram of an embodiment of a processor for performing a vector packed matrix multiply and accumulate instruction using a first matrix and a second matrix each having 8-bit data elements.

[0009] Figure 5 is a block diagram of a more detailed example embodiment of a processor operative to execute an embodiment of a vector packed matrix multiply and accumulate instruction.

[0010] Figure 6 is a block flow diagram of an embodiment of a method of executing an embodiment of a vector packed matrix multiply and accumulate instruction.

[0011] Figure 7 is a block flow diagram of an embodiment of a method of performing an embodiment of a vector packed matrix multiply and accumulate instruction using emulation or binary translation.

[0012] Figure 8 is a block diagram of an example embodiment of a suitable vector register set.

[0013] Fig. 9 An example computing system is illustrated.

[0014] Fig.10 A block diagram illustrating an example processor and / or System on a Chip (SoC) that may have one or more cores and an integrated memory controller.

[0015] 11(A) is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example.

[0016] 11(B) is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0017] Fig.12 An example of execution unit(s) circuitry is shown.

[0018] Fig.13 is a block diagram of a register architecture according to some examples.

[0019] Fig.14 An example of the instruction format is shown.

[0020] Fig.15 Figure 1 shows an example of an addressing information field.

[0021] Fig.16 An example of the first prefix is ​​illustrated.

[0022] Figure 17(A)-Figure 17(D) An example of how the R, X, and B fields of the first prefix 16 (A) are used is shown.

[0023] Figure 18 (A) - Figure 18 (B) An example of the second prefix is ​​shown in the figure.

[0024] Fig.19 An example of the third prefix is ​​shown in FIG.

[0025] Fig. 20 is a block diagram illustrating converting binary instructions in a source instruction set architecture to binary instructions in a target instruction set architecture using a software instruction converter according to an example. DETAILED DESCRIPTION

[0026] Disclosed herein are embodiments of instructions, embodiments of processors for executing instructions, embodiments of methods performed by processors when executing instructions, embodiments of systems comprising one or more processors for executing instructions, and embodiments of programs or machine-readable media that store or otherwise provide instructions. In the following description, numerous specific details are set forth (e.g., specific instruction operations, data formats, processor configurations, microarchitecture details, sequences of operations, etc.). However, embodiments may be implemented without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this specification.

[0027] Figure 1 1 is a block diagram of an embodiment of a processor 100 that operates to execute an embodiment of an instruction 101 (e.g., a vector packed matrix multiplication and accumulation instruction). In some embodiments, the processor may be a general purpose processor (e.g., a general purpose microprocessor or central processing unit (CPU) of the type used in a desktop computer, a laptop computer, a server, a smart phone, or other computer system). Alternatively, the processor may be a special purpose processor. Examples of suitable special purpose processors include, but are not limited to, machine learning processors, artificial intelligence processors, coprocessors, graphics processors, network processors, communication processors, cryptographic processors, and digital signal processors (DSP). The processor may have any of various complex instruction set computing (CISC) architectures, reduced instruction set computing (RISC) architectures, very long instruction word (VLIW) architectures, hybrid architectures, other types of architectures, or combinations with different architectures (e.g., different cores may have different architectures). In some embodiments, the processor may include at least one integrated circuit or semiconductor die (e.g., disposed on at least one integrated circuit or semiconductor die). In some embodiments, a processor may include at least some hardware (eg, transistors, capacitors, circuits, non-volatile memory storing circuit-level instructions / control signals).

[0028] Processor 100 may be coupled to receive instructions 101. For example, the processor may have an interface for coupling to an interconnect to receive instructions from a memory via the interconnect. The instructions may represent microinstructions, machine code instructions, or other instructions of an instruction set of the processor. The instructions may have various formats or encodings, such as, for example, described below (e.g., for Figure 14-Figure 19) The instruction may have one or more fields that specify, at least in part or in full, an opcode for the operation to be performed (e.g., matrix multiplication and accumulation).

[0029] In some embodiments, the instruction may explicitly specify (e.g., by one or more fields or bit sets) or otherwise indicate (e.g., implicitly indicate) a first (e.g., source) matrix 105, may specify or otherwise indicate a second (e.g., source) matrix 107, and may specify or otherwise indicate a third (e.g., source) matrix 109. For example, as shown in the illustrated embodiment, the instruction may specify or otherwise indicate a first (e.g., source) vector register 106 storing the first matrix, may specify or otherwise indicate a second (e.g., source) vector register 108 storing the second matrix, and may specify or otherwise indicate a third (e.g., source / destination) vector register 110 storing the third matrix. Vector registers are also sometimes referred to in the art as packed data registers and single instruction, multiple data (SIMD) registers. Alternatively, one or more of the first matrix, the second matrix, and the third matrix may optionally be stored in a memory or other storage location. For example, as indicated by the dashed line representing the second vector register, in another embodiment, the second matrix may optionally be stored in a memory location. The instruction may have a source and / or destination operand designation field to specify registers, memory locations, or other storage locations for storing the first, second, and third matrices.

[0030] In the illustrated embodiment, the first vector register has a 128-bit lane or portion 111 for storing the first vector 105, the second vector register has a 128-bit lane or portion 112 for storing the second matrix 107, and the third vector register has a 128-bit lane or portion 113 for storing the third matrix 109. The first matrix may have 2 rows (e.g., M=2) by K columns of data elements, each of which has a first number of bits, where K is equal to 64 bits divided by the first number of bits. The second matrix may have K rows by 2 columns (e.g., N=2) of data elements, each of which has a first number of bits. K may represent a common dimension shared by the two matrices to be multiplied, commonly referred to as a K dimension or inner product dimension. The third matrix may have 2 rows by 2 columns of data elements, each of which has a second number of bits, where the second number of bits is greater than the first number of bits. In some embodiments, each of the first, second, and third vector registers may be a 128-bit register having only corresponding 128-bit lanes. In other embodiments, each of the first, second and third vector registers can be a 256-bit register with two 128-bit channels. In other embodiments, each of the first, second and third vector registers can be a 512-bit register with four 128-bit channels. In other embodiments, each of the first, second and third vector registers can have another number of 128-bit channels (e.g., a 384-bit register can have three 128-bit channels, a 640-bit register can have five 128-bit channels, a 768-bit register can have six 128-bit channels, a 1024-bit register can have eight 128-bit channels, a 2048-bit register can have sixteen 128-bit channels, etc.). In some embodiments, each of two or more 128-bit channels of a vector register can be used to store dimensions and data element sizes identical to those dimensions and data element sizes mentioned for the first 128-bit channel of the same vector register. Specific examples of suitable 128-bit, 256-bit, and 512-bit vector registers include, but are not limited to, the 128-bit xmm, 256-bit ymm, and 512-bit zmm registers mentioned elsewhere herein.

[0031] In various different embodiments, the first bit number of the data elements of the first matrix and the second matrix may be 2 bits, 4 bits, 8 bits, 16 bits, or 32 bits. For 2-bit data elements, K may be 32. For 4-bit data elements, K may be 16. For 8-bit data elements, K may be 8. For 16-bit data elements, K may be 4. For 32-bit data elements, K may be 2. Examples of suitable types of 2-bit and 4-bit data elements of the first matrix and the second matrix include, but are not limited to, 2-bit and 4-bit signed and unsigned integers. Examples of suitable types of 8-bit data elements of the first matrix and the second matrix include, but are not limited to, 8-bit signed integers (S8), 8-bit unsigned integers (U8), and 8-bit floating-point data elements (FP8). Examples of suitable types of 8-bit floating-point data elements of the first matrix and the second matrix include, but are not limited to, bfloat8 (BF8) with 5 exponent bits and 2 explicit mantissa / significand bits and hfloat8 (HF8) with 4 exponent bits and 3 explicit mantissa / significand bits. In various embodiments, both the first matrix and the second matrix may have S8 data elements, both the first matrix and the second matrix may have U8 data elements, the first matrix may have S8 data elements and the second matrix may have U8 data elements, or the first matrix may have U8 data elements and the second matrix may have S8 data elements. In various other embodiments, both the first matrix and the second matrix may have BF8 data elements, both the first matrix and the second matrix may have HF8 data elements, the first matrix may have BF8 data elements and the second matrix may have HF8 data elements, or the first matrix may have HF8 data elements and the second matrix may have BF8 data elements. Examples of suitable types of 16-bit data elements of the first matrix and the second matrix include, but are not limited to, 16-bit signed integers (S16), 16-bit unsigned integers (U16), half-precision floating point data elements (float16, i.e., F16), and bfloat16 (BF16) floating point data elements. In various embodiments, both the first matrix and the second matrix may have F16 data elements, or both the first matrix and the second matrix may have BF16 data elements. Examples of suitable types of 32-bit data elements of the first matrix and the second matrix include, but are not limited to, 32-bit signed integers (S32), 32-bit unsigned integers (U32), single-precision floating point data elements (float32, i.e., F32), and tensor float32 floating point data elements (TF32) with 8 exponent bits and 10 explicit mantissa / significand bits. In some embodiments, the first matrix and the second matrix may both have TF32 data elements.

[0032] Conventionally, vector registers have been used to store vectors, but are not usually used to store matrices. In the art, vectors are sometimes also referred to as compact data and SIMD data. Vectors represent one-dimensional arrays or data structures. In contrast, in some embodiments, at least one vector register may be used to store matrices. A matrix may represent a two-dimensional arrangement of data elements (e.g., numbers or values) to rows and columns. However, a matrix may be stored in a single vector register (e.g., stored in a single vector and / or a one-dimensional layout), rather than a matrix being stored in a two-dimensional set of slices, registers, or other two-dimensional storage structures. Such matrices may also be referred to as vector compact matrices herein, because matrices are compacted into vectors or one-dimensional layouts.

[0033] Vector registers 106, 108, 110 may represent architecturally visible or architectural registers visible to software and / or programmers, and / or are indicated by instructions in the processor's instruction set to identify registers for operation objects. These architectural registers are contrasted with other non-architectural registers in the microarchitecture (e.g., temporary registers, reorder buffers, retirement registers, etc.). These vector registers may be implemented in different ways in different microarchitectures, and they are not limited to any particular design. Examples of suitable types of vector registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, and combinations thereof.

[0034] Reference again Figure 1, the processor may include a decoder circuit 102 (e.g., an instruction decoder). The decoder circuit may be coupled to receive an instruction. The decoder circuit may be operable to decode the instruction into one or more lower-level control signals, operations, or decoded instructions 104 (e.g., one or more microinstructions, microoperations, microcode entry points, etc.). In some embodiments, the decoder circuit may include: at least one input structure (e.g., a port, interconnect, or interface) coupled to receive the instruction; instruction recognition and decoding logic coupled to at least one input structure to recognize the instruction and decode the instruction into one or more lower-level control signals, operations, or decoded instructions; and at least one output structure (e.g., a port, interconnect, or interface) coupled to the instruction recognition and decoding logic to output the one or more lower-level control signals, operations, or decoded instructions. The decoder circuit and / or its instruction recognition and decoding logic may be implemented using various instruction decoding mechanisms, including but not limited to microcode read only memory (ROM), lookup tables, hardware implementations, programmable logic arrays (PLA), other mechanisms suitable for implementing instruction decoder circuits, and combinations of the above. In some embodiments, the decoder circuit may include at least some hardware (e.g., transistors storing microcode or other hardware-level instructions, integrated circuits, on-die read-only memory, or other non-volatile memory, and any combination of the above). In some embodiments, the decoder circuit may be included on a die, an integrated circuit, or a semiconductor substrate.

[0035] Execution circuitry 103 (e.g., an execution unit) is coupled to decoder circuitry 102 (e.g., to receive one or more lower-level control signals, operations, or decoded instructions 104). The execution circuitry is also coupled to receive first matrix 105, second matrix 107, and third matrix 109 (e.g., coupled to first vector register 106, second vector register 108, and third vector register 110). In some embodiments, the execution circuitry may be on a die or integrated circuit along with the decoder circuitry. The execution circuitry may be operable to perform operations corresponding to and / or specified by and / or controlled by instruction 101. For example, one or more lower-level control signals, operations, or decoded instructions may be executed by the execution circuitry to control the execution circuitry to perform operations corresponding to the instruction (e.g., operations specified at least in part by an opcode of the instruction).

[0036] In some embodiments, the operation may include generating a result matrix 115 having 2 rows by 2 columns (e.g., M=2, N=2) of result data elements, each of which has a second number of bits. In some embodiments, the second number of bits is 32 bits. In some embodiments, the result matrix may represent the accumulation of a third matrix 109 (e.g., an accumulation matrix) and a product matrix (e.g., having 2 rows by 2 columns), which is generated from a matrix multiplication using and / or involving and / or based on the first matrix 105 and the second matrix 107. As an example, a product matrix having M rows by N columns may be generated by a matrix multiplication involving a first matrix having M rows by K columns and a second matrix having K rows by N columns, where M and N are each 2. In some embodiments, the product matrix may be generated from a matrix multiplication using a first matrix and a second matrix, where the data elements of the first matrix and the second matrix are converted from a first number of bits to a larger number of bits (e.g., from 8 bits or 16 bits to 32 bits) prior to the matrix multiplication. In certain embodiments, the product matrix can be generated from the matrix multiplication using the first matrix and the second matrix, wherein, during matrix multiplication and / or accumulation, floating point rounding can be optionally performed as required. In various embodiments, rounding can be performed as required after being used to generate each multiplication of each result element, rounding can be performed as required after being used to generate each accumulation operation of each result element, rounding can be performed as required after being used to generate each multiplication of each result element and also after being used to generate each accumulation operation of each result element, performed once as required after all operations for generating result elements. In certain embodiments, operation can include storing the result matrix in the 128-bit channel of the third vector register that is initially used to store the third matrix. That is, the third vector register can be the source / destination vector register that is initially used as the source of the third vector and is implicitly reused as the destination where the result matrix is ​​stored subsequently.

[0037] In some embodiments, to generate and store a result matrix, the execution circuit may perform operations including the following for each column n of the two columns of the second matrix and for each row m of the two rows of the first matrix: (1) converting K data elements from row m of the first matrix into K corresponding converted data elements each having more bits than a first number of bits, and converting K data elements from column n of the second matrix into K corresponding converted data elements each having more bits than the first number of bits; (2) generating K products including multiplying the K converted data elements corresponding to row m with the K converted data elements corresponding to column n, wherein generating the K products may optionally include performing rounding as needed; (3) generating a result data element having a second number of bits including accumulating the K products with data elements from corresponding row m of the two rows and corresponding column n of the two columns of the third matrix, wherein generating the result data element may optionally include performing rounding as needed; and (4) storing the result data element in a 128-bit lane of a third vector register at a position corresponding to row m and column n of the third matrix. As mentioned immediately above for item (3), the accumulation of the K products and the data elements from the third matrix can be performed in a variety of different ways, including accumulating the K products and the data elements from the third matrix in a variety of different orders. In some embodiments, to generate and store the result matrix, the execution circuitry may perform any of the operations of the example embodiments of the instructions further shown and described below.

[0038] In some embodiments, the first vector register 106 may optionally have a second 128-bit lane to store a fourth matrix having 2 rows by K columns of data elements, each of which has a first number of bits; the second vector register 108 may optionally have a second 128-bit lane to store a fifth matrix having K rows by 2 columns of data elements, each of which has a first number of bits; and the third vector register 110 may optionally have a second 128-bit lane to store a sixth matrix having 2 rows by 2 columns of data elements, each of which has a second number of bits. In such embodiments, to perform the operation corresponding to the instruction, the execution circuit may further generate a second result matrix having 2 rows by 2 columns (e.g., M=2, N=2) of result data elements, each of which has a second number of bits. In some embodiments, the second result matrix may represent the accumulation of the sixth matrix (e.g., the second accumulation matrix) and the product matrix (e.g., having 2 rows by 2 columns) generated from the matrix multiplication using the fourth and fifth matrices. The second result matrix may be stored in the second 128-bit lane of the third vector register. In other embodiments, there may be additional 128-bit lanes or portions. Separate 2x2xK matrix multiply-accumulate operations may be performed on these 128-bit lanes or portions of the vector register.

[0039] In some embodiments, the processor may have a register (e.g., MXCSR or other floating point control register) for controlling floating point operations. In some embodiments, the register may have one or more fields (e.g., rounding mode field) for specifying a rounding mode to be used for floating point operations in a plurality of supported rounding modes. In some embodiments, in order to perform an operation corresponding to an instruction, when at least some data elements of a matrix are floating point data elements, the execution circuit may perform rounding according to only a single rounding mode (e.g., nearest to even rounding mode), regardless of and / or regardless of one or more fields in the register (e.g., rounding mode field), and / or without checking the one or more fields. In some such embodiments, rounding may be performed in a mathematically precise manner according to a single rounding mode, rather than by simplification that results in mathematically inaccurate results. In some embodiments, the register may have one or more fields (e.g., Denormals-Are-Zero, DAZ) bits or fields) for specifying whether a denormal value in an input (e.g., source matrix) to a floating point instruction / operation is to be set to zero or zeroed or treated as zero. In some such embodiments, to perform the operation corresponding to the instruction, when at least some of the data elements of the matrix are floating-point data elements, the execution circuitry may set denormals in the input to the floating-point operation to zero or cause the denormals to be zero, or treat the denormals in the input as zero, regardless of and / or regardless of whether one or more fields (e.g., DAZ bits or fields) in the register specify that denormal values ​​in the input to the floating-point operation are to be forced to zero, and / or without checking whether the one or more fields specify that denormal values ​​in the input to the floating-point operation are to be forced to zero. In some embodiments, the register may have one or more fields (e.g., Flush-To-Zero (FTZ) bits or fields) for specifying that denormal results of the floating-point operation are to be set to zero or forced to zero or set to zero. In some such embodiments, to perform the operation corresponding to the instruction, when at least some of the data elements of the matrix are floating-point data elements, the execution circuitry may set the denormal result of the floating-point operation to zero, force the denormal result to zero, or zero the denormal result, regardless of and / or regardless of whether one or more fields (e.g., FTZ bits or fields) in the register specify that the denormal result of the floating-point operation is to be set to zero, forced to zero, or zeroed, and / or without checking whether the one or more fields specify that the denormal result of the floating-point operation is to be set to zero, forced to zero, or zeroed. In some embodiments, when at least some of the data elements of the matrix are floating-point data elements, the execution circuitry may complete execution of the operation corresponding to the instruction without accessing a register (e.g., MXCSR or other floating-point control register) (e.g., without reading from the register and without writing to the register).

[0040] The execution circuitry and / or processor may include specific or particular logic (e.g., transistors, integrated circuits, or other hardware, potentially combined with firmware (e.g., instructions stored in non-volatile memory) and / or software) that operates to execute instructions, and / or store result matrices in response to or as a result of instructions (e.g., in response to one or more lower-level control signals, operations, or decoded instructions that have been decoded from the instructions). In some embodiments, the execution circuitry may include multiplication circuitry (e.g., matrix multiplication circuitry), addition circuitry (e.g., matrix addition circuitry), floating point rounding circuitry, and circuitry for performing other operations described herein. In some embodiments, the execution circuitry may include: one or more input structures (e.g., ports, interconnects, or interfaces) coupled to receive first, second, and third matrices; circuitry or logic coupled to the one or more input structures for receiving and processing the matrices to generate result matrices; and one or more output structures coupled to the circuitry or logic for outputting the result matrices (e.g., storing the result matrices in vector registers).

[0041] Figure 2 2 is a block diagram of an embodiment of a processor 200 for executing a vector packed matrix multiply and accumulate instruction 201 to perform a vector packed matrix multiply and accumulate operation using a first matrix 205 and a second matrix 207 each having 32-bit data elements. The processor includes a decoder circuit 202 for decoding the vector packed matrix multiply and accumulate instruction. The decoder circuit may be used with respect to Figure 1 The decoder circuit 102 described is similar or identical. The instruction may specify or otherwise indicate a first vector register 206 having 128 bit lanes storing a first matrix 205, a second vector register 208 having 128 bit lanes storing a second matrix 207, and a third vector register 210 having 128 bit lanes storing a third matrix 209.

[0042] For these 32-bit data elements, the first matrix and the second matrix have a common dimension K=2 (e.g., K=2=64 / 32). The first matrix has four 32-bit data elements arranged in 2 rows by 2 columns, which are labeled: A 0,0 , in bits [31:0]; A 1,0 , in bits [63:32]; A 0,1 , in bits [95:64]; and A 1,1 , in bits [127:96], where the A elements are sorted by A k,m The second matrix has four 32-bit data elements arranged in 2 rows by 2 columns, which are labeled: B 0,0, in bits [31:0]; B 0,1 , in bits [63:32]; B 1,0 , in bits [95:64]; and B 1,1 , in bits [127:96], where the B elements are ordered by B n,k The third matrix has four 32-bit data elements arranged in 2 rows by 2 columns, which are marked as C in bits [31:0]. 0,0 , C in Bit [63:32] 1,0 , C in Bit [95:64] 0,1 , and C in bits [127:96] 1,1 , where C elements are in the order of C n,m This arrangement of 32-bit data elements within a matrix may tend to be more efficient than some other arrangements (eg, more efficient in managing smaller matrices as part of an overall algorithm that multiplies and accumulates larger matrices).

[0043] Execution circuitry 203 is coupled to decoder circuitry 202. The execution circuitry may perform vector packed matrix multiplication and accumulation operations corresponding to the instruction. These operations may include generating a result matrix 215. The result matrix may have four 32-bit data elements arranged in 2 rows by 2 columns, which are labeled: D 0,0 , in bits [31:0]; D 1,0 , in bits [63:32]; D 0,1 , in bits [95:64]; and D 1,1 , in bits [127:96], where the D elements are in D n,m The result matrix may represent the accumulation of the third matrix 209 and the product matrix generated from the matrix multiplication using the first matrix 205 and the second matrix 207. This may be described elsewhere herein (e.g., for Figure 1 ), for example, optionally with conversion, optionally with rounding as needed, etc. The execution circuit may also store the result matrix in a 128-bit lane of the third vector register. For example, the result matrix may overwrite the third matrix in the 128-bit lane of the third vector register.

[0044] In some embodiments, the 32-bit data elements of the first matrix and the second matrix may each be a TF32 data element. In some embodiments, the 32-bit data elements of the third matrix and the fourth matrix may each be a single-precision floating point (F32) data element. In some embodiments, each vector register may optionally include more than one 128-bit lane (e.g., two, four, eight, or some other number of 128-bit lanes), wherein each 128-bit lane stores a corresponding matrix, and the operation may further include performing separate multiplication and accumulation operations on these different lanes of the matrix similar to those described. In some embodiments, the vector packed matrix multiplication and accumulation instruction 201 may be a VMMTF32PS instruction further described below, and the execution circuit may perform any of the operations described further below for the VMMTF32PS instruction.

[0045] Figure 3 30 is a block diagram of an embodiment of a processor 300 for executing a vector packed matrix multiply and accumulate instruction 301 to perform a vector packed matrix multiply and accumulate operation using a first matrix 305 and a second matrix 307 each having 16-bit data elements. The processor includes a decoder circuit 302 for decoding the vector packed matrix multiply and accumulate instruction. The decoder circuit may be used with respect to Figure 1 The decoder circuit 102 described is similar or identical. The instruction may specify or otherwise indicate a first vector register 306 having 128 bit lanes storing a first matrix 305, a second vector register 308 having 128 bit lanes storing a second matrix 307, and a third vector register 310 having 128 bit lanes storing a third matrix 309.

[0046] For these 16-bit data elements, the first matrix and the second matrix have a common dimension K=4 (e.g., K=4=64 / 16). The first matrix has eight 16-bit data elements arranged in 2 rows by 4 columns, which are labeled: A 0,0 , in bits [15:0]; A 1,0 , in bits [31:16]; A 2,0 , in bits [47:32]; A 3,0 , in bits [63:48]; A 0,1 , in bits [79:64]; A 1,1 , in bits [95:80]; A 2,1 , in bits [111:96]; and A 3,1 , in bits [127:112], where the A elements are sorted by A k,mThe second matrix has eight 16-bit data elements arranged in 4 rows by 2 columns, which are labeled: B 0,0 , in bits [15:0]; B 0,1 , in bits [31:16]; B 0,2 , in bits [47:32]; B 0,3 , in bits [63:48]; B 1,0 , in bits [79:64]; B 1,1 , in bits [95:80]; B 1,2 , in bits [111:96]; and B 1,3 , in bits [127:112], where the B elements are ordered by B n,k The third matrix has four 32-bit data elements arranged in 2 rows by 2 columns, which are labeled: C 0,0 , in bits [31:0]; C 1,0 , in bits [63:32]; C 0,1 , in bits [95:64]; and C 1,1 , in bits [127:96], where the C elements are in C n,m This arrangement of 16-bit data elements and 32-bit data elements within a matrix may tend to be more efficient than certain other arrangements (e.g., more efficient in managing smaller matrices as part of an overall algorithm that multiplies and accumulates larger matrices), but other arrangements may alternatively be used if desired.

[0047] Execution circuitry 303 is coupled to decoder circuitry 302. The execution circuitry may perform vector packed matrix multiplication and accumulation operations corresponding to the instruction. These operations may include generating a result matrix 315. The result matrix may have four 32-bit data elements arranged in 2 rows by 2 columns, which are labeled: D 0,0 , in bits [31:0]; D 1,0 , in bits [63:32]; D 0,1 , in bits [95:64]; and D 1,1 , in bits [127:96], where the D elements are in D n,m The result matrix may represent the accumulation of the third matrix 309 and the product matrix generated from the matrix multiplication using the first matrix 305 and the second matrix 307. This may be described elsewhere herein (e.g., for Figure 1), for example, optionally with conversion, optionally with rounding as needed, etc. The execution circuit may also store the result matrix in a 128-bit lane of the third vector register. For example, the result matrix may overwrite the third matrix in the 128-bit lane of the third vector register.

[0048] In some embodiments, the 16-bit data elements of the first matrix and the second matrix may each be a bfloat16 (BF16) data element. In other embodiments, the 16-bit data elements of the first matrix and the second matrix may each be a half-precision floating point (float16, i.e., F16) data element. In some embodiments, the 32-bit data elements of the third matrix and the fourth matrix may each be a single-precision floating point (F32) data element. In some embodiments, each vector register may optionally include more than one 128-bit channel (e.g., two, four, eight, or some other number of 128-bit channels), wherein each 128-bit channel stores a corresponding matrix, and the operation may further include performing separate multiplication and accumulation operations on these different channels of the matrix similar to those described. In some embodiments, the vector packed matrix multiplication and accumulation instruction 301 may be a VMMBF16PS instruction further described below, and the execution circuit may perform any of the operations described further below for the VMMBF16PS instruction. In other embodiments, the vector packed matrix multiply and accumulate instruction 301 may be a VMMF16PS instruction described further below, and the execution circuitry may perform any of the operations described further below for the VMMF16PS instruction.

[0049] Figure 4 4 is a block diagram of an embodiment of a processor 400 for executing a vector packed matrix multiply and accumulate instruction 401 to perform a vector packed matrix multiply and accumulate operation using a first matrix 405 and a second matrix 407 each having 8-bit data elements. The processor includes a decoder circuit 402 for decoding the vector packed matrix multiply and accumulate instruction. The decoder circuit may be used with respect to Figure 1 The decoder circuit 102 described is similar or identical. The instruction may specify or otherwise indicate a first vector register 406 having 128 bit lanes storing a first matrix 405, a second vector register 408 having 128 bit lanes storing a second matrix 407, and a third vector register 410 having 128 bit lanes storing a third matrix 409.

[0050] For these 8-bit data elements, the first matrix and the second matrix have a common dimension K=8 (e.g., K=8=64 / 8). The first matrix has sixteen 8-bit data elements arranged in 2 rows by 8 columns, which are labeled: A0,0 , in bits [7:0]; A 1,0 , in bits [15:8]; A 2,0 , in bits [23:16]; A 3,0 , in bits [31:24]; A 4,0 , in bits [39:32]; A 5,0 , in bits [47:40]; A 6,0 , in bits [55:48]; and A 7,0 , in bits [63:56]; A 0,1 , in bits [71:64]; A 1,1 , in bits [79:72]; A 2,1 , in bits [87:80]; A 3,1 , in bits [95:88]; A 4,1 , in bits [103:96]; A 5,1 , in bits [111:104]; A 6,1 , in bits [119:112]; and A 7,1 , in bits [127:120], where the A elements are sorted by A k,m The second matrix has sixteen 8-bit data elements arranged in 8 rows by 2 columns, which are labeled: B 0,0 , in bits [7:0]; B 0,1 , in bits [15:8]; B 0,2 , in bits [23:16]; B 0,3 , in bits [31:24]; B 0,4 , in bits [39:32]; B 0,5 , in bits [47:40]; B 0,6 , in bits [55:48]; B 0,7 , in bits [63:56]; B 1,0 , in bits [71:64]; B 1,1 , in bits [79:72]; B 1,2 , in bits [87:80]; B 1,3 , in bits [95:88]; B 1,4 , in bits [103:96]; B 1,5 , in bits [111:104]; B 1,6 , in bits [119:112]; and B 1,7 , in bits [127:120], where the B elements are ordered by B n,kThe third matrix has four 32-bit data elements arranged in 2 rows by 2 columns, which are labeled: C 0,0 , in bits [31:0]; C 1,0 , in bits [63:32]; C 0,1 , in bits [95:64]; and C 1,1 , in bits [127:96], where the C elements are in C n,m This arrangement of 8-bit data elements and 32-bit data elements within a matrix may tend to be more efficient than certain other arrangements (e.g., more efficient in managing smaller matrices as part of an overall algorithm that multiplies and accumulates larger matrices), but other arrangements may alternatively be used if desired.

[0051] Execution circuitry 403 is coupled to decoder circuitry 402. The execution circuitry may perform vector packed matrix multiplication and accumulation operations corresponding to the instruction. These operations may include generating a result matrix 415. The result matrix may have four 32-bit data elements arranged in 2 rows by 2 columns, which are labeled: D 0,0 , in bits [31:0]; D 1,0 , in bits [63:32]; D 0,1 , in bits [95:64]; and D 1,1 , in bits [127:96], where the D elements are in D n,m The result matrix may represent the accumulation of the third matrix 409 and the product matrix generated from the matrix multiplication using the first matrix 405 and the second matrix 407. This may be described elsewhere herein (e.g., for Figure 1 ), for example, optionally with conversion, optionally with rounding as needed, etc. The execution circuit may also store the result matrix in a 128-bit lane of the third vector register. For example, the result matrix may overwrite the third matrix in the 128-bit lane of the third vector register.

[0052] In some embodiments, the 8-bit data elements of the first matrix and the second matrix may each be a bfloat8 (BF8) data element. In other embodiments, the 8-bit data elements of the first matrix and the second matrix may each be an hfloat8 (HF8) data element. In other embodiments, the 8-bit data elements of the first matrix may each be a bfloat8 (BF8) data element, and the 8-bit data elements of the second matrix may each be an hfloat8 (HF8) data element. In other embodiments, the 8-bit data elements of the first matrix may each be an hfloat8 (HF8) data element, and the 8-bit data elements of the second matrix may each be a bfloat8 (BF8) data element. In any of the above embodiments of this paragraph, the 32-bit data elements of the third matrix and the fourth matrix may each be a single-precision floating point (F32) data element.

[0053] In yet other embodiments, the 8-bit data elements of the first matrix and the second matrix may each be an 8-bit signed integer (S8) data element. In other embodiments, the 8-bit data elements of the first matrix and the second matrix may each be an 8-bit unsigned integer (U8) data element. In other embodiments, the 8-bit data elements of the first matrix may each be an 8-bit signed integer (S8) data element, and the 8-bit data elements of the second matrix may each be an 8-bit unsigned integer (U8) data element. In other embodiments, the 8-bit data elements of the first matrix may each be an 8-bit unsigned integer (U8) data element, and the 8-bit data elements of the second matrix may each be an 8-bit signed integer (S8) data element. In any of the above embodiments of this paragraph, the 32-bit data elements of the third matrix and the fourth matrix may each be a 32-bit signed integer (int32) data element. In some embodiments, each vector register may optionally include more than one 128-bit lane (e.g., two, four, eight, or some other number of 128-bit lanes), where each 128-bit lane stores a corresponding matrix, and the operations may further include performing separate multiplication and accumulation operations on these different lanes of the matrices similar to those described. In some embodiments, the vector packed matrix multiply and accumulate instructions 401 may be any of the VPMMUUBD, VPMMSSBD, VPMMUSBD, VPMMSUBD, VMMBF8PS, VMMHF8PS, VMMBHF8PS, and VMMHBF8PS instructions described further below, and the execution circuitry may perform any of the operations described further below for any of these instructions.

[0054] Described below are example embodiments of instructions. These instructions may be labeled VMMTF32PS, VMM[BF16,F16]PS, VPMM[UU,SS,US,SU]BD, and VMM[B,H,BH,HB]F8PS. In some embodiments, VMM[BF16,F16]PS may be two separate instructions (e.g., one instruction for BF16 and another for F16), while in other embodiments, it may be one instruction with an immediate value, field, or operand for selecting or indicating one of BF16 and F16. Similarly, in some embodiments, VPMM[UU,SS,US,SU]BD may be four separate instructions (e.g., one instruction for each of UU, SS, US, and SU), while in other embodiments, it may be one instruction with an immediate value, field, or operand for selecting or indicating one of UU, SS, US, and SU. Similarly, in some embodiments, VMM[B,H,BH,HB]F8PS may be four separate instructions (e.g., one for each of B, H, BH, and HB), while in other embodiments it may be one instruction with an immediate value, field, or operand for selecting or indicating one of B, H, BH, and HB.

[0055] In the pseudocode below, "src1" specifies a first source operand, "src2" specifies a second source operand, "DEST" specifies a destination operand, "srcdest" specifies a source operand that is implicitly reused as a destination operand, and "TMP" specifies a temporary value generated during the operation. Further, in the x86 instruction set architecture (ISA), "xmm", "ymm", and "zmm" specify 128-bit, 256-bit, and 512-bit registers, respectively. These broadly represent 128-bit, 256-bit, and 512-bit registers. "ModRM:reg(r,w)", "ModRM:11:rrr:bbb", "VEX.vvvv(r)", and "ModRM:reg(r)" specify operand addressing modes used in the x86 ISA. The first two set bits "11" of ModRM:11:rrr:bbb specify register / register access in which the operand is optionally allowed only in registers rather than in memory, which is not necessary for other embodiments. "VL" (e.g., as in "VL=128") specifies the vector length, and "KL" specifies the number of 128-bit segment channels in a vector with a vector length of VL. "FOR" (e.g., as in "FOR n:=0 to x") specifies the start of a loop after a certain number of iterations (e.g., x+1 iterations). The symbol ":=" specifies that the value on the right hand side is assigned to the variable on the left hand side. The notation "[x:0]" specifies the range of bit positions. For example, "src1[127:0]" specifies the bit positions of bits 0 to 127 of src1, [31:0] in "TMP1.fp32[31:0]" specifies bits 0 to 31 of TMP1.fp32, and so on. The asterisk "*" symbol specifies multiplication. Two backslashes " / / " precede comments about pseudocode. "RET" specifies a return (eg, storage of a destination operand to a destination register).

[0056] Furthermore, in the pseudocode below, the following items specify how data elements are accessed or addressed: (1).128b specifies that vector elements are interpreted as 128 bits wide; (2).fp32 specifies that vector elements are interpreted as F32 (float32) values; (3).tf32 specifies that vector elements are interpreted as TF32 (tensor floating point 32) values; (4).bf16 specifies that vector elements are interpreted as BF16 (bfloat16) values; (5).fp16 specifies that vector elements are interpreted as Interpret as F16 (float16) values; (6).bf8 specifies that the vector elements are interpreted as BF8 (bfloat8) values; (7).hf8 specifies that the vector elements are interpreted as HF8 (hfloat8) values; (8).i32 specifies that the vector elements are interpreted as I32 (signed int32) values; (9).s8 specifies that the vector elements are interpreted as S8 (signed int8) values; (10).u8 specifies that the vector elements are interpreted as U8 (unsigned int8) values.

[0057] VMMTF32PS instruction: one or more 128-bit lanes of packed TF32 small matrix multiplication: each 128-bit lane in src1 and src2 is interpreted as a 2x2 (A) matrix or a 2x2 (B) matrix, and the A matrix and the B matrix in the corresponding 128-bit lane are matrices multiplied with each other. The result is a 2×2 intermediate matrix in FP32, and the elements of this 2×2 intermediate matrix are added to the corresponding elements of the accumulation matrix in srcdest. VL=128VMMTF32PS xmm1,xmm2,xmm3 VL=256VMMTF32PS ymm1,ymm2,ymm3 VL=512VMMTF32PS zmm1,zmm2,zmm3 Operation object 1: ModRM:reg(r,w) Operation object 2: VEX.vvvv(r) Operation object 3: ModRM:reg(r)

[0058] VMMTF32PS dest,src1,src2

[0059] Pseudo code operation tf32fp32_2x2x2_matmul(src1[127:0],src2[1 27:0])

[0060] TF32FP32Mul represents a scalar multiplication of two TF32 elements that produces an FP32 product. In some embodiments, the source data elements may optionally be converted to larger (e.g., higher precision) data elements (e.g., 32-bit single-precision floating point data elements). The operation may also implement floating point rounding as needed, handle denormals as needed (e.g., whether to FTZ, whether to DAZ), and propagate NaNs and infinities as needed.

[0061] VMM[BF16 / F16] PS instruction: One or more 128-bit lanes of packed BF16 and / or FP16 small matrix multiplication: Each 128-bit lane in src1 and src2 is interpreted as a 2×4 (A) matrix or a 4×2 (B) matrix, and the A matrix and the B matrix in the corresponding 128-bit lane are matrices multiplied with each other. The result is an intermediate 2×2 matrix in FP32, and the elements of the intermediate 2×2 matrix are added to the corresponding elements of the accumulation matrix in srcdest. VL=128VMM[BF16 / F16]PS xmm1,xmm2,xmm3 VL=256VMM[BF16 / F16]PS ymm1,ymm2,ymm3 VL=512VMM[BF16 / F16]PS zmm1,zmm2,zmm3 Operation object 1: ModRM:reg(r,w) Operation object 2: c(r) Operation object 3: ModRM:reg(r)

[0062] VMMBF16PS dest,src1,src2

[0063] Pseudo code operation bf16fp32_2x2x4_matmul(src1[127:0],src2[127:0])

[0064] BF16FP32Mul represents a scalar multiplication of two BF16 elements that generates an FP32 product. In some embodiments, the source data elements may optionally be converted to larger (e.g., higher precision) data elements (e.g., 32-bit single-precision floating point data elements). The operation may also implement floating point rounding as needed, handle denormals as needed (e.g., whether to FTZ, whether to DAZ), and propagate NaNs and infinities as needed.

[0065] VMMF16PS dest,src1,src2

[0066] Pseudo code operation f16fp32_2x2x4_matmul(src1[127:0],src2[127:0])

[0067] F16FP32Mul represents a scalar multiplication of two FP16 elements that generates an FP32 product. In some embodiments, the source data elements may optionally be converted to larger (e.g., higher precision) data elements (e.g., 32-bit single-precision floating point data elements). The operation may also implement floating point rounding as needed, handle denormals as needed (e.g., whether to FTZ, whether to DAZ), and propagate NaNs and infinities as needed.

[0068] VPMM[UU / SS / US / SU]BD instruction: One or more 128-bit lanes of packed unsigned-unsigned, signed-signed, unsigned-signed, or signed-unsigned 8-bit integer small matrix multiplication: Each 128-bit lane in src1 and src2 is interpreted as a 2×8 (A) matrix or an 8×2 (B) matrix, and the A matrix and the B matrix in the corresponding 128-bit lane are the matrices that are multiplied with each other. A and B can be signed or unsigned int8. The result is an intermediate 2×2 matrix in int32, and the elements of this intermediate 2×2 matrix are added to the corresponding elements of the accumulation matrix in srcdest. VL=128VPMM[UU / SS / US / SU]BD xmm1,xmm2,xmm3 VL=256VPMM[UU / SS / US / SU]BD ymm1,ymm2,ymm3 VL=512VPMM[UU / SS / US / SU]BD zmm1,zmm2,zmm3 Operation object 1: ModRM:reg(r,w) Operation object 2: VEX.vvvv(r) Operation object 3: ModRM:reg(r)

[0069] VPMMUUBD dest,src1,src2

[0070] Pseudo code operation uu8i32_2x2x8_matmul(src1[127:0],src2[127:0])

[0071] UU8I32Mul represents a scalar multiplication of two U8 elements that produces an I32 product. In some embodiments, the source data elements may optionally be converted to larger (eg, higher precision) data elements (eg, 32-bit integer data elements).

[0072] VPMMSSBD dest,src1,src2

[0073] Pseudo code operation ss8i32_2x2x8_matmul(src1[127:0],src2[127:0])

[0074] SS8I32Mul represents a scalar multiplication of two S8 elements that produces an I32 product. In some embodiments, the source data elements may optionally be converted to larger (eg, higher precision) data elements (eg, 32-bit integer data elements).

[0075] VPMMUSBD dest,src1,src2

[0076] Pseudo code operation us8i32_2x2x8_matmul(src1[127:0],src2[127:0])

[0077] US8I32Mul represents a scalar multiplication of a U8 element and a S8 element to generate an I32 product. In some embodiments, the source data elements may optionally be converted to larger (eg, higher precision) data elements (eg, 32-bit integer data elements).

[0078] VPMMSUBD dest,src1,src2

[0079] Pseudo code operation su8i32_2x2x8_matmul(src1[127:0],src2[127:0])

[0080] SU8I32Mul represents a scalar multiplication of an S8 element and a U8 element to generate an I32 product. In some embodiments, the source data elements may optionally be converted to larger (eg, higher precision) data elements (eg, 32-bit integer data elements).

[0081] VMM[B / H / BH / HB]F8PS instruction: One or more 128-bit lanes of packed 8-bit floating-point small matrix multiplication: Each 128-bit lane in src1 and src2 is interpreted as a 2×8 (A) matrix or an 8×2 (B) matrix, and the A matrix and the B matrix in the corresponding 128-bit lane are matrices that are multiplied with each other. The A matrix and the B matrix can have BF8 (also known as E5M2, with 5 exponent bits and 2 explicit mantissa bits) elements or HF8 (also known as E4M3, with 4 exponent bits and 3 explicit significand bits) elements independently of each other. The result is an intermediate 2×2 matrix in FP32, and the elements of this intermediate 2×2 matrix are added to the corresponding elements of the accumulation matrix in srcdest. VL=128VMM[B / H / BH / HB]F8PS xmm1,xmm2,xmm3 VL=256VMM[B / H / BH / HB]F8PS ymm1,ymm2,ymm3 VL=512VMM[B / H / BH / HB]F8PS zmm1,zmm2,zmm3 Operation object 1: ModRM:reg(r,w) Operation object 2: VEX.vvvv(r) Operation object 3: ModRM:reg(r)

[0082] VMMBF8PS dest,src1,src2

[0083] Pseudo code operation bf8fp32_2x2x8_matmul(src1[127:0],src2[127:0])

[0084] BF8FP32Mul represents a scalar multiplication of two BF8 elements that generates an FP32 product. In some embodiments, the source data elements may optionally be converted to larger (e.g., higher precision) data elements (e.g., 32-bit single-precision floating point data elements). The operation may also implement floating point rounding as needed, handle denormals as needed (e.g., whether to FTZ, whether to DAZ), and propagate NaNs and infinities as needed.

[0085] VMMHF8PS dest,src1,src2

[0086] Pseudo code operation hf8fp32_2x2x8_matmul(src1[127:0],src2[127:0])

[0087] HF8FP32Mul represents a scalar multiplication of two HF8 elements that generates an FP32 product. In some embodiments, the source data elements may optionally be converted to larger (e.g., higher precision) data elements (e.g., 32-bit single-precision floating point data elements). The operation may also implement floating point rounding as needed, handle denormals as needed (e.g., whether to FTZ, whether to DAZ), and propagate NaNs and infinities as needed.

[0088] VMMBHF8PS dest,src1,src2

[0089] Pseudo code operation bhf8fp32_2x2x8_matmul(src1[127:0],src2[127:0])

[0090] BHF8FP32Mul represents a scalar multiplication of a BF8 element and a HF8 element to generate an FP32 product. In some embodiments, the source data elements may optionally be converted to larger (e.g., higher precision) data elements (e.g., 32-bit single-precision floating point data elements). The operation may also implement floating point rounding as needed, handle denormals as needed (e.g., whether to FTZ, whether to DAZ), and propagate NaNs and infinities as needed.

[0091] VMMHBF8PS dest,src1,src2

[0092] Pseudo code operation hbf8fp32_2x2x8_matmul(src1[127:0],src2[127:0])

[0093] HBF8FP32Mul represents a scalar multiplication of HF8 elements and BF8 elements to generate an FP32 product. In some embodiments, the source data elements may optionally be converted to larger (e.g., higher precision) data elements (e.g., 32-bit single-precision floating point data elements). The operation may also implement floating point rounding as needed, handle denormals as needed (e.g., whether to FTZ, whether to DAZ), and propagate NaNs and infinities as needed.

[0094] It will be appreciated that, for each of the specific instructions described above, the accumulation of the products of matrix multiplication and the specific order of the accumulation of the accumulated values ​​from the source / destination matrix is ​​not necessary. Each of the specific instructions described above indicates a possible order for such addition / accumulation, but this specific order is only an example and is not necessary. For each instruction, multiple (if not many) other orders are also possible. Floating-point addition is not strictly associated. The result is that when floating-point addition is performed in different orders, slightly different results may be obtained, which is the reason for specifying a specific example order in the architecture description of these instructions. However, many variations of instructions in which the order is changed in various ways are contemplated. As an example, for bf8fp32_2x2x78_matmul operation, the illustrated embodiment performs column horizontal simplification, vertical simplification and then horizontal simplification, but this is not necessary. In other embodiments, many other orders of addition may optionally be used (e.g., P0e.fp32[31:0] may be added to P1e.fp32[31:0] to form a temporary value, P0e.fp32[31:0] may be added to P2e.fp32[31:0] to form a temporary value, P0e.fp32[31:0] may be added to P20.fp32[31:0] to form a temporary value, these temporary values ​​may be added in a different order, and so on).

[0095] In some embodiments, accumulation can be performed "late", because the accumulation of products and accumulated values ​​and / or registers for holding accumulated values ​​is only performed after all multiplications have been performed. In some embodiments, all products are accumulated with accumulated values ​​after all products have been generated. Another possible way can be to sequentially access the accumulated values ​​and / or registers for holding accumulated values ​​twice or more, including accessing once after a part (e.g., half) of the multiplication has been performed, and accessing again after another part (e.g., half) of the multiplication has been performed. The possible advantage of such "late" accumulation is that it may help solve latency characteristics and / or improve the quality of numerical results. Due to late accumulation, only the final result is exposed to the scheduler of the out-of-order (OoO) machine. Moreover, resetting the accumulator of operation (e.g., as may be performed for late accumulation) may tend to improve the overall result quality, because rounding errors (which may be encountered in floating points) may tend to be reduced.

[0096] In some embodiments, one or more of the instructions disclosed above, or each instruction, may have one or more optional attributes, as described below, to achieve certain advantages (e.g., improve performance, simplify implementation, make the instructions better for certain types of workloads, etc.). One area where such simplifications may be made is when dealing with floating point numbers. These simplifications apply only to instructions that operate on floating point data elements, not instructions that operate on integers.

[0097] In some embodiments, the processor may have an MXCSR, a floating point control and / or status register, or other register for controlling floating point operations. In some embodiments, the register may have one or more fields (e.g., a rounding mode field) for specifying a rounding mode to be used for floating point operations from a plurality of supported rounding modes. In some embodiments, one or more of the instructions disclosed above, or each instruction, may control rounding to be performed only according to a single rounding mode (e.g., a nearest to even rounding mode in some cases), regardless of and / or regardless of one or more fields in the register (e.g., the rounding mode field), and / or without checking the one or more fields. In some such embodiments, rounding may be performed in a mathematically precise manner according to a single rounding mode, rather than by simplification that results in a mathematically inaccurate result.

[0098] In some embodiments, the MXCSR, floating point control and / or status register, or other register for controlling floating point operations may have one or more fields (e.g., a Flush to Zero (FTZ) bit or field) for specifying that a denormal result of a floating point operation is to be set to zero or forced to zero or set to zero. In some such embodiments, one or more of the instructions disclosed above, or each instruction, may control or cause the processor to set a denormal result of a floating point operation to zero, force the denormal result to zero, or set the denormal result to zero, regardless of and / or regardless of whether one or more fields (e.g., FTZ bits or fields) in the register specify that a denormal result of a floating point operation is to be set to zero or forced to zero or set to zero, and / or without checking whether the one or more fields specify that a denormal result of a floating point operation is to be set to zero or forced to zero or set to zero.

[0099] In some embodiments, the MXCSR, floating point control and / or status register, or other register for controlling floating point operations may have one or more fields (e.g., Denormal As Zero (DAZ) bits or fields) for specifying whether denormal values ​​in an input (e.g., a source matrix) to a floating point instruction / operation are to be set to zero or zeroed or treated as zero. In some such embodiments, one or more of the instructions disclosed above, or each instruction, may control or cause processing to set denormal numbers in an input to a floating point operation to zero or zeroed, or treat denormal numbers in an input to a floating point operation as zero, regardless of and / or regardless of whether one or more fields (e.g., DAZ bits or fields) in the register specify that denormal numbers in an input to a floating point operation are to be forced to zero, and / or without checking whether the one or more fields specify that denormal numbers in an input to a floating point operation are to be forced to zero by a mode. Alternatively, in other embodiments, instructions that operate on FP16 and FP8 source floating-point data elements (e.g., VMMF16PS, VMMBF8PS, VMMHF8PS, VMMBHF8PS, and VMMHBF8PS instructions) may optionally respect the DAZ bit or field in a register (e.g., not treating denormal values ​​in the input to the floating-point operation as zero, regardless of whether one or more fields specify that denormal values ​​in the input to the floating-point operation are to be treated as zero). One possible reason to turn off DAZ for FP16 and / or FP8 data element formats is that the FP16 and / or FP8 data element formats have fewer exponent bits (e.g., a smaller numeric range), making it more appropriate to handle denormal values ​​in the input / source rather than treating denormal values ​​in the input / source as zero.

[0100] In some embodiments, the MXCSR, floating point control and / or status register, or other register for controlling floating point operations may have one or more fields for controlling whether floating point instructions / operations report floating point exceptions. In some such embodiments, one or more instructions or each instruction in the instructions disclosed above may control or cause the processor to not report floating point exceptions, regardless of and / or regardless of whether one or more fields in the register specify that floating point exceptions are to be reported, and / or without checking whether the one or more fields specify that floating point exceptions are to be reported. In some embodiments, the instruction may optionally cause the processor to propagate Not-a-Number (NaN) or infinity (Inf).

[0101] In some such embodiments, one or more or each of the instructions disclosed above may control or cause the processor to complete execution of the operations corresponding to the instructions without accessing the MXCSR, floating point control and / or status registers, or other registers used to control floating point operations (e.g., without reading from these registers and without writing to these registers).

[0102] Although such floating-point features may not be suitable for all workloads, some workloads may benefit from enhanced performance and / or simpler implementation that may result from such floating-point features. Strict compliance with floating-point standards and support for all variations of floating-point features are often achieved at a cost. Certain workloads (e.g., artificial intelligence) may not require all of these floating-point features to be supported by instructions and may benefit more from higher performance and / or simpler implementation.

[0103] In some embodiments, one or more instructions or each instruction in the instructions disclosed above may optionally only allow source and destination operands to be in registers rather than in memory, but this is not necessary. In some embodiments, even if the instruction is implemented by an ISA that is not a load-store ISA and that makes the ISA include other data processing instructions that can specify the operands in the memory and operate on the operands in the memory, this may also be the case. As an example, in x86 ISA, the instruction may use the ModRM:11:rrr:bbb operand addressing mode. A possible reason for doing this is to promote the improvement of the performance of the execution instruction (for example, there is no waiting time for the memory operand access), which may be more beneficial for some workloads than needing to access the operands in the memory. Another possible reason is to reduce the risk of side channel attacks. However, in other embodiments, it may be optionally allowed to obtain the source matrix from the memory.

[0104] In some embodiments, one or more or each of the instructions disclosed above may optionally be allowed to operate only in 64-bit mode (e.g., not in 32-bit mode), but this is not required. Supporting only 64-bit mode may potentially help improve performance (e.g., potentially allow access to a greater number of registers, potentially simplify implementation (e.g., eliminate one or more checks), etc.). However, in other embodiments, the instructions may also be supported in 32-bit mode.

[0105] In some embodiments, any one or more of the characteristics described above may optionally be implicit to instructions (e.g., implicit to their opcodes) such that instructions can only have these characteristics. In other embodiments, any one or more of the characteristics described above may optionally be configured or configurable for instructions (e.g., opcodes of instructions) such that (one or more) characteristics may be configured or configurable for instructions (e.g., enabled or disabled). In some embodiments, the processor may have one or more bits, flags, or configurable controls (e.g., in floating point status and / or control registers, in model specific registers (MSRs), etc.) to store such configuration information. Each control may have a first value to specify whether a characteristic or an alternate characteristic is to be used. For example, a control may indicate whether the FTZ field is to be followed or overridden by an instruction, etc.

[0106] The detailed instruction described above represents the specific example of suitable instruction. However, many modifications to these instructions are possible. For example, the instruction above quotes xmm, ymm and zmm registers, and they represent registers in x86 ISA. In other embodiments, in another non-x86 ISA, these xmm, ymm and zmm registers can be replaced by other 128 bits, 256 bits or 512 bit registers optionally. For example, xmm, ymm and zmm registers can be replaced by the scalable vector registers Z0-Z31 used in the scalable vector extension (Scalable Vector Extension, SVE) or SVE2 of ARM architecture optionally. Thus, other embodiments of the instruction above can widely use 128 bits, 256 bits or 512 bits registers or scalable vector registers to replace the xmm, ymm and zmm registers shown in the above example. In other embodiments, instructions can also support different vector register sizes (for example, 640 bits, 768 bits, 1024 bits, etc.) comprising different numbers of 128 bit channels. As another example, masking / predicates are optionally not used for these instructions, but in other embodiments, masking / predicates may be optionally used. As another example, some of the instructions above may use one or more of "ModRM:reg(r,w)", "ModRM:11:rrr:bbb", "VEX.vvvv(r)" or "ModRM:reg(r)", which represent operand addressing modes specific to the instruction encoding format used in the x86 ISA. In other embodiments, these operand addressing modes may broadly represent operand addressing modes that may be optionally replaced by other operand addressing modes used by the instruction encoding and / or used in other non-x86 ISAs. Further, the first two set bits "11" of ModRM:11:rrr:bbb specify register / register accesses in which the operand is optionally only allowed to be in a register rather than in a memory, but this is not necessary for other embodiments in which the source operand may originate from a memory. As another example, some of the instructions above reference MXCSR, which is a floating point status and / or control register in non-x86 ISAs. In other embodiments, MXCSR may be optionally replaced by a floating point status and / or control register in another non-x86 ISA. Thus, other embodiments of the instructions above may reference another floating point status and / or control register.

[0107] Figure 5 is an operation for executing instruction 501 (e.g., for Figure 1101) is a block diagram of a more detailed example embodiment of a processor 500 for an embodiment of the described instructions 101). The processor includes a decoder circuit 502 for decoding the instructions, an execution circuit 503 for performing operations corresponding to the instructions, and a register and / or memory 522 for storing a matrix for the instructions. In addition to aspects related to additional components of the processor 500, the instructions 501, the decoder circuit 502, the execution circuit 503, and the register / memory 522 may optionally be associated with an embodiment of the described instructions 101. Figure 1 To avoid obscuring this specification, the following will be mainly described. Figure 5 The different and / or additional components and aspects, without duplication, may optionally be combined with those already described for Figure 1 aspects that are the same or similar to those described.

[0108] An optional storage device 520 may be used to store instructions 501. As an example, the storage device may be a cache (e.g., an instruction cache, a unified cache) or a memory coupled to the processor. Decoder circuit 502 may receive instructions and decode the instructions as previously described. The decoder circuit may optionally be coupled to the storage device via an optional fetch circuit (not shown) to receive instructions.

[0109] In some examples, the optional register renaming, register allocation and / or scheduling circuitry 521 may provide functionality for one or more of the following: (1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some examples); (2) assigning status bits and flags to decoded instructions; and (3) scheduling decoded instructions from an instruction pool for execution by execution circuitry (e.g., using a reservation station in some examples). As previously described, registers and / or memory 522 may store source matrices and result matrices for instructions.

[0110] The execution circuit 503 is coupled to the decoder circuit 502 and the register / memory 522 via the intervening register renaming, register allocation and / or scheduling circuit 521. As previously described, the execution circuit can perform operations corresponding to the instructions. One possible example of an execution circuit is the (one or more) execution clusters 1160 shown in Figure 11 (B). The optional retirement / writeback circuit 523 can architecturally commit the destination register to the register / memory 522 and commit the instruction.

[0111] Figure 61 is a flowchart of an embodiment of a method 625 for executing an embodiment of a vector-tightened matrix multiplication and accumulation instruction. In various embodiments, the method may be performed by a processor, a digital logic device, or an integrated circuit. As an example, a processor 100, 200, 300, 400, or 500, a processor core 1190 of FIG. 11 (B), or a pipeline further described below may perform such a method. The components, features, and specific optional details described herein for a processor 100, 200, 300, 400, or 500, a processor core 1190, or a pipeline 1100 may be optionally applied to the method. Alternatively, the method 625 may be performed by a similar or different processor, core, or pipeline. Moreover, the processor 100, 200, 300, 400, or 500 may perform a method identical, similar, or different to the method 625.

[0112] At 626, an instance of a single vector packed matrix multiply and accumulate instruction is obtained. The single instruction can be any of those instructions described elsewhere herein. In some examples, the instruction is obtained from an instruction cache. The instruction may explicitly specify or otherwise indicate a first (e.g., source) matrix (e.g., indicating a first vector register with 128-bit lanes for storing the first matrix), the first matrix having 2 rows by K columns of data elements, each of which has a first number of bits, where K is equal to 64 bits divided by the first number of bits; may explicitly specify or otherwise indicate a second (e.g., source) matrix (e.g., indicating a second vector register with 128-bit lanes for storing the second matrix), the second matrix having K rows by 2 columns of data elements, each of which has a first number of bits; and may explicitly specify or otherwise indicate a third (e.g., source) matrix (e.g., indicating a third vector register with 128-bit lanes for storing the third matrix), the third matrix having 2 rows by 2 columns of data elements, each of which has a second number of bits, the second number of bits being greater than the first number of bits. At least one, at least two, or all three of these matrices may be stored in vector registers and / or in a one-dimensional vector format. These matrices may optionally be combined with those described elsewhere herein (e.g., as previously described for Figure 1-Figure 4 The matrix described above is the same or similar.

[0113] The fetched instructions may be decoded at 627. For example, the fetched instructions may be decoded by a decoder circuit (eg, decoder circuit 102).

[0114] When the decoded instructions are dispatched, the source operands may be retrieved at 628. For example, when one or more of the source operands are memory operands, data may be retrieved from the indicated memory locations.

[0115] At 629, the decoded instruction is executed by an execution circuit (e.g., execution circuits 103, 203, 303, 403, and (one or more) execution clusters of FIG. 11 (B)). This may include executing an operation corresponding to and / or according to the instruction. In some embodiments, the operation may include generating a result matrix having 2 rows by 2 columns (e.g., M=2, N=2) result data elements, each of which has a second number of bits. In some embodiments, the result matrix may represent an accumulation of a third matrix (e.g., an accumulation matrix) and a product matrix (e.g., having 2 rows by 2 columns), the product matrix being generated from a matrix multiplication using and / or involving and / or based on a first matrix and a second matrix. In some embodiments, the product matrix may be generated from a matrix multiplication using a first matrix and a second matrix, wherein before the matrix multiplication, the data elements of the first matrix and the second matrix are converted from a first number of bits to a larger number of bits (e.g., from 8 bits or 16 bits to 32 bits). In some embodiments, the product matrix may be generated from a matrix multiplication using the first matrix and the second matrix, wherein during the matrix multiplication, floating point rounding may be optionally performed as desired. In some embodiments, the operation may include storing the result matrix in a 128-bit lane of a third vector register originally used to store the third matrix. In some embodiments, the operation may include any of those operations described elsewhere herein, including operations described for the detailed example instructions described herein (e.g., any of VMMTF32PS, VMM[BF16,F16]PS, VPMM[UU,SS,US,SU]BD, and VMM[B,H,BH,HB]F8PS).

[0116] In some examples, the instruction may be committed or retired at 630. This may cause the resultant operand to be stored in a destination register (eg, a renamed register that was committed to an architectural register).

[0117] Figure 7It is a flowchart of an embodiment of method 732 of an embodiment of an embodiment of performing vector compact matrix multiplication and accumulation instructions using simulation or binary translation. In various embodiments, method 732 may be performed by a processor, a digital logic device, or an integrated circuit. As an example, processor 100, 200, 300, 400, or 500, the processor core 1190 of FIG. 11 (B), or the pipeline executable method 732 further described below. The components, features, and specific optional details described herein for processor 100, 200, 300, 400, or 500, processor core 1190, or pipeline 1100 may be optionally applied to the method. Alternatively, method 732 may be performed by similar or different processors, cores, or pipelines. Moreover, processor 100, 200, 300, 400, or 500 may perform the same, similar, or different methods as method 732.

[0118] At 733, an instance of a single vector packed matrix multiply and accumulate instruction of the first instruction set architecture is obtained. The single instruction can be any of those instructions described elsewhere herein (e.g., any of instructions 101, 201, 301, 401). In some examples, the instruction is obtained from an instruction cache. The instruction may explicitly specify or otherwise indicate a first (e.g., source) matrix (e.g., indicating a first vector register having 128-bit lanes for storing the first matrix), the first matrix having 2 rows by K columns of data elements, each of which has a first number of bits, where K is equal to 64 bits divided by the first number of bits; may explicitly specify or otherwise indicate a second (e.g., source) matrix (e.g., indicating a second vector register having 128-bit lanes for storing the second matrix), the second matrix having K rows by 2 columns of data elements, each of which has a first number of bits; and may explicitly specify or otherwise indicate a third (e.g., source) matrix (e.g., indicating a third vector register having 128-bit lanes for storing the third matrix), the third matrix having 2 rows by 2 columns of data elements, each of which has a second number of bits, the second number of bits being greater than the first number of bits. At least one, two, or all three of these matrices may be stored in vector registers and / or in a one-dimensional vector format. These matrices may optionally be combined with those described elsewhere herein (e.g., as previously described for Figure 1-Figure 4 The matrix described above is the same or similar.

[0119] At 734, the obtained single vector packed matrix multiply and accumulate instruction of the first instruction set architecture is translated into one or more instructions of a different second instruction set architecture. In some examples, such translation can be performed by a translation and / or emulation layer of software. In some examples, such translation can be performed by a software such as Fig. 20The instruction converter 2012 shown in FIG. 2014 is performed. In some examples, the translation may be performed by a hardware translation circuit.

[0120] At 735, one or more translated instructions of the second instruction set architecture are decoded. For example, the translated instructions may be decoded by a decoder circuit (e.g., one of decoder circuits 102, 202, 302, 402). In some examples, the operations of translating 734 and decoding 735 may optionally be combined.

[0121] When the decoded instructions are dispatched, the source operands may be retrieved at 736. For example, when one or more of the source operands are memory operands, data may be retrieved from the indicated memory locations.

[0122] At 737, the decoded instructions of the second instruction set architecture are executed by the execution circuit (e.g., the execution circuit 103, 203, 303, 403, or the execution cluster (s) 1160 of FIG. 11 (B)) to perform the operations indicated by and / or corresponding to the single instruction of the first instruction set architecture. In some embodiments, the operations may include generating a result matrix having 2 rows by 2 columns (e.g., M=2, N=2) of result data elements, each of which has a second number of bits. In some embodiments, the result matrix may represent an accumulation of a third matrix (e.g., an accumulation matrix) and a product matrix (e.g., having 2 rows by 2 columns), the product matrix being generated from a matrix multiplication using and / or involving and / or based on the first matrix and the second matrix. In some embodiments, the product matrix may be generated from a matrix multiplication using the first matrix and the second matrix, wherein the data elements of the first matrix and the second matrix are converted from a first number of bits to a larger number of bits (e.g., from 8 bits or 16 bits to 32 bits) prior to the matrix multiplication. In some embodiments, the product matrix may be generated from a matrix multiplication using the first matrix and the second matrix, wherein during the matrix multiplication, floating point rounding may be optionally performed as desired. In some embodiments, the operation may include storing the result matrix in a 128-bit lane of a third vector register originally used to store the third matrix. In some embodiments, the operation may include any of those operations described elsewhere herein, including operations described for the detailed example instructions described herein (e.g., any of VMMTF32PS, VMM[BF16,F16]PS, VPMM[UU,SS,US,SU]BD, and VMM[B,H,BH,HB]F8PS).

[0123] In some examples, the decoded instruction(s) of the second instruction set architecture are committed or retired at 738. This may cause the resultant floating-point operand to be stored in an architectural storage location for and / or corresponding to the destination register (e.g., a renamed register that was committed to an architectural register).

[0124] Figure 8 840 is a block diagram of an example embodiment of a suitable vector register set 840. The vector registers include 32 512-bit vector registers labeled ZMM0 to ZMM31. In the illustrated embodiment, the lower order 256 bits of the lower 16 registers (i.e., ZMM0-ZMM15) are aliased as corresponding 256-bit vector registers labeled YMM0-YMM15 or overlapped on these 356-bit vector registers. Similarly, in the illustrated embodiment, the lower order 128 bits of registers YMM0-YMM15 are aliased as corresponding 128-bit vector registers labeled XMM0-XMM15, or overlapped on these 128-bit vector registers. The 512-bit registers ZMM0 to ZMM31 operate to hold 512-bit vectors, 256-bit vectors, or 128-bit vectors. The 256-bit registers YMM0-YMM15 operate to hold 256-bit vectors or 128-bit vectors. 128-bit registers XMM0-XMM15 operate to hold 128-bit vectors. In some embodiments, each register may be used to store packed floating point data or packed integer data. The different data element sizes and types supported include any of the 8-bit, 16-bit, 32-bit integer and floating point formats disclosed elsewhere herein. It will be appreciated that this is merely an illustrative example of a suitable register set. In alternative embodiments, different numbers of registers may be used, and / or different register sizes may be used, and / or larger registers may or may not be aliased to smaller registers.

[0125] Example computer architecture.

[0126] The example computer architecture is described in detail below. Other system designs and configurations for laptop computers, desktop computers, handheld personal computers (personal computers, PCs), personal digital assistants, engineering workstations, servers, decomposed servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (digitalsignal processors, DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices known in the art are also appropriate. In a word, various systems or electronic devices that can include processors and / or other execution logic disclosed herein are generally appropriate.

[0127] Fig. 9 An example computing system is illustrated. Multiprocessor system 900 is an interfaced system and includes multiple processors or cores, including a first processor 970 and a second processor 980 coupled via an interface 950 (e.g., a point-to-point (PP) interconnect, a fabric, and / or a bus). In some examples, the first processor 970 and the second processor 980 are isomorphic. In some examples, the first processor 970 and the second processor 980 are heterogeneous. Although example system 900 is shown as having two processors, the system may have three or more processors, or may be a single processor system. In some embodiments, the computing system is a system on a chip (SoC).

[0128] Processors 970 and 980 are shown as including integrated memory controller (IMC) circuits 972 and 982, respectively. Processor 970 also includes interface circuits 976 and 978; similarly, second processor 980 includes interface circuits 986 and 988. Processors 970, 980 can exchange information via interface 950 using interface circuits 978, 988. IMCs 972 and 982 couple processors 970, 980 to respective memories, namely memory 932 and memory 934, which can be part of the main memory locally attached to the respective processors.

[0129] Processors 970, 980 can each utilize interface circuits 976, 994, 986, 998 to exchange information with a network interface (NW I / F) 990 via respective interfaces 952, 954. Network interface 990 (e.g., one or more of an interconnect, bus, and / or structure, a chipset in some examples) can optionally exchange information with a coprocessor 938 via interface circuit 992. In some examples, coprocessor 938 is a special-purpose processor, such as a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, and the like.

[0130] A shared cache (not shown) may be included in either processor 970, 980, or external to both processors but connected to the processors via an interface (e.g., a PP interconnect) such that if a processor is placed in a low power mode, local cache information of either or both processors may also be stored in the shared cache.

[0131] The network interface 990 can be coupled to the first interface 916 via the interface circuit 996. In some examples, the first interface 916 can be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, the first interface 916 is coupled to a power control unit (PCU) 917, which can include circuits, software, and / or firmware to perform power management operations with respect to the processors 970, 980, and / or the coprocessor 938. The PCU 917 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 917 also provides control information to control the generated operating voltage. In various examples, the PCU 917 can include various power management logic units (circuits) to perform hardware-based power management. Such power management may be entirely processor controlled (e.g., controlled by various processor hardware and may be triggered by workload and / or power constraints, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

[0132] The PCU 917 is illustrated as existing as logic separate from the processor 970 and / or the processor 980. In other cases, the PCU 917 may execute on a given one or more cores of the core (not shown) of the processor 970 or 980. In some cases, the PCU 917 may be implemented as a microcontroller (dedicated or general purpose) or other control logic that is configured to execute its own dedicated power management code (sometimes referred to as P-code). In yet other examples, the power management operations to be performed by the PCU 917 may be implemented outside the processor, such as by a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, the power management operations to be performed by the PCU 917 may be implemented within the BIOS or other system software.

[0133] Various I / O devices 914 and a bus bridge 918 can be coupled to the first interface 916, and the bus bridge 918 couples the first interface 916 to the second interface 920. In some examples, (one or more) additional processors 915 are coupled to the first interface 916, such as a coprocessor, a high-throughput integrated many-core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor. In some examples, the second interface 920 can be a low pin count (LPC) interface. Various devices can be coupled to the second interface 920, including, for example, a keyboard and / or mouse 922, a communication device 927, and a storage circuit 928. The storage circuit 928 can be one or more non-transitory machine-readable storage media described below, such as a disk drive or other mass storage device, which in some examples may include instructions / codes and data 930 and can implement the storage device `ISAB03. In addition, audio I / O 924 can be coupled to second interface 920. Note that other architectures are possible in addition to the point-to-point architecture described above. For example, a system such as multiprocessor system 900 can implement a multi-drop interface or other such architectures instead of a point-to-point architecture.

[0134] Example core architectures, processors, and computer architectures.

[0135] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of these cores may include: 1) general-purpose in-order cores for general-purpose computing purposes; 2) high-performance general-purpose out-of-order cores for general-purpose computing purposes; 3) special-purpose cores, mainly for graphics and / or scientific (throughput) computing purposes. Implementations of different processors may include: 1) a CPU including one or more general-purpose in-order cores for general-purpose computing purposes and / or one or more general-purpose out-of-order cores for general-purpose computing purposes; and 2) a coprocessor including one or more special-purpose cores mainly for graphics and / or scientific (throughput) computing purposes. These different processors result in different computer system architectures, which may include: 1) coprocessors on separate chips from the CPU; 2) coprocessors on separate dies in the same package as the CPU; 3) coprocessors on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or as dedicated cores); and 4) systems on a chip (SoCs), which may be included on the same die with the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessors described above, and additional functionality. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0136] Fig.10 A block diagram of an example processor and / or SoC 1000 is illustrated, which may have one or more cores and have an integrated memory controller. The processor 1000 illustrated in solid line boxes has a single core 1002(A), a system agent unit circuit 1010, and a set of one or more interface controller unit circuits 1016, while the optionally added dashed line boxes illustrate an alternative processor 1000 as having multiple cores 1002(A)-(N), a set of one or more integrated memory control unit circuits 1014 in the system agent unit circuit 1010, dedicated logic 1008, and a set of one or more interface controller unit circuits 1016. Note that the processor 1000 may be Fig. 9 One of the processors 970 or 980 or the coprocessors 938 or 915.

[0137] Thus, different implementations of processor 1000 may include: 1) a CPU, where dedicated logic 1008 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 1002(A)-(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 1002(A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 1002(A)-(N) are a large number of general purpose in-order cores. Thus, processor 1000 may be a general purpose processor, a coprocessor, or a special purpose processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 1000 may be part of and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0138] The memory hierarchy includes one or more levels of cache unit circuits 1004(A)-(N) within the cores 1002(A)-(N), a set of one or more shared cache unit circuits 1006, and an external memory (not shown) coupled to the set of integrated memory controller unit circuits 1014. The set of one or more shared cache unit circuits 1006 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some examples an interface network circuit 1012 (e.g., a ring interconnect) provides an interface to dedicated logic 1008 (e.g., integrated graphics logic), the set of shared cache unit circuits 1006, and the system agent unit circuit 1010, alternative examples use any number of well-known techniques to provide interfaces to these units. In some examples, coherency is maintained between one or more circuits in the shared cache unit circuits 1006 and the cores 1002(A)-(N). In some examples, interface controller unit circuitry 1016 couples the cores 1002 to one or more other devices 1018 , such as one or more I / O devices, storage, one or more communication devices (e.g., wireless network, wired network, etc.), and the like.

[0139] In some examples, one or more of the cores 1002(A)-(N) have multi-threading capabilities. The system agent unit circuit 1010 includes those components that coordinate and operate the cores 1002(A)-(N). The system agent unit circuit 1010 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be (or may include) logic and components required to adjust the power state of the cores 1002(A)-(N) and / or the dedicated logic 1008 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0140] The cores 1002(A)-(N) may be homogeneous with respect to instruction set architecture (ISA). Alternatively, the cores 1002(A)-(N) may be heterogeneous with respect to ISA; that is, a subset of the cores 1002(A)-(N) may be capable of executing one ISA, while other cores may be capable of executing only a subset of the ISA or may be capable of executing another ISA.

[0141] Example core architectures—in-order and out-of-order core block diagrams.

[0142] Figure 11(A) is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to some examples. Figure 11(B) is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example. Figure 11(A)-11(B) The solid line boxes in illustrate the in-order pipeline and in-order core, while the optionally added dashed line boxes illustrate the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0143] In FIG. 11(A), a processor pipeline 1100 includes a fetch stage 1102, an optional length decoding stage 1104, a decode stage 1106, an optional allocation (Alloc) stage 1108, an optional rename stage 1110, a dispatch (also called dispatch or issue) stage 1112, an optional register read / memory read stage 1114, an execute stage 1116, a write back / memory write stage 1118, an optional exception handling stage 1122, and an optional commit stage 1124. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 1102, one or more instructions are fetched from an instruction memory, and during the decode stage 1106, the fetched one or more instructions may be decoded, an address using a forwarding register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In one example, the decode stage 1106 and the register read / memory read stage 1114 can be combined into one pipeline stage. In one example, during the execute stage 1116, decoded instructions can be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface can be performed, multiplication and addition operations can be performed, arithmetic operations with branch results can be performed, and the like.

[0144] As an example, the example register renaming, out-of-order issue / execution architecture core of FIG. 11(B) may implement pipeline 1100 by: 1) instruction fetch circuit 1138 performs fetch and length decoding stages 1102 and 1104; 2) decoding circuit 1140 performs decoding stage 1106; 3) renaming / allocator unit circuit 1152 performs allocation stage 1108 and renaming stage 1110; 4) (one or more) scheduler circuit 1156 performs scheduling stage 1112; 5) (one or more) physical registers 1110 and 1111 are implemented as follows: The register file circuit 1158 and the memory unit circuit 1170 perform the register read / memory read phase 1114; (one or more) execution clusters 1160 perform the execute phase 1116; 6) the memory unit circuit 1170 and (one or more) physical register file circuits 1158 perform the write back / memory write phase 1118; 7) various circuits may be involved in the exception handling phase 1122; and 8) the retirement unit circuit 1154 and (one or more) physical register file circuits 1158 perform the commit phase 1124.

[0145] 11(B) shows that the processor core 1190 includes a front end unit circuit 1130 coupled to an execution engine unit circuit 1150, and both are coupled to a memory unit circuit 1170. The core 1190 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 1190 can be a special-purpose core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0146] The front end unit circuit 1130 may include a branch prediction circuit 1132 coupled to an instruction cache circuit 1134 coupled to an instruction translation lookaside buffer (TLB) 1136 coupled to an instruction fetch circuit 1138 coupled to a decode circuit 1140. In one example, the instruction cache circuit 1134 is included in the memory unit circuit 1170 instead of the front end circuit 1130. The decode circuit 1140 (or decoder) may decode the instruction and generate one or more micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals as outputs, which are decoded from the original instruction, or otherwise reflect the original instruction, or are derived from the original instruction. The decode circuit 1140 may also include an address generation unit (AGU, not shown) circuit. In one example, the AGU uses the forwarded register port to generate the LSU address and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuit 1140 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read only memory (ROM), and the like. In one example, the core 1190 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in the decode circuit 1140 or otherwise within the front end circuit 1130). In one example, the decode circuit 1140 includes a micro-op or operation cache (not shown) to save / cache decoded operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 1100. The decode circuit 1140 may be coupled to the rename / allocator unit circuit 1152 in the execution engine circuit 1150.

[0147] The execution engine circuit 1150 includes a rename / allocator unit circuit 1152 coupled to a retirement unit circuit 1154 and a set of one or more scheduler circuits 1156. The scheduler circuits 1156 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. In some examples, the scheduler circuit(s) 1156 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an address generation unit (AGU) scheduler / scheduling circuit, an AGU queue, and the like. The scheduler circuit(s) 1156 are coupled to physical register file(s) circuit(s) 1158. Each of the physical register file(s) circuit(s) 1158 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., instruction pointers, i.e., the address of the next instruction to be executed), and the like. In one example, the physical register file(s) circuit 1158 includes a vector register unit circuit, a write mask register unit circuit, and a scalar register unit circuit. These register units may provide architectural vector registers, vector mask registers, general purpose registers, and the like. The physical register file(s) circuit 1158 is coupled to a retirement unit circuit 1154 (also referred to as a retirement queue) to demonstrate various ways in which register renaming and out-of-order execution may be implemented (e.g., utilizing a reorder buffer(s) (ROB) and a retirement register file(s); utilizing a future stack(s), a history buffer(s), and a retirement register file(s); utilizing a register map and a pool of registers; and the like). The retirement unit circuit 1154 and the physical register file(s) circuit 1158 are coupled to an execution cluster(s) 1160. The execution cluster(s) 1160 includes a set of one or more execution unit circuits 1162 and a set of one or more memory access circuits 1164. The execution unit circuit(s) 1162 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some examples may include several execution units or execution unit circuits dedicated to a particular function or set of functions, other examples may include only one execution unit circuit or multiple execution units / execution unit circuits that all perform all functions.Scheduler circuit(s) 1156, physical register file circuit(s) 1158, and execution cluster(s) 1160 are shown as possibly multiple because some examples create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each with its own scheduler circuit(s), physical register file circuit(s), and / or execution cluster—and in the case of a separate memory access pipeline, only the execution cluster of that pipeline has memory access unit circuit(s) 1164 in some examples of the implementation). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest are in-order.

[0148] In some examples, the execution engine unit circuit 1150 may perform load store unit (LSU) address / data pipelining to an advanced microcontroller bus (AMB) interface (not shown), as well as address stage and writeback, data stage loads, stores, and branches.

[0149] A set of memory access circuits 1164 are coupled to the memory cell circuit 1170, which includes a data TLB circuit 1172, which is coupled to a data cache circuit 1174, which is coupled to a level 2 (L2) cache circuit 1176. In one example, the memory access circuit 1164 may include a load unit circuit, a storage address unit circuit, and a storage data unit circuit, each of which is coupled to the data TLB circuit 1172 in the memory cell circuit 1170. The instruction cache circuit 1134 is further coupled to the level 2 (L2) cache circuit 1176 in the memory cell circuit 1170. In one example, the instruction cache 1134 and the data cache 1174 are combined into a single instruction and data cache in the L2 cache circuit 1176, a level 3 (L3) cache circuit (not shown), and / or a main memory (not shown). The L2 cache circuit 1176 is coupled to one or more other levels of cache and ultimately to the main memory.

[0150] Core 1190 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added with updated versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions, such as NEON)) that include the instruction(s) described herein. In one example, core 1190 includes logic to support packed data instruction set architecture extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using packed data.

[0151] Example execution unit circuit.

[0152] Fig.12 An example of (one or more) execution unit circuits is illustrated, such as (one or more) execution unit circuits 1162 of FIG. 11 (B). As shown, (one or more) execution unit circuits 1162 may include one or more ALU circuits 1201, optional vector / single instruction multiple data (single instruction multiple data, SIMD) circuits 1203, load / store circuits 1205, branch / jump circuits 1207, and / or floating-point unit (FPU) circuits 1209. ALU circuits 1201 perform integer arithmetic and / or Boolean operations. Vector / SIMD circuits 1203 perform vector / SIMD operations on packed data (e.g., SIMD / vector registers). Load / store circuits 1205 execute load and store instructions to load data from memory into registers, or store data from registers to memory. Load / store circuits 1205 may also generate addresses. Branch / jump circuits 1207 cause branches or jumps to a certain memory address depending on the instruction. FPU circuit 1209 performs floating point arithmetic. The width of execution unit circuit(s) 1162 varies depending on the example and may range, for example, from 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0153] Example register architecture.

[0154] Fig.131 is a block diagram of a register architecture 1300 according to some examples. As shown, the register architecture 1300 includes a vector / SIMD register 1310, whose width varies from 128 bits to 1024 bits. In some examples, the vector / SIMD register 1310 is physically 512 bits, and only some low-order bits are used depending on the mapping. For example, in some examples, the vector / SIMD register 1310 is a 512-bit ZMM register: the low-order 256 bits are used for the YMM register, and the low-order 128 bits are used for the XMM register. Therefore, there is an overlay of registers. In some examples, the vector length field selects between the maximum length and one or more other shorter lengths, wherein each such shorter length is half the length of the previous length. Scalar operations are operations performed on the lowest-order data element position in the ZMM / YMM / XMM register; higher-order data element positions are either maintained as the same as before the instruction, or are zeroed, depending on the example.

[0155] In some examples, the register architecture 1300 includes a write mask / predicate register 1315. For example, in some examples, there are 8 write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate register 1315 can allow merging (e.g., allowing any set of elements in the destination to be protected from update during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 1315 corresponds to a data element position at the destination. In other examples, the write mask / predicate register 1315 is scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0156] The register architecture 1300 includes a plurality of general purpose registers 1325. These registers may be 16 bits, 32 bits, 64 bits, etc., and may be used for scalar operations. In some examples, these registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0157] In some examples, the register architecture 1300 includes a scalar floating-point (FP) register file 1345, which is used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set architecture extension, or as an MMX register to perform operations on 64-bit packed integer data, and to store operands for some operations performed between MMX and XMM registers.

[0158] One or more flag registers 1340 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 1340 can store condition code information, such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 1340 are referred to as program status and control registers.

[0159] Segment registers 1320 contain segment points for accessing memory. In some examples, these registers are referred to by the names CS, DS, SS, ES, FS, and GS.

[0160] Machine-specific registers (MSRs) 1335 control and report processor performance. Most MSRs 1335 handle system-related functions and are not accessible to applications. Machine check registers 1360 consist of control, status, and error reporting MSRs used to detect and report hardware errors.

[0161] One or more instruction pointer registers 1330 store instruction pointer values. Control register(s) 1355 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processor 970, 980, 938, 918, and / or 1000) and the characteristics of the currently executing task. Debug registers 1350 control and allow monitoring of debug operations of the processor or core.

[0162] Memory (mem) management registers 1365 specify the location of data structures used in protected mode memory management. These registers may include global descriptor table registers (GDTR), interrupt descriptor table registers (IDTR), task registers, and local descriptor table registers (LDTR).

[0163] Alternative examples may use wider or narrower registers. In addition, alternative examples may use more, less or different register files and registers. Register architecture 1300 may be used, for example, in register file / memory `ISAB08, or in physical register file circuit 1158.

[0164] Instruction set architecture.

[0165] An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., the number of bits, the position of the bits) to specify the operation to be performed (e.g., opcode) and the (one or more) operands and / or other (one or more) data fields (e.g., mask) on which the operation is to be performed, etc. Some instruction formats are further decomposed by the definition of instruction templates (or subformats). For example, an instruction template of a given instruction format may be defined as having different subsets of the fields of the instruction format (the included fields are usually in the same order, but at least some have different bit positions because there are fewer included fields) and / or defined as having a given field interpreted in a different manner. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, expressed in a given instruction template in the instruction format), and includes fields for specifying the operation and the operand. For example, the example ADD instruction has a specific opcode and instruction format, the instruction format includes an opcode field to specify the opcode, and includes an operand field to select the operand (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field that selects the specific operand. In addition, although the following description is made in the context of the x86 ISA, it is within the knowledge of those skilled in the art to apply the teachings of the present disclosure to other ISAs.

[0166] Example instruction format.

[0167] The examples of the (one or more) instructions described herein may be implemented in different formats. In addition, example systems, architectures, and pipelines are described in detail below. The examples of (one or more) instructions may be executed on these systems, architectures, and pipelines, but are not limited to those described in detail.

[0168] Fig.14An example of an instruction format is illustrated. As shown, an instruction may include multiple components, including, but not limited to, one or more fields for: one or more prefixes 1401, an opcode 1403, addressing information 1405 (e.g., a register identifier, memory addressing information, etc.), a displacement value 1407, and / or an immediate value 1409. Note that some instructions utilize some or all of the fields of the format, while other instructions may only use the opcode 1403 field. In some examples, the illustrated order is the order in which the fields are to be encoded, however, it should be understood that in other examples, the fields may be encoded in another order, combined, etc.

[0169] (One or more) prefix fields 1401 modify the instruction when used. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), provide section override (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), perform bus lock operations, and / or change operation objects (e.g., 0x66) and address sizes (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered as "traditional" prefixes. Other prefixes (one or more examples of which are described in detail herein) indicate and / or provide further capabilities, such as specifying specific registers, etc. These other prefixes are usually followed by the "traditional" prefix.

[0170] The opcode field 1403 is used to at least partially define the operation to be performed when the instruction is decoded. In some examples, the length of the primary opcode encoded in the opcode field 1403 is one, two, or three bytes. In other examples, the primary opcode can be other lengths. The additional 3-bit opcode field is sometimes encoded in another field.

[0171] The addressing information field 1405 is used to address one or more operands of the instruction, such as a location in memory or one or more registers. Fig.15An example of an addressing information field 1405 is illustrated. In this illustration, an optional MOD R / M byte 1502 and an optional Scale, Index, Base (SIB) byte 1504 are shown. The MOD R / M byte 1502 and SIB byte 1504 are used to encode up to two operands of the instruction, each operand being a direct register or an effective memory address. Note that both of these fields are optional, i.e., not all instructions include one or more of these fields. The MOD R / M byte 1502 includes a MOD field 1542, a register (reg) field 1544, and an R / M field 1546.

[0172] The content of MOD field 1542 distinguishes between memory access and non-memory access modes. In some examples, when MOD field 1542 has a binary value of 11 (11b), register direct addressing mode is utilized, otherwise register indirect addressing mode is used.

[0173] Register field 1544 may encode a destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The contents of register field 1544 specify the location (in a register or in memory) of the source or destination operand directly or through address generation. In some examples, register field 1544 is supplemented with additional bits from a prefix (e.g., prefix 1401) to allow for greater addressing.

[0174] R / M field 1546 may be used to encode an instruction operand that references a memory address, or may be used to encode a destination register operand or a source register operand. Note that in some examples, R / M field 1546 may be combined with MOD field 1542 to specify an addressing mode.

[0175] SIB byte 1504 includes a scale field 1552, an index field 1554, and a base address field 1556 for address generation. Scaling field 1552 indicates a scaling factor. Index field 1554 specifies the index register to be used. In some examples, index field 1554 is complemented with additional bits from a prefix (e.g., prefix 1401) to allow for larger addressing. Base address field 1556 specifies the base address register to be used. In some examples, base address field 1556 is complemented with additional bits from a prefix (e.g., prefix 1401) to allow for larger addressing. In practice, the contents of scale field 1552 allow the contents of index field 1554 to be scaled for memory address generation (e.g., for memory addresses using 2 缩放 * address generation of index + base address).

[0176] Some addressing forms use displacement values ​​to generate memory addresses. For example, 缩放 1405. The memory address may be generated by using a byte*index+base+displacement, index*scale+displacement, r / m+displacement, instruction pointer (RIP / EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some examples, the displacement field 1407 provides this value. Additionally, in some examples, the use of a displacement factor is encoded in the MOD field of the addressing information field 1405, which indicates a compressed displacement scheme for which the displacement value is calculated and stored in the displacement field 1407.

[0177] In some examples, the immediate value field 1409 specifies an immediate value for the instruction. The immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, and so on.

[0178] Fig.16 An example of a first prefix 1401(A) is illustrated. In some examples, the first prefix 1401(A) is an example of a REX prefix. Instructions using this prefix can specify general registers, 64-bit packed data registers (e.g., single instruction multiple data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0179] Instructions using the first prefix 1401(A) can specify up to three registers using a 3-bit field, depending on the format: 1) using the reg field 1544 and the R / M field 1546 of the MOD R / M byte 1502; 2) using the MOD R / M byte 1502 with the SIB byte 1504, including using the reg field 1544 as well as the base field 1556 and the index field 1554; or 3) using the register field of the opcode.

[0180] In the first prefix 1401 (A), bit positions 7:4 are set to 0100. Bit position 3 (W) can be used to determine the operand size, but cannot determine the operand width alone. Therefore, when W=0, the operand size is determined by the code segment descriptor (CS.D), and when W=1, the operand size is 64 bits.

[0181] Note that adding another bit allows for 16 (2 4 ) registers, while the separate MOD R / M reg field 1544 and the R / M field 1546 of MOD R / M can only address 8 registers each.

[0182] In the first prefix 1401(A), bit position 2 (R) may be an extension of the MOD R / M reg field 1544 and may be used to modify the MOD R / M reg field 1544 when the field encodes a general register, a 64-bit packed data register (e.g., an SSE register), or a control or debug register. When the MOD R / M byte 1502 specifies another register or defines an extended opcode, R is ignored.

[0183] Bit position 1 (X) may modify the SIB byte index field 1554 .

[0184] Bit position 0 (B) may modify the base address in the R / M field 1546 or SIB byte base address field 1556 of MOD R / M; or it may modify the opcode register field used to access a general register (eg, general register 1325).

[0185] Figure 17(A)-17(D) An example of how the R, X, and B fields of the first prefix 1401 (A) are used is illustrated. FIG. 17 (A) illustrates that when the SIB byte 1504 is not used for memory addressing, the R and B from the first prefix 1401 (A) are used to extend the reg field 1544 and the R / M field 1546 of the MOD R / M byte 1502. FIG. 17 (B) illustrates that when the SIB byte 1504 is not used, the R and B from the first prefix 1401 (A) are used to extend the reg field 1544 and the R / M field 1546 of the MOD R / M byte 1502 (register-register addressing). FIG. 17 (C) illustrates that when the SIB byte 1504 is used for memory addressing, the R, X, and B from the first prefix 1401 (A) are used to extend the reg field 1544 and the index field 1554 and the base address field 1556 of the MOD R / M byte 1502. 17(D) illustrates that when a register is encoded in the opcode 1403, the B from the first prefix 1401(A) is used to extend the reg field 1544 of the MOD R / M byte 1502.

[0186] Figure 18(A)-18(B)An example of a second prefix 1401(B) is illustrated. In some examples, the second prefix 1401(B) is an example of a VEX prefix. The second prefix 1401(B) encoding allows instructions to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD registers 1310) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 1401(B) provides a syntax for three operands (or more). For example, a previous two-operand instruction performs an operation such as A=A+B, which overwrites the source operand. The use of the second prefix 1401(B) enables the operands to perform non-destructive operations, such as A=B+C.

[0187] In some examples, the second prefix 1401(B) has two forms: a two-byte form and a three-byte form. The two-byte second prefix 1401(B) is mainly used for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 1401(B) provides a compact replacement for 3-byte opcode instructions and the first prefix 1401(A).

[0188] Figure 18 (A) illustrates an example of a two-byte form of the second prefix 1401 (B). In one example, the format field 1801 (byte 0 1803) contains the value C5H. In one example, byte 1 1805 includes an "R" value in bit [7]. This value is the complement of the "R" value of the first prefix 1401 (A). Bit [2] is used to specify the length (L) of the vector (wherein the value of 0 is a scalar or 128-bit vector, and the value of 1 is a 256-bit vector). Bit [1:0] provides an operation code extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form and is valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0189] Instructions using this prefix may use the R / M field 1546 of MOD R / M to encode an instruction operand that references a memory address, or to encode a destination register operand or a source register operand.

[0190] Instructions using this prefix may use the reg field 1544 of MOD R / M to encode a destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand.

[0191] For instruction syntax supporting four operands, vvvv, the R / M field 1546 of MOD R / M, and the reg field 1544 of MOD R / M encode three of the four operands. Bits [7:4] of the immediate value field 1409 are then used to encode the third source register operand.

[0192] Figure 18 (B) illustrates an example of a three-byte form of the second prefix 1401 (B). In one example, the format field 1811 (byte 0 1813) contains the value C4H. Byte 1 1815 includes "R", "X" and "B" in bits [7:5], which are the complements of these values ​​of the first prefix 1401 (A). Bits [4:0] (shown as mmmm) of byte 1 1815 include content that encodes one or more implicit leading opcode bytes as needed. For example, 00001 means 0FH leading opcode, 00010 means 0F38H leading opcode, 00011 means 0F3AH leading opcode, and so on.

[0193] The use of bit [7] of byte 2 1817 is similar to W of the first prefix 1401 (A), including helping to determine the size of the operand that can be promoted. Bit [2] is used to specify the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector, and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode the first source register operand, which is specified in inverted (inverse) form, valid for instructions with 2 or more source operands; 2) encode the destination register operand, which is specified in inverse form for certain vector shifts; or 3) do not encode any operand, this field is reserved and should contain a value, such as 1111b.

[0194] Instructions using this prefix may use the R / M field 1546 of MOD R / M to encode an instruction operand that references a memory address, or to encode a destination register operand or a source register operand.

[0195] Instructions using this prefix may use the reg field 1544 of MOD R / M to encode a destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand.

[0196] For instruction syntax supporting four operands, vvvv, the R / M field 1546 of MOD R / M, and the reg field 1544 of MOD R / M encode three of the four operands. Bits [7:4] of the immediate value field 1409 are then used to encode the third source register operand.

[0197] Fig.19 An example of a third prefix 1401(C) is illustrated. In some examples, the third prefix 1401(C) is an example of an EVEX prefix. The third prefix 1401(C) is a four-byte prefix.

[0198] The third prefix 1401 (C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, write masks / operation masks are used (see the discussion of registers in previous figures, e.g. Fig.13 ) or predicate instructions utilize this prefix. The operation mask register allows conditional processing or selection control. Operation mask instructions whose source / destination operands are operation mask registers and treat the contents of the operation mask register as a single value are encoded using the second prefix 1401 (B).

[0199] The third prefix 1401(C) may encode functionality specific to the instruction class (e.g., a packed instruction with “load+operation” semantics may support an embedded broadcast functionality, a floating-point instruction with rounding semantics may support a static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics may support a “suppress all exceptions” functionality, etc.).

[0200] The first byte of the third prefix 1401 (C) is the format field 1911, which in one example has a value of 62 H. The subsequent bytes are called payload bytes 1915-1919, and together form a 24-bit value of P[23:0], providing specific capabilities in the form of one or more fields (described in detail herein).

[0201] In some examples, P[1:0] of payload byte 1919 is the same as the two mm bits in the lower order. In some examples, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register sets when combined with P[7] and the reg field 1544 of MOD R / M. When SIB type addressing is not required, P[6] can also provide access to the upper 16 vector registers. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general registers, and memory addressing, and when combined with the MOD R / M register field 1544 and the R / M field 1546 of MOD R / M, access to the next set of 8 registers beyond the lower 8 registers is allowed. P[9:8] provides opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P

[10] is a fixed value of 1 in some examples. P[14:11], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form, valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form, used for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0202] P

[15] is similar to W of the first prefix 1401 (A) and the second prefix 1411 (B), and can be used as an opcode extension bit or an operand size increase.

[0203] P[18:16] specifies the index of a register in the operation mask (write mask) register (e.g., write mask / predicate register 1315). In one example, the particular value aaa=000 has special behavior, implying that no operation mask is used for this particular instruction (this can be implemented in a variety of ways, including using an operation mask hardwired to all ones or hardware that bypasses the masking hardware). When merging, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic operation and the enhanced operation); in another example, the old value of each element of the destination is retained (if the corresponding mask bit has a value of 0). In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the basic operation and the enhanced operation); in one example, the elements of the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span of elements modified, from first to last); however, the elements modified do not have to be consecutive. Thus, the operation mask field enables a subset of vector operations, including loads, stores, arithmetic, logical, etc. Although in the described examples, the contents of the operation mask field select which of several operation mask registers contains the operation mask to be used (so that the contents of the operation mask field indirectly identify the masking to be performed), alternative examples alternatively or additionally allow the contents of the mask write field to directly specify the masking to be performed.

[0204] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that can utilize P

[19] to access the upper 16 vector registers. P

[20] encodes various features that vary in different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0205] The following table details illustrative examples of encoding of registers in instructions using the third prefix 1401 (C). Table 1: 32-register support in 64-bit mode Table 2: Encoding register specifiers in 32-bit mode Table 3: Operation Mask Register Specifier Encoding

[0206] Program code can be applied to input information to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the present application, the processing system includes any system having a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

[0207] Program code can be implemented in a process-oriented or object-oriented high-level programming language to communicate with the processing system. If desired, program code can also be implemented in assembly or machine language. In fact, the mechanism described herein is not limited to any specific programming language in scope. In any case, the language can be a compiled language or an interpreted language.

[0208] Examples of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of these implementation approaches. Examples can be implemented as computer programs or program codes, executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0209] One or more aspects of at least one example can be implemented by representative instructions stored on a machine-readable medium, which represent various logics within a processor, and when these instructions are read by a machine, the machine makes logic for performing the technology described herein. These representations are called "intellectual property (IP) cores" and can be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into a manufacturing machine that makes the logic or processor.

[0210] These machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of items manufactured or formed by a machine or device, including storage media such as: hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic cards or optical cards, or any other type of medium suitable for storing electronic instructions.

[0211] Therefore, examples also include non-transitory tangible machine-readable media containing instructions or design data, such as hardware description languages ​​(HDL), that define the structures, circuits, devices, processors and / or system features described herein. Such examples may also be referred to as program products.

[0212] Emulation (including binary translation, code deformation, etc.).

[0213] In some cases, the instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, simulate or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented with software, hardware, firmware or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0214] Fig. 20The block diagram of illustrates the use of a software instruction converter according to an example, which is used to convert binary instructions in a source ISA into binary instructions in a target ISA. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Fig. 20 It is shown that a program in a high-level language 2002 can be compiled using a first ISA compiler 2004 to generate first ISA binary code 2006 that can be natively executed by a processor having at least one first ISA core 2016. The processor having at least one first ISA core 2016 represents any processor that is capable of natively executing or otherwise processing (1) a substantial portion of the first ISA or (2) a program that is natively executed by a processor having at least one first ISA core. The first ISA compiler 2004 represents a compiler operable to generate first ISA binary code 2006 (e.g., object code) that can be executed on a processor 2016 having at least one first ISA core with or without additional linking processing. Similarly, Fig. 20 It is shown that the program of high-level language 2002 can be compiled by alternative ISA compiler 2008 to generate alternative ISA binary code 2010, which can be executed by processor 2014 without first ISA core. Instruction converter 2012 is used to convert first ISA binary code 2006 into code that can be executed by processor 2014 without first ISA core. This converted code will not necessarily be the same as alternative ISA binary code 2010; however, the converted code will implement the total operation and be composed of instructions from the alternative ISA. Thus, instruction converter 2012 represents software, firmware, hardware or a combination thereof, which allows a processor or other electronic device without a first ISA processor or core to execute first ISA binary code 2006 through simulation, emulation or any other process.

[0215] Optionally, you can also Figure 2-Figure 4 The components, features and details described in any one of the Figure 1 , Figure 6 and Figure 7Any of. The components, features, and details described for any of the processors disclosed herein (e.g., 100, 200, 300, 400, 500) may optionally be applied to any of the methods disclosed herein (e.g., 625, 732) that may optionally be performed by and / or using such processors in an embodiment. In an embodiment, any of the processors described herein (e.g., 100, 200, 300, 400, 500) may optionally be included in any of the systems disclosed herein (e.g., Figure 9-10 In addition, in some embodiments, any of the instructions disclosed herein may optionally have the instruction format shown herein (for example, for Figure 14-Figure 19 any features or details of the format described).

[0216] References to "one example," "example," etc. indicate that the example being described may include a particular feature, structure, or characteristic, but not every example may necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. In addition, when a particular feature, structure, or characteristic is described in conjunction with an example, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other examples, whether or not explicitly described.

[0217] Processor components disclosed herein may be said and / or claimed to be operative for, operable for, capable of, able to be used for, configured for, adapted for, or otherwise used to perform operations. For example, a decoder may be said and / or claimed to be used to decode instructions, an execution unit may be said and / or claimed to be used to store results, and so on. As used herein, these expressions refer to the characteristics, properties, or attributes of a component when it is in a powered-off state, and do not imply that the components or the equipment or devices in which the components are included are currently powered on or operating. For clarity, it should be understood that the processors and devices claimed herein are not required to be powered on or running.

[0218] In the specification and claims, the terms "coupled" and / or "connected" and their derivatives may be used. These terms are not intended to be synonymous with each other. On the contrary, in many embodiments, "connected" may be used to indicate that two or more elements are in direct physical and / or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical and / or electrical contact with each other. However, "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate with each other or act on each other. For example, an execution unit may be coupled to a register and / or a decoding unit through one or more intermediate components. In the accompanying drawings, arrows are used to illustrate connections and couplings.

[0219] Some embodiments include an article (e.g., a computer program product) that includes a machine-readable medium. The medium may include a mechanism for providing (e.g., storing) information in a machine-readable form. The machine-readable medium may provide or have stored thereon instructions or sequences of instructions that, if and / or when executed by a machine, are operable to cause the machine to perform and / or cause the machine to perform one or more operations, methods, or techniques disclosed herein.

[0220] In some embodiments, the machine-readable medium may include a tangible and / or non-transitory machine-readable storage medium. For example, a non-transitory machine-readable storage medium may include a floppy disk, an optical storage medium, an optical disc, an optical data storage device, a CD-ROM, a magnetic disk, a magneto-optical disc, a read-only memory (ROM), a programmable ROM (PROM), an erasable-and-programmable ROM (EPROM), an electrically erasable-and-programmable ROM (EEPROM), a random access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a flash memory, a phase change memory, a phase change data storage material, a non-volatile memory, a non-volatile data storage device, a non-transitory memory, or a non-transitory data storage device, and the like. A non-transitory machine-readable storage medium is not composed of a transient propagation signal. In some embodiments, the storage medium may include a tangible medium, which includes a solid substance or material such as, for example, a semiconductor material, a phase change material, a magnetic solid material, a solid data storage material, and the like. Alternatively, a non-tangible transitory computer readable transmission medium may optionally be used, such as, for example, electrical, optical, acoustical, or other form of propagated signals, such as carrier waves, infrared signals, and digital signals.

[0221] Examples of suitable machines include, but are not limited to, general-purpose processors, special-purpose processors, digital logic circuits, integrated circuits, etc. Other examples of suitable machines include computer systems or other electronic devices that include processors, digital logic circuits, or integrated circuits. Examples of such computer systems or electronic devices include, but are not limited to, desktop computers, laptop computers, notebook computers, tablet computers, netbooks, smart phones, cellular phones, servers, network devices (e.g., routers and switches), mobile Internet devices (MIDs), media players, smart TVs, nettops, set-top boxes, and video game controllers.

[0222] Furthermore, in the examples described above, unless specifically noted otherwise, separating language such as phrases "at least one of A, B, or C" or "A, B and / or C" are intended to be understood to mean A, B, or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B and C).

[0223] In the above description, specific details have been set forth to provide a thorough understanding of the embodiments. However, other embodiments may be implemented without some of these specific details. Various modifications and changes may be made to the present disclosure without departing from the broader spirit and scope of the present disclosure as set forth in the claims. Therefore, the specification and the drawings should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is not intended to be determined by the specific examples provided above, but only by the appended claims. In other instances, well-known circuits, structures, devices, and operations have been shown in block diagram form and / or without details to avoid obscuring the understanding of the specification.

[0224] Example Embodiments

[0225] The following examples relate to further embodiments. The details in the examples may be used anywhere in one or more embodiments.

[0226] Example 1 is a processor or other device that includes a decoder circuit for decoding an instruction. The instruction indicates a first vector register, a second vector register, and a third vector register. The first vector register has a 128-bit channel for storing a first matrix, the first matrix having 2 rows by K columns of data elements, each of which has a first number of bits. K is equal to 64 bits divided by the first number of bits. The second vector register has a 128-bit channel for storing a second matrix, the second matrix having K rows by 2 columns of data elements, each of which has a first number of bits. The third vector register has a 128-bit channel for storing a third matrix, the third matrix having 2 rows by 2 columns of data elements, each of which has a second number of bits. The second number of bits is greater than the first number of bits. The device also includes an execution circuit coupled to the decoder circuit. The execution circuit is used to perform an operation corresponding to the instruction, including generating a result matrix having 2 rows by 2 columns of result data elements, each of which has a second number of bits. The result matrix represents the accumulation of the third matrix and the product matrix generated from the matrix multiplication using the first and second matrices. The execution unit is further configured to store the result matrix in a 128-bit lane of a third vector register.

[0227] Example 2 includes an apparatus as described in Example 1, wherein the execution circuit is to perform, in order to generate and store a result matrix: for each column n of the 2 columns of the second matrix, and for each row m of the 2 rows of the first matrix: converting K data elements from row m of the first matrix into K corresponding converted data elements each having more bits than a first number of bits, and converting K data elements from column n of the second matrix into K corresponding converted data elements each having more bits than the first number of bits; generating K products, including multiplying the K converted data elements corresponding to row m with the K converted data elements corresponding to column n; generating result data elements having a second number of bits, including accumulating the K products with data elements from corresponding row m of the 2 rows of a third matrix and corresponding column n of the 2 columns of the third matrix; and storing the result data elements in a 128-bit lane of a third vector register at a position corresponding to row m and column n of the third matrix.

[0228] Example 3 includes an apparatus as described in any of Examples 1 to 2, wherein the data elements of the first matrix and the data elements of the second matrix are 8-bit floating point data elements.

[0229] Example 4 includes the apparatus of Example 3, wherein the 8-bit floating point data elements each have 4 exponent bits and 3 explicit mantissa bits.

[0230] Example 5 includes the apparatus of Example 3, wherein the 8-bit floating point data elements each have 5 exponent bits and 2 explicit mantissa bits.

[0231] Example 6 includes an apparatus as described in Example 3, wherein the 8-bit floating-point data elements of one of the first matrix and the second matrix each have 4 exponent bits and 3 explicit mantissa bits, and wherein the 8-bit floating-point data elements of the other of the first matrix and the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

[0232] Example 7 includes an apparatus as described in any of Examples 1 to 2, wherein the data elements of the first matrix and the data elements of the second matrix are half-precision floating point data elements.

[0233] Example 8 includes the apparatus of any of Examples 1 to 2, wherein the data elements of one of the first matrix and the second matrix are 8-bit signed integers, and wherein the data elements of the other of the first matrix and the second matrix are 8-bit unsigned integers.

[0234] Example 9 includes the apparatus of any of Examples 1-2, wherein the data elements of the first matrix and the data elements of the second matrix each have 8 exponent bits and 10 explicit mantissa bits.

[0235] Example 10 includes the apparatus of any of Examples 1 to 9, wherein the data elements of the third matrix are single-precision floating point data elements.

[0236] Example 11 includes the apparatus of any of Examples 1 to 10, further comprising a register having one or more fields for specifying whether a denormal result of a floating-point operation is to be forced to zero, and optionally, wherein the execution circuitry, in order to perform the operation corresponding to the instruction, forces the denormal result of the floating-point operation to be zero, regardless of whether the one or more fields specify that the denormal result of the floating-point operation is to be forced to zero.

[0237] Example 12 includes an apparatus as described in any of Examples 1 to 11, further comprising a floating point control register, wherein the data elements of the first matrix are floating point data elements, and optionally, wherein the execution circuit is used to complete execution of the operation corresponding to the instruction without accessing the floating point control register.

[0238] Example 13 includes an apparatus as described in any of Examples 1 to 12, wherein the first vector register has a second 128-bit channel for storing a fourth matrix having 2 rows by K columns of data elements, each of which has a first number of bits; the second vector register has a second 128-bit channel for storing a fifth matrix having K rows by 2 columns of data elements, each of which has a first number of bits; and the third vector register has a second 128-bit channel for storing a sixth matrix having 2 rows by 2 columns of data elements, each of which has a second number of bits.

[0239] Example 14 includes an apparatus as described in Example 13, wherein the execution circuit is to further perform, in order to perform the operation corresponding to the instruction: generate a second result matrix having 2 rows by 2 columns of result data elements, each of which has a second number of bits. The second result matrix represents the accumulation of the sixth matrix and the product matrix generated from the matrix multiplication using the fourth and fifth matrices. The execution circuit is also used to store the second result matrix in a second 128-bit lane of the third vector register.

[0240] Example 15 is a processor or other device that includes a decoder circuit for decoding an instruction. The instruction indicates a first vector register having a 128-bit lane for storing a first matrix having 2 rows by 8 columns of 8-bit floating-point data elements; indicates a storage location having 128 bits for storing a second matrix having 8 rows by 2 columns of 8-bit floating-point data elements; and indicates a second vector register having a 128-bit lane for storing a third matrix having 2 rows by 2 columns of 32-bit single-precision floating-point data elements. The device also includes an execution circuit coupled to the decoder circuit. The execution circuit is used to perform an operation corresponding to the instruction, including generating a result matrix having 2 rows by 2 columns of 32-bit single-precision floating-point result data elements. The result matrix represents the accumulation of the third matrix and the product matrix generated from the matrix multiplication using the first and second matrices. The execution circuit is also used to store the result matrix in the 128-bit lane of the second vector register.

[0241] Example 16 includes an apparatus as described in Example 15, wherein the execution circuit is to generate and store a result matrix by: for each column n of the 2 columns of the second matrix, and for each row m of the 2 rows of the first matrix: converting 8 data elements from row m of the first matrix into 8 corresponding converted data elements each having more than 8 bits, and converting 8 data elements from column n of the second matrix into 8 corresponding converted data elements each having more than 8 bits; generating 8 products, including multiplying the 8 converted data elements corresponding to row m with the 8 converted data elements corresponding to column n; generating 32-bit single-precision floating-point result data elements, including accumulating the 8 products with data elements from corresponding row m of the 2 rows of the third matrix and corresponding column n of the 2 columns of the third matrix; and storing the 32-bit single-precision floating-point result data elements in the 128-bit lane of the second vector register at a position corresponding to row m and column n of the third matrix.

[0242] Example 17 includes the apparatus of Example 15, wherein the 8-bit floating point data elements of the first matrix and the 8-bit floating point data elements of the second matrix each have 4 exponent bits and 3 explicit mantissa bits.

[0243] Example 18 includes the apparatus of Example 15, wherein the 8-bit floating point data elements of the first matrix and the 8-bit floating point data elements of the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

[0244] Example 19 includes an apparatus as described in any of Examples 15 to 16, wherein the 8-bit floating-point data elements of the first matrix each have 4 exponent bits and 3 explicit mantissa bits, and optionally, wherein the 8-bit floating-point data elements of the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

[0245] Example 20 includes an apparatus as described in any of Examples 15 to 16, wherein the 8-bit floating-point data elements of the first matrix each have 5 exponent bits and 2 explicit mantissa bits, and optionally, wherein the 8-bit floating-point data elements of the second matrix each have 4 exponent bits and 3 explicit mantissa bits.

[0246] Example 21 includes an apparatus as described in any of Examples 15 to 20, further comprising a floating point control register having one or more fields for specifying a floating point rounding mode to be used for floating point operations, and optionally, wherein the execution circuitry, to generate a result matrix, is to: perform floating point rounding according to a round-to-even (RNE) rounding mode, regardless of whether the one or more fields specify that the floating point rounding mode is the RNE rounding mode.

[0247] Example 22 includes an apparatus as described in any of Examples 15 to 21, further comprising a floating point control register having one or more fields for specifying whether an input denormal value is to be treated as zero, and optionally, wherein the execution circuitry, in order to perform an operation corresponding to the instruction, is to: not treat the input denormal value as zero, regardless of whether the one or more fields specify that the input denormal value is to be treated as zero.

[0248] Example 23 includes an apparatus as described in any of Examples 15 to 22, further comprising a floating point control register having one or more fields for specifying whether a denormal result is to be set to zero, and wherein the execution circuitry, in order to perform the operation corresponding to the instruction, is to: set the denormal result to zero, regardless of whether the one or more fields specify that the denormal result is to be set to zero.

[0249] Example 24 includes an apparatus as described in any of Examples 15 to 23, further comprising a floating point control register having one or more fields for specifying whether a floating point exception is to be reported, and optionally, wherein the execution circuitry, in order to perform an operation corresponding to the instruction, is to: not report the floating point exception, regardless of whether the one or more fields specify that the floating point exception is to be reported.

[0250] Example 25 includes an apparatus as described in any of Examples 15 to 24, further comprising a floating point control register, and optionally, wherein the execution circuit is used to complete the execution of the operation corresponding to the instruction without accessing the floating point control register.

[0251] Example 26 includes an apparatus as described in any of Examples 15 to 25, wherein the execution circuit is to generate a result matrix by: generating all products of the matrix multiplication using the first matrix and the second matrix before accumulating any of the products with a third matrix.

[0252] Example 27 includes an apparatus as described in any of Examples 15 to 26, wherein the instruction allows the storage location to be a third vector register, but optionally does not allow the storage location to be in memory.

[0253] Example 28 includes an apparatus as described in any of Examples 15 to 27, wherein the first vector register has a second 128-bit lane for storing a fourth matrix having 2 rows by 8 columns of 8-bit floating-point data elements, the storage location has a second 128-bit lane for storing a fifth matrix having 8 rows by 2 columns of 8-bit floating-point data elements, and the second vector register has a second 128-bit lane for storing a sixth matrix having 2 rows by 2 columns of 32-bit single-precision floating-point data elements, and optionally, wherein the execution circuitry is to further perform, in order to perform the operation corresponding to the instruction: generate a second result matrix having 2 rows by 2 columns of 32-bit single-precision floating-point result data elements. The second result matrix represents the accumulation of the sixth matrix and a product matrix generated from matrix multiplication using the fourth and fifth matrices. The execution circuitry is also optionally used to store the second result matrix in the second 128-bit lane of the second vector register.

[0254] Example 29 is a method performed by a processor or other device, the method comprising decoding an instruction indicating a first vector register having a 128-bit lane for storing a first matrix having 2 rows by 8 columns of 8-bit floating-point data elements; indicating a storage location having 128 bits for storing a second matrix having 8 rows by 2 columns of 8-bit floating-point data elements; and indicating a second vector register having a 128-bit lane for storing a third matrix having 2 rows by 2 columns of 32-bit single-precision floating-point data elements. The method also includes performing an operation corresponding to the instruction, including generating a result matrix having 2 rows by 2 columns of 32-bit single-precision floating-point result data elements. The result matrix represents the accumulation of the third matrix and a product matrix generated from matrix multiplication using the first and second matrices. The operation also includes storing the result matrix in the 128-bit lane of the second vector register.

[0255] Example 30 includes a method as described in Example 29, wherein the 8-bit floating-point data elements of one of the first matrix and the second matrix each have 4 exponent bits and 3 explicit mantissa bits, and optionally wherein the 8-bit floating-point data elements of the other of the first matrix and the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

[0256] Example 31 includes a method as described in any of Examples 29 to 30, wherein generating a result matrix includes generating all products of the matrix multiplication using the first matrix and the second matrix before accumulating any of the products with a third matrix.

[0257] Example 32 is a computer system or other system that includes a decoder circuit for decoding an instruction. The instruction indicates: a first vector register having a 128-bit channel for storing a first matrix, the first matrix having 2 rows by 8 columns of 8-bit floating-point data elements; a storage location having 128 bits for storing a second matrix, the second matrix having 8 rows by 2 columns of 8-bit floating-point data elements; and a second vector register having a 128-bit channel for storing a third matrix, the third matrix having 2 rows by 2 columns of 32-bit single-precision floating-point data elements. The processor also includes an execution circuit coupled to the decoder circuit. The execution circuit is used to perform operations corresponding to the instruction, including generating a result matrix having 2 rows by 2 columns of 32-bit single-precision floating-point result data elements. The result matrix represents the accumulation of the third matrix and the product matrix generated from the matrix multiplication using the first and second matrices. The operation also includes storing the result matrix in the 128-bit channel of the second vector register. The system also includes a dynamic random access memory (DRAM) coupled to the processor.

[0258] Example 33 includes a system as described in Example 32, wherein the 8-bit floating-point data elements of one of the first matrix and the second matrix each have 4 exponent bits and 3 explicit mantissa bits, and optionally wherein the 8-bit floating-point data elements of the other of the first matrix and the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

[0259] Example 34 includes a system as described in any of Examples 32 to 33, further comprising a floating point control register having one or more fields for specifying whether denormal values ​​in the input to the floating point operation are to be treated as zero, and optionally, wherein the execution circuitry, in order to perform the operation corresponding to the instruction, is to: not treat denormal values ​​in the input to the floating point operation as zero, regardless of whether the one or more fields specify that denormal values ​​in the input to the floating point operation are to be treated as zero.

[0260] Example 35 is a processor or other device that operates to perform a method as described in any of Examples 29 to 31.

[0261] Example 36 is a processor or other device comprising one or more devices for performing a method as described in any of Examples 29 to 31.

[0262] Example 37 is a processor or other device comprising any combination of modules and / or units and / or logic and / or circuits and / or devices that operate to perform a method as described in any of Examples 29 to 31.

[0263] Example 38 is an optionally non-transitory and / or tangible machine-readable medium that optionally stores or otherwise provides instructions including a first instruction that, when executed by and / or when executed by a processor, a computer system, an electronic device, or other machine, operates to cause the machine to perform a method as described in any one of Examples 29 to 31.

Claims

1. A processor, comprising: a decoder circuit for decoding an instruction indicating a first vector register having 128-bit lanes for storing a first matrix having 2 rows by 8 columns of 8-bit floating point data elements; indicating a storage location having 128 bits for storing a second matrix having 8 rows by 2 columns of 8-bit floating point data elements; and indicating a second vector register having 128-bit lanes for storing a third matrix having 2 rows by 2 columns of 32-bit single precision floating point data elements; as well as An execution circuit is coupled to the decoder circuit, and the execution circuit is used to execute an operation corresponding to the instruction, including: generating a result matrix having 2 rows by 2 columns of 32-bit single precision floating point result data elements, the result matrix representing an accumulation of the third matrix and a product matrix generated from a matrix multiplication using the first matrix and the second matrix; as well as The result matrix is ​​stored in a 128-bit lane of the second vector register.

2. The processor of claim 1, wherein: In order to generate and store the result matrix, the execution circuit needs to perform: For each column n of the 2 columns of the second matrix, and for each row m of the 2 rows of the first matrix: converting 8 data elements from row m of the first matrix into 8 corresponding converted data elements each having more than 8 bits, and converting 8 data elements from column n of the second matrix into 8 corresponding converted data elements each having more than 8 bits; generating 8 products comprising multiplying the 8 converted data elements corresponding to row m and the 8 converted data elements corresponding to column n; generating a 32-bit single-precision floating point result data element, comprising accumulating the eight products with data elements from corresponding rows m of the two rows of the third matrix and corresponding columns n of the two columns of the third matrix; as well as The 32-bit single-precision floating-point result data element is stored in a 128-bit lane of the second vector register at a location corresponding to row m and column n of the third matrix.

3. The processor of claim 1, wherein: The 8-bit floating point data elements of the first matrix and the 8-bit floating point data elements of the second matrix each have 4 exponent bits and 3 explicit mantissa bits.

4. The processor of claim 1, wherein: The 8-bit floating point data elements of the first matrix and the 8-bit floating point data elements of the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

5. The processor of claim 1, wherein: The 8-bit floating point data elements of the first matrix each have 4 exponent bits and 3 explicit mantissa bits, and wherein the 8-bit floating point data elements of the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

6. The processor of claim 1, wherein: The 8-bit floating point data elements of the first matrix each have 5 exponent bits and 2 explicit mantissa bits, and wherein the 8-bit floating point data elements of the second matrix each have 4 exponent bits and 3 explicit mantissa bits.

7. A processor as claimed in any one of claims 1 to 6, further comprising a floating point control register having one or more fields for specifying a floating point rounding mode to be used by floating point operations, and wherein, The execution circuit is to generate the result matrix by performing floating point rounding according to a round-to-even (RNE) rounding mode, regardless of whether the one or more fields specify that the floating point rounding mode is the RNE rounding mode.

8. A processor as claimed in any one of claims 1 to 6, further comprising a floating point control register having one or more fields for specifying whether input denormal values ​​are to be treated as zero, and wherein, The execution circuitry, in order to perform an operation corresponding to the instruction, is to: not treat the input denormal value as zero, regardless of whether the one or more fields specify that the input denormal value is to be treated as zero.

9. A processor as claimed in any one of claims 1 to 6, further comprising a floating point control register having one or more fields for specifying whether denormal results are to be zeroed, and wherein, The execution circuitry, in order to perform an operation corresponding to the instruction, is to: set the denormal result to zero, regardless of whether the one or more fields specify that the denormal result is to be set to zero.

10. A processor as claimed in any one of claims 1 to 6, further comprising a floating point control register having one or more fields for specifying whether floating point exceptions are to be reported, and wherein, The execution circuitry, to perform an operation corresponding to the instruction, is to: not report the floating point exception regardless of whether the one or more fields specify that the floating point exception is to be reported.

11. A processor as claimed in any one of claims 1 to 6, further comprising a floating point control register, and wherein, The execution circuit is used to complete the execution of the operation corresponding to the instruction without accessing the floating point control register.

12. The processor according to any one of claims 1 to 6, wherein: To generate the result matrix, the execution circuit generates all products of the matrix multiplications before accumulating any product of the matrix multiplications using the first matrix and the second matrix with the third matrix.

13. The processor according to any one of claims 1 to 6, wherein: The instruction allows the storage location to be a third vector register, but does not allow the storage location to be in memory.

14. The processor according to any one of claims 1 to 6, wherein: The first vector register has a second 128-bit lane for storing a fourth matrix having 2 rows by 8 columns of 8-bit floating point data elements, the storage location has a second 128 bits for storing a fifth matrix having 8 rows by 2 columns of 8-bit floating point data elements, and the second vector register has a second 128-bit lane for storing a sixth matrix having 2 rows by 2 columns of 32-bit single precision floating point data elements, and wherein the execution circuitry, in order to perform the operation corresponding to the instruction, is to further perform: generating a second result matrix having 2 rows by 2 columns of 32-bit single precision floating point result data elements, the second result matrix representing an accumulation of the sixth matrix and a product matrix generated from matrix multiplication using the fourth matrix and the fifth matrix; and The second result matrix is ​​stored in a second 128-bit lane of the second vector register.

15. A method executed by a processor, the method comprising: decoding an instruction indicating a first vector register having 128-bit lanes for storing a first matrix having 2 rows by 8 columns of 8-bit floating point data elements, indicating a storage location having 128 bits for storing a second matrix having 8 rows by 2 columns of 8-bit floating point data elements, and indicating a second vector register having 128-bit lanes for storing a third matrix having 2 rows by 2 columns of 32-bit single precision floating point data elements; as well as Execute operations corresponding to the instructions, including: generating a result matrix having 2 rows by 2 columns of 32-bit single precision floating point result data elements, the result matrix representing an accumulation of the third matrix and a product matrix generated from a matrix multiplication using the first matrix and the second matrix; as well as The result matrix is ​​stored in a 128-bit lane of the second vector register.

16. The method of claim 15, wherein: The 8-bit floating point data elements of one of the first matrix and the second matrix each have 4 exponent bits and 3 explicit mantissa bits, and wherein the 8-bit floating point data elements of the other of the first matrix and the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

17. The method of claim 15, wherein: Generating the result data includes generating all products of the matrix multiplications before accumulation of any of the products of the matrix multiplications using the first matrix and the second matrix with the third matrix.

18. A computer system comprising: A processor, the processor comprising: A decoder circuit for decoding an instruction indicating: a first vector register having 128-bit lanes for storing a first matrix having 2 rows by 8 columns of 8-bit floating point data elements; a storage location having 128 bits for storing a second matrix having 8 rows by 2 columns of 8-bit floating point data elements; and a second vector register having 128-bit lanes for storing a third matrix having 2 rows by 2 columns of 32-bit single precision floating point data elements; and An execution circuit is coupled to the decoder circuit, and the execution circuit is used to execute an operation corresponding to the instruction, including: generating a result matrix having 2 rows by 2 columns of 32-bit single precision floating point result data elements, the result matrix representing an accumulation of the third matrix and a product matrix generated from a matrix multiplication using the first matrix and the second matrix; and storing the result matrix in a 128-bit lane of the second vector register; and A dynamic random access memory DRAM is coupled to the processor.

19. The computer system of claim 18, wherein: The 8-bit floating point data elements of one of the first matrix and the second matrix each have 4 exponent bits and 3 explicit mantissa bits, and wherein the 8-bit floating point data elements of the other of the first matrix and the second matrix each have 5 exponent bits and 2 explicit mantissa bits.

20. The computer system of any one of claims 18 to 19, further comprising a floating point control register having one or more fields for specifying whether denormal values ​​in inputs to floating point operations are to be treated as zero, and wherein, The execution circuitry, to perform an operation corresponding to the instruction, is to not treat denormal values ​​in an input to a floating point operation as zero, regardless of whether the one or more fields specify that denormal values ​​in an input to the floating point operation are to be treated as zero.

21. A processor, comprising: Decoding means for decoding an instruction indicating a first vector register having 128-bit lanes for storing a first matrix having 2 rows by 8 columns of 8-bit floating-point data elements, indicating a storage location having 128 bits for storing a second matrix having 8 rows by 2 columns of 8-bit floating-point data elements, and indicating a second vector register having 128-bit lanes for storing a third matrix having 2 rows by 2 columns of 32-bit single-precision floating-point data elements; as well as An execution device, coupled to the decoding device, configured to execute an operation corresponding to the instruction, including: generating a result matrix having 2 rows by 2 columns of 32-bit single precision floating point result data elements, the result matrix representing an accumulation of the third matrix and a product matrix generated from a matrix multiplication using the first matrix and the second matrix; as well as The result matrix is ​​stored in a 128-bit lane of the second vector register.

22. A processor, comprising: an instruction converter for converting a first instruction in a first instruction set into one or more instructions in a second instruction set, the first instruction indicating a first vector register having a 128-bit lane for storing a first matrix having 2 rows by 8 columns of 8-bit floating-point data elements, indicating a 128-bit storage location for storing a second matrix having 8 rows by 2 columns of 8-bit floating-point data elements, and indicating a second vector register having a 128-bit lane for storing a third matrix having 2 rows by 2 columns of 32-bit single-precision floating-point data elements; as well as A processor, coupled to the instruction converter, configured to execute the one or more instructions in the second instruction set, comprising: generating a result matrix having 2 rows by 2 columns of 32-bit single precision floating point result data elements, the result matrix representing an accumulation of the third matrix and a product matrix generated from a matrix multiplication using the first matrix and the second matrix; as well as The result matrix is ​​stored in a storage device corresponding to the 128-bit lanes of the second vector register.

23. A processor comprising means for performing the method of any one of claims 15 to 17.

24. A machine-readable medium comprising machine-readable instructions, which, when executed, cause a machine to perform the method of any one of claims 15 to 17.

25. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method of any one of claims 15 to 17.

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