Signal output system and method, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a signal output system and method, a storage medium and electronic equipment, and the system comprises a signal generation module and a signal monitoring module. The signal generation module is used for providing a first signal required by a first subsystem on the target chip, the first signal is used for providing clock supply and reset release for the first subsystem, and the first subsystem is any subsystem in at least one subsystem on the target chip; the signal monitoring module is used for monitoring the first subsystem under the condition that the signal generation module provides the first signal for the first subsystem, and outputting an access permission signal under the condition that the condition that the state of the first subsystem meets a target state is monitored, the target state comprises that the clock state of the first subsystem is stable, the first subsystem completes reset release, and the access permission signal is used for indicating that the first subsystem permits access.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of system on chip, and specifically, to a signal output system, method, storage medium, and electronic device. Background Art

[0002] With the development of technology, the integration of digital circuits is getting higher and higher, and the design is becoming more and more complex. In particular, the system-on-chip (SoC) is generally composed of multiple subsystems, each of which is composed of several or even dozens of intellectual property cores (IPs) and interconnected through the network on chip (NoC). When designing SoC, it is necessary to consider the secure access after the chip is powered on and reset, to ensure that when the central processing unit (CPU) accesses each subsystem, the clock reset inside the subsystem is ready, to prevent chip failure behaviors such as command loss due to the fact that the subsystem has not been fully synchronized.

[0003] In the related art, the problem of how to securely access the chip after the chip is released by power-on reset and a series of operations such as startup has not yet been effectively solved. Summary of the invention

[0004] The embodiments of the present application provide a signal output system, method, storage medium, and electronic device to at least solve the problem in the related art of how to securely access the chip after a series of operations such as power-on reset release and startup are performed on the chip.

[0005] According to an embodiment of the present application, a signal output system is provided, comprising: a signal generating module and a signal monitoring module; the signal generating module is used to provide a first signal required by a first subsystem on a target chip, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip; the signal monitoring module is used to monitor the first subsystem when the signal generating module provides the first signal to the first subsystem, and output an access permission signal when it is monitored that the state of the first subsystem meets a target state, wherein the target state includes: the clock state of the first subsystem is stable and the first subsystem completes reset release, wherein the access permission signal is used to indicate that the first subsystem allows access.

[0006] In an exemplary embodiment, the signal generating module includes: a clock generating module and a reset generating module; the clock generating module is used to provide a second signal required by the first subsystem, wherein the second signal is used to provide a clock supply to the first subsystem; the reset generating module is used to provide a third signal required by the first subsystem, wherein the third signal is used to provide a reset release to the first subsystem; wherein the first signal includes: the second signal and the third signal.

[0007] In an exemplary embodiment, the clock generation module includes a phase-locked loop clock module, and the phase-locked loop clock module is used to generate a fourth signal; the clock generation module is used to receive a chip reference clock of the target chip; when the phase-locked loop clock module is in a first state, the chip reference clock is used as the second signal; when the phase-locked loop clock module is in a second state, the fourth signal is used as the second signal.

[0008] In an exemplary embodiment, a clock distribution module is deployed in the local control unit of the first subsystem; the clock distribution module is used to receive the second signal sent by the clock generation module and use the second signal as the master clock of the first subsystem; wherein the clock distribution module includes: a clock register, at least two frequency dividers, and at least two gating units; one of the at least two frequency dividers is also used to receive the chip power-on reset of the target chip; the master clock is divided by the chip power-on reset to obtain the configuration clock of the local control unit; wherein one of the at least two frequency dividers and one of the at least two gating units are connected to each other; The clock register is connected to a control unit; the clock register is used to determine the IP clock configuration corresponding to each IP module in the multiple IP modules in the first subsystem through the configuration clock when the first subsystem is reset and released; wherein the clock register is connected to another frequency divider of the at least two frequency dividers, and the other frequency divider of the at least two frequency dividers is connected to another gating unit of the at least two gating units; the clock register is also used to provide an IP clock for each IP module through another frequency divider of the at least two frequency dividers and another gating unit of the at least two gating units, wherein the IP clock is determined by the IP clock configuration.

[0009] In an exemplary embodiment, the signal monitoring module includes: a clock monitoring module; the clock monitoring module is used to collect the first clock state of the master clock, the second clock state of the configuration clock, and the third clock state of the IP clock; the clock monitoring module is also used to determine that the clock state of the first subsystem is stable when the clock frequency of the master clock is determined to be stable through the first clock state, the clock frequency of the configuration clock is determined to be stable through the second clock state, and the clock frequency of the IP clock is determined to be stable through the third clock state.

[0010] In an exemplary embodiment, the reset generation module is used to generate the third signal, and the third signal is used to provide reset release to the first subsystem according to a target order corresponding to the first subsystem; wherein the target order is the order corresponding to the first subsystem in the reset release sequence pre-set for the at least one subsystem.

[0011] In an exemplary embodiment, the local control unit of the first subsystem is also deployed with a reset synchronization module, wherein the reset synchronization module includes: a reset register and a reset synchronizer; the reset register determines the IP reset configuration corresponding to each IP module in the multiple IP modules in the first subsystem through the third signal; the reset synchronizer provides a reset signal for each IP module through the IP reset configuration; the signal monitoring module also includes: a reset monitoring module, the reset monitoring module is used to monitor the reset state of each IP module when each IP module receives the reset signal; and when each IP module is in reset release, determine that the first subsystem completes reset release.

[0012] According to another embodiment of the present application, a signal output method is provided, which is applied to the signal output system described in any one of the above items, including: providing a first signal required by a first subsystem on a target chip to the first subsystem, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip; monitoring the first subsystem, and outputting an access permission signal when it is monitored that the state of the first subsystem meets the target state, wherein the target state includes: the clock state of the first subsystem is stable and the first subsystem completes reset release, wherein the access permission signal is used to indicate that the first subsystem allows access.

[0013] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0014] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0015] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0016] Through the present application, a signal output system is provided, including: a signal generating module and a signal monitoring module; the signal generating module is used to provide a first signal required by a first subsystem on a target chip, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip; the signal monitoring module is used to monitor the first subsystem when the signal generating module provides the first signal to the first subsystem, and output an access permission signal when it is monitored that the state of the first subsystem meets the target state, wherein the target state includes: the clock state of the first subsystem is stable, and the first subsystem completes the reset release, wherein the access permission signal is used to indicate that the first subsystem allows access. Therefore, the problem of how to safely access the chip after the chip is executed with power-on reset release and a series of operations are started in the related art can be solved. Thereby, the technical effect of being able to safely access the target chip is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is an architecture diagram of a signal output system according to an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of SoC chip system control of a signal output system according to an embodiment of the present application;

[0019] Figure 3 It is a hardware structure block diagram of a computer terminal of a signal output method according to an embodiment of the present application;

[0020] Figure 4 is a flow chart of a signal output method according to an embodiment of the present application;

[0021] Figure 5is another architecture diagram of a signal output system according to an embodiment of the present application;

[0022] Figure 6 1 is a circuit structure diagram (I) of a subsystem clock supply completion circuit of a signal output system according to an embodiment of the present application;

[0023] Figure 7 2 is a circuit structure diagram (II) of a subsystem clock supply completion circuit of a signal output system according to an embodiment of the present application;

[0024] Figure 8 is a schematic diagram of a SoC system under a reset request of a signal output system according to an embodiment of the present application;

[0025] Fig. 9 is a circuit structure diagram of a subsystem reset release completion circuit of a signal output system according to an embodiment of the present application;

[0026] Fig.10 is another flow chart of the signal output method according to an embodiment of the present application;. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0029] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0030] The following is an explanation of the technical terms used in the embodiments of the present application:

[0031] SoC: It is also called system-on-chip, which means that SoC is a product, an integrated circuit with a dedicated purpose, which contains all the contents of a complete system and embedded software. At the same time, SoC is a technology that is used to realize the entire process from determining the system function to the software / hardware division and completing the design.

[0032] SCU: System control unit, which is mainly responsible for the power-on timing control of the chip, monitoring of external interrupts, generation and control of clock reset signals, etc.

[0033] CPU: Central Processing Unit, is the computing and control core of a computer. The main function of the CPU is to interpret computer instructions and process data in computer software. It is responsible for reading instructions, decoding instructions and executing instructions.

[0034] NoC: Network on chip refers to the integration of a large number of computing resources on a single chip and the on-chip communication network that connects these resources.

[0035] In order to solve the above problems, the present application provides a signal output system. Figure 1 : is an architecture diagram of a signal output system according to an embodiment of the present application, the signal output system comprising:

[0036] A signal generating module 11 and a signal monitoring module 12;

[0037] The signal generating module 11 is used to provide a first signal required by a first subsystem 13 on the target chip, wherein the first signal is used to provide clock supply and reset release to the first subsystem 13, wherein the first subsystem 13 is any subsystem of at least one subsystem on the target chip;

[0038] The signal monitoring module 12 is used to monitor the first subsystem 13 when the signal generating module provides the first signal to the first subsystem 13, and output an access permission signal when it is monitored that the state of the first subsystem 13 meets the target state, wherein the target state includes: the clock state of the first subsystem 13 is stable and the first subsystem 13 completes reset release, wherein the access permission signal is used to indicate that the first subsystem 13 allows access.

[0039] Optionally, the target chip in the embodiment of the present application may be a SOC chip.

[0040] Through the present application, a signal output system is provided, including: a signal generating module and a signal monitoring module; the signal generating module is used to provide a first signal required by a first subsystem on a target chip, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip; the signal monitoring module is used to monitor the first subsystem when the signal generating module provides the first signal to the first subsystem, and output an access permission signal when it is monitored that the state of the first subsystem meets the target state, wherein the target state includes: the clock state of the first subsystem is stable, and the first subsystem completes the reset release, wherein the access permission signal is used to indicate that the first subsystem allows access. Therefore, the problem of how to safely access the chip after the chip is executed with power-on reset release and a series of operations are started in the related art can be solved. Thereby, the technical effect of being able to safely access the target chip is achieved.

[0041] In an exemplary embodiment, the signal generating module includes: a clock generating module and a reset generating module; the clock generating module is used to provide a second signal required by the first subsystem, wherein the second signal is used to provide a clock supply to the first subsystem; the reset generating module is used to provide a third signal required by the first subsystem, wherein the third signal is used to provide a reset release to the first subsystem; wherein the first signal includes: the second signal and the third signal.

[0042] It can be understood that the signal generation module includes a clock generation module and a reset generation module, which respectively provide the first subsystem with a second signal for clock supply and a third signal for reset release. Optionally, the signal generation module can be specifically deployed in the system control unit (System control unit, referred to as SCU) of the SOC chip. Specifically, the schematic diagram of the SOC chip system is as follows Figure 2 shown.

[0043] In an exemplary embodiment, the clock generation module includes a phase-locked loop clock module, and the phase-locked loop clock module is used to generate a fourth signal; the clock generation module is used to receive a chip reference clock of the target chip; when the phase-locked loop clock module is in a first state, the chip reference clock is used as the second signal; when the phase-locked loop clock module is in a second state, the fourth signal is used as the second signal.

[0044] It can be understood that the clock generation module includes a phase-locked loop (PLL) clock module. The input signal of the phase-locked loop clock module is the chip reference clock. When the target chip is powered on and reset is released (equivalent to the first state), the chip reference clock is used as the second signal; after waiting for uncore PLL lock (equivalent to the second state), the fourth signal generated by the phase-locked loop clock module is used as the second signal.

[0045] Optionally, the chip reference clock or the fourth signal needs to be processed by a frequency divider in the clock generation module to obtain the second signal.

[0046] Therefore, the embodiment of the present application can output the second signal even when the PLL clock module has not reached uncore PLL lock, thereby ensuring a stable clock supply to the first subsystem.

[0047] In an exemplary embodiment, a clock distribution module is deployed in the local control unit of the first subsystem; the clock distribution module is used to receive the second signal sent by the clock generation module and use the second signal as the master clock of the first subsystem; wherein the clock distribution module includes: a clock register, at least two frequency dividers, and at least two gating units; one of the at least two frequency dividers is also used to receive the chip power-on reset of the target chip; the master clock is divided by the chip power-on reset to obtain the configuration clock of the local control unit; wherein one of the at least two frequency dividers and one of the at least two gating units are connected to each other; The clock register is connected to a control unit; the clock register is used to determine the IP clock configuration corresponding to each IP module in the multiple IP modules in the first subsystem through the configuration clock when the first subsystem is reset and released; wherein the clock register is connected to another frequency divider of the at least two frequency dividers, and the other frequency divider of the at least two frequency dividers is connected to another gating unit of the at least two gating units; the clock register is also used to provide an IP clock for each IP module through another frequency divider of the at least two frequency dividers and another gating unit of the at least two gating units, wherein the IP clock is determined by the IP clock configuration.

[0048] Therefore, the embodiment of the present application processes the second signal through the clock distribution module, so that IP clocks can be further provided for multiple IP modules, thereby ensuring that the clock supply can be provided for the entire SOC chip.

[0049] In an exemplary embodiment, the signal monitoring module includes: a clock monitoring module; the clock monitoring module is used to collect the first clock state of the master clock, the second clock state of the configuration clock, and the third clock state of the IP clock; the clock monitoring module is also used to determine that the clock state of the first subsystem is stable when the clock frequency of the master clock is determined to be stable through the first clock state, the clock frequency of the configuration clock is determined to be stable through the second clock state, and the clock frequency of the IP clock is determined to be stable through the third clock state.

[0050] It should be noted that the clock frequency is the clock frequency. The clock frequency is stable, that is, the clock frequency remains within a fixed range. If the clock frequencies corresponding to the main clock, configuration clock, and IP clock can be monitored to be stable at the same time, the clock state of the first subsystem is stable.

[0051] Therefore, the embodiment of the present application implements monitoring of the clock state of the first subsystem through the clock monitoring module.

[0052] In an exemplary embodiment, the reset generation module is used to generate the third signal, and the third signal is used to provide reset release to the first subsystem according to a target order corresponding to the first subsystem; wherein the target order is the order corresponding to the first subsystem in the reset release sequence pre-set for the at least one subsystem.

[0053] That is, the reset generation module needs to provide the third signal to the first subsystem according to the preset reset release sequence.

[0054] In an exemplary embodiment, the local control unit of the first subsystem is also deployed with a reset synchronization module, wherein the reset synchronization module includes: a reset register and a reset synchronizer; the reset register determines the IP reset configuration corresponding to each IP module in the multiple IP modules in the first subsystem through the third signal; the reset synchronizer provides a reset signal for each IP module through the IP reset configuration; the signal monitoring module also includes: a reset monitoring module, the reset monitoring module is used to monitor the reset state of each IP module when each IP module receives the reset signal; and when each IP module is in reset release, determine that the first subsystem completes reset release.

[0055] That is to say, the local control unit of the first subsystem is also deployed with a reset synchronization module, which is used to determine the IP reset configurations corresponding to the multiple IP modules in the first subsystem according to the third signal provided by the reset generation module. The reset synchronizer is used to reset and synchronize each IP module according to the IP clock of each IP module provided by the clock distribution module. The reset monitoring module and the clock monitoring module can monitor the first subsystem in real time. When the reset monitoring module detects that each of the multiple IP modules is in reset release, it determines that the first subsystem has completed reset release.

[0056] Optionally, the clock distribution module and the reset synchronization module may be deployed in a local control unit of the first subsystem.

[0057] Therefore, the embodiment of the present application realizes monitoring of the reset release of the first subsystem through the deployment of the reset monitoring module.

[0058] Optionally, in an embodiment of the present application, a timing alarm module may also be deployed; a time threshold may be set for the timing alarm module.

[0059] The timing alarm module is used to start timing when the signal generating module supplies the first signal to the first subsystem.

[0060] If the accumulated time exceeds the time threshold and the signal monitoring module still does not output the access permission signal, an alarm event may be executed; wherein the alarm event includes but is not limited to indicating the following information:

[0061] Information 1: There is a problem in the signal transmission between the signal generating module and / or the signal monitoring module and the first subsystem;

[0062] Information 2: Components in the module are damaged. The module includes at least one of the following: a signal generating module, a signal monitoring module, and a first subsystem.

[0063] Therefore, an optional embodiment of the present application can deploy a timing alarm module in the signal output system to perform timeout monitoring on the entire signal output system and the first subsystem when the signal generating module supplies clock and resets the first subsystem, thereby ensuring the stability of the entire signal output system and the first subsystem.

[0064] The present application also provides a method embodiment, which can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 3 1 is a hardware structure block diagram of a computer terminal of a signal output method according to an embodiment of the present application. Figure 3 As shown, the computer terminal may include one or more ( Figure 3Only one is shown in the figure) a processor 302 (the processor 302 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 304 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 306 and an input and output device 308 for communication functions. It can be understood by those skilled in the art that Figure 3 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 3 More or fewer components as shown, or with Figure 3 Different configurations are shown.

[0065] The memory 304 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for allocating load resources in the embodiment of the present application. The processor 302 executes various functional applications and data processing by running the computer program stored in the memory 304, that is, to implement the above method. The memory 304 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 304 may further include a memory remotely arranged relative to the processor 302, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0066] The transmission device 306 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 306 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 306 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0067] Furthermore, an embodiment of the present application provides a signal output method, which is applied to the above-mentioned signal output system. Figure 4 is a flow chart of a signal output method according to an embodiment of the present application, such as Figure 4 As shown, the process includes the following steps:

[0068] Step S402, providing a first signal required by a first subsystem on a target chip to the first subsystem, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip;

[0069] Step S404: monitor the first subsystem, and output an access permission signal when it is detected that the state of the first subsystem meets the target state, wherein the target state includes: the clock state of the first subsystem is stable, and the first subsystem completes reset release, wherein the access permission signal is used to indicate that the first subsystem allows access.

[0070] Through the above steps, the first signal required by the first subsystem on the target chip is provided to the first subsystem, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip; the first subsystem is monitored, and when it is monitored that the state of the first subsystem meets the target state, an access permission signal is output, wherein the target state includes: the clock state of the first subsystem is stable, and the first subsystem completes reset release, wherein the access permission signal is used to indicate that the first subsystem allows access. Therefore, the problem of how to safely access the chip after the chip is subjected to power-on reset release and a series of operations are started in the related art can be solved. Thereby, the technical effect of being able to safely access the target chip is achieved.

[0071] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0072] Furthermore, in order to better understand the above-mentioned signal output system, the above-mentioned signal output system is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of the present application.

[0073] It should be noted that if Figure 2As shown, before the SoC chip is started, each subsystem including the internal modules are in a reset state. After the power-on reset is released, during the chip startup process, the SCU needs to sequentially supply clocks and reset release operations to the main clock and power-on reset of each subsystem. Then the local control unit (local CU) inside the subsystem will sequentially supply clocks and reset release operations to the functional clocks and resets of each IP module, so that the entire chip can enter the working state normally. At the same time, when the chip receives a reset request, it is necessary to reset the internal modules included in the subsystem when the chip is working normally. After the reset is released, since the reset needs to be released synchronously in different clock domains, during this synchronization period, the CPU needs to perform a no-operation instruction (nop instruction) for data access and wait for the reset to be fully ready before it can be safely accessed.

[0074] In an optional embodiment of the present application, in order to solve the problem of secure access after the power-on reset on the chip is released and started, a method is proposed that does not require software waiting. Through a system control circuit based on a hardware circuit (equivalent to the signal output system in the above embodiment) and an implementation method (equivalent to the signal output method in the above embodiment), the hardware circuit automatically monitors the clock and reset status of the subsystem. After the longest reset path inside the subsystem has been released and an interrupt is reported to the CPU, the CPU can perform corresponding data access. Compared with traditional software implementation methods, this invention saves software waiting operations and ensures the security of system access.

[0075] Specifically, the system control circuit based on the hardware circuit is as follows Figure 5 As shown,

[0076] Among them, the system control unit (SCU) is mainly responsible for the clock and reset control required by each subsystem (equivalent to the first subsystem in the above embodiment), and the local control unit (local CU) specifically refines the clock and reset synchronization logic within the subsystem (equivalent to the first subsystem). The SCU includes four parts: a clock generation module, a clock monitoring module, a reset generation module, and a reset monitoring module, while the local CU includes two parts: a clock distribution module and a reset synchronization module.

[0077] After the power-on reset is released, during the chip startup process, the clock generation module provides the master clock to each subsystem according to the phase-locked loop (PLL) clock, and then the local control unit inside the subsystem provides the IP clock configuration according to the clock register, including the division coefficient used by the divider and the enablement of the gating unit, and provides the corresponding clock signal (equivalent to the IP clock in the above embodiment) to each IP module. The clock monitoring module is responsible for obtaining the master clock of the subsystem and the clock status of its internal IP module.

[0078] Specifically, if Figure 6 ,as well as Figure 7 As shown, during the clock supply process:

[0079] Clock generation module: The chip reference clock is used as the input clock of the PLL module (i.e., phase-locked loop clock module). When the chip power-on reset is released (equivalent to the first state), the default clock uses the chip reference clock to work; after waiting for uncore PLL lock (equivalent to the second state), the hardware automatically switches the clock to the PLL clock (equivalent to the fourth signal). For subsystems that require frequency division, the internal frequency division module needs to first synchronize the power-on reset with the PLL clock before it can perform specific frequency division and provide it to the subsystem as the main clock.

[0080] Clock distribution module: Figure 6 The master clock output is provided to the Figure 7 The clock distribution module in the subsystem. Generally, the main clock provided to the subsystem is the highest clock frequency of the subsystem. Since the power-on reset of the subsystem has not been released at this time, the chip power-on reset is required to perform clock division and gating to obtain the configuration clock. After waiting for the reset of the subsystem to be released, the clock register works normally to provide clock configuration (equivalent to IP clock configuration). According to the IP clock configuration of the clock register, the clocks of each IP inside the subsystem can be provided. Here, the gating enable of the IP module that does not need to be accessed at power-on startup can be turned off by default to achieve low power consumption requirements.

[0081] Clock monitoring module: responsible for collecting the clock status of the subsystem's master clock, configuration clock, and IP module (corresponding to the first clock status, the second clock status, and the third clock status, respectively). Clock monitoring is performed through a delay counter. When the clock frequency of any of the master clock, configuration clock, and IP clock takes effect, a fixed delay count is performed on any clock to ensure that the clock frequency of any clock is stable. At this time, the clock status of any clock is stable. When the subsystem's master clock, configuration clock, and the clock status of all IP modules are stable, it can be used as a sign of completion of the subsystem clock supply during the power-on startup process.

[0082] Optionally, after the power-on reset is released, the reset generation module provides power-on reset to each subsystem according to the reset release order during the chip startup process, and then the local control unit inside the subsystem provides IP reset configuration according to the reset register, including reset request configuration and reset Mask configuration, and provides corresponding reset signals to each IP module. The reset monitoring module is responsible for obtaining all reset states of the IP modules inside the subsystem.

[0083] Specifically, during the power-on reset release process:

[0084] Reset generation module: used to realize the generation and distribution of power-on reset signals of subsystem modules, as well as the control of the reset release sequence of the system. In addition, there will be corresponding control of various reset sources, so as to respond to various reset requests from the source. For subsystems with local control units, only the power-on reset signal needs to be provided, and the internal IP modules are reset by the local control unit.

[0085] The reset request of the optional embodiment of the present application includes but is not limited to: watchdog (WDT) reset, software (SW) reset, CPU self-reset, I2C2AHBM debug reset, etc. Different reset requests correspond to different reset ranges, which are defined according to chip requirements. Here, efuse burning can be selected to achieve it.

[0086] Regarding the customized reset request control implemented by efuse (electronic fuse) in the reset generation module, the optional embodiment of the present application also supports the following application scenarios:

[0087] After the chip is taped out, the hardware circuit has been solidified. For different application scenarios, there are inconsistent reset conditions of the chip under the reset request, which brings about the need for inconsistent reset ranges. Reset requests include, for example, watchdog (WDT) reset, software (SW) reset, I2C2AHBM debug reset, etc. An optional embodiment of the present application provides a method for implementing a customized reset request control circuit through efuse, that is, according to the usage of the subsystem or IP inside the chip, confirm the subsystem or IP that needs to be controlled by the reset request, and the reset default value of the reset request control, and burn the impact value of the reset request into efuse. After the chip is powered on, the configuration in efuse can be directly used to complete the customized reset access rights.

[0088] like Figure 8 As shown, the same SoC chip is soldered on different PCBs due to different application scenarios, and the modules allowed to be accessed under different reset requests are inconsistent. For example, for the I2C2AHBM debug reset request, subsystems 0 and 1 under PCB1 are accessible, while subsystems 2 and 3 will be reset and not allowed to be accessed until the reset request is revoked. Therefore, the reset default values ​​and the impact values ​​of the reset request control related to the four subsystems are injected into the efuse of PCB1. PCB2 can access systems 0 and 1, as well as IP0, IP1, IP2, and IP3 inside subsystem 3, while subsystem 2 and IP4, IP5, IP6, and IP7 will be reset. Therefore, although they are all the same SOC subsystems, the access rights under different reset requests are realized according to the different injected efuse data.

[0089] Reset synchronization module: At this time, the power-on reset of the subsystem has been released, and the chip power-on reset is required to perform clock division and gating to obtain the configuration clock. The reset register works normally, and according to the IP reset configuration of the reset register, including the reset request configuration and the reset Mask configuration, the corresponding reset signal is provided to each IP module.

[0090] According to the IP clocks provided by the clock distribution module, each IP reset needs to be reset synchronously. At this time, after being sent to the IP module, there is no need to perform cross-clock processing, and logical processing can be performed directly.

[0091] If there is a reset request inside the subsystem, the SCU needs to be notified to reset it. For example, if the reference clock of the PCIe host is detected to be lost, it means that the system needs to enter power-down mode later. In this scenario, the reset status of the subsystem is obtained through the reset detection module, and the CPU is used to control each subsystem. By silencing the subsystem and turning off the power supply, the system energy consumption is further reduced, providing more energy support for data transfer.

[0092] Reset monitoring module: Fig. 9 As shown in the figure, it is responsible for collecting the reset status of each IP module of the subsystem. Only after the reset status of the last level inside the subsystem is released can it be considered to meet the requirements of the longest reset path. It serves as a subsystem reset release completion mark during the power-on startup process. At this time, the CPU can access the data of the subsystem safely without waiting for any software time.

[0093] Based on the above system control circuit, the working process after the chip is powered on and reset is as follows Fig.10 As shown, including:

[0094] Step 1: After the chip is powered on and the system reference clock is stable, release the power-on reset;

[0095] Step 2: Release PLL reset and PLL starts to work;

[0096] Step 3: After waiting for PLL lock, the hardware can automatically switch frequency;

[0097] Step 4: Start loading eFuse data and read efuse content;

[0098] Step 5: Monitor the master clock status of each subsystem;

[0099] Step 6: Determine whether the main clock of each subsystem is stable;

[0100] Step 7: Now start to release the peripheral reset and the power-on reset of each subsystem;

[0101] Step 8: Follow the CPU reset sequence for peripherals, wait for a fixed system clock cycle, and release the CPU reset;

[0102] Step 9: According to the IP clocks provided by the clock distribution module, reset synchronization is performed for each IP reset;

[0103] Step 10: At this point, the subsystem's clock and reset have been released, and the subsystem is allowed to be accessed;

[0104] Step 11: The CPU sends an instruction to the subsystem to access it;

[0105] Step 12: If a reset request occurs during the CPU operation, the system is checked. If a reset request occurs, the subsystem needs to be reset asynchronously, enter the local control unit, and then be sent to all internal IP modules after reset synchronization to ensure that all working modules can be reset under the reset request to meet the system reset requirements.

[0106] In addition, the optional embodiments of the present application involve the following two implementation schemes for subsystem reporting interruption (i.e., the access permission signal in the above embodiment is output by reporting interruption):

[0107] First, the subsystem reset release is completed and an independent interrupt is reported:

[0108] When all clocks of the subsystem are ready, all resets are completed and reset release is completed, ensuring that the longest reset path requirement is met, the hardware interrupt can be reported according to the subsystem. The system assigns an independent interrupt ID number to each subsystem. After the CPU receives the interrupt, it can complete the subsequent data access of the subsystem according to the ID number.

[0109] However, this solution is suitable for chips involving a small number of subsystems, because interrupts themselves are also hardware resources. In order to monitor the clock and reset status of the subsystem, it is a waste of resources to plan an independent interrupt for each subsystem.

[0110] Second, the subsystem reset release is completed and the shared interrupt is reported:

[0111] When all the clocks of the subsystem are ready, the reset is completed and released to ensure that the longest reset path requirement is met, the clock and reset status of the subsystem are recorded in the register of the system control unit (SCU). The system only needs to allocate a shared interrupt for all subsystem security accesses.

[0112] After the CPU receives the shared interrupt, the software reads the clock and reset status of the subsystem inside the SCU to check which subsystem triggered the interrupt, and then completes the subsequent data access of the subsystem.

[0113] Compared with the independent interrupt solution, this solution is suitable for chips involving a large number of subsystems. Only one interrupt is needed to complete the clock reset monitoring and ensure the safe access to the chip.

[0114] In summary, the optional embodiments of the present application are implemented based on hardware circuits, and the chip power-on reset and security access circuit and implementation method are applicable to SoC circuits and systems including various subsystems. Compared with the implementation method of software instructions waiting for the subsystem to release reset, this method is faster, safer and more accurate through hardware status monitoring, and once the power is released, the hardware automatically collects the clock and reset of each subsystem. The software does not need to adjust the instruction access interval for the problem of inconsistent reset release synchronization of each subsystem, and has better security. It is a simple and reliable reset monitoring control method.

[0115] As the scale and complexity of SoCs gradually increase, clock and reset control management units are increasingly large. In order to ensure secure access after the SoC is powered on and reset, the software and hardware division can be carried out during the design to give full play to the respective advantages of software and hardware. The optional embodiment of the present application proposes to use hardware circuits to ensure that the clock and reset control circuits are effective after the chip is powered on and reset, thereby reducing the waiting time of the software. Subsequently, circuit optimization for clock generation and reset path management is required to ensure the safety of the power-on startup process.

[0116] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0117] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0118] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0119] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0120] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0121] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0122] An embodiment of the present application also provides a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0123] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0124] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0125] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A signal output system, characterized in that: include: Signal generating module and signal monitoring module; The signal generating module is used to provide a first signal required by a first subsystem on the target chip, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip; The signal monitoring module is used to monitor the first subsystem when the signal generating module provides the first signal to the first subsystem, and output an access permission signal when it is monitored that the state of the first subsystem meets the target state, wherein the target state includes: the clock state of the first subsystem is stable and the first subsystem completes reset release, wherein the access permission signal is used to indicate that the first subsystem allows access.

2. The signal output system according to claim 1, characterized in that: The signal generating module comprises: a clock generating module and a reset generating module; The clock generation module is used to provide a second signal required by the first subsystem, wherein the second signal is used to provide a clock supply to the first subsystem; The reset generating module is used to provide a third signal required by the first subsystem, wherein the third signal is used to provide a reset release to the first subsystem; The first signal includes: the second signal and the third signal.

3. The signal output system according to claim 2, characterized in that: The clock generation module includes a phase-locked loop clock module. The phase-locked loop clock module is used to generate a fourth signal; The clock generation module is used to receive the chip reference clock of the target chip; When the locked loop clock module is in the first state, using the chip reference clock as the second signal; When the locked loop clock module is in the second state, the fourth signal is used as the second signal.

4. The signal output system according to claim 2, characterized in that: The local control unit of the first subsystem is deployed with a clock distribution module; The clock distribution module is used to receive the second signal sent by the clock generation module and use the second signal as the master clock of the first subsystem; wherein the clock distribution module includes: a clock register, at least two frequency dividers, and at least two gating units; One of the at least two frequency dividers is further used to receive a chip power-on reset of the target chip; the master clock is divided by the chip power-on reset to obtain a configuration clock of the local control unit; wherein one of the at least two frequency dividers is connected to one of the at least two gating units; The clock register is used to determine the IP clock configuration corresponding to each IP module in the multiple IP modules in the first subsystem through the configuration clock when the first subsystem is reset and released; wherein the clock register is connected to another frequency divider of the at least two frequency dividers, and the other frequency divider of the at least two frequency dividers is connected to another gating unit of the at least two gating units; The clock register is further used to provide an IP clock for each IP module through another frequency divider of the at least two frequency dividers and another gating unit of the at least two gating units, wherein the IP clock is determined by the IP clock configuration.

5. The signal output system according to claim 4, characterized in that: The signal monitoring module includes: a clock monitoring module; The clock monitoring module is used to collect the first clock state of the master clock, the second clock state of the configuration clock, and the third clock state of the IP clock; The clock monitoring module is also used to determine that the clock state of the first subsystem is stable when the clock frequency of the main clock is stable through the first clock state, the clock frequency of the configuration clock is stable through the second clock state, and the clock frequency of the IP clock is stable through the third clock state.

6. The signal output system according to claim 2, characterized in that: The reset generation module is used to generate the third signal, and the third signal is used to provide a reset release to the first subsystem according to the target order corresponding to the first subsystem; The target order is the order of the first subsystem in the reset release sequence preset for the at least one subsystem.

7. The signal output system according to claim 6, characterized in that: The local control unit of the first subsystem is further deployed with a reset synchronization module, wherein the reset synchronization module includes: a reset register and a reset synchronizer; The reset register determines the IP reset configuration corresponding to each IP module in the plurality of IP modules in the first subsystem through the third signal; The reset synchronizer provides a reset signal to each IP module through the IP reset configuration; The signal monitoring module also includes: a reset monitoring module, which is used to monitor the reset state of each IP module when each IP module receives the reset signal; and determine that the first subsystem has completed reset release when each IP module is in reset release.

8. A signal output method, characterized in that: The signal output system according to any one of claims 1 to 7 comprises: Providing a first signal required by a first subsystem on a target chip to a first subsystem on the target chip, wherein the first signal is used to provide clock supply and reset release to the first subsystem, wherein the first subsystem is any subsystem of at least one subsystem on the target chip; The first subsystem is monitored, and when it is monitored that the state of the first subsystem meets the target state, an access permission signal is output, wherein the target state includes: the clock state of the first subsystem is stable, and the first subsystem completes reset release, wherein the access permission signal is used to indicate that the first subsystem allows access.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in claim 8 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to claim 8 are implemented.

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