A logic synthesis and verification method based on memristor-assisted logic

Abstract

The present invention discloses a logic synthesis and verification method based on memristor-assisted logic, comprising the following steps: S1, logic synthesis: using ABC to obtain a gate-level netlist for representing a Boolean function, converting the circuit topology connection relationship in the gate-level netlist into a DAG; using DFS to obtain the execution sequence of each node in the DAG, and calculating the mapping cost value of each node; obtaining the execution order of the root node in the circuit; for each root node, recursively collecting child nodes and obtaining the corresponding execution sequence, mapping the nodes in the execution sequence to the memristor array in sequence, and generating corresponding micro-operators; S2, verification: parsing the generated micro-operators, and performing logical equivalence and design rule verification on them. This method not only reduces the number of memristor units, but also has a very limited increase in the calculation cycle, and can effectively verify the correctness of the mapping result, and the verification takes a short time.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and in particular to a logic synthesis and verification method based on memristor-assisted logic. Background Art

[0002] In the era of artificial intelligence and the Internet of Things, the separation of computing and storage in the traditional von Neumann architecture has bottlenecks such as storage wall and power consumption wall, which limits the further improvement of computing power. The integrated computing architecture that integrates storage and computing is expected to solve the above problems and thus greatly improve computing power. As a strong candidate device for realizing the integrated computing architecture, memristors provide a new solution to the above problems.

[0003] Memristors can be used to implement a variety of logical operations, such as implication logic (IMPLY) and memristor-aided logic (MAGIC). Memristor-aided logic can be used to implement all basic digital logic gates, such as AND, OR, NOT, NAND, NOR, etc.; at the same time, NOR and NOT can be directly mapped to the memristor array. In addition, since NOR is a logically complete operator, any Boolean function can be represented by NOR. In addition, the rows and columns of the memristor crossbar array have a very regular arrangement, and the mapping rules of MAGIC enable MAGIC to support parallel operations, which can significantly improve the throughput of arithmetic operations.

[0004] In order to solve the problems of storage wall and power consumption wall of traditional computing systems, it is necessary to design a digital storage and computing system based on memristors. For digital storage and computing systems based on memristors, manual design is unrealistic in order to use the system to calculate complex Boolean functions in any real-world scenario, so it is crucial to develop efficient electronic design automation (EDA) tools. The traditional digital integrated circuit EDA process includes multiple stages. After completing the architecture design and RTL design, in the logic synthesis stage, the input Boolean function is first converted into an intermediate logic representation, such as an and inverter graph (AIG), using traditional process-independent logic synthesis. Then, a logic optimization algorithm needs to be applied to the intermediate logic representation to optimize the number of nodes or logic levels of the circuit. In the subsequent process mapping stage, unlike the traditional FPGA mapping based on look-up table (LUT) and ASIC mapping based on standard cell library (SCL), the storage and computing system needs to map the optimized intermediate logic representation to the memristor crossbar array and obtain the corresponding micro-operations (MC). The micro-operator includes the number of memristor units required for mapping, the computing cycles required for mapping, and the specific computing operations corresponding to each computing cycle.

[0005] The most advanced logic synthesis framework based on memristor-assisted logic has inaccurate cost functions and fails to consider the impact of the root node execution order on the mapping results, which makes the quality of the mapped results low. At the same time, the tool has a low degree of automation and requires manual selection of the appropriate memristor array size. The mapping process is cumbersome and inefficient. In addition, there is a lack of corresponding equivalence verification methods to verify whether the micro-operators generated after mapping meet the design specifications. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a logic synthesis and verification method based on memristor-assisted logic in view of the shortcomings of the prior art. This method not only reduces the number of memristor units, but also increases the calculation cycle very limitedly. At the same time, it can effectively verify the correctness of the mapping result, and the verification takes a short time.

[0007] The technical solution adopted by the present invention to solve the above technical problem is: a logic synthesis and verification method based on memristor-assisted logic, comprising the following steps:

[0008] S1. Logic synthesis:

[0009] Step S1.1, using an open source logic synthesis tool ABC to obtain a gate-level netlist for representing a Boolean function, and converting the circuit topology connection relationship in the gate-level netlist into a directed acyclic graph (DAG);

[0010] Step S1.2, use depth-first search (DFS) to obtain the execution sequence of each node in the DAG and calculate the mapping cost value of each node;

[0011] Step S1.3, based on the logic network represented by DAG and the calculated mapping cost value, the execution order of the root nodes in the circuit is obtained;

[0012] Step S1.4: According to the execution order of the root nodes, for each root node, recursively collect the child nodes and obtain the corresponding execution sequence, map the nodes in the execution sequence to the memristor array in sequence, and generate the corresponding micro-operators;

[0013] S2. Verification:

[0014] The generated micro-operators are parsed and subjected to logical equivalence and design rule verification.

[0015] Preferably, the specific process of step S1.1 is:

[0016] Use the open source logic synthesis tool ABC to read in the Boolean function described in verilog or blif format and the process library in genlib format containing the gates nor2, inv1, zero, one, and buf, where nor2 represents a two-input NOR gate, inv1 represents a single-input inverter, zero represents a constant gate zero, one represents a constant gate one, and buf represents a buffer;

[0017] Use ABC's built-in synthesis flows resyn, resyn2, and resyn2rs to perform logic optimization on the AIG representation of Boolean functions;

[0018] Use the process mapping command map in ABC and the input process library to process map the AIG representation of the Boolean function to obtain the gate-level netlist in Verilog format;

[0019] The circuit topology connection relationship in the gate-level netlist is converted into DAG through the netlist parser, where the nodes in the DAG include two types: inv1 and nor2, and the edges in the DAG represent the connection relationship between logic gates.

[0020] Preferably, the specific process of step S1.2 is:

[0021] For each node in the DAG, DFS is used in the fan-in direction of the node to obtain the execution sequence corresponding to each node, where the execution sequence is a set of nodes;

[0022] Using the proposed cost algorithm, for each execution sequence corresponding to a node, the mapping cost value of the execution sequence is calculated and assigned as the mapping cost value of the node;

[0023] The proposed cost algorithm is: for any node and its corresponding execution sequence, the cost value cost and tag value i The initial values ​​of are initialized to 0. For each node in the execution sequence, if the fan-in quantity of the node is equal to 0, then i Add 1 if i Greater than cost , then i The value of cost ; If the fan-in quantity of the node is not equal to 0, then i Add 1 if i Greater than cost , then i The value of cost ; Get the node's child node set child nodes ,for child nodes For each node in the node, reduce the fan-out quantity of the node by 1. If the fan-out quantity of the node becomes 0, then i The value of is reduced by 1;

[0024] The final result obtained after calculating each node in the execution sequence according to the above cost algorithm cost , which is the mapping cost value of the execution sequence.

[0025] As a preferred method, in step S1.3, the execution order of the root nodes in the circuit is obtained by combining the intelligent algorithm with the proposed cost algorithm. currentRoots , the specific process is:

[0026] Propose an intelligent algorithm: a logical network represented by DAG N As the input of the intelligent algorithm, currentRoots As the output of the intelligent algorithm, initialize: counter count 0, initial temperature initTemp 10, final temperature finalTemp 0.01, cooling rate coolRate is 0.8, and the initial root node set in the circuit is obtained. initialRoots ;by initialRootsThe initial root node storage index is in ascending order as the initial root node execution order. According to the initial root node execution order and the proposed child node collection method, the initial execution sequence is obtained; the initial mapping cost of the circuit is obtained using the proposed cost algorithm. oldCost ;

[0027] Among them, the proposed child node collection method is: for a certain node M , select M When selecting a child node, first select the child node with a higher mapping cost value. If the mapping cost values ​​are the same, select the child node with the smallest maximum fan-out level. If the smallest maximum fan-out levels are the same, select the node in ascending order according to the storage index of the node in the DAG.

[0028] When the initial temperature is greater than the final temperature, the outer loop is entered; when the counter value is less than 1000, the inner loop is entered;

[0029] In the inner loop, randomly swap initialRoots The two root nodes in initialRoots , with new initialRoots The storage index of the root node is in ascending order as the execution order of the new root node, and then according to the execution order of the new root node and the proposed child node collection method, the new execution sequence is obtained. newGates , use the proposed cost algorithm to calculate the new mapping cost newCost , and then calculate the corresponding acceptance probability accp_prob , the calculation formula is as follows:

[0030] ,

[0031] Use the random number generator to generate a random number between 0 and 1. If the generated random number is less than accp_ prob , then newCost The value of oldCost , and initialRoots The value of currentRoots , then count The value of is increased by 1; when count When the value is greater than 1000, the inner loop ends;

[0032] At the end of each inner loop, calculate initTemp and coolRate The product of initTemp When initTemp The value is less than or equal to finalTemp When the value of , the outer loop ends and returns currentRoots .

[0033] Preferably, the specific process of step S1.4 is: according to the execution order of the root nodes, for each root node, the proposed child node collection method is used to recursively collect child nodes and obtain the corresponding execution sequence, and the nodes in the execution sequence are sequentially mapped to the memristor array composed of multiple memristor units, and corresponding micro-operators are generated, wherein the micro-operator includes the number of memristor units required for mapping, the calculation cycle required for mapping, and the specific calculation operation corresponding to each calculation cycle.

[0034] Preferably, the specific process of step S2 is:

[0035] The micro-operator text file is parsed by the micro-operator parser and converted into a LUT network described in bench format;

[0036] Use ABC to read the Boolean function described in Verilog or blif format, and use it as the design specification in the verification process. Convert the design specification into an AIG network, and use ABC to build a Miter circuit with the AIG network and the LUT network to obtain the corresponding CNF file.

[0037] Use the open source SAT solver kissat to solve the CNF file. If the result is UNSAT, it means that the micro-operators generated after mapping are logically equivalent to the design specifications. Otherwise, the micro-operators generated after mapping are logically not equivalent to the design specifications.

[0038] The memristor unit index in the micro-operator is parsed by the micro-operator parser and stored as a two-dimensional array with a tag value, wherein: the one-dimensional array starting with -2 in the two-dimensional array indicates that the output memristor unit is initialized to a low resistance state for the first time, that is, logic '1'; the one-dimensional array starting with -1 in the two-dimensional array indicates that the memristor is reused during the operation, that is, the memristor unit that has been used is initialized to a low resistance state, that is, logic '1';

[0039] Each one-dimensional array in the two-dimensional array represents a calculation cycle of the micro-operator. In each calculation cycle, the first element represents the index of the output memristor unit, and the remaining elements represent the corresponding indexes of the input memristor units. Each calculation cycle is sequentially checked to see if the conditions are met: the output memristor unit is initialized to a low-resistance state and the input memristor unit has been used in the previous calculation cycle. If all calculation cycles in the two-dimensional array meet the above conditions, the design rule verification is successful; if one calculation cycle does not meet the above conditions, the design rule verification fails.

[0040] Compared with the prior art, the present invention has the following advantages:

[0041] (1) The mapping result of the logic synthesis and verification method based on memristor-assisted logic proposed in the present invention is better and more automated. The method of the present invention can accurately calculate the cost value required for each node in the circuit to complete the mapping based on the topological information of the circuit. Compared with the traditional method, the present invention not only has a more accurate cost function, but also can obtain a better execution sequence. Through example verification, the number of memristor units obtained by the method of the present invention is effectively reduced.

[0042] (2) The logic equivalence and design rule verification in the method of the present invention can accurately verify the micro-operators generated by the logic synthesis step. Compared with the lack of verification of mapping results in the traditional logic synthesis process based on memristor-assisted logic, the verification method in the present invention makes up for the corresponding deficiency. The verification step of the method of the present invention can successfully detect errors in the micro-operators generated by the logic synthesis step, which once again proves the importance of the verification operation. When the verification fails, the corresponding information can be output, so that the error can be quickly located. For the results of the logic synthesis step in the method of the present invention, the verification results are all correct. Compared with the verification method of manually deriving small cases and the verification method based on simulation, the formal verification method proposed in the present invention is more accurate, reliable and complete.

[0043] (3) In a specific preferred embodiment, the present invention proposes an accurate cost algorithm by considering the topological information of the circuit, especially the information of multiple fan-out nodes. For the execution sequence with each node as the root node in the circuit, the corresponding mapping cost can be accurately calculated. At the same time, combined with the intelligent algorithm, the execution order of the root node in the circuit can be obtained with high quality. In the subsequent process of recursively collecting child nodes according to the execution order of the root node, the cost value of the node in the circuit and the fan-out level information of the node are considered. Finally, mapping is performed according to the obtained high-quality execution sequence. The method of the present invention not only reduces the number of memristor units, but also increases the calculation cycle very limitedly. The method of the present invention fills the gap of the prior art, not only can effectively verify the correctness of the mapping result, but also the verification time is short. The mapping results on the ISCAS'85 and IWLS'93 test sets show that the method of the present invention reduces the number of memristors by 13% and 10% respectively, and the calculation cycle only increases by 1% and 2% respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a process library in genlib format that contains nor2, inv1, zero, one, and buf gates;

[0045] Figure 2 The DAG generated for parsing the netlist of the c17 circuit;

[0046] Figure 3It is the overall flow chart of the intelligent algorithm;

[0047] Figure 4 The micro-operator obtained after mapping the c17 circuit;

[0048] Figure 5 Bench format file generated for the micro-operator corresponding to the c17 circuit;

[0049] Figure 6 DAG corresponding to the bench file;

[0050] Figure 7 A schematic diagram showing the verification of logical equivalence;

[0051] Figure 8 A two-dimensional array generated for parsing micro-operators. DETAILED DESCRIPTION

[0052] The present invention is further described in detail below with reference to the accompanying drawings.

[0053] Taking the c17 circuit in the international benchmark test circuit example MCNC as an example, the method of the present invention is used to perform logic synthesis and verification, and the steps are as follows:

[0054] S1. Logic synthesis:

[0055] Step S1.1, use the open source logic synthesis tool ABC to obtain the gate-level netlist used to represent the Boolean function, and convert the circuit topology connection relationship in the gate-level netlist into a directed acyclic graph DAG. The specific process is as follows:

[0056] Use the open source logic synthesis tool ABC to read the C17 circuit described in Verilog or BLIF format and the genlib format containing NOR2, INV1, ZERO, ONE, and BUF gates. Figure 1 The process library shown, where nor2 represents a two-input NOR gate, inv1 represents a single-input inverter, zero represents a constant gate zero, one represents a constant gate one, and buf represents a buffer;

[0057] Use ABC's built-in synthesis flows resyn, resyn2, and resyn2rs to perform logic optimization on the AIG representation of Boolean functions;

[0058] Use the process mapping command map in ABC and the input process library to process map the AIG representation of the Boolean function to obtain the netlist of the C17 circuit in Verilog format;

[0059] The circuit topology connection relationship in the netlist of the c17 circuit is converted into DAG through the netlist parser, such as Figure 2As shown, the red-marked nodes g03, g04, g06, g07, g10, and g11 represent two-input NOR gates, and the green-marked nodes g00, g01, g02, g05, g08, g09, and g12 represent single-input inverters; g00~g12 represent the names of the nodes in the DAG, each node name is unique, and the number immediately following the underscore '_' represents the mapping cost value of the node; the DAG has five original inputs: pi0, pi1, pi2, pi3, pi4, and two original outputs po0 and po1.

[0060] Step S1.2: Use depth-first search DFS to obtain the execution sequence of each node in the DAG and calculate the mapping cost value of each node. The specific process is as follows:

[0061] For each node in the DAG, DFS is used in the fan-in direction of the node to obtain the execution sequence corresponding to each node, where the execution sequence is a set of nodes;

[0062] Using the proposed cost algorithm, for each node corresponding to the execution sequence, the mapping cost value of the execution sequence is calculated and assigned as the mapping cost value of the node. Table 1 shows the execution sequence corresponding to each node in the DAG corresponding to the netlist of the c17 circuit, as well as the mapping cost value of the execution sequence, which is consistent with Figure 2 Each node name in the , for example, g01, has the same meaning as the number immediately following the underscore.

[0063] Table 1:

[0064]

[0065] The proposed cost algorithm is: for any node and its corresponding execution sequence, the cost value cost and tag value i The initial values ​​of are initialized to 0. For each node in the execution sequence, if the fan-in quantity of the node is equal to 0, then i Add 1 if i Greater than cost , then i The value of cost ; If the fan-in quantity of the node is not equal to 0, then i Add 1 if i Greater than cost , then i The value of cost ; Get the node's child node set child nodes ,for child nodes For each node in the node, reduce the fan-out quantity of the node by 1. If the fan-out quantity of the node becomes 0, then iThe value of minus 1; the final value obtained after calculating each node in the execution sequence according to the above cost algorithm cost , which is the mapping cost value of the execution sequence.

[0066] An example is given to illustrate how to use the proposed cost algorithm to calculate the mapping cost value of a node. Taking node g04 as an example, after using DFS, its corresponding execution sequence is: g01, g02, g03, g00, g04. The process of using the cost algorithm to calculate the mapping cost value of node g04 is as follows: First, initialize the cost value cost and tag value i are all 0. Since the fan-in quantity of node g01 in the execution sequence is 0 (the fan-in does not include the original input), the tag value i Add 1, equal to 1, now i Greater than cost cost , then i The value of cost ,at this time cost is 1. The calculation process of the mapping cost value of node g02 is the same as above. After processing g02, i is 2, cost For node g03, since its fan-in node number is 2, the tag value i Add 1, which equals 3. i Greater than cost cost , then i The value of cost ,at this time cost Also 3. Get the child node set of the current node child nodes , that is, g01 and g02. For each child node, reduce the fan-out quantity of the child node by 1. In this process, the fan-out quantity of node g01 becomes 1. Since the fan-out quantity of node g02 becomes 0, then i The value of is reduced by 1 and becomes 2. i is 2, cost The process of processing node g00 is the same as that of processing nodes g01 and g02. After completing this process, i becomes 3, cost Still 3. Next, we process node g04. After processing g04, i becomes 4, since 4 is greater than cost The value of is 3, so update cost is 4. After completing the above process, we obtain the cost value of the execution sequence corresponding to node g04 to complete the mapping, which is 4, that is, four memristor units are required to complete the mapping.

[0067] Step S1.3: Based on the logical network represented by DAG and the calculated mapping cost value, the execution order of the root nodes in the circuit is obtained. The specific process is as follows:

[0068] Propose an intelligent algorithm: a logical network represented by DAG N As the input of the intelligent algorithm, currentRoots As the output of the intelligent algorithm, initialize: counter count 0, initial temperature initTemp 10, final temperature finalTemp 0.01, cooling rate coolRate is 0.8, and the initial root node set in the circuit is obtained. initialRoots ;by initialRoots The initial root node storage index is in ascending order as the initial root node execution order. According to the initial root node execution order and the proposed child node collection method, the initial execution sequence is obtained; the initial mapping cost of the circuit is obtained using the proposed cost algorithm. oldCost The overall flow chart of the above intelligent algorithm is shown in Figure 3 ;

[0069] When the initial temperature is greater than the final temperature, the outer loop is entered; when the counter value is less than 1000, the inner loop is entered;

[0070] In the inner loop, randomly swap initialRoots The two root nodes in initialRoots , with new initialRoots The storage index of the root node is in ascending order as the execution order of the new root node, and then according to the execution order of the new root node and the proposed child node collection method, the new execution sequence is obtained. newGates , use the proposed cost algorithm to calculate the new mapping cost newCost , and then calculate the corresponding acceptance probability accp_prob , the calculation formula is as follows:

[0071] ,

[0072] Use the random number generator to generate a random number between 0 and 1. If the generated random number is less than accp_ prob , then newCost The value of oldCost , and initialRoots The value of currentRoots , then count The value of is increased by 1; when count When the value is greater than 1000, the inner loop ends;

[0073] At the end of each inner loop, calculate initTemp andcoolRate The product of initTemp When initTemp The value is less than or equal to finalTemp When the value of , the outer loop ends and returns currentRoots .

[0074] The method for collecting child nodes proposed in step S1.3 above is: for a certain node M , select M When selecting a child node, first select the child node with a higher mapping cost value. If the mapping cost values ​​are the same, select the child node with the smallest maximum fan-out level. If the smallest maximum fan-out levels are the same, select the node in ascending order according to the storage index of the node in the DAG. Taking the root node g12 as an example, the recursive collection process is as follows: recursively process the child node g11. The mapping cost values ​​of the two child nodes g10 and g04 of g11 are both 4, and the smallest maximum fan-out level is the same. Therefore, according to the storage index of the node in the default DAG, select the node in ascending order, that is, recursively process the node g04. Node g04 has two child nodes g03 and g00. The mapping cost value of g03 is greater than the mapping cost value of g00, so g03 is processed recursively first. The mapping cost values ​​and the minimum maximum fan-out level of the two child nodes of g03 are the same, so the collection order is g01 and g02. Since they do not contain child nodes, this layer of recursion ends and goes back to recursively process another child node g00 of g04. At this time, the recursion of g04 ends and recursively processes another child node g10 of g11. The child node collection method in this process is the same as above and will not be repeated. Finally, for node g11, the results obtained according to the above child node collection method are: g11, g10, g09, g04, g00, g03, g02, g01.

[0075] Step S1.4: According to the execution order of the root nodes, for each root node, the proposed child node collection method is used to recursively collect child nodes and obtain the corresponding execution sequence, and the nodes in the execution sequence are sequentially mapped to the memristor array composed of multiple memristor units, and the corresponding micro-operators are generated, wherein the micro-operators include the number of memristor units required for mapping, the calculation cycle required for mapping, and the specific calculation operation corresponding to each calculation cycle. Figure 4 is the micro-operator obtained after the c17 circuit is mapped. The micro-operator not only contains the specific information after the circuit is mapped, such as the number of memristor units required, calculation cycle, reuse cycle, etc., but also indicates the specific circuit nodes corresponding to each calculation cycle, and the index of the memristor unit corresponding to the input and output of each node. At the same time, it also contains the information of reusing and initializing the memristor unit.

[0076] S2. Verification:

[0077] Parse the generated micro-operators and verify their logical equivalence and design rules. The specific process is as follows:

[0078] The micro-operator text file is parsed by the micro-operator parser and converted into a LUT network described in the bench format. Bench is a text file format used to represent a digital circuit netlist in a readable and simple way. It is usually used in research fields such as logic synthesis and fault simulation. Figure 5 The bench format file generated for the micro-operator corresponding to the c17 circuit is as follows: Figure 5 As shown in the figure, the bench format file contains the circuit's INPUT, OUTPUT and other information, as well as the circuit's internal nodes represented in the form of a lookup table, such as "new_n9_ = LUT 0x1 (pi1)". Figure 6 DAG corresponding to the bench file;

[0079] Figure 7 To represent the schematic diagram of verifying logical equivalence, first use ABC to read in the Boolean function described in verilog or blif format, and use it as the design specification in the verification process. Convert the design specification into an AIG network, and use ABC to build a Miter circuit between the AIG network and the LUT network to obtain the corresponding CNF file;

[0080] Use the open source SAT solver kissat to solve the CNF file. If the result is UNSAT, it means that the micro-operators generated after mapping are logically equivalent to the design specifications. Otherwise, the micro-operators generated after mapping are logically not equivalent to the design specifications.

[0081] Verify whether the micro-operator complies with the memristor-assisted logic design rules: Figure 8As shown, the memristor unit index in the micro-operator is parsed by the micro-operator parser and stored as a two-dimensional array with a tag value, wherein: the one-dimensional array starting with -2 in the two-dimensional array indicates that the output memristor unit is initialized to a low resistance state for the first time, that is, logic '1'; the one-dimensional array starting with -1 in the two-dimensional array indicates that the memristor is reused during the operation, that is, the memristor unit that has been used is initialized to a low resistance state, that is, logic '1'; each one-dimensional array in the two-dimensional array represents a calculation cycle of the micro-operator, and in each calculation cycle, the first element represents the index of the output memristor unit, and the remaining elements represent the corresponding index of the input memristor unit; sequentially check whether each calculation cycle meets the conditions: the output memristor unit is initialized to a low resistance state and the input memristor unit has been used in the previous calculation cycle. If all calculation cycles in the two-dimensional array meet the above conditions, the design rule verification is successful; if one calculation cycle does not meet the above conditions, the design rule verification fails.

[0082] Compared with the current best mapping tool (R. Ben-Hur, R. Ronen, A. Haj-Ali, et al. “SIMPLER MAGIC: Synthesis and mapping of in-memory logic executed in a single row to improve throughput,” in TCAD, pp. 2434-2447, 2019), the logic synthesis and verification method based on memristor-assisted logic proposed in this invention has the following results on the ISCAS'85 and IWLS'93 test sets, as shown in Tables 2 and 3. The number of memristors used is reduced by 13% and 10%, respectively, and the calculation cycle is only increased by 1% and 2%, respectively.

[0083] Table 2:

[0084]

[0085] Table 3:

[0086]

[0087] The logic synthesis and verification method based on memristor-assisted logic proposed in the present invention can accurately verify whether the micro-operators generated after mapping are equivalent. For ten sets of equivalent test cases, the verification time is less than 1s. At the same time, we manually constructed some inequivalent cases, and the method of the present invention can also successfully detect the inequivalence of the results. The verification time of each part of the equivalent case and the inequivalent case and the total verification time are shown in Table 4 and Table 5 respectively.

[0088] Table 4:

[0089]

[0090] Table 5:

[0091]

[0092] In summary, the logic synthesis and verification method based on memristor-assisted logic proposed in the present invention not only reduces the number of memristor units, but also has a very limited increase in the calculation cycle. The method of the present invention fills the gap in the prior art, can not only effectively verify the correctness of the mapping result, but also takes a shorter time to verify.

Claims

1. A logic synthesis and verification method based on memristor-assisted logic, characterized in that: The steps include: S1. Logic synthesis: Step S1.1, using an open source logic synthesis tool ABC to obtain a gate-level netlist for representing a Boolean function, and converting the circuit topology connection relationship in the gate-level netlist into a directed acyclic graph DAG; Step S1.2, use depth-first search DFS to obtain the execution sequence of each node in DAG, and calculate the mapping cost value of each node; The specific process of step S1.2 is: For each node in the DAG, DFS is used in the fan-in direction of the node to obtain the execution sequence corresponding to each node, where the execution sequence is a set of nodes; Using the proposed cost algorithm, for each execution sequence corresponding to a node, the mapping cost value of the execution sequence is calculated and assigned as the mapping cost value of the node; The proposed cost algorithm is as follows: for any node and its corresponding execution sequence, the initial values ​​of the cost value cost and the tag value i are initialized to 0. For each node in the execution sequence, if the fan-in number of the node is equal to 0, then i is increased by 1, and if i is greater than cost, the value of i is assigned to cost; if the fan-in number of the node is not equal to 0, then i is increased by 1, and if i is greater than cost, the value of i is assigned to cost; get the child nodes of the node, for each node in the child nodes, reduce the fan-out number of the node by 1, if the fan-out number of the node becomes 0, then the value of i is reduced by 1; The final cost obtained after calculating each node in the execution sequence according to the above cost algorithm is the mapping cost value of the execution sequence; Step S1.3, based on the logic network represented by DAG and the calculated mapping cost value, the execution order of the root nodes in the circuit is obtained; In step S1.3, the execution order currentRoots of the root nodes in the circuit is obtained by combining the intelligent algorithm with the proposed cost algorithm. The specific process is as follows: An intelligent algorithm is proposed: the logic network N represented by DAG is used as the input of the intelligent algorithm, and currentRoots is used as the output of the intelligent algorithm. The counter count is initialized to 0, the initial temperature initTemp is 10, the final temperature finalTemp is 0.01, and the cooling rate coolRate is 0.

8. The initial root node set initialRoots in the circuit is obtained; the storage index of the initial root node of initialRoots is used in ascending order as the execution order of the initial root node. According to the execution order of the initial root node and the proposed child node collection method, the initial execution sequence is obtained; the proposed cost algorithm is used to obtain the initial mapping cost oldCost of the circuit; The proposed child node collection method is as follows: for a certain node M, when selecting the child nodes of M, the child nodes with higher mapping cost values ​​are selected first. If the mapping cost values ​​are the same, the child nodes with the smallest maximum fan-out level are selected; if the smallest maximum fan-out levels are the same, the nodes are selected in ascending order according to the storage index of the nodes in the DAG; When the initial temperature is greater than the final temperature, the outer loop is entered; when the counter value is less than 1000, the inner loop is entered; In the inner loop, the two root nodes in initialRoots are randomly exchanged to obtain the new initialRoots. The storage index of the root nodes of the new initialRoots is ordered from small to large as the execution order of the new root nodes. Then, according to the execution order of the new root nodes and the proposed child node collection method, the new execution sequence newGates is obtained. The proposed cost algorithm is used to calculate the new mapping cost newCost, and then the corresponding acceptance probability accp_prob is calculated. The calculation formula is as follows: Use the random number generator to generate a random number between 0 and 1. If the generated random number is less than the value of accp_prob, assign the value of newCost to oldCost, assign the value of initialRoots to currentRoots, and then add 1 to the value of count. When the value of count is greater than 1000, end the inner loop. At the end of each inner loop, the product of initTemp and coolRate is calculated to update the value of initTemp; when the value of initTemp is less than or equal to the value of finalTemp, the outer loop ends and currentRoots is returned; Step S1.4: According to the execution order of the root nodes, for each root node, recursively collect the child nodes and obtain the corresponding execution sequence, map the nodes in the execution sequence to the memristor array in sequence, and generate the corresponding micro-operators; The specific process of step S1.4 is as follows: according to the execution order of the root nodes, for each root node, the proposed child node collection method is used to recursively collect child nodes and obtain the corresponding execution sequence, and the nodes in the execution sequence are sequentially mapped to the memristor array composed of multiple memristor units in order, and the corresponding micro-operators are generated, wherein the micro-operators include the number of memristor units required for mapping, the calculation cycle required for mapping, and the specific calculation operation corresponding to each calculation cycle; S2. Verification: Parse the generated micro-operators and perform logical equivalence and design rule verification on them; The specific process of step S2 is: The micro-operator text file is parsed by the micro-operator parser and converted into a LUT network described in bench format; Use ABC to read the Boolean function described in Verilog or blif format, and use it as the design specification in the verification process. Convert the design specification into an AIG network, and use ABC to build a Miter circuit with the AIG network and the LUT network to obtain the corresponding CNF file. Use the open source SAT solver kissat to solve the CNF file. If the result is UNSAT, it means that the micro-operators generated after mapping are logically equivalent to the design specifications. Otherwise, the micro-operators generated after mapping are logically not equivalent to the design specifications. The memristor unit index in the micro-operator is parsed by the micro-operator parser and stored as a two-dimensional array with a tag value, wherein: the one-dimensional array starting with -2 in the two-dimensional array indicates that the output memristor unit is initialized to a low resistance state for the first time, that is, logic '1'; the one-dimensional array starting with -1 in the two-dimensional array indicates that the memristor is reused during the operation, that is, the memristor unit that has been used is initialized to a low resistance state, that is, logic '1'; Each one-dimensional array in the two-dimensional array represents a calculation cycle of the micro-operator. In each calculation cycle, the first element represents the index of the output memristor unit, and the remaining elements represent the corresponding indexes of the input memristor units. Each calculation cycle is sequentially checked to see if the conditions are met: the output memristor unit is initialized to a low-resistance state and the input memristor unit has been used in the previous calculation cycle. If all calculation cycles in the two-dimensional array meet the above conditions, the design rule verification is successful; if one calculation cycle does not meet the above conditions, the design rule verification fails.

2. A logic synthesis and verification method based on memristor-assisted logic according to claim 1, characterized in that: The specific process of step S1.1 is: Use the open source logic synthesis tool ABC to read in the Boolean function described in verilog or blif format and the process library in genlib format containing the gates nor2, inv1, zero, one, and buf, where nor2 represents a two-input NOR gate, inv1 represents a single-input inverter, zero represents a constant gate zero, one represents a constant gate one, and buf represents a buffer; Use ABC's built-in synthesis flows resyn, resyn2, and resyn2rs to perform logic optimization on the AIG representation of Boolean functions; Use the process mapping command map in ABC and the input process library to process map the AIG representation of the Boolean function to obtain the gate-level netlist in Verilog format; The circuit topology connection relationship in the gate-level netlist is converted into DAG through the netlist parser, where the nodes in the DAG include two types: inv1 and nor2, and the edges in the DAG represent the connection relationship between logic gates.

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