Display panel and driving method thereof

Abstract

The invention discloses a driving method of a display panel, which comprises the following steps: (a) inputting a waveform to a data line at a target time, and the longer the target time is, the lower the reflectivity of a plurality of liquid crystal molecules in the display panel is; (b) inputting a voltage to the first gate line at time intervals; (c) inputting a voltage to the second gate line at time intervals, wherein the first gate line has no input voltage; (d) inputting the voltage to the third gate line at time intervals, wherein the first gate line and the second gate line have no input voltage; and (e) repeating steps (b) to (d) until a target time, wherein the target time is at least forty milliseconds.

Description

Technical Field

[0001] The present disclosure relates to a display panel and a driving method of the display panel. Background Art

[0002] In the field of liquid crystal display, cholesterol liquid crystal is widely used in liquid crystal display because of its bistable characteristics. There are two different applications of bistable cholesterol liquid crystal: passive and active. Among them, the passive application needs to calculate the resistance multiplied by the capacitance of all pixels on the data line, so the resistance-capacitance delay (RC-Delay) will be very large.

[0003] In addition, although the application of active type can improve the resistance and capacitance delay by about two orders of magnitude, the cross-voltage required for switching cholesterol liquid crystal is very large, so a new display driving method is required. Summary of the invention

[0004] A technical aspect of the present disclosure is a driving method of a display panel.

[0005] According to one embodiment of the present disclosure, a method for driving a display panel includes (a) inputting a waveform to a data line at a target time, wherein the longer the target time is, the lower the reflectivity of multiple liquid crystal molecules in the display panel is; (b) inputting a voltage to a first gate line at a time interval; (c) inputting a voltage to a second gate line at a time interval, wherein no voltage is input to the first gate line; (d) inputting a voltage to a third gate line at a time interval, wherein no voltage is input to the first gate line and the second gate line; and (e) repeating steps (b) to (d) until the target time, wherein the target time is at least forty milliseconds.

[0006] In one embodiment of the present disclosure, the driving method of the display panel further includes inputting a positive and negative symmetrical waveform to the data line at a frequency so as to change the reflectivity of a plurality of liquid crystal molecules of the display panel.

[0007] In one embodiment of the present disclosure, the method for driving a display panel further includes resetting the data line with a constant frequency signal before step (a).

[0008] In one embodiment of the present disclosure, step (e) includes storing voltage using a plurality of thin film transistors.

[0009] In one embodiment of the present disclosure, the driving method of the display panel further includes inputting a positively and negatively symmetrical waveform to the data line at a frequency so as to change the reflectivity of multiple liquid crystal molecules of the display panel, wherein the voltage in the positive direction of the waveform changes between at least two voltages over time.

[0010] Another technical aspect of the present disclosure is a display panel.

[0011] According to one embodiment of the present disclosure, a display panel includes a voltage control unit, a first gate line, a second gate line, a third gate line, a data line, and a plurality of thin film transistors. The voltage control unit is configured to control an input voltage. The first gate line is electrically connected to the voltage control unit and configured to input a voltage through the voltage control unit at a time interval. The second gate line is electrically connected to the voltage control unit and configured to input a voltage through the voltage control unit at a time interval, wherein when the second gate line inputs a voltage, the first gate line has no input voltage. The third gate line is electrically connected to the voltage control unit and configured to input a voltage through the voltage control unit at a time interval, wherein when the third gate line inputs a voltage, the first gate line and the second gate line have no input voltage. The data line is electrically connected to the voltage control unit and configured to adjust the gray scale of the display panel through the voltage control unit. The thin film transistor is electrically connected to the data line and configured to store the voltage of the data line.

[0012] In one embodiment of the present disclosure, the voltage control unit is configured to input a positive and negative symmetrical waveform to the data line so that the reflectivity of a plurality of liquid crystal molecules of the display panel changes.

[0013] In one embodiment of the present disclosure, when the voltage control unit adjusts the gray scale of the display panel through the data line, the thin film transistor stores a voltage.

[0014] In one embodiment of the present disclosure, the voltage control unit is configured to input a positively and negatively symmetrical waveform to the data line to change the reflectivity of multiple liquid crystal molecules of the display panel, wherein the voltage in the positive direction of the waveform changes between at least two voltages over time.

[0015] In one embodiment of the present disclosure, the voltage control unit is configured to input a constant frequency signal to the data line to reset the data line.

[0016] In the above-mentioned embodiment of the present disclosure, since the voltage is repeatedly input to the first gate line, the second gate line and the third gate line until the target time, and the voltage waveform is input to the data line within the target time, the reflectivity of the liquid crystal molecules is changed, and the grayscale of the liquid crystal display can be adjusted in a shorter time to achieve the effect of adjusting the brightness of the display. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] When read together with the accompanying drawings, the aspects of the present disclosure can be best understood from the following embodiments. Note that according to standard practice in this industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0018] Figure 1 A flow chart of a method for driving a display panel according to an embodiment of the present disclosure is shown.

[0019] Figure 2 A block diagram of a display panel according to an embodiment of the present disclosure is shown.

[0020] Figure 3 A schematic diagram illustrating how the voltage of each of the first gate line, the second gate line, the third gate line, and the data line varies with time according to an embodiment of the present disclosure.

[0021] Figure 4 and Figure 5 FIG. 4 is a schematic diagram showing how the voltage of a data line varies with time according to another embodiment of the present disclosure.

[0022] Figure 6 FIG. 4 is a graph showing the relationship between the reflectivity of a display panel at different voltages and the scanning time according to an embodiment of the present disclosure.

[0023] Figure 7 FIG. 4 is a schematic diagram showing how the voltage of a data line varies with time according to another embodiment of the present disclosure.

[0024] Figure 8 FIG. 4 is a schematic diagram showing how the voltage of a data line varies with time according to another embodiment of the present disclosure.

[0025] Wherein, the reference numerals are:

[0026] 100: Display panel

[0027] 110: Voltage control unit

[0028] 120: Thin Film Transistor

[0029] G1: first gate line

[0030] G2: Second gate line

[0031] G3: The third gate line

[0032] D: Data cable

[0033] S1, S2, S3, S4, S5: Steps

[0034] t: time interval, time

[0035] t1, t2: scanning time

[0036] V: Voltage

[0037] V1: Voltage DETAILED DESCRIPTION

[0038] The following disclosed embodiments provide many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0039] Spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0040] As used herein, "about", "approximately", or "substantially" includes the stated value and an average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without one standard deviation.

[0041] Figure 1 A flow chart of a method for driving a display panel according to an embodiment of the present disclosure is shown. Figure 1 , a method for driving a display panel comprises the following steps. First, in step S1, a waveform is input to a data line at a target time, and the longer the target time is, the lower the reflectivity of a plurality of liquid crystal molecules in the display panel is. Next, in step S2, a voltage is input to a first gate line at a time interval. Next, in step S3, a voltage is input to a second gate line at a time interval, wherein no voltage is input to the first gate line. Next, in step S4, a voltage is input to a third gate line at a time interval, wherein no voltage is input to the first gate line and the second gate line. Finally, in step S5, steps S2 to S4 are repeated until the target time, wherein the target time is at least forty milliseconds.

[0042] In some embodiments, the driving method of the display panel is not limited to the above steps S1 to S5. For example, in some embodiments, other steps may be further included between steps S1 and S5, other steps may be further included before step S1, and other steps may be further included after step S5. In the following description, at least the above steps will be described.

[0043] Figure 2 A block diagram of a display panel 100 according to an embodiment of the present disclosure is shown. Figure 3 A schematic diagram showing the voltage of each of the first gate line G1, the second gate line G2, the third gate line G3 and the data line D changing with time t according to an embodiment of the present disclosure is shown. Figure 2 and Figure 3 , the display panel 100 includes a voltage control unit 110, a first gate line G1, a second gate line G2, a third gate line G3, a plurality of thin film transistors 120 and a data line D. The voltage control unit 110 is configured to control an input voltage. The first gate line G1 is electrically connected to the voltage control unit 110, and is configured to input a voltage V1 through the voltage control unit 110 at a time interval t. The second gate line G2 is electrically connected to the voltage control unit 110, and is configured to input a voltage V1 through the voltage control unit 110 at a time interval t, wherein when the second gate line G2 inputs the voltage V1, the first gate line G1 has no input voltage V1. The third gate line G3 is electrically connected to the voltage control unit 110, and is configured to input a voltage V1 through the voltage control unit 110 at a time interval t, wherein when the third gate line G3 inputs the voltage V1, the first gate line G1 and the second gate line G2 have no input voltage V1. The data line D is electrically connected to the voltage control unit 110, and is configured to adjust the gray scale of the display panel 100 through the voltage control unit 110. The thin film transistor 120 is electrically connected to the data line D, and is configured to store a voltage of the data line D.

[0044] Specifically, when the voltage V1 is applied to the first gate line G1, the second gate line G2, and the third gate line G3, in order to significantly reduce the time required for the entire process, a voltage V1 is applied to the first gate line G1 at a time interval t, and then the voltage V1 is applied to the second gate line G2 at the same time interval t, and then the voltage V1 is applied to the third gate line G3 at the same time interval t. After the first gate line G1, the second gate line G2, and the third gate line G3 have been applied in sequence, this cycle will continue to repeat until the target time is reached. The target time can be as short as 41.6 milliseconds and as long as 30 seconds. During this process, the thin film transistor 120 in the display panel 100 stores the voltage of the data line.

[0045] Figure 4 and Figure 5FIG. 5 is a schematic diagram showing how the voltage V of the data line D changes with time t according to another embodiment of the present disclosure. Figure 4 and Figure 5 The driving method of the display panel further includes resetting the data line D with a fixed frequency signal S before step S1. The fixed frequency signal S can be, for example, a 60 Hz, 40 volt signal, but the disclosure is not limited thereto. Subsequently, the data line enters a "waiting" state before starting "scanning". "Scanning" includes inputting a set of positive and negative symmetrical waveforms. Figure 4 and Figure 5 The difference is that Figure 4 The scanning time t1 is Figure 5 Even under the same voltage condition, different scanning time will result in different reflectivity results. Figure 6 Describe in detail.

[0046] Figure 6 FIG. 4 is a graph showing the relationship between the reflectivity and scanning time of a display panel at different voltages according to an embodiment of the present disclosure. Figure 6 At the same voltage, the longer the scan time (e.g. Figure 5 The longer the scan time t2), the lower the reflectivity of the display panel will be. Therefore, the scan time of the data line will change the reflectivity of multiple liquid crystal molecules in the display panel. In addition, the greater the input voltage, the more obvious the change of the reflectivity of the display panel with the scan time in the range of 0 milliseconds to 50 milliseconds.

[0047] Reference Figure 3 , Figure 3 The waveform input to the data line D when the first gate line G1, the second gate line G2 and the third gate line G3 start charging is also the aforementioned "scanning", so there is also a control display panel 100 (see Figure 2 )’s grayscale (i.e. reflectivity).

[0048] In the following description, the scanning methods of data lines in different implementations will be described in detail.

[0049] Figure 7 A schematic diagram showing the voltage variation of a data line over time according to another embodiment of the present disclosure is shown. Figure 4 or Figure 5 The difference between the implementation method and the implementation method is that in this implementation method, during the scanning step, the data line no longer has only one positive and one negative voltage and zero bias voltage, but two positive and two negative voltages. Since the page turning time of the display panel is equal to the frame time multiplied by the number of frames, the number of frames is positively correlated with the color depth, as shown in the following formula:

[0050]

[0051] For example Therefore, more voltage groups can be used to reduce the number of frames, thereby shortening the page change time.

[0052] Figure 8 A schematic diagram showing the voltage variation of a data line over time according to another embodiment of the present disclosure is shown. Figure 7 The difference between the embodiment of the present invention and the embodiment of the present invention is that in the scanning step, the data line no longer has only two voltages, positive and negative, and zero bias, but three voltages, positive and negative. As mentioned above, more voltage combinations can significantly shorten the page turning time, thereby improving the performance of the display panel.

[0053] In summary, by repeatedly inputting voltage to the first gate line, the second gate line and the third gate line until the target time, and inputting a voltage waveform to the data line within the target time, the reflectivity of the liquid crystal molecules changes, and the grayscale of the liquid crystal display can be adjusted in a shorter time to achieve the effect of adjusting the brightness of the display.

[0054] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for driving a display panel, characterized in that: Include: (a) inputting a waveform to a data line at a target time, wherein the longer the target time is, the lower the reflectivity of the liquid crystal molecules in the display panel is; (b) inputting a voltage to a first gate line at a time interval; (c) inputting the voltage to a second gate line at the time interval, wherein the voltage is not input to the first gate line; (d) inputting the voltage to a third gate line at the time interval, wherein the voltage is not input to the first gate line and the second gate line; and (e) Repeating steps (b) through (d) until the target time is at least forty milliseconds.

2. The method for driving a display panel according to claim 1, wherein: Also includes: The waveform with positive and negative symmetry is input to a data line at a frequency so that the reflectivity of the liquid crystal molecules of the display panel changes.

3. The method for driving a display panel according to claim 2, wherein: Also includes: The data line is reset with a constant frequency signal before step (a).

4. The method for driving a display panel according to claim 1, wherein: The step (e) includes storing the voltage using a plurality of thin film transistors.

5. The method for driving a display panel according to claim 1, wherein: Also includes: A waveform with positive and negative symmetry is input to a data line at a frequency so that the reflectivity of the liquid crystal molecules of the display panel changes, wherein the voltage in the positive direction of the waveform changes between at least two voltages over time.

6. A display panel, characterized in that: Include: a voltage control unit configured to control an input voltage; a first gate line electrically connected to the voltage control unit and configured to input a voltage through the voltage control unit at a time interval; a second gate line electrically connected to the voltage control unit and configured to input the voltage through the voltage control unit at the time interval, wherein when the second gate line inputs the voltage, the first gate line does not input the voltage; a third gate line electrically connected to the voltage control unit and configured to input the voltage through the voltage control unit at the time interval, wherein when the third gate line inputs the voltage, the first gate line and the second gate line do not input the voltage; a data line electrically connected to the voltage control unit and configured to adjust the gray scale of the display panel through the voltage control unit; as well as A plurality of thin film transistors are electrically connected to the data line and configured to store the voltage of the data line.

7. The display panel according to claim 6, wherein: The voltage control unit is configured to input a waveform with positive and negative symmetry to the data line so as to change the reflectivity of a plurality of liquid crystal molecules of the display panel.

8. The display panel according to claim 6, wherein: When the voltage control unit adjusts the gray scale of the display panel through the data line, the thin film transistors store the voltage.

9. The display panel according to claim 6, wherein: The voltage control unit is configured to input a waveform with positive and negative symmetry to the data line so that the reflectivity of multiple liquid crystal molecules of the display panel changes, and the voltage in the positive direction of the waveform changes between at least two voltages over time.

10. The display panel according to claim 6, wherein: The voltage control unit is configured to input a constant frequency signal to the data line to reset the data line.

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