Micro display chip and visual display method of abnormal information thereof
By performing multi-faceted checksum error reminders on the video data and internal circuits of the micro display chip, the problem of difficult to identify and report internal errors in the existing technology is solved, and higher self-test capabilities and user experience are achieved.
Patent Information
- Application Number
- CN202411732890.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-02-28
- Estimated Expiration
- 2044-11-29
AI Technical Summary
In the prior art, it is difficult for micro-display chips to effectively identify and report errors during display process. The internal circuits of the chip are in the display execution process, and they require the cooperation of the control terminal (such as CPU/MCU), which is limited in versatility.
A method for visual display of abnormal information of micro display chips is proposed. By performing CRC verification on each frame of video data and comparing it with the CRC verification results on the video source side; checking the number of rows, frames, operating temperature and operating status of the display driver circuit. If an error is found, an error reminder will be made in a visual way.
It realizes the identification and error notification reminder of errors occurring during the processing of video data and internal circuit data of micro display chips, and enhances the chip's self-test capability and user experience.
Smart Images

Figure CN119229827B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of micro-display technology, and in particular to a micro-display chip and a method for visually displaying abnormal information thereof. Background Art
[0002] Micro display chips often encounter display abnormalities during the display process. Usually, the cause of display abnormalities is caused by video data transmission errors, that is, during the transmission of video source data through protocols such as MIPI protocol, HDMI protocol, and SPI protocol, video data errors are caused by interference from the electromagnetic environment. In the prior art, the commonly used error reporting mechanism includes: transmitting the CRC check result after transmitting the video data, and the CRC check result is the CRC check result performed on the video data on the video source side. After the micro display chip receives the video data, it also performs a CRC check on the video data again. The CRC check result of the micro display chip is compared with the CRC check result sent by the video source. If the same, it means that the received video data is correct. If different, it means that the received data is wrong, and the corresponding register is set to 1, waiting for the control end (such as CPU / MCU) to read the corresponding register to determine whether the video data transmission is correct. However, this method in the prior art requires the cooperation of the control end (such as CPU / MCU), and its versatility is limited. More importantly, the above method only reports errors for abnormal video data. However, it is impossible to report errors for errors that occur in the internal circuit of the chip during the display execution process.
[0003] It can be seen that a new error information display method suitable for a micro display chip is needed in the prior art. Summary of the invention
[0004] The present invention provides a method for visually displaying abnormal information of a microdisplay chip, which can simultaneously identify error information of video data and errors occurring during data processing of an internal circuit of the microdisplay chip, and can provide error reminders to users in a visual manner.
[0005] Based on the above technical objectives, the present invention provides a method for visually displaying abnormal information of a micro display chip, the method comprising:
[0006] S100, performing a CRC check on each frame of video data, and comparing it with the CRC check result formed on the video source side and transmitted after each frame in the video data ends;
[0007] S101, checking the number of rows and columns of each frame to detect whether the picture resolution of the video data matches the physical resolution of the pixel array displayed by the video data;
[0008] S102, the number of frames of the currently transmitted video data is checked to detect whether the sequence value of the current frame is consistent with the frame sequence value transmitted by the video data;
[0009] S103, detecting the current operating temperature of the micro display chip to determine whether it exceeds a preset threshold;
[0010] S104, verifying the operating state of the display driving circuit of the micro display chip to detect whether the operating state is normal.
[0011] In one embodiment, performing a CRC check on each frame of video data further comprises:
[0012] When the field synchronization signal VS is valid, the CRC check value is initialized and given an initial value;
[0013] When the valid data selection signal DE is valid, the initial value of the CRC check value and the current RGB video data value are bitwise AND-ORed to generate an AND-OR data value;
[0014] Generate the CRC check value of the current RGB video data by calculating the initial value of the CRC check value, the video data value and the AND or data value;
[0015] The CRC check value of the current RGB video data is used as the initial value of the CRC check of the next RGB video data, and the above CRC check step is repeated for the next RGB video data until all RGB video data of the current frame are checked to obtain the CRC check value of the current frame video data.
[0016] In one embodiment, checking the number of rows and columns of each frame further comprises:
[0017] When the rising edge of the field synchronization signal VS appears, the row count value is cleared, and the row synchronization signal HS is detected. The row count value increases by one each time a rising edge of the row synchronization signal HS appears.
[0018] When the row synchronization signal HS has a falling edge, the column count value is cleared, and when the valid data selection signal DE is valid, the column count value increases by one for each falling edge of the clock signal;
[0019] When the frame of video data transmission is completed, the obtained row count value and column count value are compared with the physical resolution value of the video data display pixel array pre-stored in the micro display chip; if they are inconsistent, it means that the video data resolution is inconsistent with the physical resolution of the micro display chip.
[0020] In one embodiment, the checking of the number of frames of the currently transmitted video data further includes: after the micro display chip is powered on, the frame count value is cleared, and each time a rising edge appears on the field synchronization signal VS, the frame count value is increased by one; when the transmission of the frame video data is completed, the frame count value is compared with the sequential count of the frame in the video data, and if the two are inconsistent, it is determined that the frame number check of the frame video data is wrong.
[0021] In one embodiment, the checking of the operating state of the display driving circuit of the micro display chip further comprises:
[0022] Initialize the CRC check value of the driving circuit and assign it an initial value;
[0023] Screening the output signals of the row scan chain circuit and the column scan chain circuit to determine the column scan chain verification input data and the row scan chain verification input data;
[0024] Use the driving circuit CRC check initial value and the column scan chain check input data and the row scan chain check input data to perform CRC check operations respectively to obtain the driving circuit column scan chain CRC check value and the driving circuit row scan chain CRC check value;
[0025] The CRC check value of the column scan chain of the driving circuit and the CRC check value of the row scan chain of the driving circuit are compared with the preset value stored inside the micro display chip. If the two are inconsistent, it is determined that the display driving circuit has an operating state error.
[0026] In one embodiment, the physical pixels of the micro display chip are divided into a video data display pixel array and a verification result display pixel array; the video data display pixel array is used to display video data, and the verification result display pixel array is used to display different verification error results in different display modes.
[0027] In one embodiment, the different display modes refer to display images that are inconsistent in display brightness, grayscale, color or flickering frequency;
[0028] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0030] Figure 1It is a schematic diagram of the micro display chip system architecture of the present invention;
[0031] Figure 2 It is a schematic flow chart of a method for visually displaying abnormal information of a microdisplay chip of the present invention. DETAILED DESCRIPTION
[0032] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.
[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.
[0034] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0036] Example 1
[0037] like Figure 1-2 As shown, the micro display chip of the present invention includes a video data display pixel array 1, a verification result display pixel array 2, a display driving circuit 3, a CRC verification unit 4, a row and column verification unit 5, a frame number verification unit 6, a temperature verification unit 7 and a driving circuit verification unit 8.
[0038] Among them, the video data display pixel array 1 is a physical pixel array used for displaying video data. After the video source side transmits the video data to the display chip according to the corresponding video data transmission protocol, the display driving circuit 3 transmits the video data to the video data display pixel array 1 according to the row and column scanning timing rules to complete the display of the video data.
[0039] The verification result display pixel array 2 is a physical pixel array for displaying various verification results, which can use the physical dummy pixel area of the display chip, and the physical pixel area can be separately set during the physical pixel manufacturing process of the display chip.
[0040] The display driving circuit 3 is a row-column scan chain circuit for driving the video data display pixel array 1 and the verification result display pixel array 2. The row-column scan chain circuit controls the on or off of the light-emitting element on each physical pixel according to the display timing.
[0041] The CRC check unit 4 is used to perform a CRC check on each frame of video data, and compare it with the CRC check result formed on the video source side and transmitted after the end of the frame in the video data. When the two are inconsistent, the display driving circuit 3 is notified to drive the check result display pixel array 2 to prompt the CRC check error of the frame of video data in the first display mode. In this embodiment, the same CRC check method is used on the video source side and in the micro display chip, specifically:
[0042] When the field synchronization signal VS is valid, the CRC check value is initialized and given an initial value, for example, crc_init[15:0]=0x0000;
[0043] When the valid data selection signal DE is valid, the lower 8-bit data crc_init[7:0] of the CRC check value is bitwise AND-ORed with the input 8-bit video data data_i[7:0] to generate 8-bit AND-OR data data_xor[7:0]; and the 16-bit CRC check data value crc_out[15:0] generated for the 8-bit video data data_i[7:0] can be expressed as:
[0044] crc_out
[15] =data_xor[7]⊕data_xor[0],
[0045] crc_out
[14] =data_xor[6]⊕data_xor[1],
[0046] crc_out
[13] =data_xor[5]⊕data_xor[2],
[0047] crc_out
[12] =data_xor[4]⊕data_xor[3],
[0048] crc_out
[11] =data_xor[2],
[0049] crc_out
[10] =data_xor[7]⊕data_xor[6]⊕data_xor[5],
[0050] crc_out[9]=data_xor[6]⊕data_xor[2]⊕data_xor[1],
[0051] crc_out[8]=data_xor[5]⊕data_xor[1]⊕data_xor[0],
[0052] crc_out[7]=crc_init
[15] ⊕data_xor[4]⊕data_xor[0],
[0053] crc_out[6]=crc_init
[14] ⊕data_xor[3],
[0054] crc_out[5]=crc_init
[13] ⊕data_xor[2],
[0055] crc_out[4]=crc_init
[12] ⊕data_xor[1],
[0056] crc_out[3]=crc_init
[11] ⊕data_xor[7]⊕data_xor[3]⊕data_xor[0],
[0057] crc_out[2]=crc_init
[10] ⊕data_xor[6]⊕data_xor[2],
[0058] crc_out[1]=crc_init[9]⊕data_xor[5]⊕data_xor[1],
[0059] crc_out[0]=crc_init[8]⊕data_xor[4]⊕data_xor[0].
[0060] Wherein, “⊕” is an AND or OR operator. The above operation process shows the CRC check value for the current eight-bit video data generated by the video data and the initial CRC check value used in this embodiment. Those skilled in the art should understand that the above check process is only one of the multiple implementation methods of CRC check, and the effects achieved by other CRC check methods will not deviate from the purpose of the present invention.
[0061] The CRC check value generated after the previous group of eight-bit video data completes the CRC check is used as the initial value for the CRC check of the next group of eight-bit video data to continue the CRC check. When the field synchronization signal VS ends, the CRC check result of the last group of eight-bit video data is used as the final CRC check result of the frame of video data, and the CRC check result is compared with the CRC check result that has been completed on the video source side for the frame of video data transmission.
[0062] The row and column verification unit 5 is used to verify the number of rows and columns of each frame to detect whether the picture resolution of the video data matches the physical resolution of the data display pixel array 1. Specifically, when the rising edge of the field synchronization signal VS appears, the row count value of the row and column verification unit 5 is cleared, and the row synchronization signal HS is detected. The row count value increases by one for each rising edge of the row synchronization signal HS. At the same time, when the falling edge of the row synchronization signal HS appears, the column count value is cleared. At the same time, when the valid data selection signal DE is valid, the column count value increases by one for each falling edge of the clock signal. When the next field synchronization signal VS jumps to a high level, it indicates that the transmission of the video data of this frame is completed. The obtained row count value and column count value are compared with the physical resolution value of the video data display pixel array 1 that has been pre-stored in the micro display chip. If the two are inconsistent, the row and column verification unit 5 notifies the display driving circuit 3 to drive the verification result display pixel array 2 to indicate the row and column verification error of the video data of this frame in the second display mode.
[0063] The frame number verification unit 6 is used to verify the frame number of the currently transmitted video data. Specifically: after the micro display chip is powered on, the frame count value is cleared, and each time a rising edge appears on the field synchronization signal VS, the frame count value increases by one. When the transmission of the frame of video data is completed, the frame count value is compared with the sequential count of the frame in the video data. If the two are inconsistent, the frame number verification unit 6 notifies the display drive circuit 3 to drive the verification result display pixel array 2 to prompt the frame number verification error of the frame of video data in the third display mode. In this embodiment, it can be stipulated that the RGB data of the first pixel of the video data after the rising edge of the field synchronization signal VS sends the sequential count of the frame. That is, at this time, the RGB data represents the sequential count of the frame.
[0064] The temperature verification unit 7 is used to detect the current operating temperature of the micro display chip. When the temperature exceeds a preset threshold, the temperature verification unit 7 notifies the display driving circuit 3 to drive the verification result display pixel array 2 to prompt a high temperature alarm message in the fourth display mode.
[0065] The driving circuit verification unit 8 is used to verify the operating status of the display driving circuit 3 of the micro display chip. Specifically: the display driving circuit 3 of the micro display chip includes a row scan chain circuit and a column scan chain circuit; because the row scan chain circuit and the column scan chain circuit display video data, the action of the row scan chain circuit in each frame should be completely consistent, and the action of the column scan chain circuit in each frame should also be completely consistent. Therefore, the output signals of the row scan chain circuit and the column scan chain circuit in each frame can be CRC checked respectively to verify whether the row and column scan chain circuits of the display driving circuit 3 are working properly. Similar to the process of the aforementioned CRC verification unit 4 performing a CRC check on each frame of video data, the CRC check process of the driving circuit verification unit 8 of this example on the display driving circuit 3 includes:
[0066] Initialize the CRC check value of the driving circuit and assign it an initial value to generate crc_init[15:0];
[0067] The output signals of the row scan chain circuit and the column scan chain circuit are screened, and 8 fixed outputs are selected as the column scan chain check input data data_i_x[7:0] and the row scan chain check input data data_i_y[7:0] of the driving circuit CRC check; taking the display resolution of 640*480 as an example, if the CRC check is performed on the scan chain output of each column, the input data of the CRC check will be as many as 640. In order to reduce the computational burden of the CRC check operation, in this embodiment, 8 data are selected from the 640 data to form the column scan chain check input data data_i_x[7:0], such as selecting the 1st, 81st, 161st, 241st, 321st, 401st, 481st, and 561st data to form the column scan chain check input data data_i_x[7:0]. Similarly, 8 data need to be selected from the 480 row scan chain outputs to form the row scan chain check input data data_i_y[7:0];
[0068] The CRC check initial value of the driving circuit is used to perform CRC check operations on the column scan chain check input data data_i_x[7:0] and the row scan chain check input data data_i_y[7:0] to obtain the driving circuit column scan chain CRC check value and the driving circuit row scan chain CRC check value. The specific calculation process can refer to the aforementioned calculation process of performing CRC check on video data.
[0069] The CRC check value of the drive circuit column scan chain and the CRC check value of the drive circuit row scan chain are compared with the preset value stored in the micro display chip. If the two are inconsistent, the drive circuit check unit 8 notifies the display drive circuit 3 to drive the check result display pixel array 2 in the fifth display mode to prompt that the display drive circuit has an operating state error. The preset value stored in the micro display chip can be obtained during the simulation operation in the micro display chip design stage.
[0070] In this embodiment, the first to fifth display modes refer to display states in which display brightness, grayscale, color, and flicker frequency are inconsistent. The specific display modes of the first to fifth display modes can be selected by those skilled in the art according to actual engineering needs.
[0071] like Figure 2 As shown, the visual display method of abnormal information of a micro display chip of the present invention comprises:
[0072] S100, performing a CRC check on each frame of video data, and comparing it with the CRC check result formed on the video source side and transmitted after the end of the frame in the video data;
[0073] S101, checking the number of rows and columns of each frame to detect whether the picture resolution of the video data matches the physical resolution of the pixel array displayed by the video data;
[0074] S102, the number of frames of the currently transmitted video data is checked to detect whether the sequence value of the current frame is consistent with the frame sequence value transmitted by the video data;
[0075] S103, detecting the current operating temperature of the micro display chip to determine whether it exceeds a preset threshold;
[0076] S104, verifying the operating state of the display driving circuit of the micro display chip to detect whether the operating state is normal.
[0077] The present invention may be a system, method and / or computer program product at any possible level of integrated technical detail. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to perform various aspects of the present invention.
[0078] A computer-readable storage medium may be a tangible device that can retain and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the above. A computer-readable storage medium, as used herein, should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.
[0079] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.
[0080] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages and process programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer as an independent software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or a connection to an external computer may be made (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuits, thereby performing various aspects of the present invention.
[0081] Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present invention. It is understood that each block of the flowchart illustration and / or block diagram, and combinations of blocks in the flowchart illustration and / or block diagram, can be implemented by computer-readable program instructions.
[0082] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing device to produce a machine so that the instructions executed by the processor of the computer or other programmable data processing device create instructions for implementing the flowcharts and / or block diagrams. Figure 1 These computer-readable program instructions may also be stored in a computer-readable storage medium capable of booting a computer, a programmable data processing device and / or other device that operates in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes a manufactured product that includes instructions for implementing aspects of the functions / actions specified in the flowchart and / or block diagram blocks.
[0083] Computer readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device to cause a series of operating steps to be performed on the computer, other programmable device or other device for producing a computer-implemented process, so that the instructions executed on the computer, other programmable device or other device implement the functions / actions specified in the flowchart and / or block diagram blocks.
[0084] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some optional implementations, the functions indicated in the block may occur outside the order indicated in the figure. For example, in fact, two blocks shown in succession can be completed as a step, and depending on the functions involved, they can be executed concurrently, substantially concurrently, in a partially or fully time-overlapping manner, or sometimes these blocks can be executed in reverse order. It will also be noted that each block of the block diagram and / or flowchart illustration, as well as the combination of blocks in the block diagram and / or flowchart illustration, can be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.
[0085] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, apparatuses (devices) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0086] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0087] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
Claims
1. A method for visually displaying abnormal information of a micro display chip, characterized in that: The method comprises: S100, performing a CRC check on each frame of video data, and comparing it with the CRC check result formed on the video source side and transmitted after each frame in the video data ends; S101, checking the number of rows and columns of each frame to detect whether the picture resolution of the video data matches the physical resolution of the pixel array displayed by the video data; S102, the number of frames of the currently transmitted video data is checked to detect whether the sequence value of the current frame is consistent with the frame sequence value transmitted by the video data; S103, detecting the current operating temperature of the micro display chip to determine whether it exceeds a preset threshold; S104, verifying the operating state of the display driving circuit of the micro display chip to detect whether its operating state is normal; Verifying the operating state of the display driving circuit of the micro display chip further includes: Initialize the CRC check value of the driving circuit and assign it an initial value; Screening the output signals of the row scan chain circuit and the column scan chain circuit to determine the column scan chain verification input data and the row scan chain verification input data; Use the driving circuit CRC check initial value and the column scan chain check input data and the row scan chain check input data to perform CRC check operations respectively to obtain the driving circuit column scan chain CRC check value and the driving circuit row scan chain CRC check value; The CRC check value of the column scan chain of the driving circuit and the CRC check value of the row scan chain of the driving circuit are compared with the predetermined value stored inside the micro display chip. If the two are inconsistent, it is determined that the display driving circuit has an operating state error.
2. The method according to claim 1, characterized in that The CRC check for each frame of video data further comprises: When the field synchronization signal VS is valid, the CRC check value is initialized and given an initial value; When the valid data selection signal DE is valid, the initial value of the CRC check value and the current RGB video data value are bitwise AND-ORed to generate an AND-OR data value; Generate the CRC check value of the current RGB video data by calculating the initial value of the CRC check value, the video data value and the AND or data value; The CRC check value of the current RGB video data is used as the initial value of the CRC check of the next RGB video data. The above CRC check steps are repeated for the next RGB video data until all RGB video data of the current frame are checked to obtain the CRC check value of the current frame video data.
3. The method according to claim 1, characterized in that The checking of the number of rows and columns of each frame further comprises: When the rising edge of the field synchronization signal VS appears, the row count value is cleared, and the row synchronization signal HS is detected. The row count value increases by one each time a rising edge of the row synchronization signal HS appears. When the row synchronization signal HS has a falling edge, the column count value is cleared, and when the valid data selection signal DE is valid, the column count value increases by one for each falling edge of the clock signal; When the frame of video data transmission is completed, the obtained row count value and column count value are compared with the physical resolution value of the video data display pixel array pre-stored in the micro display chip; if they are inconsistent, it means that the video data resolution is inconsistent with the physical resolution of the micro display chip.
4. The method according to claim 1, characterized in that: Verifying the number of frames of the currently transmitted video data further includes: after the micro display chip is powered on, the frame count value is cleared, and each time a rising edge appears on the field synchronization signal VS, the frame count value is increased by one; when the transmission of the frame video data is completed, the frame count value is compared with the sequential count of the frame in the video data, and if the two are inconsistent, it is determined that the frame number verification of the frame video data is wrong.
5. The method according to claim 1, characterized in that The physical pixels of the micro display chip are divided into a video data display pixel array and a verification result display pixel array; the video data display pixel array is used to display video data, and the verification result display pixel array is used to display different verification error results in different display modes.
6. The method according to claim 5, characterized in that The different display modes refer to display images that are inconsistent in display brightness, grayscale, color or flickering frequency.
7. A micro display chip, characterized in that: It includes: Video A data display pixel array, a verification result display pixel array, a display driving circuit, a CRC verification unit, a row and column verification unit, a frame number verification unit, a temperature verification unit and a driving circuit verification unit; and the micro display chip executes the visual display method of abnormal information described in one of the preceding claims 1-6 to verify the video data and the chip operating status.
8. A computer-readable storage medium having computer instructions stored thereon, wherein: When the computer instruction is executed by a processor, the steps of the method for visually displaying abnormal information according to any one of claims 1 to 6 are implemented.
9. A display system, wherein the display system uses the micro display chip according to claim 7 to display video data.
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