NVMe write IO initiating circuit of NVMe controller

Abstract

The embodiment of the invention provides an NVMe write IO initiating circuit of an NVMe controller, and relates to the technical field of storage. The write initiation circuit includes a DMA command generation circuit coupled with the DMA transfer circuit, generating, in response to receiving addressing information, a DMA command indicative of moving data from the host memory to the storage device cache based on the addressing information, and providing the DMA command to the DMA transfer circuit; and the storage command generation circuit is coupled with the DMA transmission circuit and the storage command processing unit, responds to a first message which is sent by the DMA transmission circuit and indicates that the DMA command is processed completely, generates a storage command which indicates that the data is migrated from the storage device to the flash memory of the storage device, and provides the storage command to the storage command processing unit. The write-in initiating circuit is a hardware circuit independent of the CPU and unloads a task for generating the DMA command from the CPU, so that the burden of the CPU is reduced.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to an NVMe write IO initiation circuit of an NVMe controller. Background Art

[0002] Figure 1A The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 (hereinafter, the solid-state storage device is referred to as the storage device for short) includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] The above-mentioned NVM chip 105 includes NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc., which are common storage media.

[0004] The above-mentioned interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control part 104 issues a command to the NVM chip 105 in a manner complying with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash package that share a CE (Chip Enable) signal. A NAND flash package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash chip can execute commands and report status independently of each other.

[0008] Data is usually stored and read on a storage medium in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page on a storage medium (called a physical page) has a fixed size, such as 17664 bytes. A physical page can also have other sizes.

[0009] In the storage device 102, FTL (Flash Translation Layer) is used to maintain the mapping information from the logical address (LBA) to the physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address. The table structure that stores the mapping information from the logical address to the physical address is called the FTL table. The FTL table is an important metadata in the storage device. The data items of the FTL table record the address mapping relationship in the storage device in units of data units.

[0010] The host accesses the storage device with IO commands that follow the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, and erase commands) that follow the interface protocol of the NVM chip based on the media interface commands. The control component also tracks that all media interface commands generated from an IO command have been executed and indicates the processing results of the IO command to the host.

[0011] See also Figure 1B The control component includes a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a medium interface controller 1044 and a storage medium management unit 1045. The host interface 1041 obtains the IO command provided by the host. The host command processing unit 1042 generates a storage command according to the IO command and provides it to the storage command processing unit 1043. The storage command can access the storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. The physical page records one or more data frames. For example, the size of the physical page is 17664 bytes, and the size of the data frame is 4KB, then one physical page can store 4 data frames.

[0012] The storage medium management unit 1045 maintains the conversion of the logical address to the physical address for each storage command. For example, the storage medium management unit 1045 includes an FTL table (the FTL will be explained below). For a read command, the storage medium management unit 1045 outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For a write command, the storage medium management unit 1045 allocates an available physical address for it and records the mapping relationship between the logical address (LBA) accessed by it and the allocated physical address. The storage medium management unit 1045 also maintains functions required for managing the NVM chip such as garbage collection and wear leveling.

[0013] The storage command processing unit 1043 operates the medium interface controller 1044 to issue a storage medium access command to the NVM chip 105 according to the physical address provided by the storage medium management unit 1045 .

[0014] For the purpose of clarity, the command sent by the host to the storage device 102 is called an IO command (including, for example, an NVMe read command and an NVMe write command), the command sent by the host command processing unit 1042 to the storage command processing unit 1043 is called a storage command, the command sent by the storage command processing unit 1043 to the medium interface controller 1044 is called a medium interface command, and the command sent by the medium interface controller 1044 to the NVM chip 105 is called a storage medium access command. The storage medium access command complies with the interface protocol of the NVM chip.

[0015] In the NVMe protocol, after receiving the NVMe write command, the solid-state storage device 102 obtains data from the host's memory through the host interface 1041, and then writes the data into the flash memory. For the NVMe read command, when the data is read from the flash memory, the solid-state storage device 102 moves the data to the host memory through the host interface 1041.

[0016] like Figure 1C The basic structure of a host command processing unit 1042 of a related technology is shown. Figure 1C The host command processing unit shown in FIG. Figure 1C As shown, the host command processing unit 1042 includes a shared memory (for example, located inside the control component, and different from the storage device memory DRAM and NVM chip), a cache unit, an SGL / PRP unit, and a write control circuit. Among them, the write control circuit includes a write initiation circuit and a DMA transmission circuit, and the write initiation circuit and the DMA transmission circuit cooperate with each other to realize the process of data movement. The process of the host command processing unit 1042 processing IO commands such as NVMe write commands includes:

[0017] In response to receiving an NVMe write command, the SGL / PRP unit obtains the SGL / PRP corresponding to the write command, and stores the SGL / PRP in the cache unit; generates one or more DMA command groups according to the SGL / PRP, each DMA command group includes one or more DMA commands; and stores the DMA command group in the shared memory. After the DMA command group is generated, the SGL / PRP unit notifies the write initiation circuit to pass the DMA command group index used to indicate the location of the DMA command group in the shared memory, such as the DMA command group pointer, to the write initiation circuit. The write initiation circuit receives the above-mentioned DMA command group index, passes the upper DMA command group index to the DMA transmission circuit, and the DMA transmission circuit obtains the DMA command from the shared memory according to the DMA command group index. The DMA executes the DMA command to move data from the host memory to the storage device memory. When the data movement indicated by a DMA command ends, and when the data movement indicated by a DMA command group ends, the DMA transmission circuit generates a notification of the end of the data movement, and passes the notification of the end of the data movement to the write initiation circuit.

[0018] Among them, in the NVMe protocol, NVMe has two commands, one is the Admin command, which is used by the host to manage and control the storage device, and the other is the IO command, including the NVMe write command and the NVMe read command, which is used to control the data transmission between the host and the storage device. There are fields related to SGL or PRP in the IO command, which indicate the location of the data in the host memory (for write commands) or the host memory address to be written (for read commands). The PRP field or SGL field in the IO command can be an SGL or PRP entry pointing to the host memory address space to be accessed, or a pointer to the SGL or PRP linked list, or even a pointer to a pointer. If the IO command carries an SGL or PRP, the storage device can directly obtain the SGL or PRP in response to receiving the IO command. If the IO command carries an SGL or PRP pointer, in response to receiving the IO command, the storage device accesses the host according to the above-mentioned SGL or PRP pointer and obtains the SGL or PRP from the host.

[0019] PRP (Physical Region Page) and SGL (Scatter / Gather List) are two ways to describe the data to be transmitted between the host and the storage device. In the PRP method, a number of linked PRP entries are used, each of which includes a 64-bit memory physical address to describe a physical page (Page) of the host memory. SGL is a linked list, consisting of one or more SGL segments, each of which consists of one or more SGL descriptors; each SGL descriptor describes the address and length of the data cache of the host memory, that is, each SGL descriptor corresponds to a host memory address space; each SGL descriptor has, for example, a fixed size (for example, 16 bytes).

[0020] DMA (Direct Memory Access) commands indicate the mapping relationship between the host memory address space and the storage device memory address space (e.g., DRAM address), and are used to control the DMA transfer circuit to perform data transfer. The host memory address indicated by the DMA command is determined based on the address space indicated by the SGL or PRP, and the storage device memory address is allocated by the storage device. Each DMA command is used to perform a data movement operation between the host and the storage device. Summary of the invention

[0021] In high-performance storage devices, the control unit may process hundreds or even thousands of IO commands per second, and each IO command needs to initiate dozens of DMA transfers. Figure 1C ) requires extremely high processing power to match the performance of the storage device and can easily become a performance bottleneck. If the CPU executes software to implement the function of the write initiation circuit, its performance is limited by the CPU's processing speed. At this time, the CPU's processing power becomes the bottleneck of the performance of processing IO commands. However, the cost of improving CPU performance is high. It is hoped that a dedicated hardware circuit can be used to complete related tasks, thereby improving the processing performance of IO commands. At the same time, related tasks are also unloaded from the CPU, reducing the burden on the CPU and making it easier for the CPU to process other tasks.

[0022] In view of this, an embodiment of the present application provides a write initiation circuit and a storage device. The write initiation circuit is a hardware circuit independent of the CPU. A DMA command for instructing the movement of data from a host memory to a storage device memory is generated through the hardware circuit. In response to completion of DMA command processing, a storage command for instructing the movement of data from the storage device memory to the storage device flash memory is generated. The task of generating DMA commands and storage commands is unloaded from the CPU, thereby improving the processing efficiency of IO commands, reducing the burden on the CPU, and facilitating the CPU to process other tasks.

[0023] According to a first aspect of the present application, there is provided a write initiation circuit, comprising: a DMA command generation circuit and a storage command generation circuit;

[0024] The DMA command generation circuit is coupled to the DMA transmission circuit. In response to receiving the addressing information, the DMA command generation circuit generates a DMA command based on the addressing information and provides the DMA command to the DMA transmission circuit. The DMA command is used to instruct the DMA transmission circuit to perform data movement from the host memory to the storage device cache according to the DMA command.

[0025] The storage command generation circuit is coupled to the DMA transmission circuit. In response to receiving a first message sent by the DMA transmission circuit, the storage command generation circuit generates a storage command and provides the storage command to the storage command processing unit; wherein the first message is used to indicate that the DMA command processing performed by the DMA transmission circuit is completed.

[0026] In an optional embodiment of the present application, the DMA command generation circuit allocates a cache of the storage device for the data to be moved indicated by the DMA command.

[0027] In an optional embodiment of the present application, the operation of the DMA command generation circuit and the operation of the storage command generation circuit are executed in parallel and are independent of each other.

[0028] In an optional embodiment of the present application, the DMA command generation circuit is also coupled to a cache unit, which is used to cache the addressing information, and the addressing information includes one or more of the following: a PRP entry, an SGL entry, and a host memory address determined according to the PRP index or the SGL index.

[0029] In an optional embodiment of the present application, the DMA command generation circuit is also coupled to the storage command generation circuit, and the DMA command generation circuit provides the DMA command to the storage command generation circuit.

[0030] In an optional embodiment of the present application, the write initiation circuit further includes a PRP entry or SGL entry acquisition circuit, and the PRP entry or SGL entry acquisition circuit is coupled to the DMA command generation circuit;

[0031] In response to receiving the addressing information, the PRP entry or SGL entry acquisition circuit acquires the PRP entry or SGL entry based on the addressing information and provides the PRP entry or SGL entry to the DMA command generation circuit.

[0032] In an optional embodiment of the present application, the write initiation circuit includes one or more circuit branches and a DMA command buffer arranged in parallel, and each of the circuit branches includes a DMA command generation circuit and a flow control circuit;

[0033] The flow control circuit of each circuit branch is coupled to the DMA command generation circuit of the circuit branch where it is located, and is also coupled to the DMA command cache, and is used to control whether to provide the DMA command generated by the DMA command generation circuit of the circuit branch where it is located to the DMA command cache;

[0034] The DMA command buffer is also coupled to the DMA transmission circuit, and is used to buffer received DMA commands and provide the buffered DMA commands to the DMA transmission circuit.

[0035] In an optional embodiment of the present application, the flow control circuit of each of the circuit branches is also coupled to the quota manager, and the flow control circuit of each of the circuit branches controls whether to provide the DMA command generated by the DMA command generation circuit of the circuit branch to which it is located to the DMA command cache according to the flow control policy configured by the quota manager.

[0036] In an optional embodiment of the present application, each of the circuit branches controls whether to provide the DMA command generated by the DMA command generation circuit of the circuit branch to which it belongs to to the DMA command cache according to the configured priority.

[0037] In an optional embodiment of the present application, the multiple circuit branches arranged in parallel operate independently of each other.

[0038] In an optional embodiment of the present application, if there are multiple NVMe write commands being processed at the same time, each of the NVMe write commands indicates multiple addressing information, and for each circuit branch, the circuit branch receives multiple addressing information indicated by the same NVMe write command.

[0039] In an optional embodiment of the present application, if the namespaces indicated by the multiple processed NVMe write commands are the same, the addressing information indicated by the multiple processed NVMe write commands is received by the same circuit branch; if the namespaces indicated by the multiple processed NVMe write commands are different, the addressing information indicated by the multiple processed NVMe write commands is received by different circuit branches.

[0040] In an optional embodiment of the present application, the circuit branch that receives the addressing information indicated by the multiple processed NVMe write commands is determined according to the namespace indicated by the multiple processed NVMe write commands.

[0041] In an optional embodiment of the present application, the storage command generation circuit responds to the first message, identifies the NVMe write command to which the DMA command corresponding to the first message belongs, and generates a second message in response to identifying that all DMA commands corresponding to the NVMe write command have been processed, wherein the second message indicates that all DMA commands corresponding to the NVMe write command have been processed.

[0042] In an optional embodiment of the present application, the write initiation circuit further includes a completion message generation circuit, and the completion message generation circuit is coupled to the storage command generation circuit;

[0043] The completion message generation circuit provides the second message to the host in response to receiving the second message generated by the storage command generation circuit.

[0044] In an optional embodiment of the present application, the write initiation circuit further includes an error handling circuit, and the error handling circuit is coupled to the storage command generation circuit;

[0045] The storage command generation circuit generates a third message in response to identifying the DMA command processing error indicated by the first message, and provides the third message to the error processing circuit; or, the storage command generation circuit identifies the NVMe write command processing error indicated by the second message, generates a fourth message, and provides the fourth message to the error processing circuit; wherein the third message is used to indicate the DMA command processing error indicated by the first message, and the fourth message is used to indicate the NVMe write command processing error indicated by the second message;

[0046] The error processing circuit receives the third message or the fourth message, and processes the third message or the fourth message.

[0047] In an optional embodiment of the present application, the error handling circuit includes multiple error handling circuits, and the multiple error handling circuits correspond one-to-one to multiple circuit branches; the multiple error handling circuits respectively receive a third message indicating an NVMe write command processing error processed by the corresponding circuit branch.

[0048] In an optional embodiment of the present application, each of the circuit branches further includes an index cache, which is coupled to a DMA command generation circuit of the circuit branch in which it is located; the index cache caches the received addressing information in response to receiving the addressing information.

[0049] According to a second aspect of an embodiment of the present application, a storage device is provided, comprising the write initiation circuit described in any embodiment of the first aspect of the present application, and the data indicated by an NVMe write command is moved from a host to the storage device through the write initiation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0051] Figure 1A A block diagram of a solid-state storage device is shown;

[0052] Figure 1B A block diagram of a control component in a solid-state storage device is shown;

[0053] Figure 1C A block diagram of a host command processing unit in a control component in the related art is shown;

[0054] Figure 2 Schematic diagram showing PRP indicated by NVMe write command

[0055] Figure 3 A schematic diagram showing the structure of a write initiation circuit according to an embodiment of the present application is shown;

[0056] Figure 4 A schematic diagram showing the structure of a write initiation circuit according to another embodiment of the present application is shown;

[0057] Figure 5A A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown;

[0058] Figure 5B A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown;

[0059] Figure 6 A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown;

[0060] Figure 7 A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown;

[0061] Figure 8 A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown;

[0062] Fig. 9 A schematic diagram showing a write initiation circuit in an embodiment of the present application processing a plurality of NVMe write commands received continuously;

[0063] Fig.10 A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0064] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0065] For ease of understanding, PRP and SGL are briefly described below. PRP (Physical Region Page) and SGL (Scatter / Gather List) are two ways to describe the data to be transferred between the host and the storage device. In addition to indicating the length of the data to be written, the NVMe write command sent by the host to the storage device also needs to indicate the location where the data to be written is stored in the host memory, where the location where the data to be written is stored in the host memory can be indicated by PRP or SGL. The NVMe write command indicates one or more RPR entries or SGL descriptors. A PRP entry indicates a fixed-size storage space in the host memory (such as Figure 2 The storage blocks shown in FIG. 1 ), that is, the storage space sizes indicated by different PRP entries are the same, such as 4KB, 16KB, etc. Figure 2 As shown, the NVMe write command indicates three PRP entries (PRP0, PRP1, and PRP2), where PRP0 indicates storage block A in the host memory, PRP1 indicates storage block B in the host memory, and PRP2 indicates storage block C in the host memory, where the size of storage block A, storage block B, and storage block C is 4KB; optionally, the size of storage block A, storage block B, and storage block C is not limited to 4KB. The SGL descriptor indicates a storage space of indefinite size in the host memory, for example, the NVMe write command indicates SGL descriptors (SGL1, SGL2, and SGL3), where SGL1 indicates a storage space of 4KB, SGL2 indicates a storage space of 2KB, and SGL3 indicates a storage space of 3KB.

[0066] Whether it is a PRP entry or an SGL descriptor, the essence is to describe one or more address spaces in the host memory, and the location of these address spaces in the host memory is arbitrary. The host carries a PRP or SGL related field in the NVMe write command, which can be an SGL or PRP itself, pointing to the host memory address space to be accessed, or a pointer, pointing to an SGL or PRP linked list, or even a pointer to a pointer. Regardless of the form, according to the NVMe write command, the storage device can always obtain the corresponding SGL or PRP. Based on this, in an optional embodiment, if the NVMe write command indicates PRP (such as the PRP entry itself or the PRP pointer), the write initiation circuit receives a PRP index, and a DMA command will be generated based on the PRP index; if the NVMe write command indicates SGL (such as the SGL descriptor itself or the SGL pointer), the write initiation circuit receives an SGL index, and a DMA command will be generated based on the SGL index. It can be understood that the embodiments of the present application are not limited to describing the transmission of data between the host and the storage device in two ways, PRP or SGL, and can also describe the data to be transmitted through other similar functions.

[0067] For the purpose of clarity, in this application, addressing information is used to represent information for addressing host memory obtained according to an NVMe write command. The addressing information can be, for example, a PRP index, a PRP entry, an SGL index, an SGL descriptor, or the host memory address itself. Wherein the PRP entry or SGL descriptor carries the host memory address, and the SGL index or PRP index represents the address of the SGL descriptor or PRP entry obtained by, for example, an SGL / PRP unit and stored in a cache unit.

[0068] The following is an example of a host sending an NVMe write command to a storage device, and the NVMe write command uses PRP to describe the host memory address to illustrate the structure of the write initiation circuit of the embodiment of the present application. It can be understood that in the embodiment of the present invention, PRP entries, DMA commands, and storage commands can correspond one to one, one to many, many to one, or many to many. For the purpose of simplicity, in the embodiment according to the present application, the PRP entries, DMA commands, and storage commands are described in a one-to-one correspondence manner.

[0069] Figure 3 A structural schematic diagram of a write initiation circuit according to an embodiment of the present application is shown.

[0070] like Figure 3 As shown, the write initiation circuit includes a DMA command generation circuit and a storage command generation circuit. As an example, the SGL / PRP unit (also see Figure 1C )After obtaining, for example, a PRP entry from an NVMe write command, a PRP index indicating the PRP entry is provided to the write initiation circuit.

[0071] The DMA command generation circuit is coupled to the DMA transfer circuit, which responds to receiving the PRP index (such as Figure 3 In process (1-1), a DMA command is generated based on the PRP index, and the generated DMA command is provided to the DMA transmission circuit (such as Figure 3 in process (1-2)).

[0072] The PRP index has various forms. For example, the PRP index carries the host memory address indicated in the PRP entry, or the PRP index carries a pointer to a cache unit, in which the PRP entry is stored. The PRP entry is obtained from the cache unit through the PRP index to obtain the host memory address. Optionally, the PRP index corresponds to the PRP entry one-to-one. Obtaining the PRP entry and the PRP index from the NVMe write command belongs to the prior art and will not be repeated here.

[0073] DMA commands are commands used to control DMA to perform data transfer, which indicates the mapping relationship between the host memory address space and the storage device cache address space (such as DRAM address). The host memory address indicated by the DMA command is determined based on the address space indicated by the SGL or PRP, and the storage device cache address is allocated by the storage device. For NVMe write commands, the host memory address is the source address and the storage device cache address is the destination address. Each DMA command is used to perform a data movement operation between the host and the storage device.

[0074] Generating a DMA command requires a host memory address as a source address and a storage device cache address as a destination address. The host memory address is obtained according to the received PRP index, and the storage device cache address is obtained by allocating storage space from the storage device cache. Optionally, the DMA command generation circuit allocates a storage device cache for the DMA command, for example, the DMA command generation circuit obtains an available storage device cache address through a memory allocator (not shown).

[0075] The DMA transmission circuit responds to the received DMA command, moves data between the host memory and the storage device cache according to the DMA command, and after the data move is completed, provides a message indicating that the DMA command processing is completed to the storage command generation circuit (such as Figure 3 process (2)).

[0076] The storage command generation circuit is coupled to the DMA transmission circuit and the storage command processing unit. In response to receiving a DMA command processing completion message sent by the DMA transmission circuit, the storage command is generated and sent to the storage command processing unit (such as Figure 3As an example, the storage command causes the storage command processing unit to move the data in the storage device cache to the storage device flash memory (such as NVM chip) according to the storage command. The storage command processing unit and the storage command are both prior art and will not be described in detail here.

[0077] The DMA command generation circuit and the storage command generation circuit work in parallel and independently of each other. For example, when the DMA command generation circuit processes PRP_A, the storage command can simultaneously process the first message_A, PRP_A corresponds to the first DMA command, and the first message_A corresponds to the second DMA command, that is, PRP_A and the first message_A correspond to different DMA commands; and the first DMA command and the second DMA command may belong to the same or different NVMe write commands.

[0078] Optionally, the DMA command generation circuit is also coupled to a cache unit. The cache unit stores the PRP entry or the host memory address extracted from the PRP entry. Accordingly, the PRP index carries a pointer for the cache unit. In response to receiving the PRP index, the DMA command generation circuit also obtains the host memory address corresponding to the PRP index from the cache unit.

[0079] Still optionally, after generating the DMA command, the DMA generation circuit also provides the DMA command or an index associated with the DMA command to the storage command generation circuit (eg, Figure 3 Process (1-3)). The storage command generation circuit is aware of the message indicating that the DMA command processing is completed that it should receive from the DMA transmission circuit. After receiving the message indicating that the DMA command processing is completed from the DMA module, the storage command generation circuit searches for the DMA command corresponding to the message to determine whether the DMA command is processed correctly. Optionally, the storage command generation circuit also obtains the number of DMA commands corresponding to the NVMe write command associated with the DMA command, thereby identifying whether all DMA commands of the NVMe write command have been processed.

[0080] Figure 4 A structural schematic diagram of another write initiation circuit according to an embodiment of the present application is shown.

[0081] like Figure 4 As shown, the write initiation circuit includes a PRP acquisition circuit, a DMA command generation circuit and a storage command generation circuit.

[0082] The PRP acquisition circuit responds to receiving the PRP index (such as Figure 4 In process (1-1)), a PRP is obtained based on the PRP index, and the obtained PRP is provided to the DMA command generation circuit (such as Figure 4The DMA command generation circuit receives the PRP provided by the PRP acquisition circuit, generates a DMA command, and provides the generated DMA command to the DMA transmission circuit (such as Figure 4 The DMA transmission circuit and the storage command generation circuit can refer to the embodiment shown in FIG1 , and the present application will not repeat them here.

[0083] Optionally, the PRP acquisition circuit is coupled to a cache unit, in which the PRP entry or the host memory address extracted from the PRP entry is stored. Accordingly, the PRP index carries a pointer for indicating the cache unit. In response to receiving the PRP index, the PRP acquisition circuit acquires the PRP entry or the host memory address corresponding to the PRP index from the cache unit.

[0084] Figure 5A A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown.

[0085] like Figure 5A As shown, the write initiation circuit includes one or more circuit branches, a DMA command cache, and a storage command generation circuit arranged in parallel. Each circuit branch has the same circuit structure, and each circuit branch includes a DMA command generation circuit and a flow control circuit. Each circuit branch works independently of each other. If there are multiple NVMe write commands being processed at the same time, each NVMe write command indicates multiple PRP indexes, and each circuit branch can process the PRP indexes corresponding to one or more NVMe write commands. All PRP indexes corresponding to each NVMe write command will be sent to the same circuit branch, and multiple PRP indexes belonging to different NVMe write commands may provide the different circuit branches. If the namespaces (Name Space, NS for short) indicated by multiple processed NVMe write commands are the same, one circuit branch receives the PRP indexes corresponding to the multiple processed NVMe write commands. If the namespaces indicated by the multiple processed NVMe write commands are different, different circuit branches receive the PRP indexes corresponding to the multiple processed NVMe write commands. Optionally, the circuit branch for processing the NVMe write command can be determined according to the namespace indicated by the NVMe write command. Among them, Name Space (NS) is a certain amount of NVM (Non-Volatile Memory) collection, which can be formatted into many logical blocks. An NVMe control component can support multiple NSs identified by different namespace IDs (NSIDs). As an example, in Figure 5A The write initiation circuit includes four circuit branches: circuit branch 1, circuit branch 2, circuit branch 3, and circuit branch 4. It can be understood that the write initiation circuit may include other numbers of circuit branches.

[0086] like Figure 5A As shown, the DMA command generation circuit is coupled to the flow control circuit, which responds to receiving the PRP index (such as Figure 5A In process (1-1)), a DMA command is generated based on the PRP index, and the generated DMA command is provided to the flow control circuit (such as Figure 5A process (1-4)).

[0087] The flow control circuit of each circuit branch is coupled to the DMA command cache to control whether the DMA command generated by the DMA command generation circuit of the circuit branch is provided to the DMA command cache (such as Figure 5A process (1-5)).

[0088] According to an embodiment of the present application, by providing multiple circuit branches, the DMA command generation circuit of each circuit branch generates DMA commands in parallel according to the PRP index, thereby improving the processing capacity of the DMA command generation process. And each circuit branch works independently, and the workload of one circuit branch will not affect the performance of other circuit branches. Furthermore, each circuit branch has its own flow control circuit, so that flow control can be implemented on each circuit branch separately. For example, the operation of one or more circuit branches can be suspended, while other circuit branches are allowed to work. The flow control circuits each have, for example, a configurable bandwidth, thereby limiting the number of DMA commands provided by each flow control circuit to the DMA command cache per unit time. Each flow control circuit works independently, so that the flow control strategy of one flow control circuit will not affect the operation of other flow control circuits.

[0089] Optionally, the flow control circuit implements flow control according to the configured priority. For example, the flow control circuits are arranged in order from high to low priority: circuit branch 1, circuit branch 2, circuit branch 3, and circuit branch 4. When the flow control circuits in circuit branch 1, circuit branch 2, and circuit branch 3 all receive DMA commands, the flow control circuit in circuit branch 1 will control the priority of sending the received DMA commands to the DMA command cache, thereby realizing priority processing of the NVMe write commands processed by circuit branch 1. When the flow control circuit in circuit branch 1 sends one or more DMA commands to the DMA command cache, the flow control circuits in circuit branch 2 and circuit branch 3 can wait (for example, suspend sending DMA commands to the DMA command cache).

[0090] The DMA command buffer is coupled to the DMA transmission circuit. The DMA command buffer is used to buffer the DMA commands received from each circuit branch and send the received DMA commands to the DMA transmission circuit (such as Figure 5AIn the process (1-6)). The DMA command buffer may receive more than one DMA command from multiple circuit branches. It takes time for the DMA transmission circuit to process the DMA command. When the DMA command buffer receives multiple DMA commands, the unprocessed DMA commands are cached.

[0091] DMA transfer circuit and storage command generation circuit (such as Figure 5A For process (2) and (3)) Figure 3 The embodiments shown will not be described in detail here.

[0092] In this embodiment, since multiple circuit branches can process multiple NVMe write commands in parallel, an identifier needs to be sent to optionally, in order to identify which NVMe write command the DMA command of the DMA transmission circuit belongs to, so that the subsequent storage command generation circuit can know the NVMe write command corresponding to the DMA command when receiving the message that the DMA command processing is completed. The DMA command generation circuit of this embodiment can also obtain the corresponding CMD identification information based on the PRP index, and the CMD identification information is used to indicate the NVMe write command from which the PRP index comes.

[0093] Optionally, the storage command generation circuit can also: in response to identifying that all DMA commands corresponding to a certain NVMe write command have been processed, generate a message indicating that the NVMe write command has been processed, and send the message indicating that the NVMe write command has been processed to the host interface (such as Figure 5A In the process (4), a host is provided.

[0094] Optionally, Figure 5A The DMA command generation in the write initiation circuit shown can also be coupled to a cache unit. Still optionally, reference Figure 4 The write initiation circuit may further include a PRP acquisition circuit. Optionally, the PRP acquisition circuit may be coupled to the cache unit.

[0095] Figure 5B A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown.

[0096] like Figure 5B As shown, the flow control circuit of each circuit branch is coupled to the quota manager. The quota manager configures the flow control strategy to the flow control circuit, and the flow control circuit implements flow control according to the configured flow control strategy.

[0097] As an example, the quota manager provides a quota for each circuit branch, and the flow control circuit consumes the quota when sending DMA commands to the DMA command cache. The flow control circuit in each circuit branch controls the timing of sending DMA commands to the DMA command cache by checking the quota it has. For example, the flow control circuit provides the received DMA command to the DMA command cache based on the fact that the quota it has is greater than the specified value, and correspondingly reduces the value of the quota it has (the reduction amount is, for example, the specified value). And when the quota it has is less than the specified value, the flow control circuit does not provide DMA commands to the DMA command cache. For another example, if the flow control circuit in circuit branch 1 checks that the quota corresponding to the current circuit branch 1 is insufficient, the DMA command generated by circuit branch 1 will not be sent to the DMA command cache, and the DMA command generated by circuit branch 1 will be sent to the DMA command cache after the quota corresponding to circuit branch 1 is sufficient.

[0098] Optionally, the credit manager provides credit to each flow control circuit, and accordingly increases the credit owned by the circuit branch that receives the credit. The value of the credit increase depends on the credit value provided by the credit manager. Optionally, the credit manager provides credit to the flow control circuit periodically or at a specified time.

[0099] Optionally, the quotas provided by the quota manager for different circuit branches can be the same or different. For example, the quota manager provides more quotas for circuit branch 1 than for circuit branches 2 to 4. Since more quotas are allocated to circuit branch 1, compared with other circuit branches, the DMA commands generated by circuit branch 1 are more likely to be provided to the DMA command cache, or the probability that the DMA commands generated by circuit branch 1 are blocked by its flow control circuit is relatively small. Since sending DMA commands to the DMA command cache consumes quotas, when the current remaining quota of a circuit branch is insufficient, the DMA command will not be provided to the DMA command cache, but will wait until the quota is greater than a specified value before being provided to the DMA command cache, thereby realizing control of which write commands to process first according to the quota of each circuit branch, and then realizing flow control of write commands.

[0100] The embodiment of the present application uses a flow control manager to independently configure the bandwidth for generating DMA commands or the performance upper limit for generating DMA commands for each circuit branch, so that each circuit branch has an independent flow control strategy and the performance impact of the load change of one circuit branch on other circuit branches is reduced.

[0101] Optionally, the circuit branch corresponds to a user, virtual machine, process or namespace. By providing multiple circuit branches and allocating or binding different circuit branches to different users, virtual machines, processes or namespaces, resource reservation of the storage device is achieved, and the performance impact of a burst load of one instance of a user, virtual machine, process or namespace on other users, virtual machines, processes or namespace instances is avoided. For example, in order to allocate or bind different circuit branches to different users, virtual machines, processes or namespaces, the user, virtual machine, process or namespace associated with the NVMe write command (for example, the user, virtual machine or process that issued the NVMe write command, the namespace indicated by the NVMe write command) is identified, and all PRP indexes of the NVMe write command are provided to the specified one or more circuit branches as a basis to generate a DMA command.

[0102] Figure 6 A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown.

[0103] like Figure 6 As shown, in Figure 5B Based on the embodiment shown, the write initiation circuit further includes a completion message generation circuit, which is coupled to the storage command generation circuit.

[0104] In response to recognizing that all DMA commands corresponding to a certain NVMe write command have been processed, the storage command generation circuit generates a message indicating that the NVMe write command processing is completed, and sends the message that the NVMe write command processing is completed to the completion message generation circuit (such as Figure 6 In process (4-1)). In response to receiving the message that the NVMe write command processing is completed, the completion message generation circuit sends the message that the NVMe write command processing is completed to the host interface (such as Figure 6 process (4-2)).

[0105] Figure 7 A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown.

[0106] like Figure 7 As shown, in Figure 6 Based on the embodiment shown, the write initiation circuit further includes an error handling circuit. The error handling circuit is coupled to the storage command generation circuit.

[0107] In response to receiving the DMA command processing completion message, the storage command generation circuit identifies the DMA command processing error, generates a DMA command processing error message, and provides the DMA command processing error message to the error processing circuit (such as Figure 7Alternatively, the storage command generation circuit, in response to receiving a DMA command processing completion message, identifies the NVMe write command to which the DMA command corresponding to the DMA command processing completion message belongs, and identifies the NVMe write command processing error, generates an NVMe write command processing error message, and provides the write command processing error message to the error processing circuit (such as Figure 7 In process (4-3)). In response to receiving the DMA command processing error message or the NVMe write command processing error message, the error processing circuit processes the DMA command processing error message or the NVMe write command processing error message. Optionally, the error processing circuit may provide the DMA command processing error message or the NVMe write command processing error message to the control component (such as Figure 1B The CPU of the NVMe write command processing error message or the NVMe write command processing error message is provided to the host interface by the error handling circuit, and the DMA command processing error or the NVMe write command processing error message is notified to the host. Optionally, the error handling circuit can also perform other processing on the NVMe write command processing error message according to the prior art, which is not described in detail in this application.

[0108] In an optional embodiment, there may be multiple error handling circuits, and the multiple error handling circuits correspond to multiple circuit branches one by one. Each error handling circuit receives a message indicating an NVMe write command processing error processed by the circuit branch corresponding to it. Figure 5A As shown in the circuit branches 1-4, the write initiation circuit may include four error handling circuits corresponding to the circuit branches 1-4 respectively: error handling circuit 1, error handling circuit 2, error handling circuit 3, and error handling circuit 4. The completion message generation circuit provides a message for indicating a DMA command processing error message or an NVMe write command processing error processed by circuit branch 1 to error handling circuit 1, a message for indicating a DMA command processing error message or an NVMe write command processing error processed by circuit branch 2 to error handling circuit 2, a message for indicating a DMA command processing error message or an NVMe write command processing error processed by circuit branch 3 to error handling circuit 3, and a message for indicating a DMA command processing error message or an NVMe write command processing error processed by circuit branch 4 to error handling circuit 4.

[0109] By providing multiple error handling circuits corresponding to each circuit branch, messages of DMA command processing errors or NVMe write command processing errors processed by each circuit branch can be obtained separately, so that the processing process of the message corresponding to the NVMe write command processing error can also be flow controlled separately. For example, the error handling process of one circuit branch is prioritized, while the error handling process of another circuit branch can be postponed.

[0110] Figure 8 A structural schematic diagram of a write initiation circuit according to another embodiment of the present application is shown.

[0111] like Figure 8 As shown, in Figure 7 Based on the embodiment shown, each circuit branch of the write initiation circuit includes an index cache (such as Figure 8 The index cache is coupled to the DMA command generation circuit of the circuit branch in which it is located. The index cache caches the received PRP index in response to receiving the PRP index. The received PRP index is cached by the index cache so that the rate at which the write initiation circuit generates DMA commands matches the rate at which the PRP index is received.

[0112] by Figure 8 Taking the circuit branch 1 shown as an example, the processing process of the write initiation circuit of the embodiment of the present application is described:

[0113] Process (1-1): write one or more PRP indexes to cache 1.

[0114] Process (1-b): Cache 1 provides one or more cached PRP indexes to the DMA command generation circuit.

[0115] Process (1-4): The DMA command generation circuit generates a DMA command based on the received PRP index and provides the generated DMA command to the flow control circuit. The DMA command is used to instruct to move data in a storage block (eg, 4KB) from the host to the storage device (eg, DRAM).

[0116] Process (1-5): The flow control circuit controls whether to provide the received DMA command to the DMA command buffer according to the configured flow control strategy.

[0117] Process (1-6): The DMA command buffer provides the buffered DMA commands to the DMA transfer circuit.

[0118] Process (2): The DMA transmission circuit responds to receiving a DMA command and processes the DMA command (for example, moving the 4K data indicated by the DMA command from the host memory to the DRAM of the storage device). After the DMA command processing is completed, a message indicating that the DMA command processing is completed is generated and sent to the storage command generation circuit.

[0119] Process (3): In response to receiving a message indicating that DMA command processing is complete, for example, a message indicating that DMA command 1 is complete, i.e., the data indicated by DMA command 1 (e.g., 4KB) is moved to the DRAM, the storage command generation circuit generates a storage command (corresponding to the 4KB data) and sends the generated storage command to the storage command processing unit.

[0120] Process (3-1): If the storage command generation circuit identifies a DMA command processing error corresponding to the message of DMA command processing completion, such as a DMA command 1 processing error, it generates a DMA command processing error message and provides the DMA command to the error handling circuit.

[0121] Process (4-1): In response to recognizing that all DMA commands corresponding to a certain NVMe write command have been processed, the storage command generation circuit generates a message indicating that the NVMe write command processing has been completed, and provides the message that the NVMe write command processing has been completed to the completion message generation circuit.

[0122] Process (4-2): The completion message generation circuit sends a message of completion of NVMe write command processing to the host interface in response to receiving a message of completion of NVMe write command processing.

[0123] Process (4-3): If the storage command generation circuit identifies an NVMe write command processing error, such as an NVMe write command 1 processing error, it generates an NVMe write command processing error message and provides the NVMe write command processing error message to the error handling circuit.

[0124] Process (5) (not shown in the figure): The error handling circuit processes the DMA command processing error message or the NVMe write command processing error message in response to receiving the DMA command processing error message or the NVMe write command processing error message, for example, providing the DMA command processing error message or the NVMe write command processing error message to the CPU of the control component, or notifying the host of the error in the NVMe read command processing completion message through the host interface.

[0125] According to the write initiation circuit of the embodiment of the present application, its various components work in parallel and independently, so that the write initiation circuit can simultaneously process multiple NVMe write commands and multiple PRP indexes corresponding to each NVMe write command.

[0126] Fig. 9 It shows a situation in which the write initiation circuit of an embodiment of the present application processes multiple PRP indexes received continuously. Fig. 9 In the figure, T0-T5 represent continuous time periods, and the content below each time period represents the operation content of each circuit in the time period.

[0127] In the T0 cycle, in response to receiving the PRP0 index, the PRP acquisition circuit acquires the PRP entry PRP0 corresponding to the PRP0 index and sends PRP0 to the DMA command generation circuit.

[0128] In the T1 period, the PRP acquisition circuit acquires the PRP entry PRP1 corresponding to the PRP1 index in response to receiving the PRP1 index. Meanwhile, the DMA command generation circuit generates the corresponding DMA command 0 based on PRP0 and provides the DMA command 0 to the DMA transmission circuit.

[0129] In the T2 period, the PRP acquisition circuit obtains the PRP entry PRP2 corresponding to the PRP2 index in response to receiving the PRP2 index. Meanwhile, the DMA command generation circuit generates the corresponding DMA command 1 based on PRP1, and the DMA transmission circuit executes DMA command 0.

[0130] In the T3 cycle, the DMA command generation circuit generates the corresponding DMA command 2 based on PRP2. At the same time, the DMA transmission circuit executes DMA command 1. The storage command generation circuit generates storage command 0 in response to receiving the DMA command 0 processing completion message.

[0131] In the T4 cycle, the DMA transmission circuit executes the DMA command 2, and at the same time, the storage command generation circuit generates the storage command 1 in response to receiving the DMA command 1 processing completion message.

[0132] In the T5 cycle, the storage command generation circuit generates a storage command 2 in response to receiving the DMA command 2 processing completion message.

[0133] Fig. 9 The PRP index 0 to PRP index 2 shown in the figure may come from the same or different NVMe write commands. The DMA command generation circuit generates a DMA command based on the PRP index, and is not affected by other factors such as the order of the PRP index in the NVMe write command. Even if the PRP indexes received successively by the DMA command generation circuit belong to different NVMe write commands, the PRP indexes received successively belong to the same NVMe write command but in a different order from the order described in the NVMe write command, or the PRP indexes of other NVMe write commands are received before all the PRP indexes of an NVMe write command are completely received, the DMA command generation circuit processes and generates a DMA command in the manner provided in the embodiment of the present application.

[0134] The timing of receiving the PRP index by the write initiation circuit is arbitrary, and the write initiation circuit does not control the timing of receiving the PRP index, or the order or time relationship of receiving multiple PRP indexes. The order or time relationship of receiving multiple PRP indexes will not affect the processing of the write initiation circuit. The time for the PRP acquisition circuit, the DMA command generation circuit, and the storage command generation circuit to perform their own processing does not need to be limited to Fig. 9 In the one cycle shown, the time for the PRP acquisition circuit, the DMA command generation circuit, and the storage command generation circuit to execute their own processing can be the same or different.

[0135] The DMA transmission circuit also processes multiple DMA commands concurrently, which is a prior art and is not described in detail. Even if the communication link between the host and the storage device causes the processing time of the DMA command to change due to sleep or other reasons, the write initiation circuit according to the embodiment of the present application can still work effectively. The change in the processing delay of one DMA command will not affect the processing of other DMA commands. The storage command generation circuit of the embodiment of the present application works in response to each DMA command processing completion message and is not affected by other DMA command processing completion messages.

[0136] Figure 3-Figure 8 The illustrated embodiment uses the PRP index as an example to illustrate the write initiation circuit, and the processing process of the write initiation circuit for the PRP index is also applicable to the SGL index. For the SGL index, the DMA command generation circuit generates a DMA command based on the SGL index in response to receiving the SGL index, and provides the generated DMA command to the DMA transmission circuit. The DMA transmission circuit responds to the received DMA command and moves data between the host memory and the storage device cache according to the DMA command. After the data is moved, a message indicating that the DMA command processing is completed is provided to the storage command generation circuit. The storage command generation circuit generates a storage command in response to receiving the DMA command processing completion message sent by the DMA transmission circuit, and sends the storage command to the storage command processing unit. That is, the processing process of the write initiation circuit for receiving the PRP index or the SGL index in the embodiment of the present application is similar, and the present application will not repeat it here.

[0137] Similar to the PRP index, the SGL index also has multiple forms. For example, the SGL index carries the host memory address indicated in the SGL descriptor, or the SGL index carries a pointer to a cache unit, in which the SGL descriptor is stored. The SGL descriptor is obtained from the cache unit through the SGL index to obtain the host memory address. Optionally, the SGL index corresponds to the SGL descriptor one-to-one. Obtaining the SGL descriptor and the SGL index from the NVMe write command belongs to the prior art and will not be described here.

[0138] refer to Figure 4 The write initiation circuit shown is Fig.10 As shown, the write initiation circuit further includes an SGL acquisition circuit. In response to receiving an SGL index, the SGL acquisition circuit acquires an SGL descriptor based on the SGL index and provides the acquired SGL to the DMA command generation circuit.

[0139] Optionally, the SGL acquisition circuit may also be coupled to a cache unit. The cache unit stores the SGL descriptor or the host memory address extracted from the SGL descriptor. Accordingly, the SGL index carries a pointer for indicating the cache unit. In response to receiving the SGL index, the SGL acquisition circuit acquires the SGL descriptor or the host memory address corresponding to the SGL index from the cache unit.

[0140] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A write initiation circuit, characterized in that: include: DMA command generating circuit and storage command generating circuit; The DMA command generation circuit is coupled to the DMA transmission circuit, and in response to receiving the addressing information, the DMA command generation circuit generates a DMA command based on the addressing information and provides the DMA command to the DMA transmission circuit; the DMA command instructs the DMA transmission circuit to perform data movement from the host memory to the storage device cache according to the DMA command; The storage command generation circuit is coupled to the DMA transmission circuit. In response to receiving a first message sent by the DMA transmission circuit, the storage command generation circuit generates a storage command and provides the storage command to the storage command processing unit; wherein the first message is used to indicate that the DMA command processing performed by the DMA transmission circuit is completed.

2. The write initiation circuit according to claim 1, characterized in that: The DMA command generation circuit is also coupled to a cache unit, which is used to cache the addressing information, and the addressing information includes one or more of the following: a PRP entry, an SGL entry, and a host memory address determined according to the PRP index or the SGL index.

3. The write initiation circuit according to claim 1 or 2, characterized in that: The write initiation circuit further includes a PRP entry or SGL entry acquisition circuit, and the PRP entry or SGL entry acquisition circuit is coupled to the DMA command generation circuit; In response to receiving the addressing information, the PRP entry or SGL entry acquisition circuit acquires the PRP entry or SGL entry based on the addressing information and provides the PRP entry or SGL entry to the DMA command generation circuit.

4. The write initiation circuit according to any one of claims 1 to 3, characterized in that: The write initiation circuit includes one or more circuit branches and a DMA command buffer arranged in parallel, and each of the circuit branches includes a DMA command generation circuit and a flow control circuit; The flow control circuit of each circuit branch is coupled to the DMA command generation circuit of the circuit branch where it is located, and is also coupled to the DMA command cache, and is used to control whether to provide the DMA command generated by the DMA command generation circuit of the circuit branch where it is located to the DMA command cache; The DMA command buffer is also coupled to the DMA transmission circuit, and is used to buffer received DMA commands and provide the buffered DMA commands to the DMA transmission circuit.

5. The write initiation circuit according to claim 4, characterized in that: The flow control circuit of each circuit branch is also coupled to the quota manager, and controls whether to provide the DMA command generated by the DMA command generation circuit of the circuit branch to the DMA command cache according to the flow control strategy configured by the quota manager.

6. The write initiation circuit according to claim 4 or 5, characterized in that: If there are multiple NVMe write commands being processed at the same time, each of the NVMe write commands indicates multiple addressing information, and for each circuit branch, the circuit branch receives multiple addressing information indicated by the same NVMe write command.

7. The write initiation circuit according to claim 6, characterized in that: If the namespaces indicated by the multiple processed NVMe write commands are the same, the addressing information indicated by the multiple processed NVMe write commands is received by the same circuit branch; if the namespaces indicated by the multiple processed NVMe write commands are different, the addressing information indicated by the multiple processed NVMe write commands is received by different circuit branches.

8. The write initiation circuit according to claim 7, characterized in that: The circuit branch receiving the addressing information indicated by the multiple processed NVMe write commands is determined according to the namespace indicated by the multiple processed NVMe write commands.

9. The write initiation circuit according to any one of claims 1 to 8, characterized in that: The storage command generation circuit responds to the first message, identifies the NVMe write command to which the DMA command corresponding to the first message belongs, and generates a second message in response to identifying that all DMA commands corresponding to the NVMe write command have been processed, wherein the second message indicates that all DMA commands corresponding to the NVMe write command have been processed.

10. The write initiation circuit according to claim 9, characterized in that: The write initiation circuit further includes an error handling circuit, the error handling circuit being coupled to the storage command generation circuit; The storage command generation circuit generates a third message in response to identifying a DMA command processing error indicated by the first message, and provides the third message to the error processing circuit; Or, the storage command generation circuit identifies the NVMe write command processing error indicated by the second message, generates a fourth message, and provides the fourth message to the error processing circuit; wherein the third message is used to indicate the DMA command processing error indicated by the first message, and the fourth message is used to indicate the NVMe write command processing error indicated by the second message; The error processing circuit receives the third message or the fourth message, and processes the third message or the fourth message.

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