NVMe read IO initiating circuit of NVMe controller

Abstract

The embodiment of the invention provides an NVMe read IO initiating circuit of an NVMe controller, and relates to the technical field of storage. The read initiation circuit comprises the following steps: in response to receiving an NVMe read command or addressing information, updating an information cache by using the NVMe read command or addressing information; the DMA command generation circuit responds to the received storage command processing completion message, acquires address positioning information corresponding to the storage command, generates a DMA command based on the address positioning information, and provides the DMA command to the DMA transmission circuit; and the completion message processing circuit responds to the received message which is sent by the DMA transmission circuit and is used for indicating that the DMA command processing executed by the DMA transmission circuit is completed, and the entry associated with the NVMe read command corresponding to the message in the information cache is updated. The reading initiating circuit is a hardware circuit independent of the CPU, a task for generating the DMA command is unloaded from the CPU, and the burden of the CPU is relieved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to an NVMe read IO initiation circuit of an NVMe controller. Background Art

[0002] Figure 1A The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 (hereinafter, the solid-state storage device is referred to as the storage device for short) includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] The above-mentioned NVM chip 105 includes NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc., which are common storage media.

[0004] The above-mentioned interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control part 104 issues a command to the NVM chip 105 in a manner complying with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash package that share a CE (Chip Enable) signal. A NAND flash package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash chip can execute commands and report status independently of each other.

[0008] Data is usually stored and read on a storage medium in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page on a storage medium (called a physical page) has a fixed size, such as 17664 bytes. A physical page can also have other sizes.

[0009] In the storage device 102, FTL (Flash Translation Layer) is used to maintain the mapping information from the logical address (LBA) to the physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address. The table structure that stores the mapping information from the logical address to the physical address is called the FTL table. The FTL table is an important metadata in the storage device. The data items of the FTL table record the address mapping relationship in the storage device in units of data units.

[0010] The host accesses the storage device with IO commands that follow the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, and erase commands) that follow the interface protocol of the NVM chip based on the media interface commands. The control component also tracks that all media interface commands generated from an IO command have been executed and indicates the processing results of the IO command to the host.

[0011] See also Figure 1B The control component includes a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a medium interface controller 1044 and a storage medium management unit 1045. The host interface 1041 obtains the IO command provided by the host. The host command processing unit 1042 generates a storage command according to the IO command and provides it to the storage command processing unit 1043. The storage command can access the storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. The physical page records one or more data frames. For example, the size of the physical page is 17664 bytes, and the size of the data frame is 4KB, then one physical page can store 4 data frames.

[0012] The storage medium management unit 1045 maintains the conversion of the logical address to the physical address for each storage command. For example, the storage medium management unit 1045 includes an FTL table (the FTL will be explained below). For a read command, the storage medium management unit 1045 outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For a write command, the storage medium management unit 1045 allocates an available physical address for it and records the mapping relationship between the logical address (LBA) accessed by it and the allocated physical address. The storage medium management unit 1045 also maintains functions required for managing the NVM chip such as garbage collection and wear leveling.

[0013] The storage command processing unit 1043 operates the medium interface controller 1044 to issue a storage medium access command to the NVM chip 105 according to the physical address provided by the storage medium management unit 1045 .

[0014] For the purpose of clarity, the command sent by the host to the storage device 102 is called an IO command (including, for example, an NVMe read command and an NVMe write command), the command sent by the host command processing unit 1042 to the storage command processing unit 1043 is called a storage command, the command sent by the storage command processing unit 1043 to the medium interface controller 1044 is called a medium interface command, and the command sent by the medium interface controller 1044 to the NVM chip 105 is called a storage medium access command. The storage medium access command complies with the interface protocol of the NVM chip.

[0015] In the NVMe protocol, after receiving the NVMe read and write command, the solid-state storage device 102 obtains data from the host's memory through the host interface 1041, and then writes the data into the flash memory. For NVMe read and read commands, when the data is read from the flash memory, the solid-state storage device 102 moves the data to the host memory through the host interface 1041.

[0016] like Figure 1C The basic structure of a host command processing unit 1042 of the prior art is shown. Figure 1C The host command processing unit shown in FIG. Figure 1C As shown, the host command processing unit 1042 mainly includes a shared memory (for example, located inside the control component, and different from the storage device memory DRAM and NVM chip), a cache unit, an SGL / PRP unit, and a read control circuit. Among them, the read control circuit includes a read initiation circuit and a DMA transmission circuit, and the read initiation circuit and the DMA transmission circuit cooperate with each other to realize the process of data movement. The process of the host command processing unit 1042 processing IO commands such as NVMe read commands includes:

[0017] In response to receiving an NVMe read command, the SGL / PRP unit obtains the SGL / PRP corresponding to the read command, and stores the SGL / PRP in the cache unit; generates one or more DMA command groups according to the SGL / PRP, each DMA command group includes one or more DMA commands; and stores the DMA command group in the shared memory. After the DMA command group is generated, the SGL unit notifies the read initiation circuit and passes the DMA command group index used to indicate the location of the DMA command group in the shared memory to the read initiation circuit. The read initiation circuit requests the back-end module to read the data indicated by the read command from the flash memory (NVM) to the storage device memory (DRAM). When the data indicated by a certain DMA command group is read out to the storage device memory, the read initiation circuit can obtain the information. In response to the data indicated by a certain DMA command group being read out to the storage device memory, the read initiation circuit can provide the above DMA command group index to the DMA transmission circuit. According to the DMA command group index, the DMA transmission circuit takes out one or more DMA commands of the DMA command group from the shared memory, and the DMA transmission circuit performs a data move operation to move data from the storage device memory to the host memory.

[0018] Among them, in the NVMe protocol, NVMe has two commands, one is the admin command, which is used by the host to manage and control the storage device, and the other is the IO command, including the NVMe write command and the NVMe read command, which is used to control the data transmission between the host and the storage device. There are fields related to SGL or PRP in the IO command, which indicate the location of the data in the host memory (for write commands) or the host memory address to be written (for read commands). The PRP field or SGL field in the IO command can be an SGL or PRP entry pointing to the host memory address space to be accessed, or a pointer to the SGL or PRP linked list, or even a pointer to a pointer. If the IO command carries an SGL or PRP, the storage device can directly obtain the SGL or PRP in response to receiving the IO command. If the IO command carries an SGL or PRP pointer, in response to receiving the IO command, the storage device accesses the host according to the above-mentioned SGL or PRP pointer and obtains the SGL or PRP from the host.

[0019] PRP (Physical Region Page) and SGL (Scatter / Gather List) are two ways to describe the data to be transmitted between the host and the storage device. In the PRP method, a number of linked PRP entries are used, each of which includes a 64-bit memory physical address to describe a physical page (Page) of the host memory. SGL is a linked list, consisting of one or more SGL segments, each of which consists of one or more SGL descriptors; each SGL descriptor describes the address and length of the data cache of the host memory, that is, each SGL descriptor corresponds to a host memory address space; each SGL descriptor has, for example, a fixed size (for example, 16 bytes).

[0020] DMA (Direct Memory Access) commands indicate the mapping relationship between the host memory address space and the storage device memory address space (e.g., DRAM address), and are used to control the DMA transfer circuit to execute data transfer commands. The host memory address indicated by the DMA command is determined based on the address space indicated by the SGL or PRP, and the storage device memory address is allocated by the storage device. Each DMA command is used to perform a data movement operation between the host and the storage device. Summary of the invention

[0021] In high-performance storage devices, the control unit may process hundreds or even thousands of IO commands per second, and each IO command needs to initiate dozens of DMA transfers. Figure 1C ) requires extremely high processing power to match the performance of the storage device and can easily become a performance bottleneck. If the CPU executes software to implement the function of the read initiation circuit, its performance is limited by the CPU's processing speed. At this time, the CPU's processing power becomes the bottleneck of the performance of processing IO commands. However, the cost of improving CPU performance is high. It is hoped that a dedicated hardware circuit can be used to complete related tasks, thereby improving the processing performance of IO commands. At the same time, related tasks are also unloaded from the CPU, reducing the burden on the CPU and making it easier for the CPU to process other tasks.

[0022] In view of this, an embodiment of the present application provides a read initiation circuit and a storage device. The read initiation circuit is a hardware circuit independent of the CPU. The hardware circuit generates a DMA command for instructing the movement of data from the storage device to the host, and updates the NVMe read command in response to the completion of DMA command processing. The task of generating DMA commands is unloaded from the CPU, thereby improving the processing efficiency of IO commands, reducing the burden on the CPU, and facilitating the CPU to process other tasks.

[0023] According to a first aspect of the present application, there is provided a read initiation circuit, comprising: an information cache, a DMA command generation circuit and a completion message processing circuit;

[0024] In response to receiving an NVMe read command or addressing information, updating the information cache with the NVMe read command or addressing information;

[0025] The DMA command generation circuit is coupled to the DMA transmission circuit. In response to receiving a storage command processing completion message, the DMA command generation circuit obtains address location information corresponding to the storage command completion message, generates a DMA command based on a storage device cache address provided by the storage command completion message and a host memory address indicated by the address location information, and provides the DMA command to the DMA transmission circuit.

[0026] The completion message processing circuit is coupled to the DMA transmission circuit and the information cache. In response to receiving a first message sent by the DMA transmission circuit, the completion message processing circuit updates the entry associated with the NVMe read command corresponding to the first message in the information cache, and the first message is used to indicate that the DMA command processing performed by the DMA transmission circuit is completed.

[0027] In an optional embodiment of the present application, the DMA command generation circuit is also coupled to the completion message processing circuit, and the DMA command generation circuit provides the generated DMA command to the completion message processing circuit.

[0028] In an optional embodiment of the present application, the read initiation circuit further includes an information receiving circuit, and the information receiving circuit is coupled to the information cache;

[0029] In response to receiving an NVMe read command, the information receiving circuit adds an entry associated with the NVMe read command in the information cache; or in response to receiving addressing information, updates an entry associated with the NVMe read command to which the addressing information belongs in the information cache.

[0030] In an optional embodiment of the present application, the information receiving circuit includes an NVMe read command receiving circuit and an addressing information receiving circuit;

[0031] In response to receiving the NVMe read command, the NVMe read command receiving circuit adds an entry associated with the NVMe read command in the information cache;

[0032] In response to receiving the addressing information, the addressing information receiving circuit updates the entry associated with the NVMe read command to which the addressing information belongs in the information cache.

[0033] In an optional embodiment of the present application, the NVMe read command receiving circuit, the addressing information receiving circuit, the DMA command generating circuit and the completion message processing circuit are executed in parallel and independently of each other.

[0034] In an optional embodiment of the present application, if there are multiple NVMe read commands being processed at the same time, the first NVMe read command received by the NVMe read command receiving circuit, the second NVMe read command corresponding to the addressing information received by the addressing information receiving circuit, the third NVMe read command corresponding to the address location information obtained by the DMA command generation circuit, and the fourth NVMe read command corresponding to the first message received by the completion message processing circuit are all different.

[0035] In an optional embodiment of the present application, the information receiving circuit generates a storage command in response to receiving an NVMe read command, and provides the storage command to a back-end module, wherein the storage command instructs the back-end module to process data movement from the storage device flash memory to the storage device cache according to the storage command.

[0036] In an optional embodiment of the present application, the DMA command generation circuit updates the entry associated with the NVMe read command corresponding to the storage command processing completion message in the information cache in response to receiving the storage command processing completion message.

[0037] In an optional embodiment of the present application, the completion message processing circuit deletes the entry associated with the NVMe read command whose DMA command has been fully processed in the information cache in response to identifying that the DMA command corresponding to the NVMe read command has been fully processed.

[0038] In an optional embodiment of the present application, multiple entries are cached in the information cache, different entries correspond to different NVMe read commands, and all addressing information, all DMA commands and all first messages associated with the same NVMe read command correspond to the same entry in the information cache.

[0039] In an optional embodiment of the present application, the addressing information includes a PRP index or an SGL index; the address location information includes one or more of the following: a PRP entry, an SGL entry, and a host memory address determined according to the PRP index or the SGL index.

[0040] In an optional embodiment of the present application, the read initiation circuit further includes an error handling circuit, and the error handling circuit is coupled to the completion message processing circuit;

[0041] The completion message processing circuit generates a second message in response to identifying a DMA command processing error indicated by the first message, and provides the second message to the error handling table circuit; or, the completion message processing circuit generates a third message in response to identifying an NVMe read command processing error, and provides the third message to the error handling circuit; wherein the second message is used to indicate the DMA command processing error indicated by the first message, and the third message is used to indicate the NVMe read command processing error;

[0042] The error processing circuit receives the second message or the third message, and processes the second message or the third message.

[0043] In an optional embodiment of the present application, the completion message processing circuit generates a fourth message in response to identifying that all DMA commands corresponding to the NVMe read command have been processed, and sends the fourth message to the host interface, wherein the fourth message is used to indicate that all DMA commands corresponding to the NVMe read command have been processed.

[0044] In an optional embodiment of the present application, the read initiation circuit further includes a message sending circuit, and the message sending circuit is coupled to the completion message processing circuit;

[0045] The completion message processing circuit provides the fourth message to the message sending circuit;

[0046] The message sending circuit provides the received fourth message to the host interface.

[0047] In an optional embodiment of the present application, the read initiation circuit further includes an address location information acquisition circuit, and the address location information acquisition circuit is coupled to the DMA command generation circuit;

[0048] In response to receiving a storage command processing completion message, the DMA command generation circuit obtains addressing information indicated by an NVMe read command corresponding to the storage command processing completion message, and provides the addressing information to the address location information acquisition circuit;

[0049] In response to receiving the addressing information, the address location information acquisition circuit acquires address location information corresponding to the addressing information, and provides the acquired address location information to the DMA command generation circuit.

[0050] In an optional embodiment of the present application, the read initiation circuit further includes a plurality of flow control circuits;

[0051] Each of the flow control circuits is coupled to the information cache, and each of the flow control circuits controls whether to update the information cache with the NVMe read command or the addressing information in response to receiving the NVMe read command and the addressing information.

[0052] In an optional embodiment of the present application, each of the flow control circuits is coupled to a credit manager, and controls whether to provide the received NVMe read command or addressing information to the receiving circuit according to a flow control strategy configured by the credit manager.

[0053] In an optional embodiment of the present application, the read initiation circuit further includes a DMA command cache, and the DMA command cache is coupled with the DMA command generation circuit and the DMA transmission;

[0054] In response to receiving a DMA command sent by the DMA command generation circuit, the DMA command buffer caches the DMA command and provides the cached DMA command to the DMA transmission circuit.

[0055] In an optional embodiment of the present application, the DMA command buffer is also coupled to the completion message processing circuit, and the DMA command buffer provides the cached DMA commands to the DMA transmission circuit.

[0056] According to a second aspect of the present application, a storage device is provided, comprising the read initiation circuit described in any embodiment of the first aspect, and the data indicated by the NVMe read command is moved from the storage to the host through the read initiation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0058] Figure 1 Figure 1A shows a block diagram of a solid-state storage device;

[0059] Figure 1B A block diagram showing control components in a solid-state storage device;

[0060] Figure 1C A block diagram of a host command processing unit in a control component in the related art is shown;

[0061] Figure 2 A schematic diagram showing the PRP indicated by the NVMe write command;

[0062] Figure 3A schematic diagram of the structure of a read initiation circuit according to an embodiment of the present application is shown;

[0063] Figure 4 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown;

[0064] Figure 5 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown;

[0065] Figure 6 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown;

[0066] Figure 7 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown;

[0067] Figure 8 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown;

[0068] Fig. 9 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown;

[0069] Fig.10 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown;

[0070] Fig.11 A schematic diagram showing a read initiation circuit in an embodiment of the present application processing multiple NVMe read commands;

[0071] Fig.12 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0072] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0073] For ease of understanding, the following briefly describes PRP and SGL. PRP (Physical Region Page) and SGL (Scatter / Gather List) are two ways to describe the data to be transferred between the host and the storage device. In addition to indicating the address of the host memory to be written, the NVMe read command sent by the host to the storage device also contains the starting logical address (LBA) of the storage device to be accessed and the data length. According to the LBA, the storage device searches the FTL table, finds the corresponding physical address, and obtains the data from the physical block corresponding to the physical address. The address indicated by the NVMe read command to write data to the host memory can be indicated by a PRP entry or an SGL descriptor. The NVMe write command indicates one or more RPR entries or SGL descriptors. The PRP entry indicates a fixed-size storage space in the host memory (such as Figure 2 The storage blocks shown in FIG. 1 ), that is, the storage space sizes indicated by different PRP entries are the same, such as 4KB, 16KB, etc. Figure 2 As shown, the NVMe read command indicates three PRP entries (PRP0, PRP1, and PRP2), where PRP0 indicates storage block A in the host memory, PRP1 indicates storage block B in the host memory, and PRP2 indicates storage block C in the host memory, where the size of storage block A, storage block B, and storage block C is 4KB; optionally, the size of storage block A, storage block B, and storage block C is not limited to 4KB. The SGL descriptor indicates a storage space of indefinite size in the host memory. For example, the NVMe read command indicates three SGL descriptors (SGL1, SGL2, and SGL3), where SGL1 indicates a storage space of 4KB, SGL2 indicates a storage space of 2KB, and SGL3 indicates a storage space of 3KB.

[0074] Whether it is a PRP entry or an SGL descriptor, the essence is to describe one or more address spaces in the host memory, and the location of these address spaces in the host memory is arbitrary. The host carries a PRP or SGL related field in the NVMe read command, which can be an SGL or PRP itself, pointing to the host memory address space to be accessed, or a pointer, pointing to an SGL or PRP linked list, or even a pointer to a pointer. Regardless of the form, according to the NVMe read command, the storage device can always obtain the corresponding SGL or PRP. Based on this, in an optional embodiment, if the NVMe read command indicates PRP (such as the PRP entry itself or the PRP pointer), the read initiation circuit receives the PRP index, and a DMA command will be generated based on the PRP index; if the NVMe read command indicates SGL (such as the SGL descriptor itself or the SGL pointer), the read initiation circuit receives the SGL index, and a DMA command will be generated based on the SGL index. It can be understood that the embodiments of the present application are not limited to transmitting data between the host and the storage device in two ways of address location information, and data can also be transmitted through other information with similar functions.

[0075] For the purpose of clarity, in this application, addressing information is used to represent information for addressing host memory obtained according to an NVMe write command. The addressing information can be, for example, a PRP index, a PRP entry, an SGL index, an SGL descriptor, or the host memory address itself. Wherein the PRP entry or SGL descriptor carries the host memory address, and the SGL index or PRP index represents the address of the SGL descriptor or PRP entry obtained by, for example, an SGL / PRP unit and stored in a cache unit.

[0076] The following is an example of a host sending an NVMe read command to a storage device, and the NVMe read command uses PRP to describe the host memory address to illustrate the structure of the write initiation circuit of the embodiment of the present application. It can be understood that in the embodiment of the present invention, PRP entries, DMA commands, and storage commands can correspond one to one, one to many, many to one, or many to many. For the purpose of simplicity, in the embodiment according to the present application, the PRP entries, DMA commands, and storage commands are described in a one-to-one correspondence manner.

[0077] Figure 3 A structural schematic diagram of a read initiation circuit according to an embodiment of the present application is shown.

[0078] like Figure 3 As shown, the read initiation circuit includes an information buffer, a DMA command generation circuit and a completion message processing circuit. As an example, the SGL / PRP unit (also see Figure 1C )After obtaining, for example, a PRP entry from an NVMe read command, a PRP index indicating the PRP entry is provided to the read initiation circuit.

[0079] The information cache is coupled with the DMA generation circuit and the completion message processing circuit. In response to receiving an NVMe read command or a PRP index, the information cache is updated with the NVMe read command or the PRP index (as shown in process (1) in the figure). The information cache can accommodate multiple entries, each entry corresponds to an NVMe read command, different entries correspond to different NVMe read commands, and all addressing information, all DMA commands and all first messages associated with the same NVMe read command correspond to the same entry. Thus, the storage device concurrently processes multiple NVMe read commands at the same time. It can be understood that the NVMe read command stored in the information cache may be different in form from the NVMe read command received from the host, but each NVMe read command occupies an entry in the information cache. For example, in order to meet the needs of the read initiation circuit processing, the NVMe read command in the information cache includes information such as a command identifier, a PRP cache index, a DMA command count, and a timestamp. The command identifier is used to identify a specified NVMe read command from multiple NVMe read commands. The PRP cache index is used to indicate the storage location of the PRP entry of the NVMe command to which it belongs. The DMA command count is used to indicate the number of DMA commands that have been processed corresponding to the NVMe read command to which it belongs. The timestamp indicates the time when the NVMe read command is received.

[0080] It can be understood that the control component of the storage device also performs other processing on the NVMe read command, for example, generating a physical address based on the logical address to be accessed by the NVMe read command through the FTL table, and using the physical address to read data from the NVM chip, etc. These processing processes and the components that implement these processes belong to the prior art. The components that implement these processes are collectively referred to as back-end modules. After reading the data from the NVM chip and adding it to the storage device cache, the back-end module provides a storage command processing completion message to the read initiation circuit (such as process (2) in the figure). A single NVMe read command corresponds to one or more storage commands, and thus a single NVMe read command corresponds to one or more storage command completion messages.

[0081] The DMA command generation circuit is coupled with the information cache and the DMA transmission circuit. In response to receiving a storage command processing completion message (such as process (2) in the figure), it obtains a PRP entry corresponding to the storage command (such as process (3) in the figure), generates a corresponding DMA command based on the PRP entry, and sends the DMA command to the DMA transmission circuit (such as process (4) in the figure).

[0082] To generate a DMA command, it is necessary to know the storage device cache address as the DMA transfer source address and the host memory address as the destination address. According to an embodiment of the present application, the storage device cache address is obtained according to the storage command processing completion message, and the host memory address is obtained according to the PRP entry. Figure 3 The NVMe read command stored in the information cache includes, for example, a PRP cache index, obtaining the corresponding NVMe read command according to the storage command processing completion message, obtaining the PRP cache index from the information cache, and obtaining the PRP entry from the corresponding PRP cache. Optionally, the PRP entry is stored in Figure 3 information cache, thereby obtaining the required PRP entry directly from the information cache.

[0083] The DMA transmission circuit is coupled to the DMA command generation circuit and the completion message processing circuit. In response to receiving a DMA command, the DMA transmission circuit moves data from the storage device cache to the host memory. In response to the completion of the DMA command processing, the DMA command processing completion message is sent to the completion message processing circuit (as shown in process (5) in the figure).

[0084] The completion message processing circuit is coupled with the DMA transmission circuit and the information cache, and in response to receiving the DMA command processing completion message, updates the NVMe read command corresponding to the DMA command processing completion message in the information cache. For example, the DMA command count value is updated (for example, incremented), or if all DMA commands corresponding to the NVMe read command are processed, the NVMe read command is deleted from the information cache (such as process (6) in the figure).

[0085] According to one embodiment of the present application, during the NVMe read command processing, there are two different stages in which the information cache of the read initiation circuit is updated. Stage (1) After the control component of the storage device receives the NVMe read command and obtains the PRP entry from the host according to the NVMe read command, the entry associated with the NVMe read command is added to the information cache, and the entry associated with the NVMe read command added to the information cache includes a PRP index indicating the cache address of the PRP entry; Stage (2) In response to receiving one or more DMA command processing completion messages corresponding to the NVMe read command, the DMA command count of the NVMe read command in the information cache is updated or the NVMe read command is deleted.

[0086] According to another embodiment of the present application, during the NVMe read command processing, there are three different stages in which the information cache of the read initiation circuit is updated. Stage (1) In response to receiving the NVMe read command, an entry associated with the NVMe read command is added to the cache; Stage (2) The control component obtains the PRP entry from the host according to the NVMe read command, and adds the PRP index indicating the cache address of the PRP entry to the information cache of the read initiation circuit to update the entry associated with the NVMe read command corresponding to the PRP index in the information cache; Stage (3) In response to receiving one or more DMA command processing completion messages corresponding to the NVMe read command, the DMA command count of the NVMe read command in the information cache is updated, and in response to receiving a DMA command processing completion message corresponding to the NVMe read command, the entry associated with the NVMe read command is deleted.

[0087] Optionally, the DMA command generation circuit can also be coupled to the completion message processing circuit, which sends the generated DMA command to the completion message processing circuit (such as process (4.1) in the figure), so that the completion message processing circuit knows which DMA command completion messages it expects to receive, so as to detect DMA command processing timeout or other errors.

[0088] Further, the completion message processing circuit generates an NVMe read command processing completion message in response to the DMA command corresponding to the NVMe read command being processed completely, and sends the NVMe read command processing completion message to the host interface. The completion message processing circuit can directly send the NVMe read command processing completion message to the host interface, or send the NVMe read command processing completion message to the peripheral circuit, and send the NVMe read command processing completion message to the host interface through the peripheral circuit.

[0089] After receiving the NVMe read command, the control component of the storage device generates one or more storage commands based on the NVMe read command and sends them to the back-end module for processing. Figure 4 Not shown. According to an embodiment of the present application, since the NVMe read command will be provided to the read initiation circuit to update the information cache, optionally, the read initiation circuit forwards the received NVMe read command to the back-end module. It takes time for the back-end module to process the NVMe read command or storage command, for example, typically 50-100us, during which the read initiation circuit will not wait or stagnate, but continue to process other received NVMe commands, PRP indexes, storage command completion messages and / or DMA command completion messages.

[0090] Figure 4 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown.

[0091] like Figure 4 As shown, in Figure 3 Based on the read initiating circuit shown, the read initiating circuit further includes an information receiving circuit. The information receiving circuit is coupled to the information buffer.

[0092] In response to receiving an NVMe read command (as shown in process (1.1) in the figure, the information receiving circuit adds an entry associated with the NVMe read command in the information cache (as shown in process (1.2) in the figure; or, in response to receiving addressing information (as shown in process (1.1) in the figure, updates the entry associated with the NVMe read command to which the addressing information belongs in the information cache (as shown in process (1.2) in the figure).

[0093] In an optional embodiment, the information receiving circuit includes an NVMe read command receiving circuit and an addressing information receiving circuit, which respectively receive the NVMe read command and the addressing information. In response to receiving the NVMe read command, the NVMe read command receiving circuit adds an entry associated with the NVMe read command in the information cache. In response to receiving the addressing information, the addressing information receiving circuit updates the entry associated with the NVMe read command to which the addressing information belongs in the information cache.

[0094] Optionally, the information receiving circuit generates a storage command in response to receiving an NVMe read command, and provides the storage command to the back-end module, and the storage command instructs the back-end module to perform data migration from the storage device flash memory to the storage device cache according to the storage command. Still optionally, the information receiving circuit directly provides the received NVMe read command to the back-end module, and the module generates the storage command.

[0095] Figure 5 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown.

[0096] like Figure 5 As shown, in Figure 3 On the basis of the read initiation circuit shown, the read initiation circuit also includes a message sending circuit. The message sending circuit is coupled to the completion message processing circuit. The completion message processing circuit provides the NVMe read command processing completion message to the message sending circuit (as shown in process (5) in the figure), and the message sending circuit provides the received NVMe read command processing completion message to the host interface (as shown in process (6) in the figure).

[0097] Figure 6 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown.

[0098] like Figure 6 As shown, in Figure 3 Based on the read initiation circuit shown, the read initiation circuit further includes an error processing circuit. The error processing circuit is coupled to the completion message processing circuit.

[0099] In response to recognizing that an error has occurred in the DMA command processing indicated by the DMA command processing completion message, the completion message processing circuit provides a DMA command processing completion message indicating the error to the error processing circuit (such as process (7) in the figure). The error processing circuit performs processing, for example, providing the error information to the CPU of the control component, instructing the DMA transmission circuit to reprocess the erroneous DMA command, etc. Optionally, the completion message processing circuit also identifies an NVMe read command processing error, generates an NVMe read command processing error message, and provides the NVMe read command processing error message to the error processing circuit (such as process (7) in the figure). The error processing circuit receives the NVMe read command processing error message, processes the NVMe read command processing error message, for example, provides the error information to the CPU of the control component, or informs the host of the error in the NVMe read command processing completion message through the host interface.

[0100] The NVMe read command processing error corresponding to the NVMe read command processing completion message may include a processing timeout of a DMA command (the corresponding DMA command processing completion message has not been received for a long time), or an error in the NVMe read command corresponding to the DMA command. The error information is provided to the error handling circuit, which is processed by the error handling circuit. Optionally, the error handling circuit also provides a message such as an NVMe read command processing error to the host interface, and then to the host that issued the NVMe read command.

[0101] Figure 7 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown.

[0102] like Figure 7 As shown, in Figure 3 Based on the read initiation circuit shown, the read initiation circuit further includes a PRP acquisition circuit. The PRP acquisition circuit is coupled to the DMA command generation circuit.

[0103] In response to receiving a storage command processing completion message, the DMA command generation circuit obtains the PRP index of the NVMe read command corresponding to the storage command processing completion message, and provides the PRP index to the PRP acquisition circuit.

[0104] In response to receiving the PRP index, the PRP acquisition circuit acquires the PRP corresponding to the PRP index and provides the acquired PRP to the DMA command generation circuit.

[0105] Figure 8 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown.

[0106] like Figure 8 As shown, in Figure 3Based on the read initiation circuit shown, the read initiation circuit also includes multiple flow control circuits. Each flow control circuit is coupled to the information cache, and each flow control circuit controls whether to update the information cache with the received NVMe read command or PRP index (such as process (1.1) in the figure) in response to receiving an NVMe read command or PRP index (such as process (1) in the figure).

[0107] Figure 8 In an embodiment, the two flow control circuits operate independently. Thus, one flow control circuit may suspend processing of a received NVMe read command or PRP index, while the other flow control circuit allows the received NVMe read command or PRP index to pass through. The flow control circuits each have, for example, a configurable bandwidth, thereby limiting the number of NVMe read commands or PRP indexes that pass through the flow control circuit per unit time. Optionally, the read initiation circuit has another number of flow control circuits, each of which operates independently, so that the flow control strategy of one flow control circuit does not affect the operation of other flow control circuits.

[0108] Optionally, the flow control circuit implements flow control according to a configured priority.

[0109] Fig. 9 A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown.

[0110] like Fig. 9 As shown, each flow control circuit is coupled to the quota manager, and controls whether to provide the received NVMe read command or PRP index to the receiving circuit according to the flow control policy configured by the quota manager.

[0111] The flow control circuit implements flow control according to the configured flow control strategy. As an example, the quota manager provides a quota for each flow control circuit. Each flow control circuit controls whether to allow NVMe read commands or PRP indexes to pass by checking the quota it has. For example, the flow control circuit provides the received NVMe read command or PRP index to the cache based on the fact that the quota it has is greater than the specified value, and correspondingly reduces the value of the quota it has (the reduction amount is, for example, the specified value). And when the quota it has is less than the specified value, the flow control circuit does not allow the received NVMe read command or PRP index to pass. For another example, if the flow control circuit checks that its current quota is insufficient, it will not allow the NVMe read command or PRP index it receives to pass, and wait until its quota is sufficient before providing the NVMe read command or PRP index to the information cache.

[0112] Optionally, the credit manager provides credit to each flow control circuit, and accordingly increases the credit owned by the flow control circuit that receives the credit. The value of the credit increase depends on the credit value provided by the credit manager. Optionally, the credit manager provides credit to the flow control circuit periodically or at a specified time.

[0113] Optionally, the quotas provided to different flow control circuits may be the same or different. For example, a larger quota is provided to one flow control circuit than to other flow control circuits. Since a larger quota is allocated to one flow control circuit, compared with other flow control circuits, the NVMe read command or PRP index received by the flow control circuit with a larger quota is provided to the cache with a greater chance, or the NVMe read command or PRP index received by the flow control circuit with a larger quota is relatively less likely to be blocked.

[0114] Alternatively or further, additional multiple flow control circuits ( Fig. 9 The storage command processing completion message is coupled to the DMA command generation circuit (not shown). Before being provided to the DMA command generation circuit, the storage command processing completion message is received by one of the additional plurality of flow control circuits, and these flow control circuits are used to determine whether to provide the received storage command processing completion message to the DMA command generation circuit. The additional plurality of flow control circuits are coupled to the DMA command generation circuit. Fig. 9 The multiple flow control circuits shown in the figure correspond one to one, thereby forming multiple circuit branches, and the flow control strategy of each circuit branch can be independently configured and implemented. Still optionally, the flow control strategies of additional multiple flow control circuits are also configured by the quota manager.

[0115] Optionally, the circuit branch corresponds to a user, a virtual machine, a process or a namespace. By providing multiple circuit branches and allocating or binding different circuit branches to different users, virtual machines, processes or namespaces, resource reservation of the storage device is achieved, and the performance impact of a burst load of one instance of a user, virtual machine, process or namespace on other users, virtual machines, processes or namespace instances is avoided. For example, in order to allocate or bind different circuit branches to different users, virtual machines, processes or namespaces, the user, virtual machine, process or namespace associated with the NVMe write command (for example, the user, virtual machine or process that issued the NVMe read command, the namespace indicated by the NVMe read command) is identified, and all PRP indexes of the NVMe read command are provided to the specified one or more circuit branches to generate a DMA command. The storage command completion message of the NVMe read command also carries an identifier of the user, virtual machine, process or namespace or circuit branch associated with the NVMe read command, and the additional flow control circuit receiving the storage command completion message is determined based on the identifier.

[0116] The embodiment of the present application uses a quota manager to independently configure the bandwidth or performance upper limit for allowing NVMe read commands or PRP indexes to pass through for each flow control circuit, so that each flow control circuit has an independent flow control strategy and reduces the performance impact of load changes in one circuit branch on other circuit branches.

[0117] Fig.10A structural schematic diagram of a read initiation circuit according to another embodiment of the present application is shown.

[0118] like Fig.10 As shown, in Fig. 9 On the basis of the embodiment shown, the read initiation circuit also includes a DMA command cache. The DMA command cache is coupled with the DMA command generation circuit and the DMA transmission. In response to receiving a DMA command sent by the DMA command generation circuit (such as process (4.2) in the figure), the DMA command cache caches the DMA command and provides the cached DMA command to the DMA transmission circuit (such as process (4.3) in the figure). The DMA command cache may receive more than one DMA command from the DMA command generation circuit. It takes time for the DMA transmission circuit to process the DMA command. When the DMA command cache receives multiple DMA commands, the unprocessed DMA commands are cached.

[0119] Optionally, the DMA command buffer is also coupled to the completion message processing circuit, and the DMA command buffer provides the cached DMA commands to the completion message processing circuit (such as process (4.4) in the figure).

[0120] According to the read initiation circuit of the embodiment of the present application, its various components work in parallel and independently, so that the read initiation circuit can simultaneously process multiple NVMe read commands, multiple PRP indexes corresponding to each NVMe read command, multiple storage command processing completion messages corresponding to each NVMe read command, and multiple DMA command processing completion messages corresponding to each NVMe read command.

[0121] Fig.11 The present invention illustrates a situation in which a read initiation circuit according to an embodiment of the present application processes multiple NVMe read commands received continuously. Fig.11 In the figure, T0-T4 represent continuous time periods, and the content below each time period represents the operation content of each circuit in the time period.

[0122] As an example, the read initiation circuit receives NVMe read command 1, NVMe read command 2, and NVMe read command 3 in consecutive T0, T1, and T2 cycles, respectively. The PRP index of NVMe read command 1, the PRP index of NVMe read command 2, and the PRP index of NVMe read command 3 are received in T1, T2, and T3 cycles, respectively. The NVMe read command 1 storage command completion message, the NVMe read command 2 storage command completion message, and the NVMe read command 3 storage command completion message are received in T2, T3, and T4 cycles, respectively.

[0123] During the T0 cycle, the NVMe read command receiving circuit adds the NVMe read command 1 to the information cache.

[0124] In the T1 cycle, the NVMe read command receiving circuit adds the NVMe read command 2 to the information cache. At the same time, the PRP receiving circuit receives the PRP index of the NVMe read command 1 and updates the entry of the NVMe read command 1 in the information cache with the PRP index of the NVMe read command 1.

[0125] In the T2 cycle, the NVMe read command receiving circuit adds the NVMe read command 3 to the information cache. At the same time, the PRP receiving circuit receives the PRP index of the NVMe read command 2, updates the entry of the NVMe read command 2 in the information cache with the PRP index of the NVMe read command 2, and the DMA command generation circuit receives the storage command completion message of the NVMe read command 1, and generates the DMA command 1 ( Fig.11 DMA1).

[0126] During the T3 cycle, the PRP receiving circuit receives the PRP index of the NVMe read command 3, and updates the entry of the NVMe read command 3 in the information cache with the PRP index of the NVMe read command 3. At the same time, the DMA command generation circuit generates DMA command 2 (DMA2) in response to receiving the storage command completion message of the NVMe read command 2.

[0127] During the T4 cycle, the DMA command generation circuit generates DMA command 3 (DMA3) in response to receiving the storage command completion message of NVMe read command 3.

[0128] According to the read initiation circuit of the embodiment of the present application, the DMA command generation circuit generates a DMA command based on the PRP index, and is not affected by other factors such as the order of the PRP index in the NVMe command. Even if the PRP indexes received by the DMA command generation circuit successively belong to different NVMe commands, the PRP indexes received successively belong to the same NVMe command but the order is different from the order described in the NVMe command, or the PRP indexes of other NVMe commands are received before all the PRP indexes of an NVMe command are completely received, the DMA command generation circuit processes and generates a DMA command in the manner provided in the embodiment of the present application.

[0129] Fig.12 A structural schematic diagram of a read initiation circuit according to yet another embodiment of the present application is shown.

[0130] See also Fig.12 , NVMe read commands A-NVMe read commands D are recorded in the information cache. And currently, NVMe read command E is received. In response to receiving NVMe read command E, the NVMe read command receiving circuit adds it to the information cache (recorded as (NVMe read command E) in brackets). The NVMe read command receiving circuit also sends NVMe read command E to the backend module.

[0131] At the same time, the control component completes the operation of obtaining the PRP entry for the NVMe read command D, and provides the PRP index indicating the cache address storing the PRP entry (recorded as PRP index D to reflect its association with the NVMe read command D) to the PRP receiving circuit. In response, the PRP receiving circuit updates the NVMe read command D in the information cache with the received PRP index D. It can be understood that the timing of receiving the PRP index D does not need to be limited, and even if the PRP index D is received while receiving the NVMe read command E, the read command receiving circuit and the PRP receiving circuit can work simultaneously to process the reception of the NVMe read command E and the reception of the PRP index D respectively.

[0132] Still as an example, while receiving the PRP index D, the back-end module also provides the DMA generation circuit with a storage command completion message C. The storage command completion message C is associated with the NVMe read command C. The DMA command generation circuit generates a corresponding DMA command (referred to as DMA command C) in response to receiving the storage command completion message C, and provides it to the DMA transmission circuit to initiate DMA transmission. Since each component of the read initiation circuit according to the embodiment of the present application is an independent hardware circuit, each circuit can work separately at the same time, and the operation or occupation of one circuit will not affect the operation of another circuit.

[0133] The DMA transmission circuit also concurrently processes multiple DMA commands at the same time. Still as an example, while the DMA transmission circuit initiates the processing of DMA command C, DMA command B is processed and completed, and the corresponding DMA command processing completion message B is provided to the completion message processing circuit. DMA command processing completion message B is associated with NVMe read command B. In response, the completion message processing circuit updates the NVMe read command B in the information cache according to the DMA command processing completion message B, for example, updates its DMA command count value.

[0134] The completion message processing circuit is also responsive to identifying that all DMA commands of the NVMe read command A have been executed, and sends an NVMe read command A completion message to the host through the host. In the case where there is only a single instance of the completion message processing circuit, the generation of the NVMe read command A completion message and the processing of the DMA command processing completion message B are performed separately. In response to sending the NVMe read command A completion message to the host, the completion message processing circuit also deletes the NVMe read command A (the corresponding entry) from the information cache.

[0135] The NVMe read command receiving circuit operates in response to receiving the NVMe read command, and is not affected by the operating status of other circuits or the actions of other messages being received or sent. Similarly, the PRP receiving circuit operates in response to receiving the PRP index, the DMA command generating circuit operates in response to receiving the storage command completion message, and the completion message processing circuit operates in response to receiving the DMA command processing completion message.

[0136] The back-end module generates one or more storage commands for each NVMe read command received. Storage commands corresponding to different NVMe read commands are also processed in parallel and independently, so that the order in which the read command receiving circuit provides NVMe read commands to the back-end module has no strict correspondence with the order in which the back-end module provides storage command completion messages to the DMA command generation circuit. Thus, in the case where NVMe read command C is received first and then NVMe read command D is received, all DMA commands corresponding to NVMe read command D may be processed before all DMA commands of NVMe read command C, so that NVMe read command D in the information cache may be deleted before NVMe read command C. The read initiation circuit according to the embodiment of the present application supports such a situation to occur without limiting the order in which the back-end module / DMA transmission circuit provides storage command completion messages / DMA command processing completion messages to it. For similar reasons, the read command initiation circuit also does not limit the order in which the control component provides PRP indexes to it. This avoids blocking the processing of other NVMe read commands due to errors in a certain stage of a single NVMe read command (for example, an error occurs when reading data from an NVM chip according to a certain storage command, which causes a long data recovery process).

[0137] Figure 3-Figure 12 The illustrated embodiment uses the PRP index as an example to illustrate the read initiation circuit. The processing of the PRP index by the read initiation circuit is also applicable to the SGL index, which will not be described in detail in this application.

[0138] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A read initiation circuit, characterized in that: include: Information buffering, DMA command generation circuitry, and completion message processing circuitry; In response to receiving an NVMe read command or addressing information, updating the information cache with the NVMe read command or addressing information; The DMA command generation circuit is coupled to the DMA transmission circuit. In response to receiving a storage command processing completion message, the DMA command generation circuit obtains address location information corresponding to the storage command completion message, generates a DMA command based on a storage device cache address provided by the storage command completion message and a host memory address indicated by the address location information, and provides the DMA command to the DMA transmission circuit. The completion message processing circuit is coupled to the DMA transmission circuit and the information cache. In response to receiving a first message sent by the DMA transmission circuit, the completion message processing circuit updates the entry associated with the NVMe read command corresponding to the first message in the information cache, and the first message indicates that the DMA command processing performed by the DMA transmission circuit is completed.

2. The read initiation circuit according to claim 1, characterized in that: The DMA command generation circuit is also coupled to the completion message processing circuit, and the DMA command generation circuit provides the generated DMA command to the completion message processing circuit.

3. The read initiation circuit according to claim 1 or 2, characterized in that: The read initiation circuit further includes an information receiving circuit, and the information receiving circuit is coupled to the information cache; In response to receiving an NVMe read command, the information receiving circuit adds an entry associated with the NVMe read command in the information cache; or in response to receiving addressing information, updates an entry associated with the NVMe read command to which the addressing information belongs in the information cache.

4. The read initiation circuit according to claim 3, characterized in that: In response to receiving an NVMe read command, the information receiving circuit generates a storage command and provides the storage command to a back-end module, wherein the storage command instructs the back-end module to process data movement from the storage device flash memory to the storage device cache according to the storage command.

5. The read initiation circuit according to any one of claims 1 to 4, characterized in that: In response to receiving a storage command processing completion message, the DMA command generation circuit updates an entry associated with the NVMe read command corresponding to the storage command processing completion message in the information cache.

6. The read initiation circuit according to any one of claims 1 to 5, characterized in that: Multiple entries are cached in the information cache, different entries correspond to different NVMe read commands, and all addressing information, all DMA commands, and all first messages associated with the same NVMe read command correspond to the same entry in the information cache.

7. The read initiation circuit according to any one of claims 1 to 6, characterized in that: The addressing information includes a PRP index or an SGL index; the address location information includes one or more of the following: a PRP entry, an SGL entry, and a host memory address determined according to the PRP index or the SGL index.

8. The read initiation circuit according to any one of claims 1 to 7, characterized in that: The read initiation circuit further includes an error handling circuit coupled to the completion message processing circuit; The completion message processing circuit generates a second message in response to identifying a DMA command processing error indicated by the first message, and provides the second message to the error handling table circuit; or, the completion message processing circuit generates a third message in response to identifying an NVMe read command processing error, and provides the third message to the error handling circuit; wherein the second message is used to indicate the DMA command processing error indicated by the first message, and the third message is used to indicate the NVMe read command processing error; The error processing circuit receives the second message or the third message, and processes the second message or the third message.

9. The read initiation circuit according to any one of claims 1 to 8, characterized in that: The read initiation circuit further includes an address location information acquisition circuit, and the address location information acquisition circuit is coupled to the DMA command generation circuit; In response to receiving a storage command processing completion message, the DMA command generation circuit obtains addressing information indicated by an NVMe read command corresponding to the storage command processing completion message, and provides the addressing information to the address location information acquisition circuit; In response to receiving the addressing information, the address location information acquisition circuit acquires address location information corresponding to the addressing information, and provides the acquired address location information to the DMA command generation circuit.

10. The read initiation circuit according to any one of claims 1 to 9, characterized in that: The read initiation circuit also includes a plurality of flow control circuits; Each of the flow control circuits is coupled to the information cache, and each of the flow control circuits controls whether to update the information cache with the NVMe read command or addressing information in response to receiving the NVMe read command or addressing information.

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