Leak compensated dynamic latch

Abstract

The invention provides a dynamic latch with leakage compensation. Some embodiments include an input stage of a latch to receive input data information and clock information; a memory node coupled to the input stage to store information based on the input data information; an output stage coupled to the latch of the memory node, the output stage comprising an output node to provide output data information based on information stored at the memory node; a first circuit to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit to provide a second circuit path between the memory node and a second node in the input stage.

Description

Technical Field

[0001] Embodiments described herein relate to memory circuits.Some embodiments relate to dynamic latches. Background Art

[0002] Latches are widely used in many electronic devices or systems, such as computers, tablet devices, cellular phones, and the Internet of Things (IoT). Latches are memory circuits for storing data. Different types of latches include dynamic latches and static latches. These latches store data in the form of electric charge. Compared with typical dynamic latches, typical static latches can maintain the value of the stored data for a relatively long time interval. In a typical static latch, as long as power is provided to the static latch, the charge reflecting the value of the stored data can remain relatively unchanged. Compared with typical static latches, typical dynamic latches can operate at a higher speed. However, typical dynamic latches can only maintain the charge (reflecting the value of the stored data) for a shorter time interval. Therefore, devices containing dynamic latches often have refresh cycles (refresh operations) to periodically refresh (e.g., update) the charge storage in the dynamic latch so that the stored data remains valid in a specific (predetermined) time interval. Static latches can be used instead of dynamic latches to avoid refresh cycles. However, the size of a static latch is usually larger than that of a dynamic latch. The larger size may cause the static latch to consume more power than the dynamic latch. Thus, in devices where the operating speed, device area, power consumption, or a combination of these factors are the main concerns of the device, a dynamic latch is usually more preferred than a static latch. With the advancement of technology, the size of some dynamic latches can be extremely small. At a certain small size, charge leakage may occur at the transistor forming the dynamic latch. Charge leakage may cause the data stored in the dynamic latch to become invalid. Before the leakage charge causes the stored data to become invalid, a higher refresh rate can be used to keep the stored data valid. However, a higher refresh rate may not be suitable for some devices. In addition, a higher refresh rate may cause increased power consumption. Summary of the invention

[0003] One aspect of the present disclosure provides a device. The device includes: an input stage of a latch, used to receive input data information and clock information; a memory node coupled to the input stage, used to store data information based on the input data information; an output stage of the latch coupled to the memory node, the output stage including an output node, used to provide output data information based on the data information stored at the memory node; a first circuit, used to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit, used to provide a second circuit path between the memory node and a second node in the input stage.

[0004] Another aspect of the present disclosure provides a device. The device includes: an input stage of a latch, used to receive input data information and clock information, the input stage coupled to a first power supply node and a second power supply node; a memory node coupled to the input stage, used to store data information based on the input data information; an output stage of the latch coupled to the memory node, the output stage including an output node, used to provide output data information based on the data information stored at the memory node; a first circuit, used to provide a first circuit path between the memory node and the first power supply node; a second circuit, used to provide a second circuit path between the memory node and the second power supply node; and a third circuit, used to provide control information to the first circuit and the second circuit based on the information stored at the memory node.

[0005] Another aspect of the present disclosure provides a method. The method includes: receiving input data information at a data input node of the dynamic latch during a first state of the dynamic latch; storing data information at a node of the dynamic latch during the first state, the value of the data information at the node being based on the value of the input data information; and activating a circuit path coupled between the node and a power supply node during a second state of the dynamic latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A device in the form of a dynamic latch according to some embodiments described herein is shown.

[0007] Figure 2 Another device in the form of a dynamic latch according to some embodiments described herein is shown.

[0008] Figure 3 Another device in the form of a dynamic latch according to some embodiments described herein is shown.

[0009] Figure 4 Some embodiments described herein include Figure 1 , Figure 2 or Figure 3 A system (eg, machine) of dynamic latches.

[0010] Figure 5 The flowchart of FIG. 1 illustrates a method of operating a device according to some embodiments described herein. DETAILED DESCRIPTION

[0011] The technology described herein relates to dynamic latches and compensation for charge leakage in dynamic latches. The described dynamic latch includes a relatively small number of transistors, which allows its size to be relatively small and suitable for high-speed operation in a device or system including the described dynamic latch. The described latch includes a circuit that compensates for charge leakage during a hold state of the dynamic latch. Compared to some conventional dynamic latches, this compensation allows the dynamic latch to keep the value of data information stored in the dynamic latch valid for a relatively long time interval. This allows the device or system including the latch to have a lower data refresh rate, thereby reducing power consumption in such a device and system. The following will refer to Figures 1 to 5 These and other improvements and advantages of the described techniques are discussed in more detail.

[0012] Figure 1 A device in the form of a latch 101 according to some embodiments described herein is shown. The latch 101 is a dynamic latch. The latch 101 can be operated to receive data information D at a node (e.g., a data input node) 110, and provide (transfer) the received data information D as data information Q to a node (e.g., a data output node) 112. The data information D and the data information Q can be regarded as input data information and output data information, respectively. The latch 101 can also store data information X at a node (e.g., a memory node) 131. The node 131 can be constructed as a charge storage node (e.g., a memory node) to store data information X at the node 131 in the form of a charge. The value of the information X is based on the value of the data information D. Each of the data information D, the data information X, and the data information Q can take the form of a bit. The latch 101 can receive one bit of data information D at a time at the node 110. The latch 101 can provide one bit of data information Q at a time at the node 112. The latch 101 may store one bit of data information X at a time at the node 131 .

[0013] like Figure 1 As shown, latch 101 may include an input stage (e.g., input driver stage) 130, a node (e.g., storage node) 131 and an output stage (e.g., output driver stage) 140, circuit 151, circuit 152, clock node 121, clock node 122, power supply node 190 and power supply node 199. Input stage 140 may include transistors P1, P2, N1 and N2. Output stage 140 may include inverter 141. Power supply node 190 may be coupled to (e.g., may receive) voltage V1 (e.g., power supply voltage Vcc). Power supply node 199 may be coupled to (e.g., may receive) voltage V0 (e.g., power supply voltage Vss), which may be 0V (e.g., ground potential).

[0014] like Figure 1 As shown, transistors P1, P2, N1, and N2 can be coupled in series with each other between supply nodes 190 and 199. Transistors P1, P2, N1, and N2 can have respective gates G1, G3, G4, and G2. Non-gate terminals (e.g., sources and drains) of transistors P1, P2, N1, and N2 can be coupled to each other at respective nodes 131, 132, and 133. Figure 1 As shown, node (e.g., memory node) 131 is between transistors N1 and P2, node 132 is between transistors P1 and P2, and node 133 is between transistors N1 and N2. Each of nodes 131, 132, and 133 may be a common node shared (coupled to) by the source and drain of two corresponding transistors (e.g., two adjacent transistors) among transistors P1, P2, N1, and N2. In this specification, the source and drain of a transistor are used interchangeably.

[0015] Transistors P1 and P2 may have transistor types different from transistors N1 and N2. For example, transistors P1 and P2 may include p-type transistors, while transistors N1 and N2 may include n-type transistors. An example of a p-type transistor includes a p-channel metal oxide semiconductor (PMOS) transistor. An example of an n-type transistor includes an n-channel metal oxide semiconductor (NMOS) transistor. Transistors P1, P2, N1, and N2 may be formed using a complementary metal oxide semiconductor (CMOS) process. Thus, in one example, transistors P1, P2, N1, and N2 may include CMOS transistors. This specification uses PMOS and NMOS transistors as examples. However, other types of transistors may be used.

[0016] like Figure 1 As shown, inverter 141 may include an input node coupled to node 131 and an output node coupled to node 112. Inverter 141 may include a CMOS transistor (not shown).

[0017] Circuit 151 may include transistor P3 (eg, only one transistor P3) coupled to nodes 131, 132, and 112. Transistor P3 may be coupled in parallel with transistor P2 between nodes 131 and 132. Figure 1 As shown, transistor P3 may include a p-type transistor (eg, PMOS). Transistor P3 may include a terminal P3 coupled (eg, directly coupled) to node 131. D(eg, drain), coupled (eg, directly coupled) to terminal P3 of node 132 S (eg, source), and a gate P3 coupled (eg, directly coupled) to the node 112 G The gate of transistor P3 is G The latch 101 may be controlled (e.g., turned on or off) by the value (e.g., the value of a bit) of the data information Q (at the node 112), and the value of the data information Q is based on the value (e.g., the value of a bit) of the data information X (at the node 131). The latch 101 may include a circuit path (e.g., a current path) 151', which includes the transistor P3. The circuit path 151' is a portion of a circuit path (e.g., a current path from the node 131 to the power supply node 190) coupled between the node 131 and the power supply node 190. Thus, as Figure 1 As shown, circuit 151 may provide a circuit path (eg, circuit path 151 ′) between node 131 and node 132 , wherein the circuit path (eg, circuit path 151 ′) is a portion of a path between node 131 and a power supply node 190 .

[0018] Circuit 152 may include transistor N3 (eg, only one transistor N3) coupled to nodes 131, 133, and 112. Transistor N3 may be coupled in parallel with transistor N1 between node 131 and node 133. Figure 1 As shown, transistor N3 may include an n-type transistor (eg, NMOS). Transistor N3 may include an N3 coupled (eg, directly coupled) to node 131. D (eg, drain), a terminal N3 coupled (eg, directly coupled) to the node 132 S (eg, source), and a gate N3 coupled (eg, directly coupled) to the node 112 G The gate of transistor N3 is G The gate N3 of transistor N3 can be controlled (e.g., turned on or off) by the value (e.g., bit value) of data information Q (at node 112), and the value of data information Q is based on the value (e.g., bit value) of data information X (at node 131). G and the gate N3 of transistor P3 G The latch 101 may include a circuit path (e.g., a current path) 152', which includes transistor N3. The circuit path 152' is a portion of a circuit path (e.g., a current path from node 131 through transistors N3 and N2 to power supply node 199) coupled between node 131 and power supply node 199. Thus, as Figure 1As shown, circuit 152 may provide a circuit path (eg, circuit path 152 ′) between node 131 and node 133 , wherein the circuit path (eg, circuit path 152 ′) is a portion of a path between node 131 and supply node 199 .

[0019] Thus, in Figure 1 In the example of FIG. 1 , the circuits 151 and 152 of the latch 101 may include a relatively small number of transistors (e.g., only two transistors P3 and N3). The small number of transistors allows the overall size of the latch 101 to be relatively small, suitable for inclusion in a circuit (e.g., a high-speed circuit) in a device or system including the described latch 101. Such circuits may include, or may be part of, a clock distribution network (e.g., a clock spine), a data path, a register circuit, a timing circuit, and other types of circuits. In addition, due to its small size, the latch 101 may consume a relatively small amount of power.

[0020] like Figure 1 As shown, clock nodes 121 and 122 can be coupled to gates G2 and G3 of transistors P2 and N1, respectively. Clock node 121 can be configured to receive a clock signal CLK. Clock node 122 can be configured to receive a clock signal CLK*. Clock signal CLK* is an inversion (inverted version) of clock signal CLK, and vice versa. Clock signals CLK and CLK* can have the same frequency. Clock signals CLK and CLK* are clock information. In latch 101, clock information (e.g., clock signals CLK and CLK*) is different from data information (e.g., input data information D) because clock information is used as timing information (e.g., one or more timing signals) to receive data information and store data information.

[0021] Figure 1 2 shows a waveform showing the timing relationship between the clock signals CLK and CLK*. Figure 1 As shown, the clock signal CLK may have two different phases: a phase associated with CLK="0" and a phase associated with CLK="1". The term CLK="1" means that the clock signal CLK has a higher level (e.g., a level corresponding to a logic "1" or a binary "1"). The term CLK="0" means that the clock signal CLK has a lower level (e.g., a level corresponding to a logic "0" or a binary "0". As shown in FIG. Figure 1 As shown, the clock signal CLK* may also have two different phases: a phase associated with CLK*=“0” and a phase associated with CLK*=“1”. The term CLK*=“0” means that the clock signal CLK* has a low level (e.g., a level corresponding to a logical “0” or a binary “0”). Figure 1As shown in the waveforms of the clock signals CLK and CLK* in , for a given time interval (e.g., half of the period of the clock signal CLK), the clock signals CLK and CLK* have opposite phases, so that when CLK=“1”, CLK=“0”, and when CLK=“0”, CLK*=“1”.

[0022] Latch 101 can use clock signal CLK to control (e.g., turn on or off) transistor N1. For example, when CLK = "1", it turns transistor N1 on (e.g., conducts current). When CLK = "0", it turns transistor N1 off (e.g., does not conduct current). Latch 101 can use clock signal CLK* to control (e.g., turn on or off) transistor P2. For example, when CLK* = "0", it turns transistor P2 on. When CLK* = "1", it turns transistor P2 off. Since clock signals CLK and CLK* have opposite phases during a specific time interval, transistors P2 and N1 can be turned on during the same time interval and turned off during the same time interval.

[0023] Thus, when CLK=“1” (CLK*=“0”), transistors P2 and N1 are turned on. When transistors P2 and N1 are turned on, a circuit path (e.g., a current path) may be formed between node 131 and power supply node 190 or between node 131 and power supply node 199, depending on the value of data information D received at node 110 (provided to node 110). When CLK=“0” (CLK*=“1”), transistors P2 and N1 are turned off. When transistors P2 and N1 are turned off, no circuit path is formed between node 131 and power supply node 190 or between node 131 and power supply node 199, regardless of the value of data information D.

[0024] The data information (e.g., input data information) D may include information bits that can be received one bit at a time based on the timing (e.g., frequency) of the clock signals CLK and CLK*. Each bit of the data information may have a binary value of "0" (binary zero) or "1" (binary one). In this specification, the term D="0" means that the bit of the data information D received (provided to the node 110) at a specific time has a value of binary zero ("0"). The term D="1" means that the bit of the data information D received (provided to the node 110) at a specific time has a value of binary one ("1"). Figure 1 An example is shown where the data information D (received at the node 110) has four bits, with four corresponding binary values ​​"1, 1, 0, 1".

[0025] The node 131 may store the data information X based on the data information D received at the node 110. The node 131 may store the data information X one bit at a time. The value of the bit stored at the node 131 is opposite to (an inverted version of) the value of the bit of the data information D. Thus, based on the above example in which the values ​​of the four bits of the data information D received at the node (one bit is received at a time) are "1, 1, 0, 1", the values ​​of the four corresponding bits (one bit is stored at a time) stored at the node 131 are "0, 0, 1, 0", as shown in FIG. Figure 1 In this specification, the term X=“0” means that the bit of data information X stored (held) at the node 131 at a specific time has a value of binary zero (“0”). The term X=“1” means that the bit of data information X stored (held) at the node 131 at a specific time has a value of binary one (“1”).

[0026] Node 112 may provide (e.g., output) data information (e.g., output data information) Q based on data information X at node 131. Node 131 may provide data information X one bit at a time. The bit value provided at node 112 is opposite to (an inverted version of) the bit value of data information X and is the same as the bit value at node 110. Thus, in the above example where latch 101 receives four bits with values ​​of "1, 1, 0, 1", the values ​​of the four corresponding bits provided at node 112 are also "1, 1, 0, 1", as shown in FIG. Figure 1 As shown. In this specification, the term Q = "0" means that the bit of data information Q provided (output) at the node 112 at a particular time has a value of binary zero ("0"). The term Q = "1" means that the bit of data information Q provided (output) at the node 112 at a particular time has a value of binary one ("1").

[0027] Latch 101 may include a write state and a hold state. When CLK = "1" (CLK * = "0"), latch 101 may enter the write state (e.g., after exiting the hold state). Thus, transistors P2 and N1 are turned on in the write state. Transistors P1, P2, N1, and N2 may form an input driver to drive data information D as data information X from node 110 to node 131 during the write state. During the hold state, latch 101 may hold data information X at node 131.

[0028] During the write state, the latch 101 may receive a bit of data information D at the node 110, and store (e.g., write) the received bit as data information X at the node 131 in the form of charge (charge amount). The bit of data information D received at the data input node may have a value of "0" or "1" (i.e., D="0" or D="1"). The bit value of the data information X at the node 131 is based on the bit value of the data information D (e.g., has a value opposite thereto). For example, if D="0", then X="1". In another example, if D="1", then X="0".

[0029] When CLK=“0” (CLK*=“1”), latch 101 may enter a hold state (e.g., after exiting a write state). During the hold state, transistors P2 and N1 are turned off. During the hold time, latch 101 may keep (retain) the value of the bit of data information X stored at node 131 (e.g., X=“0” or X=“1”) valid until the next write state (or the next refresh cycle).

[0030] The latch 101 may be included in a device or system (not shown) that may perform a refresh cycle (refresh operation) so that the value of the bit of the data information X stored at the node 131 remains valid in a specific time interval (e.g., in at least one cycle of the clock signal CLK). The refresh cycle may be performed at a refresh rate to maintain (or refresh) the amount of charge at the node 131 so that the amount of charge at the node 131 can reflect the value (expected value) of the bit stored in the specific time interval. The specific time interval may be the time interval between one refresh cycle and the next refresh cycle. The power consumption may be proportional to the refresh rate, so that the higher the refresh rate, the higher the power consumption, and the lower the refresh rate, the lower the power consumption.

[0031] The following description presents some example operations of the latch 101 during a write state and a hold state, wherein different values ​​of data information D (eg, D="1" and D="0") are provided to the input node 110 at different times.

[0032] The following write state example assumes that during the write state of latch 101, D = "1" is received at node 110. In this example (e.g., the current write state), latch 101 receives a bit of D = "1" (at node 110) and stores the received bit as a bit of X = "0" (at node 131). Latch 101 provides (e.g., outputs) a bit of Q = "1" at node 112.

[0033] In this example, latch 101 operates as follows in the write state (D="1"). In the write state, CLK="1" and CLK*="0". CLK*="0" turns on transistor P2. D="1" (assumed in this example) turns off transistor P1. Thus, no conduction path through transistors P1 and P2 is formed between node 131 and power supply node 190. In the write state, CLK="1" turns on transistor N1. D="1" turns on transistor N2. The turned-on transistors N1 and N2 form a conduction path that couples node 131 to power supply node 199. Node 131 discharges to power supply node 199 through transistors N1 and N2. The voltage V0 (e.g., ground) at power supply node 199 corresponds to "0". Thus, in this example, node 131 has X="0" (e.g., the current write state).

[0034] In this example, latch 101 may operate as follows in a hold state (X="0"). In the hold state, CLK="0" and CLK*="1". CLK*="1" turns transistor P2 off. CLK="0" turns transistor N1 off. Thus, node 131 is isolated (e.g., electrically isolated) from power supply node 190 and power supply node 199. In this way, node 131 can maintain a value of X="0". However, in some cases, the value of X="0" may become X="1". For example, in the hold state in this example, D="0" at node 110 may occur. This may be because in the current hold state, when CLK="0", the data information D returns (flips back) to its previous value (e.g., flipped back value) D="0" after (e.g., immediately after) the current write state (D="1"). In the current hold state, D="0" (e.g., flipped back value) causes transistor P1 to turn on. Due to charge leakage (e.g., from smaller node technology, or temperature effects, or both), transistor P2 (in the current hold state) may leak charge and begin charging node 131 through transistor P1, which is turned on. This may change (e.g., increase) the charge at node 131 (which has X="0" in the current hold state). Depending on the parasitic capacitance associated with node 131 (which is relatively low), if CLK="0" remains unchanged in the current hold state, the change (e.g., increase) in charge at node 131 (e.g., caused by charge leakage at transistor P2) may change X="0" (the expected value to be held) to X="1" (an invalid value). For example, if the next write state (or the next refresh cycle) does not occur before the valid X="0" becomes invalid X="1", CLK="0" may remain unchanged. The change from X="0" to X="1" also causes Q="1" (the expected value) to become Q="0" (an invalid value). The situation described here (in which X="0" may become X="1", causing the data information to be invalid) assumes that circuit 152 is excluded from latch 101 (not included in latch 101).

[0035] Circuit 152 can operate to prevent the above situation (e.g., X=“0” becomes X=“1”) from occurring, so as to maintain the validity of the data information X stored at node 131 for a relatively longer time period than a similar conventional dynamic latch that does not include circuits such as circuit 152. Figure 1 As shown, because D = "0" (flip value) in the current hold state, transistor N2 is turned off. The turned-off transistor N2 may not provide a balancing force to compensate for the charge leakage caused by transistor P2 (described above). However, circuit 152 can operate to provide such compensation. Figure 1 As shown, gate N3 GCoupled to node 112, where Q = "1" (the current write state and hold state). Q = "1" causes transistor N3 to turn on and activate circuit path 152' (e.g., allowing circuit path 152' to conduct current). This provides a path for the amount of charge discharged from node 131 (through transistor N3). Due to the charge leakage caused by transistor P2, this amount of charge can at least match the amount of charge from supply node 190 to node 131 (through transistors P1 and P2). Therefore, the amount of charge at node 131 can be maintained close to its expected value (e.g., the value corresponding to X = "0" in the current hold state) until the next write state or the next refresh cycle.

[0036] Thus, as described above, compared to similar conventional dynamic latches, including circuit 152 allows latch 101 to compensate for changes (e.g., increases) in the amount of charge that may occur at node 131 (due to charge leakage through transistors P1 and P2), so that valid data information X at node 131 and valid data information Q at node 112 can be maintained for a relatively longer time interval. Compared to similar conventional dynamic latches, this can improve the performance of latch 101 and a device or system including latch 101 (e.g., a higher data rate). In addition, the longer data retention time of latch 101 can make it possible to use it to replace some conventional static latches, which typically consume more power than dynamic latches. Thus, if latch 101 is used in a device or system to replace some conventional static latches, including circuit 152 can allow latch 101 to save more power. In addition, including circuit 152 also provides an option for a device or system including latch 101 to have a relatively low refresh rate, because the data retention time at node 131 can be relatively longer than a similar conventional dynamic latch. The lower refresh rate can result in lower power consumption in latch 101 and a device or system including latch 101 compared to a similar conventional dynamic latch.

[0037] The above example assumes that D = "1" is received at node 110 during the write state of latch 101. However, if D = "0" is received at node 110, latch 101 can enter another write state (and another hold state) and operate in a similar but opposite manner, thereby providing similar improvements and benefits as described above.

[0038] The following write state example assumes that during the write state of latch 101, D = "0" is received at node 110. In this example (e.g., the current write state), latch 101 stores D = "0" (received at node 110) as X = "1" (stored at node 131) and provides (e.g., outputs) Q = "0" at node 112 (i.e., Q = "0" and D = "0" in this example).

[0039] In this example, latch 101 operates as follows in the write state (D="0"). In the write state, CLK="1" and CLK*="0". CLK*="1" turns on transistor N1. D="0" (assumed in this example) turns off transistor N2. Thus, no conduction path through transistors N1 and N2 is formed between node 131 and power supply node 199. CLK*="0" turns on transistor P2. D="0" turns on transistor P1. The turned-on transistors P1 and P2 form a conduction path that couples node 131 to power supply node 190. Node 131 charges power supply node 190 through transistors P1 and P2. The voltage V1 (e.g., voltage Vcc) at power supply node 190 corresponds to "1". Thus, in this example, node 131 has X="1" (e.g., current write state).

[0040] In this example, latch 101 may operate as follows in the hold state (X="1"). In the hold state, CLK="0" and CLK*="1". CLK*="1" turns off transistor P2. CLK="0" turns off transistor N1. Thus, node 131 is isolated (e.g., electrically isolated) from power supply node 190 and power supply node 199. In this way, node 131 can maintain the value of X="1". However, in some cases, the value of X="1" may become X="0". For example, in the hold state in this example, D="1" at node 110 may appear. This may be because in the current hold state, when CLK="0", the data information D returns (flips back) to its previous value (flipped back value) D="1" after (e.g., immediately after) the current write state (D="0"). In the current hold state, D="1" (e.g., flipped back value) turns on transistor N2. Due to charge leakage (e.g., from smaller node technology, or temperature effects, or both), transistor N1 (in the current hold state) may leak charge and begin discharging node 131 through transistor N2, which is turned on. This may change (e.g., reduce) the charge at node 131 (which has X="1" in the current hold state). Depending on the parasitic capacitance associated with node 131 (which is relatively low), if CLK*="1" remains unchanged in the current hold state, the change (e.g., decrease) in charge at node 131 (e.g., caused by charge leakage at transistor N1) may change X="1" (the expected value to be held) to X="0" (an invalid value). For example, if the next write state (or the next refresh cycle) does not occur before the valid X="1" becomes invalid X="0", then CLK*="1" may remain unchanged. The change from X="1" to X="0" also causes Q="0" (the expected value) to become Q="1" (an invalid value). The situation described here (in which X="1" may become X="0", resulting in invalid data information) assumes that circuit 151 is excluded from latch 101 (not included in latch 101).

[0041] Circuit 151 can operate to prevent the above situation (e.g., X=“1” becomes X=“0”) from occurring, so as to maintain the validity of data information X stored at node 131 for a relatively longer time period than a similar conventional dynamic latch that does not include circuits such as circuit 151. Figure 1 As shown, because D = "1" (flip value) in the current hold state, transistor P1 is turned off. The turned-off transistor P1 may not provide a balancing force to compensate for the charge leakage caused by transistor N1 (described above). However, circuit 151 can operate to provide such compensation. Figure 1 As shown, gate P3 GCoupled to node 112, where Q = "0" (the current write state and hold state). Q = "0" causes transistor P3 to turn on and activate circuit path 152' (e.g., enables circuit path 152' to conduct current). This provides a path for the amount of charge to go to node 131 (through transistor P3). Due to the charge leakage caused by transistor N1, this amount of charge can at least match the amount of charge discharged from node 131 to supply node 199 (through transistors N1 and N2). Therefore, the amount of charge at node 131 can be maintained close to its expected value (e.g., the value corresponding to X = "1" in the current hold state) for a long enough time until the next write state or the next refresh cycle.

[0042] Thus, as described above, compared to similar conventional dynamic latches, including circuit 151 enables latch 101 to compensate for changes (e.g., increases or decreases) in the amount of charge that may occur at node 131 (due to charge leakage through transistors N1 and N2), thereby enabling valid data information X at node 131 and valid data information Q at node 112 to be maintained for a relatively longer time interval. Compared to similar conventional dynamic latches, this can improve the performance of latch 101 and a device or system including latch 101 (e.g., increase the data rate). In addition, the longer data retention time of latch 101 can enable it to be used to replace some conventional static latches, which typically consume more power than dynamic latches. Thus, if latch 101 is used in a device or system to replace some conventional static latches, including circuit 151 can allow latch 101 to save more power. In addition, including circuit 151 also provides an option for a device or system including latch 101 to have a relatively low refresh rate, because the data retention time at node 131 can be relatively longer than a similar conventional dynamic latch. The lower refresh rate can result in lower power consumption in latch 101 and a device or system including latch 101 compared to a similar conventional dynamic latch.

[0043] Figure 2 2 shows a device in the form of a latch 201 according to some embodiments described herein. The latch 201 is a dynamic latch. The latch 201 may include some Figure 1 Elements similar (or identical) to elements of latch 101 of FIG. Similar or identical elements between latch 101 and 201 are given the same labels. For example, Figure 1 Like latch 101, Figure 2The latch 201 in FIG. 1 may include an input stage 130 (e.g., transistors P1, P2, N1, and N2) and an output stage (e.g., inverter 141). For simplicity, similar or identical elements between latches 101 and 201 are not repeatedly described. The differences between latches 101 and 201 include circuit 251, circuit 252, and circuit 230 of latch 201.

[0044] like Figure 2 As shown, circuit 251 can be coupled to node (e.g., memory node) 131, power supply node 190, and circuit 230. Circuit 230 may include inverter 231, which may include a CMOS transistor (not shown). Inverter 231 may include an input node coupled to node 131, and an output node coupled to node 231' in circuits 251 and 252. Node 231' may be a common node coupled to circuits 251 and 252. For example, node 231' may be a common gate of transistors P23 and N23.

[0045] Circuit 251 may be coupled to node 131, power supply node 190, and circuit 230. Circuit 251 may include transistor (e.g., PMOS transistor) P23 and current generator (e.g., current source) 290. Transistor P23 and current generator 290 may form (or may be part of) a circuit path (e.g., current path) 251′ between node 131 and power supply node 190. Current generator 290 may generate (e.g., may source) current I on circuit path 251′. P The current generator 290 may be configured as a relatively weak current generator so that the current I P As described below, weak current generator 290 allows normal operation of latch 201 during the write state (eg, when D="1").

[0046] Circuit 252 may be coupled to node 131, power supply node 199, and circuit 230. Circuit 252 may include transistor (e.g., NMOS transistor) N23 and current generator (e.g., current sink) 299. Transistor N23 and current generator 299 may form (or may be part of) a circuit path (e.g., current path) 252′ between node 131 and power supply node 199. Current generator 299 may generate (e.g., may sink) current I on circuit path 252′. N The current generator 299 can be configured as a relatively weak current generator so that the current I N As described below, weak current generator 299 allows normal operation of latch 201 during the write state (eg, when D="0").

[0047] Latch 201 may include a write state and a hold state similar to latch 101. In the write state in latch 201, data information D may be received at node 110 and may be stored as data information X at node 131. In the hold state, latch 201 may hold data information X and operate to compensate for charge leakage that may occur at node 131 so as to keep the value of data information X at node 131 valid for a specific time interval (e.g., based on a refresh rate).

[0048] like Figure 2 As shown, the input node of inverter 231 can receive data information X at node 131. Inverter 231 can provide control information Qi at its output node, which is coupled to node 231'. Thus, the value of control information Qi is opposite to the value of data information X at node 131. For example, if X = "0", then Qi = "0". If X = "1", then Qi = "1"

[0049] Circuit 230 operates to provide control information to circuits 251 and 252 based on information X stored at node 131. For example, circuit 230 (including inverter 231) is operable to select which circuit path (e.g., current path) between circuit paths 251' and 252' is to be used in order to compensate for charge leakage that may occur at node 131 during the hold state. The selection can be based on the value of data information X at node 131, which can be used as feedback information for compensation. Since control information Qi (at node 231') is based on information X (at node 131), control information Qi can also be regarded as feedback information (for compensation) to control circuit 251 (e.g., control the gate of transistor P23) and control circuit 252 (e.g., control the gate of transistor N23).

[0050] For example, when Qi = "1" (indicating that X = "1"), inverter 231 selects circuit path 251' for compensation. In this example, since X = "1", Qi = "0". Qi = "0" turns on transistor P23. The turned-on transistor P23 activates circuit path 251' and current generator 290 (e.g., enables circuit path 251' to conduct current). This allows node 131 to charge power node 190 (e.g., with current I P ) to compensate for charge leakage that may occur at transistor N1 (through transistor N2) to supply node 199. This compensation can maintain the value of X="1" at node 131 for a relatively long time interval (e.g., longer than the time interval of latch 201 without circuit 251).

[0051] In another example, when Qi=“0” (indicating that X=“0”), inverter 231 selects circuit path 252′ for compensation. In this example, since X=“0”, Qi=“1”. Qi=“1” causes transistor N23 to turn on. The turned-on transistor N23 activates circuit path 252′ and current generator 299 (e.g., enables circuit path 252′ to conduct current). This allows node 131 to discharge (e.g., with current I N 252) to supply node 199 to compensate for charge leakage that may occur at transistor P2 (through transistor P1) to supply node 190. This compensation can maintain the value of X="0" at node 131 for a relatively long time interval (e.g., longer than the time interval of latch 201 without circuit 252).

[0052] In the write state, data information D written from node 110 to node 131 by input driver (formed by transistors P1, P2, N1, and N2) may initially face contention from node 131 from current generator 290 or current generator 299. However, since current generators 290 and 299 are constructed as relatively weak current generators (e.g., current I P and I N is relatively small), so the input driver (formed by transistors P1, P2, N1 and N2) can suppress the node 131 and change the value of the data information X, thereby deactivating the opposite polarity current on the current path 251' or 252'.

[0053] The following example describes an example write state where "1" (e.g., X="1") is to be written to node 131, while node 131 currently has X="0" previously written in the previous write state (held by active circuit path 252'). In this example, D="0" and CLK*="0", and transistors P1 and P2 are turned on. The turned-on transistors P1 and P2 can suppress transistor N23 and current generator 299. Transistors P1 and P2 couple node 131 to power supply node 190 and deactivate circuit path 252' (e.g., prohibit circuit path 252' from conducting current). This causes X="0" (written in the previous write state) to become the expected write value X="1" (corresponding to the value of voltage V1 at power supply node 190) in the current write state.

[0054] The following example describes an example current write state, where "0" (e.g., X="0") is to be written to node 131, while node 131 currently has X="1" previously written in the previous write state (maintained by active circuit path 251'). In this example, D="1" and CLK*="0", and transistors N1 and N2 are turned on. The turned-on transistors N1 and N2 can suppress transistor P23 and current generator 290. Transistors N1 and N2 couple node 131 to power supply node 199 and deactivate circuit path 251' (e.g., prohibit circuit path 251' from conducting current). This causes X="1" (written in the previous write state) to become the expected write value X="0" (corresponding to the value of voltage V0 at power supply node 199) in the current write state.

[0055] Latch 201 may include similar improvements and benefits as latch 101. In addition, the inclusion of circuits 230, 251, and 252 enables latch 201 to maintain data information X at node 131 for a relatively longer time interval (e.g., more than one clock cycle of clock signals CLK and CLK*) than some conventional dynamic latches.

[0056] Figure 3 301 according to some embodiments described herein. Latch 301 is a dynamic latch. Latch 301 may include some Figure 2 Elements similar to (or identical to) the elements of latch 201 of FIG. Similar or identical elements between latch 201 and 301 are given the same labels. For example, Figure 2 Like latch 201 in, Figure 3 The latch 301 in FIG. 2 may include an input stage 130 (eg, transistors P1, P2, N1, and N2), an output stage 140 (eg, inverter 141), and a circuit 230. For simplicity, similar or identical elements between latches 201 and 301 are not repeatedly described. Figure 3 As shown, the latch may include circuits 351 and 352. Latch 301 may operate like latch 201, in that portions of circuits 351 and 352 may be formed (or may be) separately. Figure 2 The latch 301 may include a portion of the current generator 290 and the current generator 299 of the latch 201. Figure 2 Similar improvements and benefits are provided for latch 201.

[0057] like Figure 3As shown, circuit 351 may include transistors (e.g., PMOS transistors) P33, P34, and P35 coupled to transistor P23. Transistors P23 and P33 may be coupled in series between node (e.g., memory node) 131 and power supply node 190. Transistors P23, P33, P34, and P35 may form a current mirror (current mirror circuit). Transistors P23 and P33 may form a portion (e.g., one branch) of the current mirror. Transistors P34 and P35 may form another portion (e.g., another branch) of the current mirror. Circuit 351 may generate current I on a circuit path (e.g., current path) 351′ between node 131 and power supply node 190. P The transistor P23 is part of (included in) the circuit path 351'. The current I P The value of can be based on the current (eg, reference current) I P_REF (For example, it may be its mirror current).

[0058] Circuit 351 and circuit 230 are operable to enable latch 301 to compensate for charge leakage that may occur at node 131 so that the value of data information X at node 131 remains valid for a relatively long time interval. For example, when node 131 has X="1", Qi="0". Qi="0" turns on transistor P23. The turned-on transistor P23 activates circuit path 351' to allow a certain amount of charge (e.g., with current I P The charge is then transferred from the supply node 190 to the node 131 via the circuit path 351' (in the form of a charge). This amount of charge can compensate for the amount of charge that may be transferred from the node 131 to the supply node 199 due to charge leakage that may occur at the transistor N1 (through the transistor N2). This compensation can maintain the value of X="1" at the node 131 for a relatively long time interval (e.g., longer than the time interval of the latch 301 without the circuit 251).

[0059] like Figure 3 As shown, circuit 352 may include transistors (e.g., NMOS transistors) N33, N34, and N35 coupled to transistor N23. Transistors N23 and N33 may be coupled in series between node 131 and power supply node 199. Transistors N23, N33, N34, and N35 may form a current mirror (current mirror circuit). Transistors N23 and N33 may form a portion (e.g., one branch) of the current mirror. Transistors N34 and N35 may form another portion (e.g., another branch) of the current mirror. Circuit 351 may generate current I on a circuit path (e.g., current path) 352′ between node 131 and power supply node 199. N Transistor N23 is part of (included in) circuit path 352'. Current IN The value of can be based on the current (eg, reference current) I N_REF (For example, it may be its mirror current).

[0060] Circuit 352 and circuit 230 can operate so that latch 301 can compensate for charge leakage that may occur at node 131, so that the value of data information X at node 131 remains valid for a relatively long time interval. For example, when node 131 has X="0", Qi="1". Qi="1" turns on transistor N23. The turned-on transistor N23 activates circuit path 352' to allow a certain amount of charge (e.g., with current I N The charge is then transferred from the node 131 to the supply node 199 via the circuit path 352' (in the form of a charge). This amount of charge can compensate for the amount of charge that may have been transferred from the supply node 190 to the node 131 due to charge leakage that may have occurred at the transistor P2 (through the transistor P1). This compensation can maintain the value of X = "0" at the node 131 for a relatively long time interval (e.g., longer than the time interval of the latch 301 without the circuit 252).

[0061] Latch 301 may include similar improvements and benefits relative to some conventional dynamic latches, such as latches 101 and 201. In addition, the biasing scheme in circuits 351 and 352 is a relatively low power biasing scheme and may be shared by multiple latches, such as latch 301. This may provide power savings (e.g., static power savings) in circuits that include latches, such as latch 301.

[0062] Figure 4 An apparatus in the form of a system (e.g., electronic system) 400 is shown according to some embodiments described herein. The system 400 may be considered a machine. The system (e.g., machine) 400 may include or be included in a computer, a cellular phone, or other electronic system. Figure 4 As shown, system 400 may include components (e.g., devices) located on a circuit board (e.g., a printed circuit board (PCB)) 402. These components may include a hardware processor 415, a memory device 420, a memory controller 430, a graphics controller 440, an input and output (I / O) controller 450, a display 452, a keyboard 454, a pointing device 456, at least one antenna 458, a storage device 460, and a bus 470. System 400 may be configured to perform one or more methods and / or operations described herein.

[0063] The hardware processor 415 may include a general-purpose processor or an application specific integrated circuit (ASIC). The hardware processor 415 may include a central processing unit (CPU) and a processing circuit. The graphics controller 440 may include a graphics processing unit (GPU) and a processing circuit. The memory device 420 may include a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, a flash memory device, a phase change memory, or a combination of these memory devices, or other types of memory. Figure 4 An example is shown in which the memory device 420 is a stand-alone memory device, separate from the hardware processor 415. In an alternative configuration, the memory device 420 and the hardware processor 415 may be located on the same integrated circuit (IC) chip (e.g., a semiconductor die or an IC die). In such an alternative configuration, the memory device 420 is an embedded memory in the hardware processor 415, such as embedded DRAM (eDRAM), embedded SRAM (eSRAM), embedded flash memory, or another type of embedded memory.

[0064] The storage device 460 may include a drive unit (e.g., a hard disk drive (HHD), a solid-state drive (SSD), or another large-capacity storage device). The storage device 460 may include a machine-readable medium 462 and a processing circuit. The machine-readable medium 462 may store one or more sets of data structures or instructions 464 (e.g., software) that embody or are used by any one or more of the techniques or functions described herein. During execution of the instructions 464 by the system (e.g., machine) 400, the instructions 464 may also exist completely or at least partially within the memory device 420, the memory controller 430, the hardware processor 415, or the graphics controller 440.

[0065] In one example, one of the hardware processor 415, memory 420, memory controller 430, graphics controller 440, and storage device 460 (or any combination thereof) may constitute a machine-readable medium. Non-limiting examples of machine-readable media may include solid-state memory, and optical and magnetic media. Specific examples of machine-readable media may include non-volatile memory, such as semiconductor memory devices (e.g., EPROM or EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROM and DVD-ROM disks.

[0066] Figure 4 Machine-readable medium 462 is shown as an example of a single medium. However, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store instructions 464. In addition, the term "machine-readable medium" may include any medium that is capable of storing, encoding, or carrying instructions for execution by system 400 and causing system 400 to perform any one or more techniques of the present disclosure, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. In some examples, the machine-readable medium may include a non-transitory machine-readable medium. In some examples, the machine-readable medium may include a machine-readable medium that is not a transient propagation signal.

[0067] Display 452 may include a liquid crystal display (LCD), a touch screen (e.g., a capacitive or resistive touch screen), or another type of display. Pointing device 456 may include a mouse, a stylus, or another type of pointing device. In some configurations, system 400 does not necessarily include a display. Thus, in such configurations, display 452 may be omitted from system 400.

[0068] Antenna 458 may include one or more directional or omnidirectional antennas, such as dipole antennas, monopole antennas, patch antennas, loop antennas, microstrip antennas, or other types of antennas suitable for transmission of radio frequency (RF) signals. In some configurations, system 400 does not necessarily include an antenna. Thus, in such configurations, antenna 458 may be omitted from system 400.

[0069] I / O controller 450 may include a communication module for wired or wireless communication (e.g., communication through one or more antennas 458). Such wireless communication may include communication according to WiFi communication technology, Long Term Evolution Advanced (LTE-A) communication technology, or other communication technology.

[0070] The I / O controller 450 may also include a module to allow the system 400 to communicate with other devices or systems in accordance with one or more of the following standards or specifications (e.g., I / O standards or specifications), including Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), Ethernet, and other specifications.

[0071] Connector 455 may include terminals (e.g., pins) to allow system 400 to couple with an external device (or system). This may allow system 400 to communicate (e.g., exchange information) with such a device (or system) via connector 455. Connector 455 and at least a portion of bus 470 may include conductive wires that conform to at least one of USB, DP, HDMI, Thunderbolt, PCIe, Ethernet, and other specifications.

[0072] Figure 4 Components (e.g., devices) of system 400 are shown as an example and arranged separately from each other. For example, each of hardware processor 415, memory device 420, memory controller 430, graphics controller 440, and I / O controller 450 can be included in (e.g., formed in or formed on) a separate integrated circuit (IC) chip (e.g., a separate semiconductor die or a separate IC die). In some configurations of system 400, two or more components of system 400 (e.g., hardware processor 415, memory device 420, graphics controller 440, and I / O controller 450) can be included in (e.g., formed in or formed on) the same IC chip (e.g., the same semiconductor die), forming a system-on-chip (SoC), or alternatively, a system-in a package (SiP).

[0073] like Figure 4 As shown, each of the hardware processor 415, the memory device 420, the memory controller 430, the graphics controller 440, and the I / O controller 450 may include a circuit 490. The circuit 490 may include a relatively high-speed digital logic circuit. The circuit 490 may include a clock distribution network, a data path, or both. Each clock distribution network and data path of the circuit 490 may include a latch 401. The latch 401 may include the latch 401 described above. Figure 1 , Figure 2 and Figure 3 Any of latches 101, 201, and 301 described above. In an alternative configuration of system 400, a clock distribution network or data path (as described above) may be eliminated from circuit 490 of at least one of hardware processor 415, memory device 420, memory controller 430, graphics controller 440, and I / O controller 450. In another alternative configuration of system 400, circuit 490 may be eliminated from some of hardware processor 415, memory device 420, memory controller 430, graphics controller 440, and I / O controller 450. A device (e.g., hardware processor 415, memory device 420, memory controller 430, graphics controller 440, or I / O controller 450 of system 400) or a system (e.g., system 400) that includes a latch such as latch 401 may have the same configuration as described above with reference to FIG. Figure 1 , Figure 2 and Figure 3 Similar improvements and benefits apply to latches 101 , 201 , and 301 as described.

[0074] Figure 5 The flowchart of FIG. 5 shows a method 500 of operating a device according to some embodiments described herein. The device used in the method 500 may include the device described above with reference to FIG. Figures 1 to 4 Any of the apparatus described (e.g., latches 101, 201, and 301 and system 400). Some of the activities in method 500 may be performed by hardware, software, firmware, or any combination of hardware, software, and firmware of a device (e.g., processor 415, memory device 420, memory controller 430, graphics controller 440, or I / O controller 450 of system 400) or a system (e.g., system 400). In one example, some of the activities in method 500 may be performed by circuitry (e.g., circuitry 490 including at least one of a clock distribution network and a data path) of a device (e.g., processor 415, memory device 420, memory controller 430, graphics controller 440, or I / O controller 450) or a system (e.g., system 400). At least a portion of the activities (e.g., operations) of method 500 may be performed by a latch of the circuitry, wherein the latch may include the latches described above with reference to Figures 1 to 4 One of latches 101, 201, and 301 described.

[0075] like Figure 5 As shown, method 500 may include activities (eg, operations) 510, 520, and 530. Activity 510 may include performing a dynamic latch (eg, as described above with reference to FIG. 5 ). Figures 1 to 4Activity 520 may include storing data information at a node of the dynamic latch during a state (e.g., a write state) of the dynamic latch. The node of the dynamic latch may include a charge storage node (e.g., a memory node) of the dynamic latch (e.g., node 131 of one of latches 101, 201, and 301). Activity 530 may include activating a circuit path (e.g., a current path) coupled between a node and a power supply node during an additional state (e.g., a hold state) of the dynamic latch. The circuit path may include the circuit path described above with reference to FIG. Figures 1 to 4 Any of the circuit paths 151', 152', 251', 252', 351', and 352' of the various latches 101, 201, and 301 described. Activating the circuit path in activity 530 of method 500 may include turning on a transistor of the circuit path. The transistor may be a transistor as described above with reference to Figures 1 to 4 One of transistors P13, N13, P23, and N23 of the depicted respective latches 101, 201, and 301. In activity 530, the gate of the transistor can be controlled based on the value of the information at the node in the additional state.

[0076] Relative to Figure 5 In the activities 510, 520 and 530 in the method 500, the method 500 may include fewer or more activities. For example, the method 500 may include the above reference Figures 1 to 4 The activities and operations of the described apparatus (eg, latches 101, 201, and 301 and system 400). Thus, method 500 may have similarities to those described above with reference to Figures 1 to 4 Similar improvements and benefits apply to latches 101 , 201 , and 301 as described.

[0077] The description of the apparatus (e.g., latches 101, 201, and 301 and system 400) and the described methods (e.g., the operation of latches 101, 201, and 301 and system 400 and the methods of operating latches 101, 201, and 301 and system) described above is intended to provide a general understanding of the structure of different embodiments, and is not intended to provide a complete description of all elements and features of the apparatus that may utilize the structure described herein. For example, an apparatus herein refers to a device (e.g., latch 101, 201, or 301, processor 415, memory device 420, memory controller 430, graphics controller 440, or I / O controller 450) or a system (e.g., system 400).

[0078] References Figures 1 to 5Any of the components described can be implemented in several ways, including simulating via software. Thus, the devices described above can all be characterized as (one or more) "modules" in this article. As desired and / or appropriate in accordance with the specific implementation of various embodiments, such modules may include hardware circuits, single processors and / or multiprocessor circuits, memory circuits, software program modules and objects and / or firmware, and combinations thereof. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware for operating or simulating the operation of various potential embodiments.

[0079] The apparatus and methods described above may include or be included in high-speed computers, communication and signal processing circuits, single or multi-processor modules, single or multi-embedded processors, multi-core processors, message information switches, and dedicated modules including multi-layer, multi-chip modules. Such apparatus may further be included as a subcomponent in various other apparatuses (e.g., electronic systems), such as televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radio stations, video players, audio players (e.g., MP3 (Moving Picture Experts Group, Audio Layer 3) players), vehicles, medical equipment (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, and other apparatuses.

[0080] In the detailed description and claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0081] In the detailed description and claims, the term "adjacent" generally refers to the location of one thing next to (e.g., next to or close to with one or more things in between) or adjacent to (e.g., adjacent to or in contact with (e.g., directly coupled with)) another thing.

[0082] In the detailed description and claims, a list of items linked by the term “at least one of…” may mean any combination of the listed items. For example, if items A and B are listed, then the phrase “at least one of A and B” means only A; only B; or A and B. In another example, if items A, B, and C are listed, then the phrase “at least one of A, B, and C” means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0083] In the detailed description and claims, a list of items linked by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, then the phrase "one of A and B" means only A (excluding B), or only B (excluding A). In another example, if items A, B, and C are listed, then the phrase "one of A, B, and C" means only A; only B; or only C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0084] Implementations of the described subject matter may include one or more of the features, alone or in combination, as described below by way of example.

[0085] Example 1 is a device comprising: an input stage of a latch, used to receive input data information and clock information; a memory node coupled to the input stage, used to store data information based on the input data information; an output stage of the latch coupled to the memory node, the output stage comprising an output node, used to provide output data information based on the data information stored at the memory node; a first circuit, used to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit, used to provide a second circuit path between the memory node and a second node in the input stage.

[0086] In Example 2, the subject matter as described in Example 1 includes the following subject matter: wherein the input stage includes transistors coupled in series with each other between a first power supply node and a second power supply node, the transistors include respective gates, and at least one of the gates of the transistors is used to receive the input data information.

[0087] In Example 3, the subject matter of Example 2 includes the subject matter wherein at least one of the gates of the transistors is used to receive the clock information.

[0088] In Example 4, the subject matter as described in any of Examples 1-3 includes the following subject matter: wherein the first circuit includes a first additional transistor, the first additional transistor includes a first terminal coupled to the memory node, a second terminal coupled to the first node in the input stage, and a gate coupled to the output node.

[0089] In Example 5, the subject matter as described in any of Examples 1-4 includes the following subject matter: wherein the second circuit includes a second additional transistor, the second additional transistor includes a first terminal coupled to the memory node, a second terminal coupled to a second node in the input stage, and a gate coupled to the output node.

[0090] In Example 6, the subject matter of Example 5 includes subject matter wherein the first additional transistor and the second additional transistor are of different transistor types.

[0091] In Example 7, the subject matter of Example 5 includes subject matter wherein the first additional transistor is an n-type transistor and the second additional transistor is a p-type transistor.

[0092] In Example 8, the subject matter as described in any of Examples 1-3 includes the following subject matter: wherein the first circuit includes a p-type transistor, the p-type transistor includes a first terminal coupled to the memory node, a second terminal coupled to the first node, and a gate coupled to the output node, and the second circuit includes an n-type transistor, the n-type transistor includes a first terminal coupled to the memory node, a second terminal coupled to the second node, and a gate coupled to the output node.

[0093] In Example 9, the subject matter as described in any one of Examples 1-8 includes the following subject matter: wherein the input stage includes: a first clock node, used to receive a first clock signal of the clock information; a second clock node, used to receive a second clock signal of the clock information; a first transistor, which has a gate coupled to the first clock node; and a second transistor, which has a gate coupled to the second clock node.

[0094] In Example 10, the subject matter of Example 9 includes the following subject matter: wherein the second clock signal is an inversion of the first clock signal.

[0095] In Example 11, the subject matter as described in Example 1 includes the following subject matter: wherein the input stage includes: a data node for receiving the input data information; a first transistor coupled between a first power supply node and the first node, the first transistor including a gate coupled to the data node; a second transistor coupled between the first node and the memory node, the second transistor including a gate for receiving a first clock signal of the clock information; a third transistor coupled between the memory node and the second node, the third transistor including a gate for receiving a second clock signal of the clock information; and a fourth transistor coupled between the second node and the second power supply node, the fourth transistor including a gate coupled to the data node.

[0096] In Example 12, the subject matter of Example 11 includes subject matter wherein the first transistor and the second transistor have a first transistor type, and the third transistor and the fourth transistor have a second transistor type.

[0097] In Example 13, the subject matter of Example 11 includes subject matter wherein the first and second transistors are p-type transistors, and the third and fourth transistors are n-type transistors.

[0098] In Example 14, the subject matter of any of Examples 1-13 includes the following subject matter: wherein the device includes a circuit that includes a clock distribution network and at least one of a data path, and wherein the latch is a dynamic latch and at least one of the clock distribution network and the data path includes the dynamic latch.

[0099] In Example 15, the subject matter of any one of Examples 1-13 includes the following subject matter: wherein the device includes an integrated circuit (IC) chip, and the IC chip includes the input stage, the memory node, the output stage, the first circuit, and the second circuit.

[0100] In Example 16, the subject matter of any of Examples 1-13 includes the following subject matter: wherein the apparatus includes a processor, the processor including the input stage, the memory node, the output stage, the first circuit, and the second circuit.

[0101] Example 17 is a device comprising: an input stage of a latch, used to receive input data information and clock information, the input stage coupled to a first power supply node and a second power supply node; a memory node coupled to the input stage, used to store data information based on the input data information; an output stage of the latch coupled to the memory node, the output stage comprising an output node, used to provide output data information based on the data information stored at the memory node; a first circuit, used to provide a first circuit path between the memory node and the first power supply node; a second circuit, used to provide a second circuit path between the memory node and the second power supply node; and a third circuit, used to provide control information to the first circuit and the second circuit based on the information stored at the memory node.

[0102] In Example 18, the subject matter as described in Example 17 includes the following subject matter: wherein the first circuit includes at least one transistor coupled between the memory node and the first power supply node, the second circuit includes at least one transistor coupled between the memory node and the second power supply node, and the third circuit includes an inverter, the inverter including an input node coupled to the memory node, and an output node coupled to the following items: a gate of a transistor of the first circuit and a gate of a transistor of the second circuit.

[0103] In Example 19, the subject matter as described in Example 17 includes the following subject matter: wherein the first circuit includes at least one transistor coupled between the memory node and the first power supply node, and the second circuit includes at least one transistor coupled between the memory node and the second power supply node.

[0104] In Example 20, the subject matter as described in Example 19 includes the following subject matter: wherein at least one transistor coupled between the memory node and the first power supply node has a first transistor type, and at least one transistor coupled between the memory node and the second power supply node has a second transistor type.

[0105] In Example 21, the subject matter as described in any of Examples 19-20 includes the following subject matter: wherein at least one transistor of the first circuit includes a first transistor coupled in series between the memory node and the first power supply node, and at least one transistor of the second circuit includes a second transistor coupled in series between the memory node and the second power supply node.

[0106] In Example 22, the subject matter of Example 21 includes subject matter wherein the first transistor has a first transistor type and the second transistor has a second transistor type.

[0107] In Example 23, the subject matter of any of Examples 17-22 includes the following subject matter: wherein the first circuit includes a first current generator coupled between the memory node and the first power supply node, and the second circuit includes a second current generator coupled between the memory node and the second power supply node.

[0108] In Example 24, the subject matter of any of Examples 17-23 includes the following subject matter: wherein the first circuit includes a first current generator coupled between the memory node and the first power supply node, and the second circuit includes a second current generator coupled between the memory node and the second power supply node.

[0109] In Example 25, the subject matter of any of Examples 17-23 includes subject matter wherein the first circuit is part of a first current mirror and the second circuit is part of a second current mirror.

[0110] In Example 26, the subject matter as described in any of Examples 17-23 includes the following subject matter: wherein the memory node is configured to store the data information during a first phase of a clock signal of the clock information, and the memory node is configured to maintain the data information during a second phase of the clock signal.

[0111] In Example 27, the subject matter as described in Example 17 includes the following subject matter: wherein the input stage includes: a first p-type transistor coupled between a first power supply node and the first node, the first p-type transistor including a gate for receiving the input data information; a second p-type transistor coupled between the first node and the memory node, the second p-type transistor including a gate for receiving a first clock signal for the clock information; a first n-type transistor coupled between the memory node and the second node, the first n-type transistor including a gate for receiving a second clock signal for the clock information; and a second n-type transistor coupled between the second node and the second power supply node, the second n-type transistor including a gate for receiving the input data information.

[0112] In Example 28, the subject matter as described in any one of Examples 17-27 includes the following subject matter: wherein the device includes a system on chip (SoC), the SoC includes an integrated circuit (IC) chip, and the IC chip includes the input stage, the memory node, the output stage, the first circuit, the second circuit, and the third circuit.

[0113] In Example 29, the subject matter as described in any of Examples 17-27 includes a connector, and an integrated circuit (IC) chip coupled to the connector, the IC chip including the input stage, the memory node, the output stage, the first circuit, the second circuit, and the third circuit, wherein the connector complies with at least one of the following: Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications.

[0114] Example 30 is a method comprising: receiving input data information at a data input node of the dynamic latch during a first state of the dynamic latch, storing data information at a node of the dynamic latch during the first state, the value of the data information at the node being based on the value of the input data information at the data input node, and activating a circuit path coupled between the node and a power supply node during a second state of the dynamic latch.

[0115] In Example 31, the subject matter of Example 30 includes the following subject matter: wherein activating the circuit path includes turning on a transistor of the circuit path, and wherein a gate of the transistor is controlled based on a value of the data information at the node in the second state.

[0116] In Example 32, the subject matter of any of Examples 30-31 includes the subject matter wherein activating the circuit path includes turning on a p-type transistor of the circuit path.

[0117] In Example 33, the subject matter of any of Examples 30-31 includes the subject matter wherein activating the circuit path includes turning on an n-type transistor of the circuit path.

[0118] In Example 34, the subject matter as described in Example 30, including: during an additional state of the dynamic latch, activating an additional circuit path coupled between the node and an additional power supply node, includes the following subject matter: wherein the first state of the latch is a first write state of the latch, and the additional state of the latch is a second write state of the latch.

[0119] In Example 35, the subject matter of any of Examples 30-33 includes the following subject matter: wherein, during the first write state, the bit of data information at the data input node has a first binary value, and during the first state, the bit of data information at the node of the dynamic latch has a second binary value.

[0120] Example 36 is at least one machine-readable medium comprising instructions that, when executed by a processing circuit, cause the processing circuit to perform operations to implement any of Examples 1-35.

[0121] Example 37 is an apparatus comprising components for implementing any of Examples 1-35.

[0122] Example 38 is a system for implementing any of Examples 1-35.

[0123] Example 39 is a method for implementing any of Examples 1-35.

[0124] The above description and accompanying drawings illustrate some embodiments of the inventive theme to enable those skilled in the art to implement embodiments of the inventive theme. Other embodiments may include structural, logical, electrical, process and other changes. Examples represent possible variations. Parts and features of some embodiments may be included in other embodiments, or replace parts and features of other embodiments. Many other embodiments will be clear to those skilled in the art after reading and understanding the above description.

[0125] The Abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims. The appended claims are hereby incorporated into the Detailed Description section, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: The input stage of the latch is used to receive input data information and clock information; a memory node coupled to the input stage for storing data information based on the input data information; an output stage of the latch coupled to the memory node, the output stage including an output node for providing output data information based on data information stored at the memory node; a first circuit for providing a first circuit path between the memory node and a first node in the input stage; as well as A second circuit is provided for providing a second circuit path between the memory node and a second node in the input stage.

2. The device according to claim 1, wherein: The input stage includes transistors coupled in series between a first power supply node and a second power supply node, the transistors include respective gates, and at least one of the gates of the transistors is used to receive the input data information.

3. The device as claimed in claim 2, wherein: At least one of the gates of the transistors is used to receive the clock information.

4. The device of claim 2, wherein: The first circuit includes a first additional transistor including a first terminal coupled to the memory node, a second terminal coupled to a first node in the input stage, and a gate coupled to the output node.

5. The device of claim 2, wherein: The second circuit includes a second additional transistor including a first terminal coupled to the memory node, a second terminal coupled to a second node in the input stage, and a gate coupled to the output node.

6. The device according to claim 1, wherein: The input stage comprises: A first clock node, used to receive a first clock signal of the clock information; A second clock node, used to receive a second clock signal of the clock information; a first transistor having a gate coupled to the first clock node; and A second transistor has a gate coupled to the second clock node.

7. The device of claim 1, wherein: The input stage comprises: A data node, used to receive the input data information; a first transistor coupled between a first supply node and the first node, the first transistor including a gate coupled to the data node; a second transistor coupled between the first node and the memory node, the second transistor comprising a gate for receiving a first clock signal of the clock information; a third transistor coupled between the memory node and the second node, the third transistor including a gate configured to receive a second clock signal of the clock information; and A fourth transistor is coupled between the second node and the second supply node, the fourth transistor including a gate coupled to the data node.

8. The device of claim 1, wherein: The apparatus comprises a circuit comprising at least one of a clock distribution network and a data path, and wherein the latch is a dynamic latch and the at least one of the clock distribution network and the data path comprises the dynamic latch.

9. The device of claim 1, wherein: The apparatus includes a processor including the input stage, the memory node, the output stage, the first circuit, and the second circuit.

10. An apparatus comprising: an input stage of the latch, for receiving input data information and clock information, the input stage being coupled to a first power supply node and a second power supply node; a memory node coupled to the input stage for storing data information based on the input data information; an output stage of the latch coupled to the memory node, the output stage including an output node for providing output data information based on data information stored at the memory node; a first circuit for providing a first circuit path between the memory node and the first supply node; a second circuit for providing a second circuit path between the memory node and the second supply node; as well as A third circuit is configured to provide control information to the first circuit and the second circuit based on the information stored at the memory node.

11. The apparatus of claim 10, wherein: The first circuit includes at least one transistor coupled between the memory node and the first supply node; the second circuit comprising at least one transistor coupled between the memory node and the second supply node; and The third circuit includes an inverter including an input node coupled to the memory node, and an output node coupled to: a gate of a transistor of the first circuit and a gate of a transistor of the second circuit.

12. The apparatus of claim 10, wherein: The first circuit includes a first current generator coupled between the memory node and the first supply node; and The second circuit includes a second current generator coupled between the memory node and the second supply node.

13. The apparatus of claim 10, wherein: The first circuit is part of a first current mirror; and The second circuit is part of a second current mirror.

14. The apparatus of claim 10, wherein: The memory node is configured to receive data information during a first phase of a clock signal of the clock information; and The memory node is configured to retain the data information during a second phase of the clock signal.

15. The device of claim 10, wherein: The input stage comprises: a first p-type transistor coupled between a first power supply node and the first node, the first p-type transistor comprising a gate for receiving the input data information; a second p-type transistor coupled between the first node and the memory node, the second p-type transistor comprising a gate for receiving a first clock signal of the clock information; a first n-type transistor coupled between the memory node and the second node, the first n-type transistor comprising a gate configured to receive a second clock signal of the clock information; and A second n-type transistor is coupled between the second node and the second power supply node, wherein the second n-type transistor comprises a gate configured to receive the input data information.

16. The apparatus of claim 10, further comprising a connector, and an integrated circuit (IC) chip coupled to the connector, the IC chip comprising the input stage, the memory node, the output stage, the first circuit, the second circuit, and the third circuit, wherein The connector complies with at least one of: Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications.

17. A method comprising: receiving input data information at a data input node of the dynamic latch during a first state of the dynamic latch; During the first state, storing data information at a node of the dynamic latch, the value of the data information at the node being based on the value of the input data information; and During a second state of the dynamic latch, a circuit path coupled between the node and a supply node is activated.

18. The method of claim 17, wherein: activating the circuit path comprises turning on a transistor of the circuit path; and The gate of the transistor is controlled based on the value of the data information at the node in the second state.

19. The method of claim 17, wherein: Activating the circuit path includes turning on a p-type transistor of the circuit path.

20. The method of claim 17, wherein: Activating the circuit path includes turning on an n-type transistor of the circuit path.

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