Storage device and refresh control method thereof

Abstract

A memory device according to an embodiment includes a memory cell array including a plurality of memory cells placed in a plurality of rows, a register configured to store row addresses corresponding to the plurality of rows and access counts of the plurality of rows, and a refresh controller configured to refresh the plurality of rows of the memory cells. The refresh controller is configured to determine a refresh address based on a stored row address and a received refresh command, and change a refresh cycle of a target row based on the refresh address being associated with a refresh previously performed on the target row and an access count of a row corresponding to the target row reaching a threshold.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0083634 filed in the Korean Intellectual Property Office on June 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The invention relates to a memory device and a refresh control method thereof. Background Art

[0004] As computing devices continue to decrease in size and their capacity and capabilities continue to increase, the minimum device geometry for manufacturing components continues to decrease. As the density of memory cells in a memory device increases, the charge of memory cells in adjacent rows may be affected by the voltage distribution in a particular row. Specifically, when rows are accessed in a concentrated manner, the data stored in memory cells of adjacent rows may change due to the voltage in the activated state of the corresponding row. This phenomenon is called row hammer. For row hammer defense, the function of periodically refreshing the entire memory cell and the function of refreshing the rows of memory cells that are under concentrated attack can be applied to the memory device. Summary of the invention

[0005] The present invention seeks to provide a memory device and a refresh control method thereof, which can prevent bit flipping caused by refresh due to access when some rows are accessed intensively.

[0006] A memory device according to an embodiment includes a memory cell array including a plurality of memory cells placed in a plurality of rows, a register configured to store row addresses corresponding to the plurality of rows and access counts of the plurality of rows, and a refresh controller configured to determine a refresh address based on the stored row addresses and upon receiving a refresh command, and to change a refresh cycle of a target row based on the refresh address being associated with a refresh previously performed on the target row and the access count of the row corresponding to the target row reaching a threshold.

[0007] A memory device according to an embodiment includes a memory cell array, the memory cell array includes a plurality of memory cells placed in a plurality of rows, a register counter includes a first register counter configured to store r row addresses corresponding to r rows among a plurality of rows and access counts of the r rows, r being an integer greater than 1, and a second register counter configured to store s row addresses corresponding to s rows among a plurality of rows and access counts of the s rows, s being an integer greater than 1, and the register counter is configured to increase the access count based on receiving an activation command, and a refresh controller configured to determine a refresh address based on the stored row address, determine whether to perform concentrated access to the r rows based on a received refresh signal when the access count of the second register counter matches a predetermined value, and increase a refresh cycle of a target row corresponding to the refresh address based on determining that concentrated access is performed to the r rows.

[0008] A refresh control method for a memory device including a plurality of memory cells placed in a plurality of rows, the method according to an embodiment comprising: determining a refresh address when a refresh command is received; determining whether only one row is accessed based on the refresh address; determining whether only n (n is an integer greater than 1) rows or less are accessed based on the refresh address when it is not determined that only one row is accessed; and changing the refresh cycle of the target row when it is determined that only n rows or less are accessed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic block diagram of a memory system according to an embodiment of the present invention.

[0010] Figure 2 According to the embodiment Figure 1 A schematic block diagram of a memory device.

[0011] Figure 3 A row access table managed by a refresh control circuit according to an embodiment is described.

[0012] Figure 4 A victim table managed by a refresh control circuit according to an embodiment is described.

[0013] Figure 5 is a block diagram of a refresh control circuit according to an embodiment.

[0014] Figure 6 is a block diagram of a refresh control circuit according to an embodiment.

[0015] Figure 7 is a block diagram of a refresh control circuit according to an embodiment.

[0016] Figure 8 is a flow chart of a refresh control method according to an embodiment.

[0017] Fig. 9 is a flow chart of a refresh control method according to an embodiment.

[0018] Figures 10 to 12 is a flow chart of a refresh control method according to an embodiment.

[0019] Fig.13 is a schematic block diagram of a computer system according to an embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As will be appreciated by those skilled in the art, the described embodiments can be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0021] The drawings and descriptions are to be considered illustrative and non-restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In the flowcharts described with reference to the drawings in this specification, the order of operations may be changed, several operations may be combined, certain operations may be divided, and certain operations may not be performed.

[0022] In the description, expressions described in the singular in this specification may be interpreted as singular or plural unless an explicit expression such as "one" or "single" is used. Although the terms "first", "second", etc. are used to explain various constituent elements, the constituent elements are not limited to these terms. These terms are only used to distinguish one constituent element from another constituent element.

[0023] Figure 1 is a schematic block diagram of a memory system according to an embodiment of the present invention.

[0024] refer to Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200 .

[0025] The memory controller 100 may control the overall operation of the memory system 10 .

[0026] The memory controller 100 may write data DQ to the memory device 200 or read data DQ from the memory device 200 using the clock signal CLK, the command CMD, and the address ADDR. For example, the memory controller 100 may control the operation of the memory device 200 by providing the command CMD and the address ADDR to the memory device 200 in synchronization with the clock signal CLK. The memory device 200 may transmit the data DQ and the data strobe signal DQS to the memory controller 100. For example, the memory controller 100 and the memory device 200 may be connected using individual pins and individual transmission lines to exchange the clock signal CLK, the command CMD, the address ADDR, the data DQ, or the data strobe signal DQS.

[0027] The memory controller 100 may control the memory device 200 in response to a command from the host 20. For example, the memory controller 100 may send a command CMD to the memory device 200 based on a refresh-related command periodically received from the host 20. The host 20 may communicate with the memory controller 100 using an interface protocol, such as Compute Express Link CXL, Peripheral Component Interconnect Express PCIe, Advanced Technology Attachment ATA, Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). In addition, the interface protocol between the host 20 and the memory controller 100 is not limited to the above examples, and may be implemented as any one of other interface protocols, such as Universal Serial Bus USB, Multimedia Card MMC, Enhanced Small Disk Interface ESDI, or Integrated Drive Electronics IDE.

[0028] The memory device 200 may be a dynamic random access memory (DRAM) such as double data rate synchronous DRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphics double data rate SDRAM (GDDR SDRAM), rambus DRAM (RDRAM), etc.

[0029] The memory device 200 may include a refresh control circuit RCC 230 for performing a refresh by recharging the data in the memory cell. The refresh control circuit 230 may perform a refresh based on a command CMD of the memory controller 100. For example, the refresh control circuit 230 may perform a normal refresh, a target row refresh (TRR), a self refresh, and the like. Here, a normal refresh may refer to a refresh operation performed by the memory device 200 to maintain data stored in a memory cell of the memory device 200, a target row refresh may refer to a refresh operation performed by the memory device 200 on a row adjacent to a row where concentrated access occurs, and a self refresh may refer to a refresh operation performed by the memory device 200 while changing an address by itself. A normal refresh may be performed in response to an external refresh command or a refresh address. According to an embodiment, the memory controller 100 may determine the refresh type, or the refresh control circuit 230 of the memory device 200 may determine the refresh type.

[0030] The refresh control circuit 230 can control the refresh cycle of the target row. The refresh cycle for the target row can be referred to as the target row refresh cycle TRR PERIOD (TRR cycle). That is, the refresh control circuit 230 can control the frequency of executing the target row refresh. For example, the refresh control circuit 230 can skip the target row refresh of a specific row. The refresh control circuit 230 can skip the target row refresh, remain in an idle state, or perform normal refresh. In another embodiment, the refresh control circuit 230 can change the ratio of the target row refresh to other refreshes (e.g., normal refresh). For example, the refresh control circuit 230 can perform two normal refreshes and one target row refresh TRR based on three refresh commands before changing the target row refresh cycle TRR PERIOD, and the refresh control circuit 230 can perform only three normal refreshes based on three refresh commands after changing the target row refresh cycle TRR PERIOD. Therefore, the memory device 200 can reduce power consumption and improve reliability by preventing unnecessary target row refreshes and promoting effective refreshes.

[0031] In an embodiment, when a row is accessed continuously, the refresh control circuit 230 may change the cycle (or frequency) of the target row refresh cycle. Hereinafter, the content of the change cycle may be understood as the content of the change frequency or replaced with the content of the change frequency. The refresh control circuit 230 may determine whether to access only one row in a centralized manner. For example, when the first row is accessed continuously, the refresh control circuit 230 may refresh the target row for the second row adjacent to the first row. After the refresh control circuit 230 refreshes the target row for the second row, the first row may continue to be accessed. The refresh control circuit 230 may determine whether the first row is accessed continuously based on an internal signal ISG or a row address ROW_ADDR. For example, the refresh control circuit 230 may determine that the first row is accessed continuously when the first row is accessed continuously for a predetermined number of times or when the first row is accessed for a predetermined number or more during a predetermined time period. When the first row is accessed continuously, the refresh control circuit 230 may determine whether to refresh the target row for the second row based on the number of refreshes of the target row for the second row. For example, when the number of target row refreshes of the second row is greater than or equal to the reference value, the refresh control circuit 230 may change the target row refresh cycle.

[0032] In an embodiment, when continuous access is performed on rows equal to or less than a reference number, the refresh control circuit 230 may change the target row refresh cycle. The refresh control circuit 230 may determine whether only a few rows are accessed in a concentrated manner. For example, the refresh control circuit 230 may store and manage n (n is an integer greater than 1) row addresses for target row refresh. The refresh control circuit 230 may store a row access table for managing frequently accessed rows. In an embodiment, the reference number may be n / 2, but the embodiment is not necessarily limited thereto, and various numbers (such as n / 3 and n / 4, etc.) may be used to implement it. When continuous access is performed on n / 2 or less third rows, the refresh control circuit 230 may perform target row refresh on the fourth row adjacent to the third row. After the refresh control circuit 230 performs target row refresh on the fourth row, the third row may continue to be accessed. The refresh control circuit 230 may determine whether to perform target row refresh on the fourth row based on the number of target row refreshes of the fourth row. For example, when the number of target row refreshes of the fourth row is equal to or greater than the reference value, the refresh control circuit 230 may change the target row refresh cycle.

[0033] Figure 2 According to the embodiment Figure 1 A schematic block diagram of a memory device, Figure 3 shows a row access table managed by a refresh control circuit according to an embodiment, and Figure 4 A victim table managed by a refresh control circuit according to an embodiment is shown.

[0034] refer to Figure 2, the memory device 200 may include a control logic 210, an address register 220, a refresh control circuit 230 and a bank control logic 240, a plurality of row decoders 250, a plurality of column decoders 260, an input / output selection circuit 270, a data input / output buffer 280, a plurality of memory cell arrays 290 and a plurality of sense amplifiers 295.

[0035] The control logic 210 may control the operation of the memory device 200. For example, the control logic 210 may generate an internal signal ISG based on a command CMD so that the memory device 200 performs a write operation, an erase operation, a read operation, a refresh operation, and the like.

[0036] The control logic 210 may include a command decoder 215. The command decoder 215 may decode the command CMD received from the memory controller 100 and generate an internal signal ISG so that the memory device 200 operates according to the command CMD. The command CMD may include a write enable signal WEB, a row address strobe signal RASB, a column address strobe signal CASB, a chip select signal CSB, a clock enable signal CKE, etc. The internal signal ISG may include an activation signal (or an activation command), a precharge signal (or a precharge command), a refresh signal (or a refresh command), a write signal (or a write command), an erase signal (or an erase command), a read signal (or a read command), etc. The refresh signal may include a normal refresh signal, a target row refresh signal, etc. According to an embodiment, the command decoder 215 may generate an internal signal ISG based on the command CMD and the address information received from the address register 220. Figure 2 The control logic 210 is shown to output the internal signal ISG to the refresh control circuit 230, but is not necessarily limited thereto, and the control logic 210 may also output the internal signal ISG to other components of the memory device 200. For example, the control logic 210 may provide the internal signal ISG to the plurality of row decoders 250, and the plurality of row decoders 250 may operate based on the internal signal ISG.

[0037] The address register 220 may receive an address ADDR from the memory controller 100. The address ADDR may include a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 220 may provide the row address ROW_ADDR to the refresh control circuit 230 and the row decoder 250, provide the bank address BANK_ADDR to the refresh control circuit 230 and the bank control logic 240, and provide the column address COL_ADDR to a plurality of column decoders 260.

[0038] exist Figure 2, the control logic 210 and the address register 220 are illustrated as separate constituent elements, but are not necessarily limited thereto, and the control logic 210 and the address register 220 may be implemented as one inseparable constituent circuit.

[0039] Reference together Figure 3 , the refresh control circuit 230 may store and manage frequently accessed rows in the memory cell array 290 in the row access table 1000. The refresh control circuit 230 may manage the access count of the row (i.e., the number of row accesses) based on the activation signal. The refresh control circuit 230 may include a counter that counts the access count of the row. For example, the refresh control circuit 230 may store the access count of each row in the row access table 1000. The refresh control circuit 230 may manage the row access table 1000 of each memory bank. The refresh control circuit 230 may generate the row access table 1000 based on at least one of the memory bank address BANK_ADDR and the row address ROW_ADDR.

[0040] The memory controller 100 randomly accesses addresses of the memory device 200 according to a command from the host 20, and may sometimes centrally access a specific address. When a specific row is centrally accessed, data stored in memory cells of neighboring rows of the specific row may change due to a voltage in an activated state of the specific row.

[0041] The row access table 1000 may include a row having a maximum access count and an access count of the corresponding row. The row access table 1000 may manage rows in descending order of access counts.

[0042] The row access table 1000 manages frequently accessed rows and row access counts in the first memory cell array 290_1. In the first memory cell array 290_1, row 462 may have been accessed 500 times, row 3 may have been accessed 448 times, row 9 may have been accessed 411 times, row 50 may have been accessed 357 times, and row 1032 may have been accessed 271 times.

[0043] Reference together Figure 4 , the refresh control circuit 230 may calculate the victim point based on the access count of the row. For example, the refresh control circuit 230 may calculate the victim point based on Figure 3 The victim point is calculated based on the row access table 1000 of the refresh control circuit 230. The refresh control circuit 230 may increase the first value to the victim points of two rows directly adjacent to the accessed row (e.g., the row at position +1 and the row at position -1). For example, the victim point of a particular row may be calculated based on the access counts of the neighboring rows of the particular row.

[0044] According to an embodiment, the refresh control circuit 230 may add a second value to a victim point of a row within a predetermined distance from the accessed row (e.g., a row at position -p to position +q relative to the accessed row, where p and q are integers greater than 1 and may be the same or different depending on the embodiment). The second value may be less than the first value.

[0045] The refresh control circuit 230 may manage a victim table 2000 storing a victim row VROW and a victim point of the victim row VROW. The victim table 2000 may be stored with a victim point 520 of row 461, a victim point 503 of row 463, a victim point 477 of row 4, a victim point 449 of row 2, and a victim point 411 of row 10. For example, the victim point 520 of row 461 may be determined based on the access count 500 of row 462 and the access count 20 of row 460.

[0046] The refresh control circuit 230 may generate a refresh address REF_ADDR based on at least one of the row access table 1000 and the victim table 2000. In an embodiment, the refresh control circuit 230 may output a row adjacent to a row with the highest access count (e.g., row 462) in the row access table 1000 as the refresh address REF_ADDR. In an embodiment, the refresh control circuit 230 may output a victim row (e.g., row 461) with the highest victim point in the victim table 2000 as the refresh address REF_ADDR. Figure 3 and Figure 4 In the description, although the refresh control circuit 230 generates the refresh address REF_ADDR based on at least one of the row access table 1000 and the victim table 2000, the embodiment is not necessarily limited thereto, and the refresh control circuit 230 may generate the refresh address REF_ADDR using various methods utilizing the access count of the row.

[0047] The refresh control circuit 230 may change the target row refresh cycle. In an embodiment, when it is detected that only one row is refreshed in a concentrated manner, the refresh control circuit 230 may change the target row refresh cycle. For example, the memory device 200 may perform a refresh operation using a changed refresh cycle during a predetermined time period. In an embodiment, when it is detected that only a small number of rows are refreshed in a concentrated manner, the refresh control circuit 230 may change the target row refresh cycle. For example, the refresh control circuit 230 may not output the refresh address REF_ADDR, or may change (increase or decrease) the cycle of outputting the refresh address REF_ADDR, or may output a normal refresh address instead of the target row refresh address, or may enter an idle state.

[0048] When the refresh control circuit 230 outputs the refresh address REF_ADDR to the plurality of row decoders 250, the row decoders 250 may perform a refresh on the plurality of memory cell arrays 290 based on the refresh address REF_ADDR. When the refresh is performed on the plurality of memory cell arrays 290, the refresh control circuit 230 may initialize at least one of an access count and a victim point. For example, the refresh control circuit 230 may initialize an access count of row 462 in the row access table 1000 or a victim point of row 461 in the victim table 2000.

[0049] The bank control logic 240 may generate a bank control signal in response to a bank address BANK_ADDR, and output the generated bank control signal to a plurality of row decoders 250 and a plurality of column decoders 260. The plurality of row decoders 250 may include a first row decoder 250_1 to an n-th row decoder 250_n (n is an integer greater than 1). The plurality of column decoders 260 may include a first column decoder 260_1 to an n-th column decoder 260_n (n is an integer greater than 1). In response to the bank control signal, a row decoder corresponding to the bank address BANK_ADDR may be activated among the first row decoder 250_1 to the n-th row decoder 250_n, and a column decoder corresponding to the bank address BANK_ADDR may be activated among the first column decoder 260_1 to the n-th column decoder 260_n.

[0050] The plurality of memory cell arrays 290 may include first to nth memory cell arrays 290_1 to 290_n (n is an integer greater than 1). That is, the number of memory cell arrays 290 may be equal to the number of row decoders 250 and the number of column decoders 260. For example, n may be implemented as 8, 16, 32, etc.

[0051] The first row decoders 250_1 to the nth row decoders 250_n may be connected to the first memory cell arrays 290_1 to the nth memory cell arrays 290_n, respectively. The first column decoders 260_1 to the nth column decoders 260_n may be connected to the first memory cell arrays 290_1 to the nth memory cell arrays 290_n, respectively. In addition, the plurality of sense amplifiers 295 may include first sense amplifiers 295_1 to nth sense amplifiers 295_n connected to the first memory cell arrays 290_1 to the nth memory cell arrays 290_n, respectively.

[0052] The first row decoder 250_1 to the nth row decoder 250_n, the first column decoder 260_1 to the nth column decoder 260_n, the first sense amplifier 295_1 to the nth sense amplifier 295_n, and the first memory cell array 290_1 to the nth memory cell array 290_n can configure the first memory bank to the nth memory bank respectively. Each of the first memory cell array 290_1 to the nth memory cell array 290_n may include a plurality of memory cells placed in a plurality of rows and a plurality of columns. For example, a plurality of memory cells may be placed at the intersection of a plurality of rows and a plurality of columns. Each memory cell may have a DRAM cell structure. The plurality of rows to which the memory cells are connected may be designated as a plurality of word lines, and the plurality of columns to which the memory cells are connected may be designated as a plurality of bit lines. A plurality of memory cells may be connected to a plurality of word lines and a plurality of bit lines.

[0053] Among the first row decoders 250_1 to the nth row decoders 250_n, the row decoders activated by the memory control logic 240 can be decoded by selecting the row address ROW_ADDR output from the address register 220 or the refresh address REF_ADDR output from the refresh control circuit 230. Each of the first row decoders 250_1 to the nth row decoders 250_n may include a multiplexer MUX for selecting one of the row address ROW_ADDR and the refresh address REF_ADDR. The activated row decoder may activate the row corresponding to the decoded address. For example, the activated row decoder may apply a row drive voltage (or a word line drive voltage) to the row corresponding to the decoded address.

[0054] The plurality of column decoders 260 may activate the sense amplifiers 295 through the input / output gating circuit 270. For example, among the first to nth column decoders 260_1 to 260_n, the column decoders activated by the bank control logic 240 may activate the sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR among the first to nth sense amplifiers 295_1 to 295_n through the input / output gating circuit 270. The plurality of column decoders 260 may include a column address latch that temporarily stores the column address COL_ADDR.

[0055] The input / output gating circuit 270 may include a circuit for gating input / output data, an input data mask logic, a read data latch for storing data output from the memory cell array 290 , and a write driver for writing data to the memory cell array 290 .

[0056] Data DQ read from one of the first to n-th memory cell arrays 290_1 to 290_n may be detected by a sense amplifier corresponding to the memory cell array and stored in a read data latch. The data DQ stored in the read data latch may be provided to the memory controller 100 through the data input / output buffer 280. In addition, data DQ to be written into one of the first to n-th memory cell arrays 290_1 to 290_n may be provided from the memory controller 100 to the data input / output buffer 280. The data DQ provided to the data input / output buffer 280 may be written into one of the memory cell arrays through a write driver.

[0057] Figure 5 is a block diagram of a refresh control circuit according to an embodiment.

[0058] refer to Figure 5 , the refresh control circuit 300 according to the embodiment may include a TRR controller (TCTR) 310, a register (RGST) 320, and a TRR counter (TCNT) 330. The TRR controller 310 may perform a target row refresh on the memory cell array. The TRR controller 310 may output a refresh address REF_ADDR of the target row refresh based on an internal signal ISG. The TRR controller 310 may receive an internal signal ISG from a control logic of the memory device. The internal signal ISG may be a refresh signal.

[0059] When the internal signal ISG is received, the TRR controller 310 may receive a row address RADR from the register 320. The row address RADR may be the address of a row related to the target row refresh. For example, the row address RADR may be the address of a row that is the target of the target row refresh, or the address of a row with the highest access count. The register 320 manages the access count of the row, and may output the row address RADR to the TRR controller 310 based on the access count. For example, the register 320 may receive the internal signal ISG and send the row address RADR to the TRR controller 310. As another example, when the internal signal ISG is received, the TRR controller 310 may send an address request signal to the register 320, and the register 320 may send the row address RADR to the TRR controller 310 in response to the address request signal.

[0060] Register 320 may include a row access table ( Figure 3 1000) or the victim table ( Figure 42000 in ). For example, the register 320 may determine the row with the maximum access count based on the row access table, and output the address of the adjacent row of the determined row as the row address RADR. As another example, the register 320 may determine the victim row with the highest victim point based on the victim table, and output the address of the victim row as the row address RADR.

[0061] The TRR controller 310 may determine the refresh address REF_ADDR based on the row address RADR. The TRR controller 310 may determine whether the refresh address REF_ADDR is the same as the address previously refreshed. For example, the TRR controller 310 may store the refreshed address history. The TRR controller 310 may store the refreshed address history in the register 320, or store the refreshed address history in a separate storage space. When the refresh address REF_ADDR is the same as the previously executed refresh address, the TRR controller 310 may output a match signal MSG to the TRR counter 330. The match signal MSG may include information about the refresh address REF_ADDR. In one embodiment, when the refresh address REF_ADDR is the same as the previously executed refresh address, the TRR controller 310 may output a match signal MSG. For example, when the refresh address REF_ADDR matches the address of the target row that was just refreshed, the match signal MSG is output. In an embodiment, when the refresh address REF_ADDR is included in the previously executed x times (where x is an integer greater than 1) refresh history, the TRR controller 310 may output a match signal MSG.

[0062] Depending on the embodiment, x may be determined to be a different number.

[0063] When the match signal MSG is received, the TRR counter 330 may increase the count value corresponding to the refresh address REF_ADDR. The TRR counter 330 may determine whether the count value corresponding to the refresh address REF_ADDR has reached a threshold value. When the count value corresponding to the refresh address REF_ADDR does not reach the threshold value, the TRR counter 330 may maintain the count value corresponding to the refresh address REF_ADDR. When the count value corresponding to the refresh address REF_ADDR reaches the threshold value, the TRR counter 330 may output the threshold signal TSG to the TRR counter 330. According to an embodiment, the TRR counter 330 may manage multiple count values ​​corresponding to multiple refresh addresses. For example, the TRR counter 330 may store a first refresh address, a first count value corresponding to the first refresh address, a second refresh address, and a second count value corresponding to the second refresh address. The TRR counter 330 may use an identifier instead of a refresh address. When the match signal MSG includes information about the first refresh address, the TRR counter 330 may increase the first count value. When the first count value reaches the threshold value, the TRR counter 330 may output the threshold signal TSG. Similarly, the same description can be applied to the case where the match signal MSG includes information on the second refresh address.

[0064] When receiving the threshold signal TSG, the TRR controller 310 may change the target row refresh period. The TRR controller 310 may be in an idle state without outputting the refresh address REF_ADDR. As another example, the TRR controller 310 may output a normal refresh address without outputting the refresh address REF_ADDR. In this case, the TRR controller 310 may include a logic circuit for generating a normal refresh address, or may receive a normal refresh address from a logic circuit outside the TRR controller 310.

[0065] For example, even if the internal signal ISG as the refresh signal is received, the TRR controller 310 may remain in an idle state without outputting the refresh address REF_ADDR, or may output a normal refresh address.

[0066] When the TRR controller 310 sends a match signal MSG and does not receive a threshold signal TSG, the TRR controller 310 may output the row address RADR as a refresh address REF_ADDR to the row decoder. In one embodiment, the TRR controller 310 may send a match signal MSG and wait for the threshold signal TSG for a certain period of time. When the threshold signal TSG is not received within a specific period of time, the TRR controller 310 may output the row address RADR. In one embodiment, the TRR counter 330 may send a response signal to the TRR controller 310 in response to the match signal MSG. The TRR counter 330 may output a first response signal when the count value reaches the threshold value, and may output a second response signal when the count value does not reach the threshold value (ie, when the count value is less than the threshold value). The first response signal may include the threshold signal TSG. The TRR controller 310 may output the row address RADR based on the second response signal.

[0067] Therefore, the refresh control circuit 300 according to the embodiment can reduce power consumption by reducing the frequency of target row refresh when accessing one row intensively, and can also prevent the target row refresh operation from being a self-hammering operation and causing bit flipping of adjacent cells.

[0068] Although register 320 and TRR counter 330 are Figure 5 3. Although illustrated as being implemented as separate constituent circuits, the embodiment is not necessarily limited thereto, and the register 320 and the TRR counter 330 may also be implemented by being adjacently placed in one block and communicating with the TRR controller 310.

[0069] Figure 6 is a block diagram of a refresh control circuit according to an embodiment.

[0070] refer to Figure 6 , the refresh control circuit 400 according to the embodiment may include a TRR controller (TCTR) 410, a register counter (RGCT) 420, a comparator (COMP) 430, and a TRR counter (TCNT) 440. The TRR controller 410 may perform a target row refresh on the memory cell array. The TRR controller 410 may output a refresh address REF_ADDR of the target row refresh based on the first internal signal ISG1. The TRR controller 410 may receive the first internal signal ISG1 from the control logic of the memory device. The first internal signal ISG1 may also be a refresh signal (or refresh command).

[0071] When receiving the first internal signal ISG1 , the TRR controller 410 may control the target row refresh period based on the threshold signal TSG.

[0072] When the first internal signal ISG1 is received but the threshold signal TSG is not received from the TRR counter 440, the TRR controller 410 may output the refresh address REF_ADDR. For example, when the threshold signal TSG is not received within a specific period of time after the first internal signal ISG1 is received, the TRR controller 410 may output the refresh address REF_ADDR. The TRR controller 410 may output the refresh address REF_ADDR based on the row address of the register counter 420. According to an embodiment, when the first internal signal ISG1 is received, the TRR controller 410 may send a request signal to the TRR counter 440 to determine whether the count value has reached the threshold value. The TRR counter 440 may send a response signal to the TRR controller 410 in response to the request signal. The response signal may include the threshold signal TSG or information indicating that the count value has not reached the threshold value.

[0073] The comparator 430 may be a counter comparator. When receiving the first internal signal ISG1, the comparator 430 may check the count value of the register counter 420. For example, the comparator 430 may compare the count value of the register counter 420 with a predetermined value (eg, '0') and output a trigger signal TRS when the values ​​match. The register counter 420 uses the row access table ( Figure 3 1000 in ) to manage the access count of the row. In this case, the count value may be the access count. According to an embodiment, register counter 420 uses victim table ( Figure 4 2000 in) to manage the victim point. In this case, the count value may be a victim point. The register counter 420 may include a first register counter (RCT1) 421 and a second register counter (RCT2) 422. The first register counter 421 may store r (r is an integer greater than 1) row addresses and count values ​​of r row addresses, and the second register counter 422 may store s (s is an integer greater than 1) row addresses and count values ​​of s row addresses. Depending on the embodiment, r and s may be set to the same value, or to different values. Depending on the embodiment, the count values ​​of the first register counter 421 and the second register counter 422 may be access counts or victim points.

[0074] When receiving the second internal signal ISG2 , the register counter 420 may increase the count value of the row address.

[0075] The second internal signal ISG2 may include row address information. Depending on the embodiment, the second internal signal ISG2 may be an activation signal or a refresh signal. First, the first register counter 421 stores the row address based on the second internal signal ISG2. When the first register counter 421 stores r row addresses, the second register counter 422 may store the row address based on the second internal signal ISG2. The first register counter 421 and the second register counter 422 may store the row address and the count value in a row access table or a victim table.

[0076] When the first internal signal ISG1 is received, the comparator 430 may check the count value of the second register counter 422. In an embodiment, the comparator 430 may check the count value whenever a refresh signal is received, or check the count value whenever a target row refresh signal is received in the refresh signal. When all count values ​​of the row addresses managed by the second register counter 422 are '0', the comparator 430 may output a trigger signal TRS to the TRR counter 440. It is understood that the count value of the second register counter 422 is '0' indicating a situation where only a few rows are accessed.

[0077] The TRR counter 440 may increase the count value when receiving the trigger signal TRS from the comparator 430. When the count value reaches a threshold value, the TRR counter 440 may output a threshold signal TSG.

[0078] When the first internal signal ISG1 is received and the threshold signal TSG is received from the TRR counter 440, the TRR controller 410 may change the target row refresh period. For example, the TRR controller 410 may be in an idle state without outputting the refresh address REF_ADDR. As another example, the TRR controller 410 may output a normal refresh address without outputting the refresh address REF_ADDR. In this case, the TRR controller 410 may include a logic circuit for generating a normal refresh address, or may receive the normal refresh address from a logic circuit outside the TRR controller 410. For example, even if the first internal signal ISG1 as a refresh signal is received, the TRR controller 410 may remain in an idle state without outputting the refresh address REF_ADDR, or may output a normal refresh address.

[0079] Therefore, the refresh control circuit 400 according to the embodiment can reduce power consumption by reducing the target row refresh frequency when a small number of rows are accessed intensively, and can also prevent bit flipping of adjacent cells due to the target row refresh operation.

[0080] Figure 7 is a block diagram of a refresh control circuit according to an embodiment.

[0081] refer to Figure 7, the refresh control circuit 500 according to the embodiment may include a TRR controller (TCTR) 510, a register counter (RGCT) 520, a comparator (COMP) 530, a first TRR counter (TCNT1) 540 and a second TRR counter (TCNT2) 550. The TRR controller 510 may perform a target row refresh on the memory cell array. The TRR controller 510 may output a refresh address REF_ADDR of the target row refresh based on the first internal signal ISG1. The TRR controller 510 may receive the first internal signal ISG1 from the control logic of the memory device. The first internal signal ISG1 may be a refresh signal.

[0082] When receiving the first internal signal ISG1, the TRR controller 510 may control the target row refresh period based on the first threshold signal TSG1 and the second threshold signal TSG2. The TRR controller 510 may receive the first threshold signal TSG1 from the first TRR counter 540 and the second threshold signal TSG2 from the second TRR counter 550. In the case of intensively accessing a small number of rows, the first TRR counter 540 may output the first threshold signal TSG1 to the TRR controller 510. For example, the first TRR counter 540 may output the first threshold signal TSG1 to the TRR controller 510 when the first count value managed by the first TRR counter 540 reaches the first threshold.

[0083] In the case of collectively accessing one row, the second TRR counter 550 may output a second threshold signal TSG2 to the TRR controller 510. For example, when the second count value managed by the second TRR counter 550 reaches the second threshold, the second TRR counter 550 may output the second threshold signal TSG2 to the TRR controller 510. Depending on the embodiment, the first threshold and the second threshold may be the same or different from each other.

[0084] When the first internal signal ISG1 is received and the first threshold signal TSG1 and the second threshold signal TSG2 are received from the first TRR counter 540, the TRR controller 510 may change the target row refresh period. For example, the TRR controller 510 may be in an idle state without outputting the refresh address REF_ADDR. As another example, the TRR controller 510 may output a normal refresh address without outputting the refresh address REF_ADDR. In this case, the TRR controller 510 may include a logic circuit for generating a normal refresh address, or may receive the normal refresh address from logic outside the TRR controller 510. For example, even if the first internal signal ISG1 as a refresh signal is received, the TRR controller 510 may remain in an idle state without outputting the refresh address REF_ADDR, or may output a normal refresh address.

[0085] When the first internal signal ISG1 is received but the first threshold signal TSG1 and the second threshold signal TSG2 are not received, the TRR controller 510 may output the refresh address REF_ADDR. For example, when the first threshold signal TSG1 and the second threshold signal TSG2 are not received within a specific period of time after the first internal signal ISG1 is received, the TRR controller 510 may output the refresh address REF_ADDR. The TRR controller 510 may output the refresh address REF_ADDR based on the row address of the register counter 520. According to an embodiment, when the first internal signal ISG1 is received, the TRR controller 510 may send a request signal to the first TRR counter 540 and the second TRR counter 550 to determine whether the count value has reached the threshold. The first TRR counter 540 and the second TRR counter 550 may send a response signal to the TRR controller 510 in response to the request signal. Each response signal may include the first threshold signal TSG1 and the second threshold signal TSG2, or information indicating that the count value has not reached the threshold.

[0086] When the first internal signal ISG1 is received, the comparator 530 may check the count value of the register counter 520. The register counter 520 may manage the access count of the row using a row access table. According to an embodiment, the register counter 520 may manage the victim point using a victim table. The register counter 520 may include a first register counter (RCT1) 521 and a second register counter (RCT2) 522. The first register counter 521 may store r (r is an integer greater than 1) row addresses and count values, and the second register counter 522 may store s (s is an integer greater than 1) row addresses and count values. Depending on the embodiment, r and s may be set to the same value, or may be set to different values.

[0087] When the second internal signal ISG2 is received, the register counter 520 may increase the count value of the row address. For example, the second internal signal ISG2 may be an activation signal. Depending on the embodiment, the first internal signal ISG1 and the second internal signal ISG2 may be the same refresh signal. First, the first register counter 521 stores the row address based on the second internal signal ISG2, and when the first register counter 521 is full, the second register counter 522 may store the row address based on the second internal signal ISG2.

[0088] When the first internal signal ISG1 is received, the comparator 530 may check the count value of the second register counter 522. In an embodiment, the comparator 530 may check the count value whenever a refresh signal is received, or check the count value whenever a target row refresh signal is received in the refresh signal. When all count values ​​of the row addresses managed by the second register counter 522 are '0', the comparator 530 may output a trigger signal TRS to the first TRR counter 540. It can be understood that the count value of the second register counter 522 is '0' indicating a situation where only a few rows are accessed. When the trigger signal TRS is received from the comparator 530, the first TRR counter 540 may increase the first count value. When the first count value reaches the first threshold, the first TRR counter 540 may output a threshold signal TSG1.

[0089] In addition, when the first internal signal ISG1 is received, the TRR controller 510 may receive a row address RADR from the register counter 520. The row address RADR may be the address of a row related to the target row refresh. For example, the row address RADR may be the address of a row that is the target of the target row refresh, or the address of a row with the highest access count. The register counter 520 manages the access count of the row, and may output the row address RADR to the TRR controller 510 based on the access count. For example, the register counter 520 may receive the second internal signal ISG2 and send the row address RADR to the TRR controller 510. As another example, the TRR controller 510 may send an address request signal to the register counter 520 when the first internal signal ISG1 is received, and the register counter 520 may send the row address RADR to the TRR controller 510 in response to the address request signal.

[0090] The register counter 520 may include a row access table or a victim table. For example, the register counter 520 may determine the row with the maximum access count based on the row access table, and output the address of the adjacent row of the determined row as the row address RADR. As another example, the register counter 520 may determine the victim row with the highest victim point based on the victim table, and output the address of the victim row as the row address RADR.

[0091] The TRR controller 510 may determine the refresh address REF_ADDR based on the row address RADR. The TRR controller 510 may determine whether the refresh address REF_ADDR is the same as the previously refreshed address. For example, the TRR controller 510 may store a refreshed address history. When the refresh address REF_ADDR is the same as the previously executed refresh address, the TRR controller 510 may output a match signal MSG to the second TRR counter 550. The match signal MSG may include information about the refresh address REF_ADDR. In an embodiment, when the refresh address REF_ADDR is the same as the previously refreshed address, the TRR controller 510 may output a match signal MSG. In an embodiment, when the refresh address REF_ADDR is included in the previously executed x times (where x is an integer greater than 1) refresh history, the TRR controller 510 may output a match signal MSG. Depending on the embodiment, x may be determined as a different number.

[0092] When the match signal MSG is received, the second TRR counter 550 may increase the count value of the refresh address REF_ADDR. The second TRR counter 550 may determine whether the second count value of the refresh address REF_ADDR has reached the second threshold. When the second count value does not reach the second threshold, the second TRR counter 550 may maintain the second count value. When the second count value reaches the second threshold, the second TRR counter 550 may output the second threshold signal TSG2 to the TRR controller 510.

[0093] Therefore, the refresh control circuit 500 according to the embodiment can reduce power consumption by reducing the target row refresh frequency when one row or a small number of rows are accessed intensively, and can also prevent bit flipping of adjacent cells due to the target row refresh operation.

[0094] Figure 8 is a flow chart of a refresh control method according to an embodiment.

[0095] refer to Figure 8 The refresh control method according to the embodiment may be performed by a memory device. For example, a refresh control circuit of the memory device may perform the refresh control method.

[0096] The memory device may obtain a refresh address REF_ADDR (S810). For example, when a refresh command is received from a memory controller outside the memory device, the memory device may obtain the refresh address REF_ADDR. The refresh address REF_ADDR may be the address of a row that is the target of the target row refresh TRR. The memory device may manage the access count of the row and determine the refresh address REF_ADDR based on the access count.

[0097] The memory device may determine whether the refresh address REF_ADDR matches the previously refreshed address PR_ADR (S820). In an embodiment, the previously refreshed address PR_ADR may represent a previously refreshed address. In an embodiment, the previously refreshed address PR_ADR may represent an address included in a previously executed x-times refresh history (where x is an integer greater than 1). For example, the memory device may determine whether the refresh address REF_ADDR matches the previously refreshed address or is included in a previously refreshed history of x times.

[0098] The memory device may include storage space to store and manage the refresh history.

[0099] When the refresh address REF_ADDR matches the previously refreshed address PR_ADR, the memory device may increase the count value CNT_VAL (S830). The memory device includes a TRR counter, and the TRR counter may increase the count value CNT_VAL by 1 bit. If the refresh address REF_ADDR does not match the previously refreshed address PR_ADR, the memory device may perform a target row refresh TRR based on the refresh address REF_ADDR (S860). The memory device may obtain a next refresh address after performing the target row refresh TRR (S810).

[0100] The memory device may determine whether the count value CNT_VAL matches the threshold value (S840). For example, at step S840, the memory device may determine whether the count value CNT_VAL increased by 1 bit reaches the threshold value. For example, the threshold value may be 100, but the embodiment is not necessarily limited thereto, and the threshold value may be set differently according to the embodiment.

[0101] If the count value CNT_VAL does not match the threshold value (ie, if the count value CNT_VAL is less than the threshold value), the memory device may perform a target row refresh TRR based on the refresh address REF_ADDR (S860), and may obtain a next refresh address (S810).

[0102] When the count value CNT_VAL matches the threshold value, the memory device may adjust the target row refresh period TRRPERIOD (S850). For example, the memory device may be in an idle state, may not output the refresh address REF_ADDR, may change the ratio between the normal refresh and the target row refresh TRR, or may perform a normal refresh. The memory device may adjust the target row refresh period TRR PERIOD and initialize the count value CNT_VAL.

[0103] Therefore, the refresh control method according to the embodiment can reduce power consumption by reducing the frequency of target row refresh (TRR) when accessing one row intensively, and can also prevent the target row refresh (TRR) operation from acting as a self-hammer operation and causing bit flipping of adjacent cells.

[0104] Fig. 9 is a flow chart of a refresh control method according to an embodiment.

[0105] Reference Fig. 9 The refresh control method according to the embodiment may be performed by a memory device. For example, a refresh control circuit of the memory device may perform the refresh control method.

[0106] The memory device may receive a refresh command REF_CMD (S910). For example, the memory device may receive a refresh command REF_CMD from a memory controller outside the memory device. When the refresh command REF_CMD is received, the memory device may check the count value of the register. For example, the register may include a first register and a second register storing the address and count value (e.g., access count) of the row. The first register and the second register may store a plurality of row addresses and a plurality of count values ​​corresponding to the plurality of row addresses. The first register may store a (a is an integer greater than 1) row addresses and count values, and the second register may store b (b is an integer greater than 1) row addresses and count values. Depending on the embodiment, a and b may be set to the same value or to different values. The memory device may first store the row address and count value in the first register based on the activation signal. When the first register is full, the memory device may store the row address and count value in the second register.

[0107] The memory device may determine whether only a small number of rows (e.g., Z rows (where Z is an integer greater than 1) or less) are accessed (S920). Z may be predetermined and may be less than or equal to a, where a is the size of the first register. For example, the memory device may check the count value of the row address stored in the second register. When all count values ​​of the row address stored in the second register are '0', the memory device may determine that only some rows are accessed. The case where all count values ​​of the row address stored in the second register are '0' may be a case where only the count value of the first register changes and the count value of the second register does not change.

[0108] When only some rows are accessed, the memory device may increase the count value CNT_VAL (S930). The memory device includes a TRR counter, and the TRR counter may increase the count value CNT_VAL by 1 bit. For example, when all count values ​​of the row address stored in the second register are '0', the TRR counter may increase the count value CNT_VAL by 1 bit based on the received refresh signal (e.g., refresh command REF_CMD). Unless only some rows are accessed (i.e., more than Z rows are accessed), the memory device may perform a target row refresh (TRR) based on the row address and count value of the register (S960). The memory device may receive the next refresh command REF_CMD (S910) after performing the target row refresh (TRR).

[0109] The memory device may determine whether the count value CNT_VAL matches the threshold value (S940). For example, at step S940, the memory device may determine whether the count value CNT_VAL increased by 1 bit has reached the threshold value. For example, the threshold value may be 100, but the embodiment is not necessarily limited thereto, and the threshold value may be set differently according to the embodiment.

[0110] If the count value CNT_VAL does not match the threshold (ie, if the count value CNT_VAL is less than the threshold), the memory device may perform a target row refresh TRR based on the row address and the count value of the register (S960), and may receive a next refresh command (S910).

[0111] When the count value CNT_VAL matches the threshold value, the memory device may adjust the target row refresh period TRRPERIOD (S950). For example, the memory device may be in an idle state, may not output a scheduled refresh address of the target row refresh TRR, may change the ratio between normal refresh and target row refresh TRR, or may perform normal refresh. The memory device may adjust the target row refresh period TRR PERIOD and initialize the count value CNT_VAL.

[0112] Therefore, the refresh control method according to the embodiment can reduce power consumption by reducing the frequency of the target row refresh TRR when a small number of rows are accessed intensively, and can also prevent the bit flip of the adjacent cells caused by the target row refresh TRR operation.

[0113] Figures 10 to 12 is a flow chart of a refresh control method according to an embodiment.

[0114] refer to Fig.10 The refresh control method according to the embodiment may be performed by a memory device. For example, a refresh control circuit of the memory device may perform the refresh control method.

[0115] The memory device may receive a refresh command REF_CMD (S1010). For example, the memory device may receive a refresh command REF_CMD from a memory controller outside the memory device. When the refresh command REF_CMD is received, the memory device may check the count value of the register. For example, the register may include a first register and a second register storing the address and count value (e.g., access count) of the row. The first register and the second register may store a plurality of row addresses and a plurality of count values ​​corresponding to the plurality of row addresses. The first register may store a (a is an integer greater than 1) row addresses and count values, and the second register may store b (b is an integer greater than 1) row addresses and count values. Depending on the embodiment, a and b may be set to the same value or to different values. The memory device may first store the row address and count value in the first register based on the activation signal. When the first register is full, the memory device may store the row address and count value in the second register.

[0116] The memory device may determine whether only one row is accessed (S1020). Fig.11 , the memory device may obtain a TRR history (S1021). The memory device may store a row address in which a target row refresh TRR is performed.

[0117] When the refresh address REF_ADDR generated based on the refresh command REF_CMD is included in the TRR history by more than a predetermined number (eg, the predetermined number is H, where H is an integer greater than 1), the memory device may determine that this is a case of accessing only one row and proceed to step S1050.

[0118] When the number of refresh addresses REF_ADDR is less than or equal to a predetermined number in the TRR history, the memory device may determine that this is not a case of accessing only one row, and may proceed to step S1030.

[0119] Return to reference Fig.10 , the memory device may determine whether only a small number of rows (eg, less than or equal to Z rows (where Z is an integer greater than 1)) are accessed ( S1030 ).

[0120] Z may be predetermined and may be less than or equal to a, where a is the size of the first register. Fig.12 , the memory device may obtain a count value R2_CVAL of the row address stored in the second register ( S1031 ).

[0121] The memory device may determine whether all count values ​​R2_CVAL of the row address stored in the second register are '0' (S1032). When all count values ​​R2_CVAL of the row address stored in the second register are '0', the memory device may determine that only some rows are accessed and proceed to step S1050. The case where all count values ​​R1_CVAL of the row address stored in the first register are '0' may be a case where only the count value of the first register changes and the count value R2_CVAL of the second register does not change. When at least one of the count values ​​R2_CVAL of the row address stored in the second register is not '0', the memory device may determine that this is not a case where only some rows are accessed, and proceed to step S1040.

[0122] Return to reference Fig.10 , unless only some rows are accessed, the memory device may perform a target row refresh TRR based on the row address and the count value of the register (S1040). When only one row or only some rows are accessed, the memory device may adjust the target row refresh period TRR PERIOD (S1050). For example, the memory device may be in an idle state, may not output a scheduled refresh address of the target row refresh TRR, may change a ratio between a normal refresh and a target row refresh TRR, or may perform a normal refresh.

[0123] Therefore, the refresh control method according to the embodiment can reduce power consumption by reducing the frequency of the target row refresh TRR when one or a small number of rows are accessed intensively, and can prevent bit flipping of adjacent cells caused by the target row refresh TRR operation.

[0124] Fig.13 is a schematic block diagram of a computer system according to an embodiment.

[0125] refer to Fig.13 , the computing system 3000 may include a processor 3010, a memory 3020, a memory controller 3030, a storage device 3040, a communication interface 3050, and a bus 3060. The computing system 3000 may also include other general components.

[0126] The processor 3010 controls the overall operation of each component of the computing system 3000. The processor 3010 may be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphic processing unit (GPU).

[0127] The memory 3020 stores various data and instructions. The memory 3020 may be implemented as a reference Figures 1 to 12For example, the memory 3020 can control the target row refresh cycle when only a specific row or only a small number of rows are accessed. Therefore, the memory 3020 can prevent bit flipping, and the computing system 3000 can reduce power consumption.

[0128] The memory controller 3030 controls the transfer of data or instructions to and from the memory 3020. The memory controller 3030 may be implemented as a reference Figures 1 to 12 In some embodiments, the memory controller 3030 may be provided as a chip separate from the processor 3010. In some embodiments, the memory controller 3030 may be provided as an internal component of the processor 3010.

[0129] The storage device 3040 stores programs and data non-temporarily. In some embodiments, the storage device 3040 may be implemented as a non-volatile memory. The communication interface 3050 supports wired and wireless Internet communications of the computing system 3000. In addition, the communication interface 3050 may support various communication methods other than Internet communications. The bus 3060 provides a communication function between the components of the computing system 3000. The bus 3060 may include at least one type of bus according to the communication protocol between the components.

[0130] In some embodiments, reference Figures 1 to 13 Each constituent element described or a combination of two or more constituent elements may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or the like.

[0131] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells disposed in a plurality of rows; a register configured to store row addresses corresponding to the plurality of rows and access counts of the plurality of rows; as well as The refresh controller is configured as: determining a refresh address based on the stored row address and the received refresh command, and A refresh cycle of the target row is changed based on the refresh address being associated with a refresh previously performed on the target row and an access count of a row corresponding to the target row reaching a threshold.

2. The memory device of claim 1 , further comprising: a counter configured to increase a count value when a match signal is received from the refresh controller, and to output a threshold signal to the refresh controller when the count value reaches a threshold value, The refresh controller is configured to output a match signal when the refresh address is associated with a refresh previously performed on the target row, and to change a refresh period of the target row in response to receiving a threshold signal.

3. The memory device of claim 2, wherein: The refresh controller is configured to output information of the refresh address and the match signal to the counter, and The counter is configured to store a plurality of count values ​​corresponding to a plurality of refresh addresses, increase a first count value corresponding to the refresh address among the plurality of count values, and output a threshold signal in response to the first count value reaching a threshold. 4 . The memory device according to claim 1 , wherein the memory device is configured such that when the refresh address matches an address of a target row whose refresh was just performed before, the refresh controller changes a refresh cycle of the target row. 5 . The memory device of claim 1 , wherein the memory device is configured such that when the refresh address is included in addresses of a plurality of target rows for which refresh was previously performed, the refresh controller changes a refresh cycle of the target row. 6 . The memory device of claim 1 , wherein the refresh controller is configured to change a refresh cycle of the target row by skipping output of a refresh address, by outputting a normal refresh address, or by entering an idle state of the memory device.

7. The memory device of claim 1, wherein: The register is configured to further store victim points of the plurality of rows determined based on the access count, and The refresh controller is configured to determine a refresh address based on the victim point.

8. A memory device comprising: a memory cell array comprising a plurality of memory cells disposed in a plurality of rows; Register counters, including: a first register counter configured to store r row addresses of a plurality of row addresses corresponding to r rows of the plurality of rows and access counts of the r rows, r being an integer greater than 1, and a second register counter configured to store s row addresses of a plurality of row addresses corresponding to s rows of the plurality of rows and access counts of the s rows, s being an integer greater than 1, and The register counter is configured to increase the access count based on receiving the activate command; as well as The refresh controller is configured as: Determine the refresh address based on the stored row address, determining whether to perform collective access to the r rows based on receiving a refresh signal when the access count of the second register counter matches a predetermined value, and A refresh cycle of a target row corresponding to a refresh address is increased based on determining that the collective access is performed on the r rows.

9. The memory device of claim 8, further comprising: a comparator configured to output a trigger signal based on a refresh signal when the second register counter matches a predetermined value, The refresh controller is configured to increase a refresh period of the target row based on the trigger signal.

10. The memory device of claim 9, further comprising: The TRR counter is configured to increase a count value when receiving a trigger signal from the comparator, and output a threshold signal to the refresh controller when the count value reaches a threshold value, The refresh controller is configured to increase a refresh period of the target row upon receiving a threshold signal. 11 . The memory device of claim 9 , wherein the comparator is configured to output a trigger signal when the access counts corresponding to the s rows of the second register counter match a predetermined value. 12 . The memory device of claim 11 , wherein the second register counter is configured to store the s row addresses and the access counts of the s rows when the first register counter is full.

13. The memory device of claim 9, wherein: The refresh controller is configured to perform a refresh based on the refresh address when receiving a refresh signal, and The comparator is configured to determine whether the value of the second register counter matches a predetermined value upon receiving the refresh signal. 14 . The memory device of claim 13 , wherein the comparator is configured to determine whether the value of the second register counter matches a predetermined value when the refresh signal is a target row refresh signal. 15 . The memory device of claim 8 , wherein the refresh controller is configured to increase a refresh cycle of the target row by skipping output of a refresh address, by outputting a normal refresh address, or by entering an idle state of the memory device.

16. The memory device of claim 8, wherein: The register counter is configured to further store a victim point of the row determined based on the access count of the row, and The refresh controller is configured to determine a refresh address of a target row based on an access count of the row or a victim point of the row, and perform a refresh based on the refresh address of the target row.

17. A refresh control method for a memory device, the memory device comprising a plurality of memory cells arranged in a plurality of rows, the method comprising: determining a refresh address when a refresh command is received; determining whether only one row is accessed based on the refresh address; When it is not determined that only one row is accessed, determining whether only n rows or less are accessed based on the refresh address, where n is an integer greater than 1; as well as When it is determined that only n rows or less are accessed, the refresh cycle of the target row is changed.

18. The method according to claim 17, wherein: Determining whether only one row is accessed involves: When the refresh address is included m times (m is an integer greater than 1) or more in the target row refresh history, it is determined that only one row is accessed.

19. The method according to claim 17, further comprising: storing r row addresses corresponding to r rows of the plurality of rows and access counts of the r rows in a first register counter; storing s row addresses corresponding to s rows of the plurality of rows and access counts of the s rows in a second register counter, Determining whether to access only n rows or less includes: When all values ​​of the second register counter are '0', it is determined that only n rows or less are accessed.

20. The method of claim 17, further comprising: When it is determined that more than n rows are accessed, refresh is performed on the target row based on the refresh address.

Images