Channel forming method of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and SiC MOSFET device
By using a combination technology of inner mask layer and outer mask layer in the SiC MOSFET device manufacturing process, the injection region is defined and ion implanted to form a source implantation window and P well region, the SiC MOSFET device has been solved by using a combination of inner mask layer and outer mask layer technology, and the SiC MOSFET device has been defined and ion implanted, forming a source implantation window and P well region. The SiC MOSFET device has high on-resistance and source The problem of injecting unnecessary areas has achieved optimization of channel length and process simplification.
Patent Information
- Application Number
- CN202310797935.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-29
- Publication Date
- 2024-12-31
AI Technical Summary
In the SiC MOSFET device manufacturing process, it is difficult for the prior art to achieve this in the channel formation process to reduce the on-resistance of the device and avoid source injection in areas where source injection is not required.
By creating an inner mask layer and an outer mask layer on the SiC epitaxial layer, the injection area is defined for N-type and P-type ion implantation, forming a JFET region and a P-well region, and forming a source injection window in the terminal area for source injection, The inner mask layer acts as an injection barrier layer, and the control channel length is the same as the mask thickness to avoid source injection in unnecessary areas.
Effectively reduce the on-resistance of the channel, avoid N+ ion implantation in areas where source implantation is not required, simplifies the process flow and reduces manufacturing costs.
Smart Images
Figure CN119230404A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a channel forming method of a SiC MOSFET device and a SiC MOSFET device. Background Art
[0002] Modern power electronic devices are developing towards high power density and high efficiency. Silicon carbide power devices have been rapidly developed in the field of efficient power conversion in recent years due to their excellent device characteristics such as high voltage, high frequency, high temperature and high power density. SiC MOSFET devices have the advantages of fast switching speed, high voltage resistance and low power consumption. They are mainly divided into planar gate type and trench type.
[0003] In the manufacturing process of planar gate SiC Mosfet devices, the mainstream channel formation method is the self-alignment process. In this process, the channel length corresponds to the thickness of the self-alignment mask. In order to reduce the on-resistance, a shorter channel is usually required, so the thickness of the self-alignment mask needs to be reduced. However, a thinner self-alignment mask will cause N+ ions to be injected into structures that do not require source injection (such as the terminal structure of the SiC Mosfet device); if the thickness of the self-alignment mask is increased, although the injection of N+ ions into areas where source injection is not required can be avoided, the channel length corresponds to the thickness of the self-alignment mask. Increasing the thickness of the self-alignment mask will increase the length of the channel, making the channel on-resistance larger. Therefore, how to reduce the device on-resistance and avoid source injection in areas where source injection is not required during the channel formation process of the SiC Mosfet device manufacturing process is a problem that needs to be solved. Summary of the invention
[0004] The present application provides a channel formation method for a SiC MOSFET device and a SiC MOSFET device, so as to solve the problem in the prior art that it is impossible to reduce the on-resistance of the device and avoid source injection in an area where source injection is not required during the channel formation process of the SiC MOSFET device manufacturing process.
[0005] An embodiment of the present application provides a channel forming method of a SiC MOSFET device, the method comprising:
[0006] Making a first mask on the SiC epitaxial layer, wherein the first mask sequentially includes an inner mask layer and an outer mask layer in a direction away from the SiC epitaxial layer;
[0007] Defining a first implantation region based on the first mask, and performing N-type ion implantation on the first implantation region to form a JFET region;
[0008] Removing the outer mask layer corresponding to the terminal region of the SiC MOSFET device, and retaining the inner mask layer corresponding to the terminal region;
[0009] Making a second mask on the surface of the JFET region and the surface of the inner mask layer corresponding to the terminal region, defining a second injection region based on the second mask, and performing P-type ion implantation on the second injection region to form a P-well region in the JFET region and a terminal structure in the terminal region;
[0010] Growing and depositing a third mask on the surface of the SiC epitaxial layer;
[0011] removing the third mask corresponding to the positions of the P-well region and the terminal structure, and retaining the third mask distributed on the sidewall surface of the remaining portion of the second mask;
[0012] The third mask distributed on the side wall surface of the remaining part of the second mask forms a source injection window, source injection is performed based on the source injection window, and the inner mask layer is used as an injection barrier layer in the terminal area to form a channel in the P-well area, and the length of the channel is the same as the thickness of the third mask distributed on the side wall surface of the remaining part of the second mask.
[0013] In some embodiments, the inner mask layer and the outer mask layer correspond to different materials, and a selection ratio between the inner mask layer and the outer mask layer is higher than a predetermined threshold;
[0014] The removing the outer mask layer corresponding to the terminal region of the SiC MOSFET device and retaining the inner mask layer corresponding to the terminal region includes:
[0015] The outer mask layer corresponding to the terminal region of the SiC epitaxial layer is removed by a wet etching process, while the inner mask layer corresponding to the terminal region is retained.
[0016] In some embodiments, the inner mask layer is silicon nitride and the outer mask layer is silicon dioxide;
[0017] The step of removing the outer mask layer corresponding to the terminal region of the SiC epitaxial layer by a wet etching process while retaining the inner mask layer corresponding to the terminal region comprises:
[0018] Chemical etching is performed using hydrofluoric acid to remove silicon dioxide corresponding to the terminal region of the SiC epitaxial layer, and to retain silicon nitride corresponding to the terminal region.
[0019] In some embodiments, an ion implantation protection layer is further included between the inner mask layer and the SiC epitaxial layer;
[0020] The defining of the first implantation region based on the first mask includes: using the ion implantation protection layer as an etching stop layer, and performing photolithography etching on the inner mask layer and the outer mask layer, so as to define the first implantation region.
[0021] In some embodiments, removing the outer mask layer corresponding to the terminal region of the SiC MOSFET device and retaining the inner mask layer corresponding to the terminal region includes:
[0022] The ion implantation protection layer corresponding to the JFET region and the outer mask layer corresponding to the terminal region are removed, and the inner mask layer and the ion implantation protection layer corresponding to the terminal region are retained.
[0023] In some embodiments, the material of the ion implantation protection layer is the same as that of the outer mask layer of the first mask, and the thickness of the ion implantation protection layer is less than the thickness of the outer mask layer.
[0024] In some embodiments, the method further includes: removing the inner mask layer, the second mask, and the third mask.
[0025] In some embodiments, removing the third mask corresponding to the positions of the P-well region and the terminal structure and retaining the third mask distributed on the sidewall surface of the remaining portion of the second mask includes:
[0026] The third mask is etched by using an etching process to retain the third mask deposited on the side wall surface of the second mask.
[0027] In some embodiments, the third mask is polysilicon, and the source injection based on the source injection window includes: using the polysilicon as an injection barrier layer of the source injection window to inject N+ ions.
[0028] According to another aspect of the present invention, a SiC MOSFET device is provided, wherein a channel of the SiC MOSFET device is manufactured by the channel forming method of the SiC MOSFET device as described above.
[0029] Compared with the prior art, this application has the following advantages:
[0030] The SiC provided in the embodiment of the present application The channel forming method of the MOSFET device comprises: making a first mask on a SiC epitaxial layer, the first mask sequentially comprising an inner mask layer and an outer mask layer in a direction away from the SiC epitaxial layer; defining a first injection region based on the first mask, and performing N-type ion injection on the first injection region to form a JFET region; removing the outer mask layer corresponding to the terminal region of the SiCMOSFET device, and retaining the inner mask layer corresponding to the terminal region; making a second mask on the surface of the JFET region and the surface of the inner mask layer corresponding to the terminal region, defining a second injection region based on the second mask, and performing P-type ion injection on the second injection region to form a P-well region in the JFET region and a terminal structure in the terminal region; growing and depositing a third mask on the surface of the SiC epitaxial layer; removing the third mask corresponding to the position of the P-well region and the terminal structure, and retaining the third mask distributed on the side wall surface of the remaining part of the second mask; forming a source injection window with the third mask distributed on the side wall surface of the remaining part of the second mask, performing source injection based on the source injection window, and using the inner mask layer as an injection barrier layer of the terminal region to form a channel in the P-well region. In the process of forming a channel by the above-mentioned self-alignment process, due to the existence of the inner mask layer, when performing source injection, the area where source injection is not required (such as the terminal structure in the terminal area) will not be able to inject N+ ions due to the shielding of the inner mask layer, so that the injection energy is no longer limited by the thickness of the third mask (self-alignment mask) (corresponding to the channel length), that is, no matter how large or small the injection energy is, the thickness of the self-alignment mask can be reduced to shorten the channel length and thus reduce the on-resistance, and the inner mask layer can be used as an injection barrier layer in the terminal area to avoid source injection in the area where source injection is not required.
[0031] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specifically cites the preferred embodiments and describes them in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A schematic diagram of a process for a method provided in an embodiment of the present application;
[0033] Figure 2-Figure 12 A schematic diagram of a channel formation process of a SiC MOSFET device provided in an embodiment of the present application;
[0034]
Explanation of symbols
[0035] Inner mask layer 1, outer mask layer 2, ion implantation protection layer 3, JFET region 4, second mask 5, P well region 6, terminal structure 7, third mask 8, source implantation window 9, source implantation region 10, channel 11 DETAILED DESCRIPTION
[0036] Many specific details are described in the following description to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present application, so the present application is not limited by the specific implementation disclosed below.
[0037] Compared with traditional silicon (Si) materials, silicon carbide (SiC) has the advantages of wide bandgap, high critical breakdown electric field, large saturation drift velocity and high thermal conductivity. It is an ideal material for preparing high-voltage and high-power devices. It is widely used in high-efficiency, high-power and high-temperature power electronics technology and has become a research hotspot in current power semiconductor technology. Power MOSFET devices based on SiC have the advantages of high current density, high breakdown voltage, low loss, good high-temperature characteristics and radiation resistance. Compared with traditional Si-based power MOSFET devices, they can simplify the topology of power electronic systems, reduce system volume and reduce power loss. There are two types of power SiC MOSFET device structures: planar gate type and trench type. Planar gate power SiC MOSFET devices have the JFET effect (that is, there is a depletion region in the PN junction, the depletion region cannot flow current, the on-resistance increases, and the device power consumption increases). Therefore, in planar gate power SiC MOSFET devices, how to reduce the on-resistance is a problem that needs to be solved.
[0038] In the current manufacturing process of planar gate SiC Mosfet devices, the mainstream channel formation method is a self-aligned process. For example, a layer of silicon dioxide is grown on a silicon carbide epitaxial layer to form a mask for injecting the JFET area; the injection area is defined on the mask by an etching process, and ion implantation is performed to form a JFET area to reduce the on-resistance of the device, thereby reducing the device loss; then, the mask is removed by a chemical corrosion method, and a mask for injecting the P-well area is deposited (defining the functional layer), and then the injection area is defined on the mask by a photolithography etching process, and P-type ion implantation is performed; then, another mask layer (polysilicon) is deposited and grown on the basis of the mask, and the thickness of the polysilicon is positively correlated with the channel length, and then the area that does not need to be removed is defined using photoresist. Etching polysilicon, that is, using photoresist to shield the terminal area where source injection is not required, and self-aligning etching is performed on the polysilicon in the JFET area that is not shielded by the photoresist. Due to the geometric effect of the sidewall, only the polysilicon deposited on the sidewall will remain, forming the so-called "spacer". The thickness of the sidewall polysilicon is the same as that of the polysilicon deposited before etching, thereby forming a source injection window (the terminal area is shielded by the photoresist, and the polysilicon at the bottom is retained, which is used as an ion injection protection layer during the subsequent N+ ion injection, so that the terminal area is exempted from the subsequent N+ ion injection). Subsequently, the photoresist is removed, and N+ ion injection is performed. The distance between the boundary of the N+ ion injection area and the boundary of the longitudinal polysilicon (i.e., the thickness of the polysilicon) is the channel length. The so-called self-alignment means that the length of the channel can be controlled by setting the thickness of the self-alignment mask.
[0039] In the above self-alignment process, the channel length corresponds to the thickness of the self-alignment mask. In order to reduce the on-resistance, a shorter channel is usually required, so the thickness of the self-alignment mask needs to be reduced. However, a thinner self-alignment mask will cause N+ ions to be injected into structures that do not require source injection (such as the terminal structure of the SiC Mosfet device). For example, when the above N+ ion injection is performed, under the same ion injection energy, when the source injection is realized in the JFET region, since the thickness of the polysilicon as the ion injection protection layer in the terminal region is thinner, some N+ ions may pass through the ion injection protection layer; if the thickness of the self-alignment mask is increased, although the above situation can be avoided, since the channel length corresponds to the thickness of the self-alignment mask, increasing the thickness of the self-alignment mask will increase the length of the channel, making the channel on-resistance larger. Therefore, how to reduce the on-resistance of the device and avoid source injection in the region where source injection is not required during the channel formation process of the SiC Mosfet device manufacturing process is a problem that needs to be solved.
[0040] In view of the above problems existing in the channel formation process of the existing SiC MOSFET device, in order to reduce the on-resistance of the device and avoid source injection in the area where source injection is not required during the channel formation process of the SiCMosfet device manufacturing process, the embodiment of the present application provides a channel formation method of a SiC MOSFET device and a SiC MOSFET device including a channel formed by the method, please refer to Figure 1 , Figure 2-Figure 12 To understand this embodiment, Figure 1 A schematic diagram of a process for forming a channel of a SiC MOSFET device provided in this embodiment, Figure 2-Figure 12 A schematic diagram of a channel formation process of a SiC MOSFET device provided in this embodiment is provided in this embodiment.
[0041] like Figure 1 as well as Figure 2-Figure 12 As shown, the channel forming method of the SiC MOSFET device provided in this embodiment includes the following steps:
[0042] S1: A first mask is made on a SiC epitaxial layer (SiC EPI), wherein the first mask includes an inner mask layer 1 and an outer mask layer 2 in sequence along a direction away from the SiC epitaxial layer; in the present embodiment, the inner mask layer 1 is thicker so that it can act as an injection barrier layer during ion implantation, and the inner mask layer 1 and the outer mask layer 2 correspond to different materials, and the selectivity between the inner mask layer 1 and the outer mask layer 2 is higher than a predetermined threshold value, so that when the outer mask layer 2 is removed by a wet method, the inner mask layer 1 can be removed without loss or with less loss.
[0043] S2: Define a first implantation region based on a first mask (eg Figure 3 As shown), and N-type ion implantation is performed on the first implantation region to form a JFET region 4 (as shown Figure 4 As shown), for example, the inner mask layer 1 and the outer mask layer 2 are etched by an etching process to define a first injection region, and the first injection region is N-type ion implanted with a preset doping concentration to obtain a JFET region 4, the implantation energy may be 400-600Kev, and the implantation dose may be E12 atoms per square centimeter; due to the existence of a JFET effect in a planar gate power SiC MOSFET device (i.e., a depletion region exists in a PN junction, current cannot flow through the depletion region, the on-resistance increases, and the power consumption of the device increases), the purpose of the JFET region 4 is to weaken the JFET effect, that is, after the N-type ion implantation is performed on the first injection region to form the JFET region 4, the doping concentration in the N region is increased, and the width of the depletion region in the N region is reduced, so that the area where the current is allowed to flow is wider, and the on-resistance can be reduced.
[0044] S3: removing the outer mask layer 2 corresponding to the terminal region of the SiC MOSFET device, and retaining the inner mask layer 1 corresponding to the terminal region (such as Figure 5 In this embodiment, the outer mask layer 2 corresponding to the terminal region of the SiC MOSFET device is removed, and the inner mask layer 1 corresponding to the terminal region is retained. Specifically, it can refer to: using a wet etching process to remove the outer mask layer 2 corresponding to the terminal region of the SiC epitaxial layer, while retaining the inner mask layer 1 corresponding to the terminal region. For example, the inner mask layer 1 is silicon nitride and the outer mask layer 2 is silicon dioxide. Hydrofluoric acid is used for chemical etching to remove the silicon dioxide corresponding to the terminal region of the SiC epitaxial layer and retain the silicon nitride corresponding to the terminal region. Since the selectivity of silicon dioxide and silicon nitride is relatively high, when the chemical agent hydrofluoric acid is used to etch silicon dioxide, silicon nitride will be retained.
[0045] S4: Make a second mask 5 (such as Figure 6 As shown), based on the second mask 5, a second injection region is defined (as shown Figure 7 As shown), and P-type ion implantation is performed on the second implantation region to form a P-well region 6 (Pbody) in the JFET region 4 and a terminal structure 7 (as shown) in the terminal region. Figure 8 As shown); for example, a photoresist with a thickness of 2 um is coated on the surface of the silicon carbide epitaxial layer (including the surface of the JFET region 4 and the surface of the inner mask layer 1 corresponding to the terminal region), and the photoresist is patterned by a photolithography process to form a patterned photoresist. Based on the patterned photoresist, a second injection region (that is, the second injection region may be an injection region including multiple P-well regions 6 and multiple terminal structures 7) for injection into the JFET region 4 to form a P-well region 6 and into the terminal region to form a main junction, a field limiting ring and other terminal structures 7 is defined by a wet back-etching process. Then, Al ion injection is performed on the second injection region. The injection energy may be 70-500 Kev, and the injection dose may be E13 atoms per square centimeter to form two P-well regions 6 in the JFET region 4, and to form multiple terminal structures 7 including a main junction and a field limiting ring in the terminal region.
[0046] S5: A third mask 8 (such as Fig. 9 As shown), in this embodiment, the third mask 8 may be polysilicon, and its thickness may be 400nm;
[0047] S6: remove the third mask corresponding to the position of the P-well region 6 and the terminal structure 7, and retain the third mask distributed on the side wall surface of the remaining part of the second mask 5; for example, use an etching process to perform self-aligned etching on the upper surface of the SiC epitaxial layer. Due to the geometric effect of the side wall, only the third mask deposited on the side wall of the second mask will remain to form a so-called "spacer", and the second mask and the third mask on the surface of the SiC epitaxial layer are etched away, that is, use the same etching process to etch the third mask distributed in the JFET region 4 and the terminal region, and do not etch the polysilicon distributed on the side wall surface of the remaining part of the second mask 5, so as to remove the polysilicon corresponding to the position of the P-well region 6 and the terminal structure 7, and retain the polysilicon distributed on the side wall surface of the remaining part of the second mask 5 (such as Fig.10 shown).
[0048] S7: The third mask 8 distributed on the sidewall surface of the remaining portion of the second mask 5 forms a source injection window 9, and source injection is performed based on the source injection window 9 to form a source injection region 10 (such as Fig.11 As shown), for example, the polysilicon (vertical mask) distributed on the side wall surface of the remaining part of the second mask 5 is used as the injection barrier layer of the source injection window 9 to perform N+ ion injection (for example, the injection energy can be 50-150Kev, and the injection dose can be E15 atoms per square centimeter), and the remaining inner mask layer 1 (for example, silicon nitride) of the terminal region is used as the injection barrier layer of the terminal region, so that N+ ions cannot be injected into the terminal structures 7 such as the main junction and the field limiting ring in the terminal region, thereby forming a channel 11 in the P-well region 6, and the length of the channel 11 is positively correlated with the thickness of the third mask 8 distributed on the side wall surface of the remaining part of the second mask 5, that is, the distance between the boundary of the N+ ion injection region and the boundary of the P-well region 6 is the channel length, and the third mask 8 distributed on the side wall surface of the remaining part of the second mask 5 is a self-aligned mask, and the length of the channel 11 can be controlled by controlling the thickness of the self-aligned mask. The position of the self-aligned mask is determined, and the length of the channel 11 is determined.
[0049] S8: Remove the inner mask layer 1, the second mask 5 and the third mask 8 (such as Fig.12 ), and then proceed to the subsequent process.
[0050] In this embodiment, an ion implantation protection layer 3 (such as Figure 2As shown), the material of the ion implantation protection layer 3 is the same as that of the outer mask layer 2 of the first mask, and the thickness of the ion implantation protection layer 3 is less than that of the outer mask layer 2, that is, due to the relatively large stress of silicon nitride, it is necessary to use silicon dioxide to deposit a thinner buffer layer between the silicon nitride and the SiC epitaxial layer. For example, the inner mask layer 1 is silicon nitride, the outer mask layer 2 is silicon dioxide, and the ion implantation protection layer 3 is a thinner silicon dioxide made of the same material as the outer mask layer 2. In the above step S1, silicon dioxide with a thickness of 500A, silicon nitride with a thickness of 6000A, and silicon dioxide with a thickness of 14000A are sequentially deposited on the surface of the SiC epitaxial layer; in the above step S2, defining the first implantation region based on the first mask may specifically refer to: using the ion implantation protection layer 3 as an etching stop layer, photolithography etching is performed on the inner mask layer 1 and the outer mask layer 2, so as to define the first implantation region (as shown in FIG. Figure 3 In the above step S3, the outer mask layer 2 corresponding to the terminal region of the SiC MOSFET device is removed, and the inner mask layer 1 corresponding to the terminal region is retained. Specifically, it can refer to: removing the ion implantation protection layer 3 corresponding to the JFET region 4 and the outer mask layer 2 corresponding to the terminal region, and retaining the inner mask layer 1 and the ion implantation protection layer 3 corresponding to the terminal region (as shown in FIG. Figure 5 As shown, for example, since the selectivity ratio of silicon dioxide and silicon nitride is higher than a predetermined threshold, when silicon dioxide is etched using a chemical agent (such as hydrofluoric acid), silicon nitride will be retained and the thinner silicon dioxide under the silicon nitride will also be protected by the silicon nitride.
[0051] The channel forming method of the SiC MOSFET device provided in this embodiment comprises: making a first mask on the SiC epitaxial layer, wherein the first mask comprises an inner mask layer 1 and an outer mask layer 2 in a direction away from the SiC epitaxial layer; defining a first implantation region based on the first mask, and performing N-type ion implantation on the first implantation region to form a JFET region 4; removing the SiC epitaxial layer; and removing the inner mask layer 1 from the SiC epitaxial layer. An outer mask layer 2 corresponding to the terminal region of the MOSFET device is retained, and an inner mask layer 1 corresponding to the terminal region is retained; a second mask 5 is made on the surface of the JFET region 4 and the surface of the inner mask layer 1 corresponding to the terminal region, a second injection region is defined based on the second mask 5, and P-type ion injection is performed on the second injection region to form a P-well region 6 in the JFET region 4 and a terminal structure 7 in the terminal region; a third mask 8 is grown and deposited on the surface of the SiC epitaxial layer; the third mask 8 corresponding to the position of the P-well region 6 and the terminal structure 7 is removed, and the third mask 8 distributed on the side wall surface of the remaining part of the second mask 5 is retained; a source injection window 9 is formed on the third mask 8 distributed on the side wall surface of the remaining part of the second mask 5, source injection is performed based on the source injection window 9, and the inner mask layer 1 is used as an injection barrier layer in the terminal region to form a channel in the P-well region 6, and the length of the channel is the same as the thickness of the third mask 8 distributed on the side wall surface of the remaining part of the second mask 5. In the process of forming a channel by a self-alignment process, due to the existence of the inner mask layer 1, when performing source injection, the area where source injection is not required (i.e., the terminal structure 7 in the terminal area) cannot be injected with N+ ions due to the shielding of the inner mask layer 1, so that the injection energy during source injection is no longer limited by the thickness of the third mask 8 (self-alignment mask) (corresponding to the channel length). That is, no matter whether the injection energy is large or small, the thickness of the self-alignment mask can be reduced to shorten the channel length and thus reduce the on-resistance, and the inner mask layer 1 acts as an injection barrier layer in the terminal area to avoid source injection into the area where source injection is not required.
[0052] Furthermore, in the process of forming the source injection window 9 to define the source injection region 10, the third mask 8 corresponding to the position of the P-well region 6 and the terminal structure 7 is removed (for example, the same etching process can be used to remove the third mask 8 distributed in the JFET region 4 and the terminal region), and there is no need to use photoresist to define the area that does not need to be removed, that is, there is no need to use photoresist to block the terminal region, so that the process of forming the source injection window 9 to define the source injection region 10 does not require the use of a photoresist, which can simplify the process flow and reduce manufacturing costs.
[0053] Another embodiment of the present application further provides a SiC MOSFET device, wherein a channel of the SiC MOSFET device is manufactured by the channel formation method of the SiC MOSFET device provided in the above embodiment. For the specific contents of the channel of the SiC MOSFET device, please refer to the relevant description of the above embodiment, which will not be repeated here.
[0054] It should be noted that although the present application is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field may make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.
Claims
1. A method for forming a channel of a SiC MOSFET device, characterized in that: The method comprises: Making a first mask on the SiC epitaxial layer, wherein the first mask sequentially includes an inner mask layer and an outer mask layer in a direction away from the SiC epitaxial layer; Defining a first implantation region based on the first mask, and performing N-type ion implantation on the first implantation region to form a JFET region; Removing the outer mask layer corresponding to the terminal region of the SiC MOSFET device, and retaining the inner mask layer corresponding to the terminal region; Making a second mask on the surface of the JFET region and the surface of the inner mask layer corresponding to the terminal region, defining a second injection region based on the second mask, and performing P-type ion implantation on the second injection region to form a P-well region in the JFET region and a terminal structure in the terminal region; Growing and depositing a third mask on the surface of the SiC epitaxial layer; removing the third mask corresponding to the positions of the P-well region and the terminal structure, and retaining the third mask distributed on the sidewall surface of the remaining portion of the second mask; The third mask distributed on the sidewall surface of the remaining part of the second mask forms a source injection window, source injection is performed based on the source injection window, and the inner mask layer is used as an injection barrier layer in the terminal area to form a channel in the P-well area.
2. The method according to claim 1, characterized in that The inner mask layer and the outer mask layer correspond to different materials, and a selection ratio between the inner mask layer and the outer mask layer is higher than a predetermined threshold; The removing the outer mask layer corresponding to the terminal region of the SiC MOSFET device and retaining the inner mask layer corresponding to the terminal region includes: The outer mask layer corresponding to the terminal region of the SiC epitaxial layer is removed by a wet etching process, while the inner mask layer corresponding to the terminal region is retained.
3. The method according to claim 2, characterized in that The inner mask layer is silicon nitride, and the outer mask layer is silicon dioxide; The step of removing the outer mask layer corresponding to the terminal region of the SiC epitaxial layer by a wet etching process while retaining the inner mask layer corresponding to the terminal region comprises: Chemical etching is performed using hydrofluoric acid to remove silicon dioxide corresponding to the terminal region of the SiC epitaxial layer, and to retain silicon nitride corresponding to the terminal region.
4. The method according to claim 1, characterized in that An ion implantation protection layer is also included between the inner mask layer and the SiC epitaxial layer; The defining of the first implantation region based on the first mask includes: using the ion implantation protection layer as an etching stop layer, and performing photolithography etching on the inner mask layer and the outer mask layer, so as to define the first implantation region.
5. The method according to claim 4, characterized in that The removing the outer mask layer corresponding to the terminal region of the SiC MOSFET device and retaining the inner mask layer corresponding to the terminal region includes: The ion implantation protection layer corresponding to the JFET region and the outer mask layer corresponding to the terminal region are removed, and the inner mask layer and the ion implantation protection layer corresponding to the terminal region are retained.
6. The method according to claim 4 or 5, characterized in that: The material of the ion implantation protection layer is the same as that of the outer mask layer of the first mask, and the thickness of the ion implantation protection layer is smaller than the thickness of the outer mask layer.
7. The method according to claim 1, characterized in that The method further includes removing the inner mask layer, the second mask, and the third mask.
8. The method according to claim 1, characterized in that The step of removing the third mask corresponding to the positions of the P-well region and the terminal structure and retaining the third mask distributed on the sidewall surface of the remaining portion of the second mask comprises: The third mask is etched by using an etching process to retain the third mask deposited on the side wall surface of the second mask.
9. The method according to claim 1, characterized in that: The third mask is polysilicon, and the source injection is performed based on the source injection window, including: using the polysilicon as an injection barrier layer of the source injection window to perform N+ ion injection.
10. A SiC MOSFET device, characterized in that: The channel of the SiC MOSFET device is manufactured by the channel forming method of the SiC MOSFET device according to any one of claims 1 to 9.