Low resistance via structure

Abstract

Techniques for forming low resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending over the semiconductor region in a second direction. Any semiconductor device may be separated from an adjacent semiconductor device along a second direction by a dielectric structure through which a via passes. The via may include a conductive portion extending through the dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive filler on the conductive liner. The conductive liner includes a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel-aluminum alloy, where there is no metal nitride or barrier layer between the conductive liner and the dielectric wall.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits, and more particularly, to via structures. Background Art

[0002] As the size of integrated circuits continues to shrink downward, many challenges arise. For example, it becomes increasingly difficult to reduce the size of memory and logic cells, especially given the competing interests that exist within a relatively small amount of space. For example, routing signals and power throughout a circuit can be challenging given the limited space and density of the device. The resistance of the interconnect structures that route signals and power affects the overall speed and feasibility of the device. Therefore, there are still many challenges with respect to the formation of semiconductor devices in memory or logic cells that are difficult to ignore. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A is a cross-sectional view of an integrated circuit structure including a low resistance via structure according to an embodiment of the present disclosure.

[0004] Figure 1B According to the embodiment of the present disclosure Figure 1A A plan view of an integrated circuit showing low resistance via structures extending between devices.

[0005] Figure 2A-2I is a cross-sectional diagram illustrating stages in an example process for forming an integrated circuit configured with a low resistance via structure according to some embodiments of the present disclosure.

[0006] Figure 3A and Figure 3B is a cross-sectional view illustrating a further stage in an example process for forming an integrated circuit configured with a low resistance via structure including removal of a substrate according to some embodiments of the present disclosure.

[0007] Figure 4 Energy dispersive x-ray spectroscopy (EDX) analysis across a low resistance via structure is shown.

[0008] Figure 5 A cross-sectional view of a chip package containing one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0009] Figure 6 is a flow chart of a manufacturing process for a semiconductor device having a low resistance via structure according to an embodiment of the present disclosure.

[0010] Figure 7 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0011] Although the following description of the specific embodiments will be made with reference to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent in light of the present disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For example, although some of the drawings generally indicate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topology or otherwise be non-smooth, given the real-world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0012] Provided herein is a technique for forming a low resistance via structure. The technique can be used for any number of via applications, and is particularly useful for forming a via structure having a relatively high aspect ratio (e.g., a deep via structure extending vertically through a device layer of an integrated circuit). The via structure can, for example, pass through a dielectric material filling material layer, or through a dielectric structure that separates adjacent devices of a given die (e.g., such as a gate cutout structure or a dielectric wall). For example, a via can be used to couple one or more front interconnect features (e.g., a transistor contact) to one or more back interconnect features (e.g., a power delivery network), although any number of interconnect schemes can be used. In any such case, the dielectric material can be a low-k dielectric material, although other dielectric materials can also be used. In an example, the via structure includes a conductive liner directly on the dielectric wall and a conductive filler on the conductive liner. The conductive liner can be an elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel-aluminum alloy, wherein there is no metal nitride or barrier layer between the conductive liner and the dielectric wall. In some such examples, the conductive liner is a first metal (e.g., molybdenum) deposited by a first deposition process (e.g., physical vapor deposition, PVD), and the conductive filler is a second metal (e.g., tungsten) deposited by a second deposition process (e.g., chemical vapor deposition CVD or atomic layer deposition ALD). In other such examples, the first metal and the second metal are the same elemental metal. In any such examples, the conductive liner can have a greater thickness at the bottom of the via structure relative to its thickness on the sidewalls of the via structure. Many variations and embodiments will be apparent in light of this disclosure.

[0013] General Overview

[0014] As described above, there are still many challenges that are difficult to ignore regarding the formation of various semiconductor structures. Considering the number and density of semiconductor devices on a single die, power and signal transmission can be challenging. For example, power and signal transmission can be performed by passing conductive traces such as conductive lines and vias through dielectric materials. For example, some vias can be used to connect any front-side interconnects with power traces on the back of the die (e.g., deep vias). The manufacture of such deep vias is important, and the resistance of such structures can be difficult to keep low because a barrier layer is typically used between the metal material and the dielectric in which the via is formed (e.g., to promote better adhesion and / or inhibit electromigration). The barrier layer typically includes a metal nitride material (e.g., titanium nitride, tantalum nitride, tungsten carbonitride), which can be relatively high in resistance or low in conductivity compared to the metal-filled portion of the via.

[0015] Therefore, and in accordance with embodiments of the present disclosure, techniques for forming low-resistance vias along semiconductor devices are provided herein. Due to the lack of any nitride-based barrier layer, these techniques allow the formation of vias with overall higher conductivity. In an example, each semiconductor device includes a semiconductor or channel region extending between a source region or a drain region in a first direction, such as a fin of a semiconductor material or a nanobelt, nanowire, or nanosheet of a semiconductor material. A gate structure including both a gate dielectric and a gate electrode extends over a semiconductor region in a second direction different from the first direction (e.g., perpendicular to the first direction). The gate structure may extend over multiple semiconductor regions of different semiconductor devices along a second direction. According to some embodiments, the gate structure is interrupted by any number of gate cuts extending through the entire thickness of the gate structure, and may also extend through any number of gate trenches and source / drain trenches in the first direction. In some such cases, deep vias are formed in the dielectric material of the gate cuts. In other cases, deep vias are formed in the dielectric filling material between the devices. In any such case, the dielectric material may be a low-k dielectric material to help reduce parasitic capacitance. The via includes a metal liner and a metal filler on the metal liner. In an example, the metal liner is deposited using an ionized physical vapor deposition (PVD) technique to provide enhanced adhesion to the dielectric surface of the dielectric wall. The metal liner can be a pure elemental metal, such as tungsten, molybdenum, ruthenium, nickel aluminum alloy, or any other suitable metal or metal alloy with a high atomic weight (e.g., greater than 90). The metal filler can be deposited on the metal liner using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). The metal filler can be the same pure elemental metal as the metal liner, but can also be a different elemental metal. According to some embodiments, the use of PVD to deposit the liner means that there are no traces of carbon, fluorine, or chlorine in the liner. In addition, the deposition of the metal liner and the metal filler can be performed in situ so that there are no traces of oxygen at the boundary between the metal liner and the metal filler. In addition, resistive materials such as metal nitrides are avoided.

[0016] According to an embodiment, an integrated circuit includes a semiconductor device having a semiconductor region extending from a first source or drain region in a first direction, a gate electrode extending above the semiconductor region in a second direction, and a conductive via extending through the entire thickness of the gate electrode in a third direction and adjacent to the semiconductor device in the second direction. In some examples, the conductive via passes through a dielectric material layer, such as a dielectric fill material or a dielectric wall (separate from any gate cutouts). In any such case, the conductive via includes a conductive liner and a conductive filler on the conductive liner. The conductive liner can be a pure elemental metal or otherwise free of nitride.

[0017] According to another embodiment, an integrated circuit includes a first semiconductor device and a second semiconductor device, the first semiconductor device having a first semiconductor region extending from a first source or drain region to a second source or drain region in a first direction, and a first gate structure extending over the first semiconductor region in a second direction, the second semiconductor device having a second semiconductor region extending from a third source or drain region to a fourth source or drain region in the first direction, and a second gate structure extending over the second semiconductor region in the second direction. The third source or drain region is aligned with the first source or drain region along the second direction, and the fourth source or drain region is aligned with the second source or drain region along the second direction. The integrated circuit also includes a dielectric wall extending between and contacting the first gate structure and the second gate structure in the first direction. The dielectric wall also extends through the entire thickness of each of the first gate structure and the second gate structure in a third direction. The integrated circuit also includes a conductive via extending through the entire thickness of the dielectric wall in the third direction. The conductive via includes a conductive liner and a conductive filler on the conductive liner. The conductive liner can be a pure elemental metal directly on the dielectric wall.

[0018] According to another embodiment, a method of forming an integrated circuit includes: forming a fin including a semiconductor material, the fin extending above a substrate and extending in a first direction; forming a dielectric layer adjacent to a sub-fin portion of the fin; forming a source region or a drain region at opposite ends of the fin; forming a gate structure on the dielectric layer and above the semiconductor material, and the gate structure extends in a second direction; forming a dielectric wall through the entire thickness of the gate structure, the dielectric wall extending adjacent to the fin in the first direction; forming a trench through the dielectric wall so that the trench extends along at least the entire thickness of the gate structure; forming a conductive liner of pure elemental metal within the trench; and forming a conductive filler within the remaining portion of the trench on the conductive liner.

[0019] These techniques can be used with any type of non-planar transistor, including finFETs (sometimes called dual-gate transistors or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called full-all-around transistors), to name just a few examples. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions deposited during etching and alternative source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate or RMG process), or any other gate formation process. Any number of semiconductor materials can be used to form transistors, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0020] The use of the techniques and structures provided herein can be detected using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; X-ray crystallography or diffraction (XRD); energy dispersive X-ray spectroscopy (EDX); energy dispersive spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name just a few suitable example analytical tools. For example, in some example embodiments, such tools can indicate the presence of a via structure having a highly conductive liner (e.g., without a metal nitride adhesion or barrier layer) and a fill material thereon. Any form of EDX or EDS analysis can be used to show that the via includes pure elemental metal directly on the adjacent dielectric wall. In addition, such analysis can also indicate that the structure includes a metal liner and a metal filler, and that there are no carbon, fluorine, or chlorine atoms within the metal liner. In some cases, due to the PVD process, the thickness of the liner at the bottom of the via can be greater relative to its thickness on the sidewalls of the via. The absence of oxygen at the interface between the liner and the fill material can further indicate an in-situ liner fill process. Many configurations and variations will be apparent in light of this disclosure.

[0021] It should be readily understood that the meaning of "above" and "above" in the present disclosure should be interpreted in the broadest manner, so that "above" and "above" not only mean "directly on something", but also include the meaning of being above something with intermediate features or layers therebetween. In addition, for ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", "top", "bottom", etc. may be used herein to describe the relationship between one element or feature and another one or more elements or features as shown in the figures. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0022] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure, wherein the thickness of the layer is less than the thickness of the continuous structure. For example, a layer may be located between or between any pair of horizontal planes between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved) and have a relatively uniform thickness over the entire layer.

[0023] As used herein, "compositionally different" or "compositionally dissimilar" materials refer to two materials having different chemical compositions. This compositional difference can be, for example, due to an element in one material that is not in the other material (e.g., SiGe is compositionally different from silicon), or it can be present as one material having all of the same elements as a second material, but intentionally providing at least one of these elements in a different concentration in one material relative to the other material (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this chemical composition diversity, the materials can also have different dopants (e.g., gallium and magnesium) or the same dopants but in different concentrations. In other embodiments, compositionally different materials can further refer to two materials having different crystallographic orientations. For example, (110) silicon is compositionally dissimilar or different from (100) silicon. Creating stacks of different orientations can be achieved, for example, using blanket wafer layer transfer. If two materials are elementally different, then one of the materials has an element that is not in the other material.

[0024] Architecture

[0025] 1 is a cross-sectional view of a portion of an integrated circuit including a semiconductor device and a deep via according to an embodiment of the present disclosure. Each semiconductor device can be a non-planar metal oxide semiconductor (MOS) transistor, such as a tri-gate or gate-all-around (GAA) transistor, but other transistor topologies and types can also benefit from the techniques provided herein. The examples herein illustrate semiconductor devices having a GAA structure (e.g., having nanoribbons, nanowires, or nanosheets extending between source and drain regions).

[0026] One or more semiconductor regions of the device may include fins that may be, for example, substrate native (formed by the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins may be formed from materials deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In other embodiments, the fins include alternating layers of material (e.g., alternating silicon layers and SiGe layers) that facilitate the formation of nanowires and nanoribbons during a gate formation process, wherein one type of alternating layers is selectively etched away to release another type of alternating layers within the channel region so that a full-ring gate process may then be performed. Again, the alternating layers may be blanket deposited and then etched into fins or deposited into fin trenches.

[0027] The semiconductor material used in each semiconductor device can be formed by a semiconductor substrate 101. Substrate 101 can be, for example, a bulk substrate including a Group IV semiconductor material (such as silicon, germanium, or silicon germanium), a Group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which a transistor can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate having a desired semiconductor layer above a buried insulator layer (e.g., silicon above silicon dioxide). Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, substrate 101 is removed and replaced with one or more back-side interconnect layers to form back-side signal and power wiring.

[0028] Each semiconductor device includes one or more semiconductor regions, such as one or more nanoribbons 102 extending between epitaxial source regions or drain regions (not shown in this view) in a first direction along the X-axis. This example includes four nanoribbons 102 per device, but other examples may have two or three or other numbers of nanoribbons. As can be further seen, according to an embodiment, the dielectric layer 103 extends across the bottom portion of the integrated circuit and adjacent to the sub-fin 104 of each semiconductor device. The dielectric layer 103 may include any suitable dielectric material, such as silicon dioxide. The dielectric layer 103 may provide shallow trench isolation (STI) between adjacent semiconductor devices. According to some embodiments, the sub-fin 104 is a portion of the corresponding semiconductor fin retained after the formation of various transistors, and may be formed by a semiconductor substrate 101. Thus, the sub-fin 104 may include the same semiconductor material as one or more semiconductor regions of the semiconductor device.

[0029] A gate structure including a gate electrode 106 and a gate dielectric 108 extends over one or more semiconductor regions in a second direction (e.g., along the Y-axis) to form a transistor gate. The gate dielectric 108 may represent any number of dielectric layers. The gate electrode 106 may include any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some embodiments, the gate electrode 106 includes one or more work function metals around one or more semiconductor regions. In some embodiments, a p-channel device includes a work function metal having titanium around one or more semiconductor regions thereof, and an n-channel device includes a work function metal having tungsten around one or more semiconductor regions thereof. The gate electrode 106 may also include a fill metal or other conductive material around the work function metal to provide an entire gate electrode structure. A given gate structure may extend over semiconductor regions of more than one semiconductor device.

[0030] According to some embodiments, one or more vias 110 may extend across the gate structure in a first direction (e.g., parallel to the length of nanoribbon 102), and may continue to extend across any number of other gate trenches and source / drain trenches in the first direction. Vias 110 may include dielectric walls 112 and conductive portions extending through or within dielectric walls 112 along a third direction (e.g., along the Z-axis) to transmit logic signals, power, or ground between top-side interconnects and bottom-side interconnects.

[0031] The dielectric wall 112 may include any suitable dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride. In some examples, the dielectric wall 112 is a low-k dielectric material (a material having a dielectric constant equal to or lower than that of silicon dioxide, such as porous silicon dioxide). According to some embodiments, the dielectric wall 112 extends at least through the entire thickness of the gate structure within the gate trench. In some examples, the dielectric wall 112 also extends through the entire thickness of the dielectric layer 103 (as shown).

[0032] According to some embodiments, the conductive portion of via 110 includes a metal liner 114 and a metal filler 116. According to some embodiments, the metal liner 114 includes a pure elemental metal directly on the dielectric wall 112. For example, the metal liner 114 may include pure tungsten, pure molybdenum, pure ruthenium, or a nickel aluminum alloy, without other material layers between itself and the dielectric wall 112. The metal liner 114 may be deposited on the inner sidewall of the dielectric wall 112 using an ionized PVD process. According to some such embodiments, the PVD process allows ionized metal ions to penetrate into the dielectric wall 112, thereby providing greater adhesion between the metal liner 114 and the dielectric wall 112. According to some embodiments, the metal filler 116 may also include a pure elemental metal (e.g., the same pure elemental metal as the metal liner 114). The metal filler 116 may be deposited on the metal liner 114 using a CVD or ALD process. Since both the PVD process and the CVD / ALD process for depositing the metal liner 114 and the metal filler 116 can be performed in situ, according to some embodiments, the deposited metal does not oxidize, so that there are no oxygen atoms at the boundary between the metal liner 114 and the metal filler 116. In addition, the PVD process for depositing the metal liner 114 produces a film that is substantially free of any impurities. For example, the metal liner 114 may not contain any carbon, fluorine, and chlorine atoms. In some examples, the via 110 has a top width between about 20nm and about 30nm. The example shown has a relatively straight via sidewall, but in other examples, the via may taper gradually inward toward the bottom of the via. In any such case, the thickness of the liner 114 at the bottom of the via may be thicker than the thickness of the liner 114 on the via sidewall. For example, in some such examples, the thickness of the liner 114 at the bottom of the via may be about 2nm to 4nm (20 angstroms to 40 angstroms) thicker than the thickness of the liner 114 on the via sidewall.

[0033] Figure 1B Shown by Figure 1A1B plane intercepted in the plan view of the integrated circuit shown in . Nanoribbons 102 from different devices extend between corresponding source or drain regions 118 in a first direction. The source or drain region 118 can be formed at the end of one or more semiconductor regions of each device (such as at the end of the nanoribbon 102), so that it can be aligned with each other along the second direction in the common source / drain trench. According to some embodiments, the source or drain region 118 is an epitaxial region disposed on the semiconductor region in an etching and replacement process. In other embodiments, the source or drain region 118 can be a native part of an implanted doping of a fin or substrate, for example. Any semiconductor material suitable for the source or drain region (e.g., IV group and III-V group semiconductor materials) can be used. The source or drain region 118 can include multiple layers, such as a liner and a capping layer, to improve the contact resistance. In any such case, depending on the polarity of the transistor, the composition and doping of the source or drain region 118 can be the same or different. Any number of source or drain configurations and materials can be used. According to some embodiments, a dielectric filler 120 is provided within the source / drain trench adjacent to the source or drain region 118. The dielectric filler 120 may be any suitable dielectric material, such as silicon dioxide, and may also extend above the top surface of either the source or drain region 118. Figure 1B The example also shows a parallel pattern of different vias 110, all of which extend longitudinally in the first direction. According to some embodiments, the spacer structure 122 is present between the gate trench and the source / drain trench and can be formed on the sidewall of the gate structure. Therefore, the spacer structure 122 can extend longitudinally along the second direction with the gate structure. The spacer structure 122 may include any suitable dielectric material, such as silicon nitride, silicon dioxide, or silicon oxynitride.

[0034] Manufacturing method

[0035] Figure 2A-2I are cross-sectional views collectively illustrating an example process for forming an integrated circuit configured with unobstructed deep vias according to an embodiment of the present disclosure. The accompanying drawings represent cross-sectional views taken along the YZ plane, as shown in FIG. Figure 1A Each figure shows an example structure resulting from the process flow up to that point in time, so the structure shown evolves as the process flow continues, ultimately forming Fig.2I The structure shown is similar to Figure 1AThe structure shown. Such a structure may be part of an entire integrated circuit (e.g., a processor or memory chip) including, for example, digital logic cells and / or memory cells and analog mixed signal circuits. Thus, the integrated circuit structure shown may be part of a larger integrated circuit including other integrated circuits not shown. Example materials and process parameters are given, but as will be understood, the present disclosure is not intended to be limited to any particular such materials or parameters.

[0036] Figure 2A A cross-sectional view of multiple material layers formed over a substrate according to an embodiment of the present disclosure is shown. Alternating material layers may be deposited over a substrate 201 that includes sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 204 and sacrificial layers 202 may be deposited over the substrate 201.

[0037] According to some embodiments, sacrificial layer 202 has a different material composition than semiconductor layer 204. In some embodiments, sacrificial layer 202 is silicon germanium (SiGe), while semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material, such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layer 202 and semiconductor layer 204, the germanium concentration between sacrificial layer 202 and semiconductor layer 204 is different. For example, sacrificial layer 202 can include a higher germanium content than semiconductor layer 204. In some examples, semiconductor layer 204 can be doped with an n-type dopant (to produce a p-channel transistor) or a p-type dopant (to produce an n-channel transistor).

[0038] Although the dimensions may vary between example embodiments, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each of the semiconductor layers 204 may be substantially the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of the sacrificial layer 202 and the semiconductor layer 204 may be deposited using any known material deposition technique, such as CVD, plasma enhanced chemical vapor deposition (PECVD), PVD, or ALD.

[0039] Figure 2B FIG. 2 shows a structure after forming a capping layer 206 and subsequently forming a fin under the capping layer 206 according to an embodiment. Figure 2A. The capping layer 206 may be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The capping layer 206 is patterned into rows to form corresponding rows of fins from the alternating layer stack of sacrificial layer 202 and semiconductor layer 204. The rows of fins extend longitudinally in a first direction (e.g., into and out of the page of each cross-sectional view).

[0040] In accordance with some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of the substrate 201, wherein the unetched portion of the substrate 201 below the fin forms a sub-fin region 208. The etched portion of the substrate 201 may be filled with a dielectric filler 210 that acts as a shallow trench isolation (STI) between adjacent fins. The dielectric filler 210 may be any suitable dielectric material, such as silicon dioxide, and may be recessed to a desired depth as shown (in this example case, down to around the upper surface of the sub-fin region 210) to define an active portion of the fin that will be covered by the gate structure. In some embodiments, the dielectric filler 210 is recessed below the top surface of the sub-fin region 208.

[0041] Figure 2C FIG. 2 shows a schematic diagram of a fin after forming a sacrificial gate 212 extending across the fin in a second direction different from the first direction in accordance with some embodiments. Figure 2B . The sacrificial gate 212 may extend across the fin in a second direction perpendicular to the first direction. According to some embodiments, the sacrificial gate material is formed in parallel strips across the integrated circuit and is removed in all areas not protected by the gate masking layer. The sacrificial gate 212 may be any suitable material that may be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 212 includes polysilicon.

[0042] While etching away the exposed portions of the fins between the gate spacers, the sacrificial gate 212 (along with any gate spacers formed on the sidewalls of the sacrificial gate 212) protects the underlying portions of the fins. In accordance with some embodiments, both the semiconductor layer 204 and the sacrificial layer 202 are etched at substantially the same rate using an anisotropic reactive ion etching (RIE) process to form source / drain trenches. In some embodiments, inner gate spacers may be formed after etching the source / drain trenches and before any formation of source or drain regions. For example, a selective etch may be used to laterally recess the sacrificial layer 202, which may then be filled with an inner gate spacer material (e.g., silicon nitride or silicon oxynitride). Any excess gate spacer material may be removed using a directional etch.

[0043] According to some embodiments, a source region or a drain region is formed after forming the sacrificial gate 212. The source region or the drain region is not shown in this cross section because they will exist at the end of the semiconductor layer 204 entering and exiting the page. According to some embodiments, the source or drain region can be epitaxially grown from the exposed end of the semiconductor layer 204 so that the materials grow together or otherwise merge toward the middle of the trench between the fins. Note that the epitaxial growth on one semiconductor layer 204 can be completely or partially merged with the epitaxial growth on one or more other semiconductor layers 204 in the same vertical stack. The extent of any such merger can vary between different embodiments. In the example of a PMOS device, a given source or drain region can be a semiconductor material (e.g., a group IV or group III-V semiconductor material) with a p-type dopant having a higher dopant concentration than an n-type dopant. In the example of an NMOS device, a given source or drain region can be a semiconductor material (e.g., a group IV or group III-V semiconductor material) with an n-type dopant having a higher dopant concentration than a p-type dopant. According to some embodiments, various source or drain regions grown from different semiconductor devices may be aligned along the source / drain trenches in the second direction.

[0044] Figure 2D FIG. 2 shows a schematic diagram of a semiconductor layer 204 after forming nanoribbons 214 from semiconductor layer 204 according to some embodiments. Figure 2C , a cross-sectional view of the structure shown in . Depending on the size of the structure, the nanoribbons 214 may also be considered nanowires or nanosheets. The sacrificial gate 212 may be removed using any wet or dry isotropic process to expose the alternating layer stack of fins within the trench left after the sacrificial gate 212 is removed. Once the sacrificial gate 212 is removed, the sacrificial layer 202 may also be removed using a selective isotropic etching process that removes the material of the sacrificial layer 202 but does not remove (or removes very little) the semiconductor layer 204 or any other exposed layer (e.g., an internal gate spacer). At this point, the suspended (sometimes referred to as released) semiconductor layer 204 forms a nanoribbon 214 that extends between the corresponding source or drain regions in a first direction (in and out of the page).

[0045] Figure 2E FIG. 2 shows a gate structure after forming a gate structure around the nanoribbon 214 in the gate trench according to some embodiments. Figure 2D. As described above, the gate structure includes a gate dielectric 216 and a gate electrode 218. The gate dielectric 216 may be conformally deposited around the nanoribbon 214 using any suitable deposition process, such as atomic layer deposition (ALD). The gate dielectric 216 may also be formed along the bottom of the gate trench along the top surface of the dielectric filler 210 and the sub-fin region 208. The gate dielectric 216 may include any suitable dielectric, such as silicon dioxide and / or a high-k dielectric material. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide just a few examples. According to some embodiments, the gate dielectric 216 is hafnium oxide with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 216 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some examples, the gate dielectric 216 may be a multilayer structure. For example, the gate dielectric 216 may include a first layer on the nanoribbon 214 and a second layer on the first layer. The first layer may be, for example, an oxide of a semiconductor layer (e.g., silicon dioxide), and the second layer may be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, when a high-k dielectric material is used, an annealing process may be performed on the gate dielectric 216 to improve its quality. In some embodiments, the high-k material may be nitrided to improve its aging resistance.

[0046] The gate electrode 218 may be deposited over the gate dielectric 216 and may be any conductive structure. In some embodiments, the gate electrode 218 comprises doped polysilicon, a metal, or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. The gate electrode 218 may include, for example, one or more work function layers, a resistance reduction layer, and / or a barrier layer. The work function layer may include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate.

[0047] Figure 2F FIG. 2 shows a dielectric wall 220 extending in a first direction after forming between adjacent devices according to some embodiments. Figure 2E. The dielectric wall 220 extends to a depth of at least through the entire thickness of the gate structure to isolate the individual gate structures along the second direction. In some embodiments, the dielectric wall 220 extends into at least a portion of the dielectric filler 210 or extends through the entire thickness of the dielectric filler 210. In some embodiments, the dielectric wall 220 extends completely through the dielectric filler 210 and into a portion of the substrate 201.

[0048] According to some embodiments, dielectric wall 220 may be formed by first forming a corresponding gate cut recess through at least the entire thickness of gate electrode 218 using any suitable metal gate etching process. The gate cut recess may extend through a plurality of gate trenches and source / drain trenches in a first direction to isolate adjacent gate structures and source or drain regions. The gate cut recess may be filled with one or more dielectric materials to form dielectric wall 220. For example, dielectric wall 220 may include only silicon oxide or silicon nitride or silicon carbide, or a low-k form of any of these. According to some embodiments, dielectric wall 220 is not formed between each pair of adjacent devices along the second direction. Dielectric wall 220 may have a top width (along the second direction) between about 40nm and about 400nm, but any number of widths may be used depending on the device spacing. In other embodiments, dielectric wall 220 may include a dielectric filler spanning an arbitrary width (e.g., 10 or 100 or 1000 nanometers wide).

[0049] Figure 2G FIG. 2 shows a via recess 222 after forming the via recess 222 through the dielectric wall 220 according to some embodiments. Figure 2F . Any suitable RIE process may be used to form the recess 222 to etch through the dielectric wall 220. According to some embodiments, the recess 222 extends at least along the entire thickness of the gate structure. The recess 222 may continue to extend through the entire thickness of the dielectric filler 210. Due to the etching process, the bottom surface of the recess 222 may have a tapered or otherwise concave shape. Although the sidewalls of the recess 222 are shown as straight, the sidewalls may be tilted or tapered inwardly so that the width of the recess 222 along the second direction decreases from the top to the bottom of the recess. In some examples, the recess 222 may have a top width (along the second direction) between about 20nm and about 30nm, which will define the upper width of the via structure being formed. Other examples may have recesses 222 of other widths.

[0050] Figure 2H FIG. 2 shows a diagram of a via hole after a metal liner 224 is formed in the via recess 222 according to some embodiments. Figure 2G. The liner 224 may be a pure elemental metal, such as pure tungsten, pure molybdenum, pure ruthenium, or a nickel aluminum alloy, but other metals (e.g., titanium, tantalum, cobalt, or any alloy thereof) may also be used. According to some embodiments, the liner 224 is deposited within the recess 222 using an ionized PVD process that produces better adhesion of the metal material to the dielectric surface of the dielectric wall 220. In some examples, the liner 224 may be deposited within the recess 222 to a final sidewall thickness of between about 2 nm and about 5 nm. According to some embodiments, the liner 224 may be thicker on the bottom surface of the recess 222. In some examples, the liner 224 has a thickness of between about 5 nm and about 10 nm (e.g., 60 angstroms) on the bottom surface and a thickness of between about 2 nm and 5 nm (e.g., 20 to 40 angstroms) on the sidewalls.

[0051] Fig.2I FIG. 2 shows a diagram of a metal filling 226 formed on the metal liner 224 in the recess 222 according to some embodiments. Figure 2H . A metal filler 226 may fill any remaining volume within the recess 222 to form a via 228. The metal filler 226 may include the same pure elemental metal as the metal liner 224. For example, the metal filler 226 may include tungsten, molybdenum, ruthenium, titanium, tantalum, cobalt, any alloy thereof, or a nickel-aluminum alloy. As described above, the via 228 may extend at least below the bottom surface of the gate structure and may also extend below the bottom surface of the dielectric filler 210.

[0052] According to some embodiments, the metal fill 226 is formed using a CVD or ALD process such as PECVD. In some examples, the PVD process for forming the metal liner 224 and the CVD or ALD process for forming the metal fill 226 are performed in situ so that neither metal material is oxidized. In addition, the pure elemental metal of the metal liner 224 may be substantially free of any impurities, such as any of carbon, fluorine, and chlorine. The top surfaces of both the metal liner 224 and the metal fill 226 may be polished to be substantially planar with the top surface of the gate electrode 218, or substantially planar with the top surface of the dielectric cap layer on the gate electrode 218. The polishing process may be performed using chemical mechanical polishing (CMP).

[0053] As can be seen in this example, vias 228 may be formed to route various signals to or from the backside interconnect, but other interconnect schemes may readily benefit from the via structures described herein. Figure 3A 2 shows the structure of the substrate 201 after removal according to some embodiments. Fig.2I. Any topside interconnect structures (e.g., back-end structures) may be formed before removing substrate 201. Substrate 201 may be polished via CMP or another grinding process to remove substrate material. According to some embodiments, thinning of substrate 201 continues at least until any portion of metal liner 224 or metal fill 226 is exposed from the back side. In some examples, thinning of substrate 201 continues at least until the bottom surface of sub-fin region 208 and / or dielectric fill 210 is exposed from the back side in the gate trench.

[0054] Figure 3B FIG. 1 shows a schematic diagram of a backside interconnect feature after forming the backside interconnect feature according to some embodiments. Figure 3A . The sub-fin region 208 may first be removed from the back side and replaced with another dielectric filler 302. In some examples, the dielectric filler 302 is the same material as the dielectric filler 210. In some examples, the dielectric filler 210 is also removed to be replaced by the dielectric filler 302.

[0055] In accordance with some embodiments, an example backside interconnect layer includes a dielectric layer 304 and one or more conductive traces 306. Dielectric layer 304 may include any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. Conductive traces 306 may include any suitable conductive material, such as tungsten, ruthenium, molybdenum, or cobalt. In some examples, conductive traces 306 include the same conductive material as metal fill 226 and / or metal liner 224. In some examples, conductive traces 306 contact the lower surface of metal fill 226 and / or metal liner 224 to transmit power or signals to / from conductive traces 306. In accordance with some embodiments, dielectric wall 220 does not extend through any portion of backside dielectric layer 304.

[0056] Figure 4 An EDX analysis is shown across a metal via (including both metal liner 224 and metal fill 226) and across a portion of dielectric wall 220. In this example, tungsten (W) is the pure metal used in both metal liner 224 and metal fill 226, while silicon (Si) is present within dielectric wall 220 (e.g., silicon dioxide or silicon nitride). The dashed lines identify the approximate location of the sidewalls of dielectric wall 220.

[0057] According to some embodiments, during the deposition process, elements from the metal liner 224 penetrate into the sidewalls of the dielectric wall 220. For example, the PVD process causes some metal atoms to penetrate into the sidewalls, thereby improving adhesion to the sidewall surface. As can be observed in the EDX data, tungsten has penetrated laterally into the sidewalls of the dielectric wall 220 by about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm. In addition, the physical bombardment causes some mixing of silicon atoms with the metal liner 224. Therefore, according to some embodiments, silicon atoms are mixed into the metal liner 224 by about 2 nm, about 2.5 nm, about 3 nm, or about 3.5 nm. Outside the metal liner 224, the metal filler 226 is observed to have 100% or nearly 100% pure tungsten.

[0058] Figure 5 An example embodiment of a chip package 500 according to an embodiment of the present disclosure is shown. It can be seen that the chip package 500 includes one or more dies 502. The one or more dies 502 may include at least one integrated circuit having a semiconductor device (e.g., any of the semiconductor devices disclosed herein). In some example configurations, the one or more dies 502 may include any other circuits for interfacing with other devices formed on the die or other devices connected to the chip package 500.

[0059] As can be further seen, the chip package 500 includes a housing 504 bonded to a package substrate 506. The housing 504 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 500. One or more dies 502 can be conductively coupled to the package substrate 506 using a connection 508, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonding, to name a few examples. The package substrate 506 can be any standard or proprietary package substrate, but in some cases includes a dielectric material with conductive paths (e.g., including conductive vias and lines) extending through the dielectric material between the faces of the package substrate 506 or between different locations on each face. In some embodiments, the package substrate 506 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), but any number of package geometries can be used. Additional conductive contacts 512 can be provided at the opposite face of the package substrate 506 for conductively contacting, for example, a printed circuit board (PCB). One or more vias 510 extend through the thickness of the package substrate 506 to provide a conductive path between one or more connections 508 to one or more contacts 512. For ease of illustration, the vias 510 are shown as a single inline through the package substrate 506, but other configurations may be used (e.g., inlaid, dual inlaid, through-silicon vias, or interconnect structures that meander through the thickness of the substrate 506 to contact one or more intermediate locations therein). In other embodiments, the vias 510 are made of multiple smaller stacked vias, or are staggered at different locations on the package substrate 506. In the illustrated embodiment, the contacts 512 are solder balls (e.g., for bump-based connections or ball grid array arrangements), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or pads in a land grid array arrangement). In some embodiments, solder resist is provided between the contacts 512 to inhibit shorting.

[0060] In some embodiments, molding material 514 can be disposed around one or more dies 502 included within housing 504 (e.g., as an underfill material between die 502 and package substrate 506, and as an overfill material between die 502 and housing 504). Although the size and mass of molding material 514 can vary between different embodiments, in some embodiments, the thickness of molding material 514 is less than 1 millimeter. Example materials that can be used for molding material 514 include epoxy molding materials, as appropriate. In some cases, in addition to being electrically insulating, molding material 514 is thermally conductive.

[0061] method

[0062] Figure 6 is a flow chart of a method 600 for forming at least a portion of an integrated circuit according to an embodiment. The various operations of the method 600 may be performed in Figure 2A-2I 600. However, the correlation of the various operations of method 600 with the specific components shown in the aforementioned figures is not intended to imply any structural and / or use limitations. Instead, the aforementioned figures provide an example embodiment of method 600. Other operations may be performed before, during, or after any operation of method 600. For example, method 600 does not explicitly describe the many processes that are performed to form a common transistor structure. In other examples, the operations of method 600 may be performed in an order different from the order shown.

[0063] According to some embodiments, method 600 begins at operation 602, where a plurality of semiconductor fins are formed. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins may be formed from a material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins may be formed in a so-called aspect ratio capture-based process, in which the native fins are etched away to leave fin-shaped trenches, which may then be filled with alternative semiconductor materials (e.g., group IV or group III-V materials). In other embodiments, the fins include alternating material layers (e.g., alternating silicon layers and SiGe layers) that facilitate the formation of nanowires and nanoribbons during a gate formation process, in which one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region so that a full-all-around gate (GAA) process may then be performed. Again, the alternating layers may be blanket deposited and then etched into fins, or deposited into fin-shaped trenches.

[0064] According to some embodiments, a dielectric filler is formed adjacent to the sub-fin portion of each of the fins. The dielectric filler may include silicon dioxide. According to some embodiments, the dielectric filler acts as an STI region between adjacent fins.

[0065] According to some embodiments, each semiconductor device includes a sub-fin portion beneath the fin of alternating semiconductor layers and adjacent to the dielectric fill. The sub-fin may include the same material as a bulk region of the underlying semiconductor substrate.

[0066] Method 600 continues with operation 604, where a sacrificial gate and sidewall spacers are formed over the fins. The sacrificial gate may include any material that can be safely removed in a later process without etching or otherwise damaging the spacers and / or the fins. The sacrificial gate may include polysilicon, and the spacers may include silicon nitride. The spacers are formed on the sidewalls of the sacrificial gate and are etched back to remove the spacer material from any horizontal surface. According to some embodiments, the fins extend longitudinally in a first direction, and the sacrificial gate and the spacers extend longitudinally in a second direction over each of the fins, the second direction being substantially perpendicular to the first direction.

[0067] Method 600 continues with operation 606, where a source or drain region is formed at the end of the semiconductor channel layer in each of the fins. The exposed portion of the fin not covered by the sacrificial gate and the sidewall spacer structure may be removed first using, for example, an RIE process. Removing the fin portion exposes the ends of one or more semiconductor channel layers extending through the sacrificial gate and the sidewall spacer structure in a first direction. The source or drain region may be epitaxially grown from the exposed end of the semiconductor layer. In the example of a PMOS device, the corresponding source or drain region may be a semiconductor material (e.g., a Group IV or Group III-V semiconductor material) having a higher dopant concentration of a p-type dopant than an n-type dopant. In the example of an NMOS device, the corresponding source or drain region may be a semiconductor material (e.g., a Group IV or Group III-V semiconductor material) having a higher dopant concentration of an n-type dopant than a p-type dopant.

[0068] The method 600 continues with operation 608 where the sacrificial material is removed and a gate structure is formed. The sacrificial gate may be removed using an isotropic etching process that selectively removes all material from the sacrificial gate, thereby exposing the first and second fins between the spacer structures. In the example case of using a GAA transistor, any sacrificial layer within the exposed fins between the spacer structures may also be removed to leave behind nanoribbons, nanosheets, or nanowires of semiconductor material.

[0069] The gate structure may include both a gate dielectric and a gate electrode. According to some embodiments, the gate dielectric is first formed over the exposed semiconductor region between the spacer structures, and then the gate electrode is formed within the remainder of the trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process such as ALD. The gate electrode may include any conductive material, such as a metal, a metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples.

[0070] Method 600 continues with operation 610, where a dielectric wall is formed between devices or at least through the gate structure. A deep recess is first formed through at least the entire thickness of the gate structure and extending into the source / drain trenches and through other gate trenches in a first direction. The deep recess can be formed using a metal gate etching process that repeatedly etches through portions of the gate electrode while protecting the sidewalls of the recess from lateral etching. According to some embodiments, the deep recess also cuts through at least a portion of the dielectric filler adjacent to the sub-fin portion.

[0071] The deep recesses are filled with one or more dielectric materials to form dielectric walls. For example, the dielectric material may include silicon dioxide, silicon nitride, or silicon oxynitride. In some examples, the deep recesses are filled with the same dielectric material as the dielectric filler between the semiconductor fins.

[0072] The method 600 continues with operation 612, where a trench is formed through the dielectric wall and along at least the entire thickness of the gate structure. The trench can be formed through a central portion of the dielectric wall and extends longitudinally in a first direction along with the dielectric wall. According to some embodiments, the trench extends below a bottom surface of a dielectric filler between semiconductor fins. The trench can be formed using a deep reactive ion etching (DRIE) process.

[0073] Method 600 continues with operation 614, wherein a conductive liner having a pure elemental metal is formed within the trench. According to some embodiments, the conductive liner comprises pure tungsten, pure molybdenum, pure ruthenium, or a nickel aluminum alloy. In other examples, the conductive liner comprises any suitable metal having a high atomic weight (e.g., greater than 90). According to some embodiments, the conductive liner is deposited using an ionized PVD process (such as sputtering) that produces better adhesion of the metal material to the dielectric surface of the dielectric wall. In some examples, the conductive liner may be deposited within the trench to a final sidewall thickness of between about 2 nm and about 5 nm. According to some embodiments, the conductive liner may be thicker on the bottom surface of the trench, such as between about 5 nm and about 10 nm on the bottom surface.

[0074] The method 600 continues with operation 616 where a conductive fill is formed within the remaining portion of the trench and on the conductive liner. The conductive fill may include the same pure elemental metal as the conductive liner, or may include any other suitable conductive material, such as titanium, tantalum, cobalt, or any alloys thereof.

[0075] According to some embodiments, the conductive filler is formed using a CVD or ALD process (such as PECVD). In some examples, the PVD process for forming the conductive liner and the CVD process for forming the conductive filler are performed in situ so that neither metal material is oxidized. In addition, the pure elemental metal of the conductive liner may be substantially free of any impurities, such as any of carbon, fluorine, and chlorine.

[0076] Example System

[0077] Figure 7 700 is an example computing system implemented using one or more of the integrated circuit structures as disclosed herein according to some embodiments of the present disclosure. As can be seen, computing system 700 accommodates motherboard 702. Motherboard 702 may include multiple components, including but not limited to processor 704 and at least one communication chip 706, each of which may be physically and electrically coupled to motherboard 702, or otherwise integrated therein. As will be appreciated, motherboard 702 may be, for example, any printed circuit board, whether a motherboard, a daughterboard mounted on a motherboard, or the only board of system 700, etc.

[0078] Depending on its application, the computing system 700 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 702. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any component included in the computing system 700 may include one or more integrated circuit structures or devices configured according to an example embodiment (e.g., a module including an integrated circuit device on a substrate having one or more semiconductor devices with low resistance vias, as provided in various ways herein). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 706 may be part of the processor 704 or otherwise integrated therein).

[0079] The communication chip 706 implements wireless communication to transmit data to and from the computing system 700. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data via non-solid media using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 706 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.8, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. The computing system 700 may include multiple communication chips 706. For example, the first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, while the second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0080] The processor 704 of the computing system 700 includes an integrated circuit die packaged within the processor 704. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented using one or more semiconductor devices as variously described herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0081] The communication chip 706 may also include an integrated circuit die packaged within the communication chip 706. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be understood in light of the present disclosure, note that multi-standard wireless capabilities may be integrated directly into the processor 704 (e.g., where the functionality of any chip 706 is integrated into the processor 704, rather than having a separate communication chip). Further note that the processor 704 may be a chipset with such wireless capabilities. In short, any number of processors 704 and / or communication chips 706 may be used. Likewise, any one chip or chipset may have multiple functions integrated therein.

[0082] In various embodiments, computing system 700 may be a laptop computer, a netbook, a notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices, as variously described herein.

[0083] It will be appreciated that in some embodiments, the various components of computing system 700 may be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0084] Additional Example Embodiments

[0085] The following examples relate to further embodiments from which numerous permutations and configurations will be apparent.

[0086] Example 1 is an integrated circuit including a semiconductor device having a semiconductor region extending from a first source or drain region in a first direction, a gate electrode extending over the semiconductor region in a second direction, and a conductive via extending through the entire thickness of the gate electrode in a third direction and adjacent to the semiconductor device in the second direction. The conductive via includes a conductive liner and a conductive filler on the conductive liner. The conductive liner includes pure elemental metal.

[0087] Example 2 includes the integrated circuit of Example 1, further comprising a dielectric wall extending through an entire thickness of the gate electrode in a third direction, wherein the conductive via extends through an entire thickness of the dielectric wall in the third direction.

[0088] Example 3 includes the integrated circuit of Example 2, wherein the dielectric wall comprises a low-k dielectric material.

[0089] Example 4 includes the integrated circuit of Example 2 or 3, wherein the conductive liner consists essentially of pure elemental metal and is directly on the dielectric wall.

[0090] Example 5 includes the integrated circuit of any of Examples 1-4, wherein the pure elemental metal is tungsten.

[0091] Example 6 includes the integrated circuit of any of Examples 1-4, wherein the pure elemental metal is molybdenum.

[0092] Example 7 includes the integrated circuit of any of Examples 1-6, wherein the conductive fill comprises a pure elemental metal.

[0093] Example 8 includes the integrated circuit of any of Examples 1-7, wherein the pure elemental metal is a first pure elemental metal, and wherein the conductive fill includes a second pure elemental metal different from the first pure elemental metal.

[0094] Example 9 includes the integrated circuit of Example 8, wherein the first pure elemental metal is molybdenum and the second pure elemental metal is tungsten.

[0095] Example 10 includes the integrated circuit of any of Examples 1-9, wherein the conductive liner has a first thickness on a sidewall of the via and a second thickness on a bottom of the via, the second thickness being at least 2 nm thicker than the first thickness.

[0096] Example 11 includes the integrated circuit of any of Examples 1-10, wherein no oxygen atoms are present at an interface between the conductive liner and the conductive filler.

[0097] Example 12 includes the integrated circuit of any of Examples 1-11, wherein no carbon, fluorine, or chlorine atoms are present in the conductive liner.

[0098] Example 13 includes the integrated circuit of any of Examples 1-12, wherein the semiconductor region includes a plurality of semiconductor nanoribbons.

[0099] Example 14 includes the integrated circuit of Example 13, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0100] Example 15 includes the integrated circuit of any of Examples 1-14, wherein the second direction is substantially perpendicular to the first direction, and the third direction is substantially perpendicular to the first direction and the second direction.

[0101] Example 16 includes the integrated circuit of any of Examples 1-15, wherein the conductive via extends adjacent to the source or drain region in the first direction.

[0102] Example 17 is a printed circuit board comprising the integrated circuit of any one of Examples 1-16.

[0103] Example 18 is an electronic device, comprising a chip package having one or more dies. At least one of the one or more dies comprises a semiconductor region extending from a first source or drain region to a second source or drain region in a first direction, a gate structure extending over the semiconductor region in a second direction, and a conductive via extending through the entire thickness of the gate structure in a third direction and adjacent to the semiconductor region in the second direction. The conductive via comprises a conductive liner and a conductive filler on the conductive liner. The conductive liner comprises a pure elemental metal.

[0104] Example 19 includes the electronic device of Example 18, wherein at least one of the one or more dies further comprises a dielectric wall extending through the entire thickness of the gate structure in a third direction, wherein the conductive via extends through the entire thickness of the dielectric wall in the third direction.

[0105] Example 20 includes the electronic device of Example 19, wherein the dielectric wall comprises a low-k dielectric material.

[0106] Example 21 includes the electronic device of Example 19 or 20, wherein the conductive liner is directly on the dielectric wall.

[0107] Example 22 includes the electronic device of any of Examples 18-21, wherein the pure elemental metal is tungsten.

[0108] Example 23 includes the electronic device of any of Examples 18-21, wherein the pure elemental metal is molybdenum.

[0109] Example 24 includes the electronic device of any of Examples 18-23, wherein the conductive filler comprises the pure elemental metal.

[0110] Example 25 includes the electronic device of any of Examples 18-24, wherein no oxygen atoms are present at an interface between the conductive liner and the conductive filler.

[0111] Example 26 includes the electronic device of any of Examples 18-25, wherein no carbon, fluorine, or chlorine atoms are present in the conductive liner.

[0112] Example 27 includes the electronic device of any of Examples 18-26, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

[0113] Example 28 includes the electronic device of Example 27, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0114] Example 29 includes the electronic device of any of Examples 18-28, wherein the second direction is substantially perpendicular to the first direction, and the third direction is substantially perpendicular to the first direction and the second direction.

[0115] Example 30 includes the electronic device of any of Examples 18-29, wherein the conductive via extends adjacent to the first source or drain region and the second source or drain region in the first direction.

[0116] Example 31 includes the electronic device of any of Examples 18-30, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0117] Example 32 is a method of forming an integrated circuit. The method includes: forming a fin including a semiconductor material, the fin extending above a substrate and extending in a first direction; forming a dielectric layer adjacent to a sub-fin portion of the fin; forming a source region or a drain region at opposite ends of the fin; forming a gate structure on the dielectric layer and above the semiconductor material, and the gate structure extends in a second direction; forming a dielectric wall through the entire thickness of the gate structure, the dielectric wall extending adjacent to the fin in the first direction; forming a trench through the dielectric wall so that the trench extends along at least the entire thickness of the gate structure; forming a conductive liner of pure elemental metal within the trench; and forming a conductive filler within the remaining portion of the trench on the conductive liner.

[0118] Example 33 includes the method of Example 32, wherein forming the conductive liner includes forming the conductive liner using an ionized physical vapor deposition (PVD) process.

[0119] Example 34 includes the method of Example 32 or 33, wherein forming the conductive filler includes forming the conductive filler using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.

[0120] Example 35 includes the method of any of Examples 32-34, wherein forming a conductive fill includes forming the conductive fill including a pure elemental metal.

[0121] Example 36 includes the method of any of Examples 32-35, wherein the pure elemental metal is tungsten or molybdenum.

[0122] Example 37 includes the method of any of Examples 32-36, further comprising forming a conductive layer below the dielectric layer such that the conductive layer contacts the conductive filler and / or the conductive liner.

[0123] Example 38 is an integrated circuit comprising a first semiconductor device and a second semiconductor device, the first semiconductor device having a first semiconductor region extending from a first source or drain region to a second source or drain region in a first direction, and a first gate structure extending above the first semiconductor region in a second direction, the second semiconductor device having a second semiconductor region extending from a third source or drain region to a fourth source or drain region in the first direction, and a second gate structure extending above the second semiconductor region in the second direction. The third source or drain region is aligned with the first source or drain region along the second direction, and the fourth source or drain region is aligned with the second source or drain region along the second direction. The integrated circuit also includes a dielectric structure extending between and contacting the first gate structure and the second gate structure in the first direction. The dielectric structure also extends through the entire thickness of each of the first gate structure and the second gate structure in a third direction. The integrated circuit also includes a conductive via extending through the entire thickness of the dielectric structure in the third direction. The conductive via includes a conductive liner and a conductive filler on the conductive liner. The conductive liner is substantially composed of pure elemental metal directly on the dielectric structure.

[0124] Example 39 includes the integrated circuit of Example 38, wherein the dielectric structure comprises a low-k dielectric material.

[0125] Example 40 includes the integrated circuit of Example 38 or 39, wherein the pure elemental metal is tungsten.

[0126] Example 41 includes the integrated circuit of Example 38 or 39, wherein the pure elemental metal is molybdenum.

[0127] Example 42 includes the integrated circuit of any of Examples 38-41, wherein the conductive fill comprises the pure elemental metal.

[0128] Example 43 includes the integrated circuit of any of Examples 38-42, wherein no oxygen atoms are present at an interface between the conductive liner and the conductive filler.

[0129] Example 44 includes the integrated circuit of any of Examples 38-43, wherein no carbon, fluorine, or chlorine atoms are present in the conductive liner.

[0130] Example 45 includes the integrated circuit of any of Examples 38-44, wherein the second direction is substantially perpendicular to the first direction, and the third direction is substantially perpendicular to the first direction and the second direction.

[0131] Example 46 includes the integrated circuit of any of Examples 38-45, wherein the conductive via extends in the first direction between the first source or drain region and the third source or drain region, and extends in the first direction between the second source or drain region and the fourth source or drain region.

[0132] Example 47 includes the integrated circuit of any of Examples 38-46, wherein the pure elemental metal is a first pure elemental metal, and wherein the conductive fill includes a second pure elemental metal different from the first elemental metal.

[0133] Example 48 includes the integrated circuit of Example 47, wherein the first pure elemental metal is molybdenum and the second pure elemental metal is tungsten.

[0134] Example 49 includes the integrated circuit of any of Examples 38-48, wherein the conductive liner has a first thickness on the sidewalls of the dielectric structure and a second thickness on the bottom of the via, the second thickness being at least 2 nm thicker than the first thickness.

[0135] Example 50 is a printed circuit board comprising the integrated circuit of any one of Examples 38-49.

[0136] Example 51 includes the integrated circuit of any of Examples 2-4, wherein tungsten atoms of the conductive liner penetrate approximately 4.5 nm into the dielectric wall.

[0137] Example 52 includes the integrated circuit of any of Examples 2-4 or 51, wherein silicon atoms of the dielectric wall penetrate approximately 3.0 nm into the conductive liner.

[0138] The foregoing description of the embodiments of the present disclosure has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in light of the present disclosure. The scope of the present disclosure is not intended to be limited by this specific embodiment, but rather by the limitations of the appended claims.

Claims

1. An integrated circuit, comprising: A semiconductor device having a semiconductor region extending from a source or drain region in a first direction, and a gate electrode extending over the semiconductor region in a second direction; as well as A conductive via extending through the entire thickness of the gate electrode in the third direction and adjacent to the semiconductor device in the second direction, wherein the conductive via comprises a conductive liner and a conductive filler on the conductive liner, and wherein the conductive liner comprises pure elemental metal.

2. The integrated circuit of claim 1 , further comprising a dielectric wall extending through the entire thickness of the gate electrode in the third direction, wherein The conductive via extends through the entire thickness of the dielectric wall in the third direction.

3. The integrated circuit according to claim 2, wherein: The conductive liner consists essentially of the pure elemental metal and is located directly on the dielectric wall.

4. The integrated circuit according to claim 1, wherein: The pure elemental metal is tungsten or molybdenum.

5. The integrated circuit according to claim 1, wherein: The conductive filler includes the pure elemental metal.

6. The integrated circuit of claim 1, wherein: The pure elemental metal is a first pure elemental metal, and wherein the conductive filler comprises a second pure elemental metal different from the first pure elemental metal.

7. The integrated circuit according to claim 6, wherein: The first pure elemental metal is molybdenum and the second pure elemental metal is tungsten.

8. The integrated circuit according to any one of claims 1 to 7, wherein: The conductive liner has a first thickness on the sidewalls of the via and a second thickness on the bottom of the via, the second thickness being at least 2 nm thicker than the first thickness.

9. The integrated circuit according to any one of claims 1 to 7, wherein: No oxygen atoms are present at the interface between the conductive liner and the conductive filler.

10. The integrated circuit according to any one of claims 1 to 7, wherein: No carbon, fluorine or chlorine atoms are present in the conductive liner.

11. The integrated circuit according to any one of claims 1 to 7, wherein: The semiconductor region includes a plurality of semiconductor nanoribbons.

12. The integrated circuit according to any one of claims 1 to 7, wherein: The second direction is substantially perpendicular to the first direction, and the third direction is substantially perpendicular to the first direction and the second direction.

13. The integrated circuit according to any one of claims 1 to 7, wherein: The conductive via extends adjacent to the source or drain region in the first direction.

14. A printed circuit board comprising the integrated circuit according to any one of claims 1 to 7.

15. An electronic device, comprising: A chip package, the chip package comprising one or more dies, at least one of the one or more dies comprising: a semiconductor region extending in a first direction from a first source or drain region to a second source or drain region; a gate structure extending in a second direction over the semiconductor region; and A conductive via extending through the entire thickness of the gate structure in a third direction and adjacent to the semiconductor region in the second direction, wherein the conductive via comprises a conductive liner and a conductive filler on the conductive liner, and wherein the conductive liner comprises pure elemental metal.

16. The electronic device according to claim 15, wherein: At least one of the one or more dies further includes a dielectric wall extending through an entire thickness of the gate structure in the third direction, wherein the conductive via extends through an entire thickness of the dielectric wall in the third direction.

17. The electronic device according to claim 16, wherein: The conductive liner is located directly on the dielectric wall.

18. The electronic device according to any one of claims 15 to 17, wherein: The pure elemental metal is tungsten, molybdenum, ruthenium or a nickel aluminum alloy.

19. The electronic device according to any one of claims 15 to 17, wherein: No oxygen atoms are present at the interface between the conductive liner and the conductive filler.

20. The electronic device according to any one of claims 15 to 17, wherein: No carbon, fluorine or chlorine atoms are present in the conductive liner.

21. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region to a second source or drain region in a first direction, and a first gate structure extending over the first semiconductor region in a second direction; a second semiconductor device having a second semiconductor region extending from a third source or drain region to a fourth source or drain region in the first direction, and a second gate structure extending over the second semiconductor region in the second direction, the third source or drain region being aligned with the first source or drain region along the second direction, and the fourth source or drain region being aligned with the second source or drain region along the second direction; a dielectric structure extending laterally between the first semiconductor device and the second semiconductor device; as well as A conductive via extending in a third direction through the entire thickness of the dielectric structure, wherein the conductive via includes a conductive liner and a conductive filler located on the conductive liner, and wherein the conductive liner is substantially composed of pure elemental metal directly on a sidewall of the dielectric structure.

22. The integrated circuit of claim 21, wherein: The conductive filler includes the pure elemental metal.

23. The integrated circuit of claim 21, wherein: No carbon, fluorine or chlorine atoms are present in the conductive liner.

24. An integrated circuit according to any one of claims 21 to 23, wherein: The pure elemental metal is a first pure elemental metal, and wherein the conductive filler comprises a second pure elemental metal different from the first elemental metal.

25. An integrated circuit according to any one of claims 21 to 23, wherein: The conductive liner has a first thickness on the sidewalls of the dielectric structure and a second thickness on the bottom of the via, the second thickness being at least 2 nm thicker than the first thickness.

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