Semiconductor device having test pattern

Abstract

A semiconductor device includes: a semiconductor substrate; a first test pattern disposed on the semiconductor substrate; and a second test pattern adjacent to the first test pattern. The first test pattern includes an overlapping pattern, and the second test pattern includes a test element group.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0084528 filed in the Korean Intellectual Property Office on June 29, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Various inventive concepts relate to a semiconductor device including a test pattern and a semiconductor device including an overlapping pattern and / or a test element group. Background Art

[0004] Various methods are used to align the overlap between layers of different vertical levels within an error range. For example, optical methods and methods using scanning electron microscopes are also used. However, as the size of the pattern to be manufactured on the substrate becomes smaller, the overlap consistency deteriorates. Therefore, a semiconductor device with excellent or improved overlap consistency is needed even if the size of the pattern is reduced. Summary of the invention

[0005] Various inventive concepts provide a semiconductor device with improved and / or increased space efficiency.

[0006] Furthermore, it should be understood that the present inventive concept is not limited to the foregoing, and various changes and modifications not described herein can be made and clearly understood by those skilled in the art from the following description.

[0007] In some example embodiments, a semiconductor device is provided, including: a semiconductor substrate; a first test pattern on the semiconductor substrate; and a second test pattern adjacent to the first test pattern, wherein the first test pattern includes an overlapping pattern and the second test pattern includes a test element group.

[0008] In some example embodiments, a semiconductor device is provided, including: a semiconductor substrate including an intra-cell region and a scribe line defining the intra-cell region; a first test pattern on the semiconductor substrate; and a second test pattern adjacent to the first test pattern, wherein the first test pattern includes a first overlapping pattern, the first test pattern includes a plurality of lower marks and a plurality of upper marks located at different vertical levels, at least one of the plurality of lower marks and at least one of the plurality of upper marks overlap each other in a vertical direction, and a spacing of each of the plurality of lower marks is different from a spacing of each of the plurality of upper marks.

[0009] In some example embodiments, a semiconductor device is provided, including: a semiconductor substrate including an intra-cell region and a scribe line defining the intra-cell region; a first overlapping pattern on the semiconductor substrate; and a second overlapping pattern surrounded by the first overlapping pattern, wherein the first overlapping pattern includes a plurality of lower marks and a plurality of upper marks located at different vertical levels, at least one of the plurality of lower marks and at least one of the plurality of upper marks overlap each other in a vertical direction, a spacing of each of the plurality of lower marks is different from a spacing of each of the plurality of upper marks, the first overlapping pattern includes an after-development inspection (ADI) overlapping pattern, and the second overlapping pattern includes an after-cleaning inspection (ACI) overlapping pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing a semiconductor substrate for forming a semiconductor device according to example embodiments;

[0012] Figure 2 yes Figure 1 A partial magnified view of some semiconductor dies;

[0013] Figure 3 is a plan view showing a test pattern group according to an example embodiment;

[0014] Figure 4 is a cross-sectional view illustrating a test pattern group according to an example embodiment;

[0015] Figure 5 is a plan view showing a test pattern group according to an example embodiment;

[0016] Figure 6 is a plan view showing a test pattern group according to an example embodiment;

[0017] Figure 7 is a plan view showing a test pattern group according to an example embodiment;

[0018] Figure 8 is a plan view showing a test pattern group according to an example embodiment;

[0019] Fig. 9 is a block diagram illustrating a process system for manufacturing a semiconductor device according to an example embodiment;

[0020] Fig.10 It is used to explain Fig. 9 A block diagram of a first measuring device and a second measuring device and a control device;

[0021] Fig.11is a flowchart illustrating a method of testing a semiconductor device using a test group according to example embodiments; and

[0022] Fig.12 yes Figure 1 A magnified view of some semiconductor dies. DETAILED DESCRIPTION

[0023] Hereinafter, various exemplary embodiments are described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are given to the same elements, and repeated descriptions thereof are omitted.

[0024] As described herein, an element "on" another element may be above or below another element or adjacent to another element (e.g., horizontally adjacent). An element on another element may be directly on another element, such that the element is in direct contact with the other element. An element on another element may be indirectly on another element, such that the element is isolated from the other element by one or more intervening spaces and / or structures and is not in direct contact with the other element.

[0025] It will be understood that elements and / or their characteristics (e.g., structures, surfaces, directions, etc.) that may be referred to as being “perpendicular”, “parallel”, “coplanar”, etc., relative to other elements and / or their characteristics (e.g., structures, surfaces, directions, etc.) may be “perpendicular”, “parallel”, “coplanar”, etc., respectively, relative to other elements and / or their characteristics, or may be “substantially perpendicular”, “substantially parallel”, “substantially coplanar”, etc., respectively, relative to other elements and / or their characteristics.

[0026] It will be understood that the elements and / or characteristics set forth herein may be "the same" or "equivalent" to other elements, and it will also be understood that elements and / or characteristics set forth herein as "equivalent," "identical," or "equivalent" to other elements may be "equivalent," "identical," or "equivalent," or "substantially equivalent," "substantially identical," or "substantially equivalent" to other elements and / or characteristics. Elements and / or characteristics that are "substantially equivalent," "substantially identical," or "substantially equivalent" to other elements and / or characteristics will be understood to include elements and / or characteristics that are equivalent, identical, or equivalent to other elements and / or characteristics within manufacturing tolerances and / or material tolerances. Elements and / or characteristics that are equivalent or substantially equivalent and / or identical or substantially identical to other elements and / or characteristics may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition.

[0027] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the freedom for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0028] Figure 1 is a plan view illustrating a semiconductor substrate 10 for forming a semiconductor device according to example embodiments. Figure 2 yes Figure 1 A magnified view of some semiconductor dies.

[0029] Reference Figure 1 and Figure 2 , the semiconductor substrate 10 may have a plurality of shot areas SA. Each of the shot areas SA may refer to an area exposed by a single exposure process. One shot area SA may include one chip area CA or a plurality of chip areas CA. The scribe area SL may be located between the chip areas CA. The chip area CA may be defined by the scribe area SL.

[0030] Each of the chip areas CA may include a plurality of circuit areas 20. Each of the circuit areas 20 may include a logic circuit area 20a, a memory area 20b, an input / output element area 20c, etc. Here, the chip area CA may be referred to as an "intra-cell area".

[0031] In some example embodiments, the plurality of test pattern groups 100 may be substantially uniformly arranged on the semiconductor substrate 10. In some example embodiments, the plurality of test pattern groups 100 may be uniformly arranged on the scribe lane region SL. In some example embodiments, the plurality of test pattern groups 100 may be uniformly arranged on the chip region CA (intra-cell region). In some example embodiments, the plurality of test pattern groups 100 may be uniformly arranged on the semiconductor substrate 10 regardless of the scribe lane region SL and the chip region CA.

[0032] Figure 3 is a plan view showing a test pattern group 100 according to an example embodiment, and Figure 4 is a cross-sectional view illustrating a test pattern set 100 according to example embodiments.

[0033] Reference Figure 3 and Figure 4, the test pattern group 100 may include a first test pattern 110a and a second test pattern 120a. The first test pattern 110a may also be referred to as a first overlapping pattern 110a. The second test pattern 120a may also be referred to as a second overlapping pattern 120a.

[0034] The test pattern group 100 may include a first overlapping pattern 110a and a second overlapping pattern 120a. In a plan view, the test pattern group 100 may include a central region CR and an edge region ER surrounding the central region CR. The central region CR and the edge region ER may be adjacent to each other. The horizontal area of ​​the central region CR may be smaller than the horizontal area of ​​the edge region ER. The first overlapping pattern 110a may be disposed on the edge region ER, and the second overlapping pattern 120a may be disposed on the central region CR. The first width W1, which is the horizontal width of the test pattern group 100, may be in a range between about 9 microns and about 60 microns. Figure 3 The test pattern group 100 is shown to have a square shape, but various modifications may be made to the shape of the test pattern group 100. For example, the test pattern group 100 may have a rectangular shape, a circular shape, a diamond shape, a polygonal shape, and / or an atypical shape, but example embodiments are not limited thereto.

[0035] The edge region ER may be divided into four quadrants having a quadrilateral shape (e.g., a rectangular shape or a square shape). The first overlapping pattern 110a may be located in each of the quadrants. The first overlapping pattern 110a may include a plurality of grid-like patterns, a plurality of strip-like patterns, and / or a plurality of slit-like patterns, but example embodiments are not limited thereto. For example, the first overlapping pattern 110a may include a line and spaced pattern. The first overlapping pattern 110a may have a pinwheel shape, and the line and spaced patterns of the first overlapping pattern 110a in each of the four quadrants may be arranged perpendicularly and parallel to each other.

[0036] The first overlapping pattern 110a may include a plurality of first overlapping marks 110X-1, which include a plurality of line and space patterns extending in a first horizontal direction (X direction). In addition, the first overlapping pattern 110a may include a plurality of second overlapping marks 110Y-1, which include a plurality of line and space patterns extending in a second horizontal direction (Y direction). Each of the first overlapping mark 110X-1 and the second overlapping mark 110Y-1 may have a horizontal length in the direction in which each of the first overlapping mark 110X-1 and the second overlapping mark 110Y-1 extends. Each of the first overlapping mark 110X-1 and the second overlapping mark 110Y-1 may have a horizontal width in a horizontal direction (X direction and / or Y direction) perpendicular to the direction in which each of the first overlapping mark 110X-1 and the second overlapping mark 110Y-1 extends. The first overlapping mark 110X-1 may have a horizontal length in the first horizontal direction (X direction) and may have a horizontal width in the second horizontal direction (Y direction). Likewise, the second overlapping mark 110Y-1 may have a horizontal width in the first horizontal direction (X direction) and may have a horizontal length in the second horizontal direction (Y direction). The second width W2, which is the length of each of the first overlapping mark 110X-1 and the second overlapping mark 110Y-1, may be in the range of about 5 microns to about 40 microns. For example, the second width W2, which is the length of the long side of each of the four quadrants, may be in the range of about 5 microns to about 40 microns, and the third width W3, which is the length of the short side of each of the four quadrants, may be in the range of about 3 microns to about 20 microns. In addition, the horizontal width WD of each of the first overlapping mark 110X-1 and the second overlapping mark 110Y-1 may be in the range of about 100 nanometers to about 500 nanometers.

[0037] As used herein, a direction parallel to a main surface of the semiconductor substrate 10 may be referred to as a horizontal direction (X direction and / or Y direction), and a direction perpendicular to the horizontal direction (X direction and / or Y direction) may be referred to as a vertical direction (Z direction).

[0038] The first overlapping pattern 110a can be used to measure the first measurement device 11( Fig. 9 ) to measure the overlap. For example, by performing a photolithography process on the first overlap pattern 110a, a photoresist pattern is formed on the first overlap pattern 110a. In addition, before performing a subsequent process (e.g., an etching process) using the photoresist pattern, an overlay measurement may be performed using the photoresist pattern. For example, the first overlap pattern 110a may include an overlap pattern measured during after-development inspection (ADI).

[0039] The first overlapping pattern 110a may include an image-based overlapping (IBO) mark. The IBO mark may include a main pattern MP-1 formed on a lower layer (LAYER 1) and a vernier pattern VP-1 formed on a current layer (LAYER 2). For example, in the first overlapping pattern 110a, a dark pattern may be formed on the lower layer (LAYER 1) as the main pattern MP-1, and a bright pattern may be formed on the current layer (LAYER 2) as the vernier pattern VP-1. The horizontal width of the main pattern MP-1 may be the same as the horizontal width of the vernier pattern VP-1. In another example embodiment, the horizontal width of the main pattern MP-1 may be different from the horizontal width of the vernier pattern VP-1.

[0040] The first measuring device 11 ( Fig. 9 ) can measure the overlap by performing signal processing on the optical / camera image of the IBO marker. For example, the first measuring device 11 ( Fig. 9 ) can perform signal processing on the images of the main pattern MP-1 and the vernier pattern VP-1 to calculate the relative position between the main pattern MP-1 and the vernier pattern VP-1, thereby measuring the overlap.

[0041] The first overlapping pattern 110a may include, for example, a moiré pattern. The moiré pattern may include an interference pattern generated when a plurality of different regular patterns overlap each other. In order to form the moiré pattern, a first pitch P1 as a pitch of the main pattern MP-1 and a second pitch P2 as a pitch of the vernier pattern VP-1 may be different from each other. Each of the first pitch P1 and the second pitch P2 may be in a range of about 300 nanometers to about 900 nanometers. In another example embodiment, each of the first pitch P1 and the second pitch P2 may have the same range as the wavelength of ultraviolet (UV) and / or near infrared (NIR) light. Since the first pitch P1 and the second pitch P2 are different from each other, the main pattern MP-1 and the vernier pattern VP-1 may be arranged to have an overlapping offset d. At least one of the plurality of main patterns MP-1 may at least partially overlap with at least one of the plurality of vernier patterns VP-1 in the vertical direction (Z direction).

[0042] The second overlapping pattern 120a can be used to measure the second measurement device 12 ( Fig. 9 ) to measure the overlap. The second overlap pattern 120a may include a conductive pattern. For example, an etching process and a cleaning process may be performed on the substrate to form a metal pattern, and the overlay measurement may be performed using the conductive pattern.

[0043] For example, the second overlay pattern 120a may include an overlay pattern measured during after-cleaning inspection (ACI). ACI may actually refer to an inspection after an etching process for forming a pattern on a substrate.

[0044] For clarity, you can zoom in Figure 3 . In some example embodiments, the second overlapping pattern 120a may have a smaller plane area than the first overlapping pattern 110a. The fourth width W4, which is the horizontal width of the second overlapping pattern 120a, may be in the range of about 3 microns to about 20 microns. For example, each of the plurality of first to third additional overlapping marks 120X, 120Y-1, and 120Y-2 of the second overlapping pattern 120a may have a length of about 3 microns to about 20 microns.

[0045] The second overlapping pattern 120a may include a first additional overlapping mark 120X extending in a first horizontal direction (X direction) and a second additional overlapping mark 120Y-1 and a third additional overlapping mark 120Y-2 extending in a second horizontal direction (Y direction). In a plan view, each of the first to third additional overlapping marks 120X, 120Y-1 and 120Y-2 may have a grating shape, a stripe shape and / or a slit shape, but example embodiments are not limited thereto. The second additional overlapping mark 120Y-1 and the third additional overlapping mark 120Y-2 may be spaced apart from each other in the first horizontal direction (X direction). The first additional overlapping mark 120X and the second additional overlapping mark 120Y-1 may overlap each other in a vertical direction (Z direction), and the first additional overlapping mark 120X and the third additional overlapping mark 120Y-2 may overlap each other in a vertical direction (Z direction). The shape of the second overlapping pattern 120a is not limited thereto, and various modifications may be made. The length of each of the plurality of first overlay marks 110X-1 and the second overlay mark 110Y-1 of the first overlay pattern 110a may be greater than the length of each of the plurality of first to third additional overlay marks 120X, 120Y-1, and 120Y-2 of the second overlay pattern 120a.

[0046] Each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2 may have a corresponding unit pattern in the chip area CA. In some example embodiments, each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2 may be formed simultaneously with a specific unit pattern located in the chip area CA, and the specific unit pattern is at the same vertical level as each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2. In another example embodiment, each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2 may be formed at a different time point from the specific unit pattern located in the chip area CA, and the specific unit pattern is at the same vertical level as each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2.

[0047] Figure 3 As an example, the second overlap pattern 120a is shown to be located in the center region CR, but Figures 6 to 8 The test element group 120b may be located in the central region CR.

[0048] In a general test pattern group, the first overlapping pattern and the second overlapping pattern are spaced apart from each other. Since the first overlapping pattern and the second overlapping pattern are spaced apart from each other, a measurement error may increase depending on the arrangement position of the pattern. In addition, in a general test pattern group, a space for arranging the first overlapping pattern and a space for arranging the second overlapping pattern are required or advantageous, and therefore, a relatively large space is required or preferred in the semiconductor substrate.

[0049] On the other hand, in the test pattern group 100 according to the inventive concept, the first overlap pattern 110a and the second overlap pattern 120a are arranged adjacent to each other. Therefore, the first overlap and the second overlap can be measured without occupying a relatively large space in the semiconductor substrate 10. In addition, since the first overlap pattern 110a and the second overlap pattern 120a are adjacent to each other, a measurement error of the first overlap and a measurement error of the second overlap can be reduced or prevented.

[0050] Figure 5 1 is a plan view showing a test pattern group 100a according to an exemplary embodiment. Figures 1 to 4 Give a description.

[0051] Reference Figure 5The test pattern group 100a may include a first overlapping pattern 110b and a second overlapping pattern 120a. The first overlapping pattern 110b may include a third overlapping mark 110X-2 extending in a first horizontal direction (X direction) and a fourth overlapping mark 110Y-2 extending in a second horizontal direction (Y direction).

[0052] The first overlay pattern 110b may include a diffraction-based overlay (DBO) mark. The DBO mark may include a lower pattern DBO1 and an upper pattern DBOu. The first measurement device 110( Fig. 9 ) can detect light incident on the DBO mark and diffracted from the DBO mark, and can perform signal processing on the diffracted light to measure the overlap. For example, the first measuring device 11 ( Fig. 9 ) can detect the signals reflected and diffracted from the DBO marker, compare the intensities of the main components of the diffracted signals, and measure the overlap.

[0053] The first overlapping pattern 110b may further include a moiré pattern. Therefore, the third pitch P3 as the pitch of the upper pattern DBOu and the fourth pitch P4 as the pitch of the lower pattern DBOl may be different from each other. At least one of the plurality of upper patterns DBOu may overlap at least one of the plurality of lower patterns DBOl in the vertical direction (Z direction).

[0054] Figure 5 As an example, the second overlap pattern 120a is shown to be located in the center region CR, but Figures 6 to 8 The test element group 120b may be located in the central region CR.

[0055] Figure 6 1 is a plan view showing a test pattern group 100b according to an example embodiment. Figures 1 to 5 Give a description.

[0056] Reference Figure 6 , the test pattern group 100b may include a first overlapping pattern 110c and a test element group (TEG) 120b. In a plan view, the first overlapping pattern 110c may be located in an edge region ER of the test pattern group 100b, and the TEG 120b may be located in a center region CR of the test pattern group 100b.

[0057] The first overlay pattern 110c may include an IBO mark. The IBO mark may include a main pattern MP-2 formed on a lower layer (LAYER 1) and a vernier pattern VP-2 formed on a current layer (LAYER 2).

[0058] Figure 6As an example, the case where the first overlapping pattern 110c includes an advanced image metrology (AIM) overlap mark is shown, but the inventive concept is not limited thereto. For example, the first overlapping pattern 110c may include a box-in-box (BIB) overlap mark. In another example embodiment, the first overlapping pattern 110c may include a moiré pattern.

[0059] The first overlapping pattern 110c may include a plurality of fifth overlapping marks 110X-3, which include a plurality of line and space patterns extending in a first horizontal direction (X direction). In addition, the first overlapping pattern 110c may include a plurality of sixth overlapping marks 110Y-3, which include a plurality of line and space patterns extending in a second horizontal direction (Y direction). Each of the fifth overlapping mark 110X-3 and the sixth overlapping mark 110Y-3 may have a horizontal length in the direction in which each of the fifth overlapping mark 110X-3 and the sixth overlapping mark 110Y-3 extends. Each of the fifth overlapping mark 110X-3 and the sixth overlapping mark 110Y-3 may have a horizontal width in a horizontal direction (X direction and / or Y direction) perpendicular to the direction in which each of the fifth overlapping mark 110X-3 and the sixth overlapping mark 110Y-3 extends. The fifth overlapping mark 110X-3 may have a horizontal length in the first horizontal direction (X direction) and may have a horizontal width in the second horizontal direction (Y direction). Likewise, the sixth overlap mark 110Y-3 may have a horizontal width in the first horizontal direction (X direction) and may have a horizontal length in the second horizontal direction (Y direction).The fifth width W5 may be in the range of about 3 micrometers to about 20 micrometers.

[0060] In four quadrants, a plurality of main patterns MP-2 and a plurality of vernier patterns VP-2 may be spaced apart from each other in horizontal directions (X direction and / or Y direction) parallel to a direction in which each of the main patterns MP-2 and the vernier patterns VP-2 extend, respectively.

[0061] In a plan view, the main pattern MP-2 may not overlap the vernier pattern VP-2 in a vertical direction (Z direction). For example, the main pattern MP-2 and the vernier pattern VP-2 may be spaced apart from each other in a horizontal direction (X direction and / or Y direction).

[0062] The TEG 120b may include a mark for measuring a critical dimension (CD) of a pattern of the semiconductor substrate 10. For example, the TEG 120b may include a mark for measuring a thickness and / or a line width of a pattern of the semiconductor substrate 10.

[0063] The TEG 120 b may include a plurality of marks for testing a manufacturing process of a semiconductor device and characteristics of a completed semiconductor device. Figure 6 It is illustrated as an example that the TEG 120 b includes a rectangular mark and another rectangular mark surrounding the rectangular mark, but the shapes and arrangements of the marks of the TEG 120 b may be variously modified.

[0064] The TEG 120b may have a smaller planar area than the first overlap pattern 110c. For example, each of the plurality of marks of the TEG 120b may have a smaller planar area than each of the plurality of overlap marks of each of the first overlap pattern 110c.

[0065] Figure 7 1 is a plan view showing a test pattern group 100c according to an example embodiment. Figures 1 to 6 Give a description.

[0066] Reference Figure 7 , the test pattern group 100c may include a first overlapping pattern 110d and a TEG 120b. Figure 7 The TEG120b and Figure 6 The TEG 120b is substantially the same, and therefore, the first overlapping pattern 110d is mainly described below.

[0067] The first overlapping pattern 110d may include a DBO mark. The DBO mark may include a lower pattern DBO1 and an upper pattern DBOu. The first measuring device 110d may include a DBO mark. Fig. 9 ) can detect light incident on the DBO mark and diffracted from the DBO mark, and can perform signal processing on the diffracted light to measure the overlap. For example, the first measuring device 11 ( Fig. 9 ) can detect the signals reflected and diffracted from the DBO marker, compare the intensities of the main components of the diffracted signals, and measure the overlap.

[0068] The first overlapping pattern 110d may include a plurality of upper patterns DBOu and a plurality of lower patterns DBOl. In a plan view, the plurality of upper patterns DBOu may overlap with the plurality of lower patterns DBOl in a vertical direction (Z direction), respectively. Each of the plurality of upper patterns DBOu may have the same pitch as each of the plurality of lower patterns DBOl.

[0069] Figure 8 1 is a plan view showing a test pattern group 100d according to an example embodiment. Figures 1 to 7 Give a description.

[0070] Reference Figure 8 , the test pattern group 100d may include a first overlapping pattern 110e and a TEG 120b. Figure 8 The TEG120b and Figure 6The TEG 120b is substantially the same, and therefore, the first overlapping pattern 110e is mainly described below.

[0071] The first overlapping pattern 110e may include a plurality of upper patterns DBOu and a plurality of lower patterns DBOl. In a plan view, the plurality of upper patterns DBOu may not overlap with the plurality of lower patterns DBOl in a vertical direction (Z direction). For example, the plurality of upper patterns DBOu may be spaced apart from the plurality of lower patterns DBOl in a horizontal direction (X direction and / or Y direction). In the four quadrants, the plurality of upper patterns DBOu and the plurality of lower patterns DBOl may be spaced apart from each other in a horizontal direction (X direction and / or Y direction) perpendicular to the direction in which each of the plurality of upper patterns DBOu and each of the plurality of lower patterns DBOl extend. Each of the plurality of upper patterns DBOu may have the same spacing as each of the plurality of lower patterns DBOl.

[0072] Fig. 9 is a block diagram showing a process system for manufacturing a semiconductor device according to an example embodiment. Figures 1 to 8 Give a description.

[0073] Reference Fig. 9 , the semiconductor process system 1 may include a lithography process equipment 13 for performing a lithography process, a first measurement device 11 for performing a first overlay measurement using a photoresist pattern formed using the lithography process equipment 13, a semiconductor process equipment 15 for performing a subsequent process using the photoresist pattern, and a second measurement device 12 for performing a second overlay measurement using a second test pattern formed by using the semiconductor process equipment 15. The second test pattern may include a second overlay pattern 120a and / or a TEG 120b. In addition, the second measurement may include a second overlay measurement and / or a CD measurement of a pattern of the semiconductor substrate 10 using the TEG 120b. In addition, the semiconductor process system 1 may include a control device 17 capable of sending and receiving signals to and from the first measurement device 11 and the second measurement device 12.

[0074] Reference Fig.10 The first measuring device 11 and the second measuring device 12 as well as the control device 17 are described. Fig.10 It is used to explain Fig. 9 11 and 12 and a block diagram of a control device 17 .

[0075] Reference Fig. 9 and Fig.10The first measuring device 11 may include a first tray portion 11a on which a semiconductor substrate 10 having a photoresist pattern (first test pattern) formed by a photolithography process equipment 13 is placed, and a first measuring portion 11b that performs measurement using the photoresist pattern. The first measuring portion 11b may measure a test target pattern (e.g., a first overlay measurement) using diffraction of light, and the control device 17 may generate first error data using measurement data obtained from the first measuring portion 11b. The first error data generated as described above may be fed back to the photolithography process equipment 13.

[0076] The second measurement device 12 may include a second tray portion 12 a on which the semiconductor substrate 10 having the second test pattern formed by the semiconductor process equipment 15 is placed, and a second measurement portion 12 b that performs measurement using the second test pattern.

[0077] In some example embodiments, when the second test pattern includes the second overlapping pattern 120a, the second measuring device 12 may include a measuring device using a scanning electron microscope (SEM). For example, the second measuring device 12 may emit an electron beam having a landing energy of about 10 keV or more, thereby extracting a SEM image of a metal pattern stacked in at least two or three layers. The control device 17 may generate overlapping error data using the SEM image extracted from the second measuring device 12. The overlapping error data generated as described above may be fed back to the photolithography process equipment 13.

[0078] Furthermore, in some example embodiments, when the second test pattern includes the TEG 120 b , the second measurement device 12 may include a SEM and / or an X-ray spectrometer. The test error data generated as described above may be fed back to the photolithography process equipment 13 .

[0079] According to some example embodiments, a semiconductor process system 1 including a first measuring device 11 and a second measuring device 12 capable of performing measurements in different ways may be provided. In addition, the first measuring device 11 uses a photoresist pattern, and therefore, fast feedback is possible. In addition, the second measuring device 12 uses a second overlapping pattern 120a and / or a TEG 120b similar to an actual circuit pattern, and therefore, a misalignment value similar to the misalignment of the actual circuit pattern may be extracted. Therefore, test consistency may be improved and / or increased. In a semiconductor device formed using the semiconductor process system 1 according to some example embodiments, defects due to misalignment may be reduced or prevented. In addition, the semiconductor process system 1 may improve and / or increase productivity.

[0080] Fig.11is a flow chart showing a method for testing a semiconductor device using a test group according to an example embodiment. Figures 1 to 10 Give a description.

[0081] Reference Fig.11 , a substrate may be introduced into a substrate processing space (S110). The substrate processing space may include, for example, a processing chamber of a cluster tool.

[0082] Subsequently, a photoresist pattern may be formed on the semiconductor substrate 10 (S120). The photoresist pattern may include Figures 3 to 8 The first overlapping patterns 110a, 110b, 110c, 110d and 110e are shown.

[0083] As described above, the first overlapping patterns 110a, 110b, 110c, 110d, and 110e may include a plurality of grid-like patterns, a plurality of strip-like patterns, and / or a plurality of slit-like patterns, but example embodiments are not limited thereto. For example, the first overlapping patterns 110a, 110b, 110c, 110d, and 110e may include line and space patterns. Each of the first overlapping patterns 110a, 110b, 110c, 110d, and 110e may have a pinwheel shape, and the line and space patterns of each of the first overlapping patterns 110a, 110b, 110c, 110d, and 110e in each of the four quadrants may be arranged perpendicularly and parallel to each other.

[0084] Figure 3 and Figure 5 The first overlapped patterns 110a and 110b may include a moiré pattern. In the moiré pattern, a pitch of an upper pattern and a pitch of a lower pattern may be different from each other.

[0085] also, Figure 3 and Figure 6 The first overlay patterns 110a and 110c may include an IBO mark. The IBO mark may include main patterns MP-1 and MP-2 formed in a lower layer and vernier patterns VP-1 and VP-2 formed in a current layer.

[0086] Figure 5 , Figure 7 and Figure 8 The first overlapping patterns 110b, 110d and 110e may include a DBO mark. For example, the DBO mark may include a lower pattern DBO1 and an upper pattern DBOu. Figure 5 , Figure 7 and Figure 8 In the embodiment, the lower pattern DBO1 may be formed on a lower layer of the semiconductor substrate 10, and the upper pattern DBOu may be formed on an upper layer of the semiconductor substrate 10.

[0087] Next, the first consistency is measured using the first overlapping patterns 110a, 110b, 110c, 110d, and 110e (S130). For example, the first consistency may include a first overlapping consistency. For example, using Fig. 9 The first measuring device 11 is used to measure the first overlap consistency.

[0088] Figure 3 and Figure 6 The first overlapping patterns 110a and 110c include an IBO mark, and therefore, the first measuring device 11 can measure the overlap by performing signal processing on an optical / camera image of the IBO mark. For example, the first measuring device 11 can perform signal processing on images of the main patterns MP-1 and MP-2 and the vernier patterns VP-1 and VP-2 to calculate the relative positions between the main patterns MP-1 and MP-2 and the vernier patterns VP-1 and VP-2, thereby measuring the overlap.

[0089] Figure 5 , Figure 7 and Figure 8 The first overlapping patterns 110b, 110d, and 110e include DBO marks, and therefore, the first measuring device 11 can detect light incident on and diffracted from the DBO marks, and can perform signal processing on the diffracted light to measure the overlap. For example, the first measuring device 11 can detect signals reflected and diffracted from the DBO marks, compare the intensities of the main components of the diffracted signals, and measure the overlap.

[0090] Then, it is determined whether the measured first consistency is within the allowable error range (S140). If the first consistency is outside the allowable error range, the photoresist pattern formed in operation S120 can be removed, and a new photoresist pattern can be formed by rework (S145). To this end, the measured first consistency data can be fed back (S190).

[0091] Otherwise, if the first consistency is within the allowable error range, etching using the photoresist pattern as an etching mask can be performed in a subsequent process (S150). In addition, even if the first consistency is not outside the allowable error range, the measured first consistency data can be fed back to perform more accurate processing on the next die, substrate or batch (S190).

[0092] In some example embodiments, a process of forming a conductor wiring may be additionally performed on the etched pattern. The process of forming the conductor wiring may be performed by, for example, a damascene process, but example embodiments are not limited thereto.

[0093] Subsequently, a second test pattern may be formed on the semiconductor substrate 10. The second test pattern may include Figures 3 to 8The second test pattern may include a conductive material. In another example embodiment, the second test pattern may not include a conductive material. The plane area of ​​each of the second test patterns may be smaller than the plane area of ​​each of the first overlapping patterns 110a, 110b, 110c, 110d, and 110e. In addition, the length, width, and spacing of the marks of each of the second test patterns may be smaller than the length, width, and spacing of each of the overlapping marks of the first overlapping patterns 110a, 110b, 110c, 110d, and 110e.

[0094] For example, the second overlay pattern 120a may include an overlay pattern measured during ACI. ACI may actually refer to an inspection after an etching process for forming a pattern on a substrate.

[0095] For example, the second overlapping pattern 120a may include a conductive material. The second overlapping pattern 120a may include a first additional overlapping mark 120X extending in a first horizontal direction (X direction) and a second additional overlapping mark 120Y-1 and a third additional overlapping mark 120Y-2 extending in a second horizontal direction (Y direction). In a plan view, each of the first additional overlapping mark to the third additional overlapping mark 120X, 120Y-1 and 120Y-2 may have a grating shape, a stripe shape and / or a slit shape. The second additional overlapping mark 120Y-1 and the third additional overlapping mark 120Y-2 may be spaced apart from each other in the first horizontal direction (X direction). The shape of the second overlapping pattern 120a is not limited thereto, and various modifications may be made.

[0096] Each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2 may have a corresponding unit pattern in the chip area CA. In some example embodiments, each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2 may be formed simultaneously with a specific unit pattern located in the chip area CA, and the specific unit pattern is at the same vertical level as each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2. In another example embodiment, each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2 may be formed at a different time point from the specific unit pattern located in the chip area CA, and the specific unit pattern is at the same vertical level as each of the first to third additional overlap marks 120X, 120Y-1, and 120Y-2.

[0097] The TEG 120b may include a pattern for measuring the CD of the pattern of the semiconductor substrate 10. For example, the TEG 120b may include a pattern for measuring the thickness and / or line width of the pattern of the semiconductor substrate 10.

[0098] The TEG 120b may include a plurality of patterns for testing the manufacturing process of the semiconductor device and the characteristics of the completed semiconductor device. As an example, Figures 6 to 8 It is illustrated that the TEG 120 b includes a rectangular mark and another rectangular mark surrounding the rectangular mark, but the shape and arrangement of the marks of the TEG 120 b may be variously modified.

[0099] The test pattern group 100 including the first test patterns 110a, 110b, 110c, 110d, and 110e and the second test patterns 120a and 120b may include a central region CR and an edge region ER surrounding the central region CR. The horizontal area of ​​the central region CR may be smaller than the horizontal area of ​​the edge region ER. The horizontal area of ​​each of the marks of the first test patterns 110a, 110b, 110c, 110d, and 110e may be larger than the horizontal area of ​​each of the marks of the second test patterns 120a and 120b.

[0100] The first test patterns 110a, 110b, 110c, 110d, and 110e may be disposed on the edge region ER, and the second test patterns 120a and 120b may be disposed on the center region CR. The edge region ER may be divided into four quadrants having a quadrilateral shape (e.g., a rectangular shape or a square shape). The first test patterns 110a, 110b, 110c, 110d, and 110e may be located in each of the quadrants.

[0101] Subsequently, the second consistency is measured using the second test patterns 120a and 120b (S160).

[0102] You can use, for example Fig. 9 The second measurement device 12 measures the second consistency. For example, when measuring the second overlapping pattern 120a, the second measurement device 12 may include a SEM. In addition, when measuring the TEG 120b, the second measurement device 12 may include a SEM and / or an X-ray spectrometer.

[0103] Then, it is determined whether the measured second consistency is within the allowable error range (S170). If the second consistency is outside the allowable error range, the substrate can be discarded (S185). However, in some example embodiments, even if the second consistency is outside the allowable error range, the substrate does not have to be discarded. In some cases, rework can be performed on the substrate, and subsequent processes can be continued after feedback of relevant data. However, in some example embodiments, the measured second test consistency data can be fed back to perform more accurate processing on the next substrate or batch (S190).

[0104] Otherwise, if the second consistency is within the allowable error range, the scheduled subsequent process can be continued (S180). In addition, even if the second consistency is not outside the allowable error range, the measured second consistency data can be fed back to perform more accurate processing on the next die, substrate or batch (S190).

[0105] Fig.12 yes Figure 1 Some enlarged pictures of semiconductor die. Figures 1 to 11 Give a description.

[0106] Reference Fig.12 , a plurality of test pattern groups 100 may be arranged on the semiconductor substrate 10 , and may be uniformly arranged within one shot area SA.

[0107] In some example embodiments, a plurality of chip areas CA may be arranged in one shooting area SA. The test pattern group 100 may be arranged at the same position in each of the plurality of chip areas CA. For example, the position of the test pattern group 100 arranged in one chip area CA among the plurality of chip areas CA may be the same as the position of the test pattern group 100 arranged in another chip area CA among the plurality of chip areas CA.

[0108] exist Figures 5 to 8 The test pattern groups 100 a , 100 b , 100 c , and 100 d shown in FIG. 1 may be arranged on a semiconductor substrate 10 .

[0109] One or more of the elements disclosed above may include or may be implemented in the following: a processing circuit such as hardware including a logic circuit; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0110] While the inventive concepts have been shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device comprising: Semiconductor substrate; a first test pattern on the semiconductor substrate; as well as a second test pattern, which is adjacent to the first test pattern, wherein: The first test pattern includes an overlapping pattern, and The second test pattern includes a test element group.

2. The semiconductor device according to claim 1, wherein In a plan view, the first test pattern surrounds the second test pattern.

3. The semiconductor device according to claim 1, wherein The first test pattern includes a first line and space pattern extending in a first horizontal direction and a second line and space pattern extending in a second horizontal direction.

4. The semiconductor device according to claim 1, wherein The first test pattern includes a plurality of lower marks and a plurality of upper marks located at different vertical levels, and The plurality of lower marks and the plurality of upper marks overlap each other in a vertical direction, respectively.

5. The semiconductor device according to claim 1, wherein The first test pattern includes a plurality of lower marks and a plurality of upper marks located at different vertical levels, and The plurality of lower marks and the plurality of upper marks are spaced apart from each other in a horizontal direction, respectively.

6. The semiconductor device according to claim 5, wherein: The first test pattern is arranged in a plurality of quadrants, and In each of the plurality of quadrants, The plurality of lower marks and the plurality of upper marks are respectively spaced apart from each other in a horizontal direction parallel to a direction in which each of the plurality of lower marks and each of the plurality of upper marks extend.

7. The semiconductor device according to claim 5, wherein: The first test pattern is arranged in a plurality of quadrants, and In each of the plurality of quadrants, The plurality of lower marks and the plurality of upper marks are respectively spaced apart from each other in a horizontal direction perpendicular to a direction in which each of the plurality of lower marks and each of the plurality of upper marks extend.

8. The semiconductor device according to claim 1, wherein The first test pattern includes at least one of an image-based overlay pattern and a diffraction-based overlay pattern.

9. A semiconductor device comprising: A semiconductor substrate including an intra-cell region and a scribe line defining the intra-cell region; a first test pattern on the semiconductor substrate; as well as a second test pattern, which is adjacent to the first test pattern, wherein: The first test pattern comprises a first overlapping pattern, the first test pattern includes a plurality of lower marks and a plurality of upper marks located at different vertical levels, At least one of the plurality of lower marks and at least one of the plurality of upper marks overlap each other in a vertical direction, and A pitch of each of the plurality of lower marks is different from a pitch of each of the plurality of upper marks.

10. The semiconductor device according to claim 9, wherein The second test pattern includes a first sub-pattern and a second sub-pattern, the first sub-pattern and the second sub-pattern respectively corresponding to a first unit pattern and a second unit pattern located at different vertical levels in the intra-cell region.

11. The semiconductor device according to claim 9, wherein The second test pattern includes a plurality of marks for measuring a critical dimension.

12. The semiconductor device according to claim 9, wherein: A pitch between each of the plurality of lower marks and the plurality of upper marks is in a range of 300 nanometers to 900 nanometers.

13. The semiconductor device according to claim 9, wherein: A length of each of the plurality of lower marks and a length of each of the plurality of upper marks are greater than a length of a mark of the second test pattern.

14. The semiconductor device according to claim 9, wherein The plurality of lower marks and the plurality of upper marks are arranged in a moiré pattern.

15. The semiconductor device according to claim 9, wherein: The first test pattern and the second test pattern correspond to one test pattern group, and The test pattern group is located on the scribe line.

16. A semiconductor device comprising: A semiconductor substrate including an intra-cell region and a scribe line defining the intra-cell region; a first overlapping pattern on the semiconductor substrate; as well as a second overlapping pattern, which is surrounded by the first overlapping pattern, wherein the first overlapping pattern comprises a plurality of lower marks and a plurality of upper marks located at different vertical levels, at least one of the plurality of lower marks and at least one of the plurality of upper marks overlap each other in a vertical direction, The pitch of each of the plurality of lower marks is different from the pitch of each of the plurality of upper marks, The first overlay pattern comprises a post-development inspection overlay pattern, and The second overlay pattern includes a post-cleaning inspection overlay pattern.

17. The semiconductor device according to claim 16, wherein: The first overlapping pattern includes a first line and space pattern extending in a first horizontal direction and a second line and space pattern extending in a second horizontal direction, and The second overlapping pattern includes a third line and space pattern extending in the first horizontal direction and a fourth line and space pattern extending in the second horizontal direction.

18. The semiconductor device according to claim 17, wherein: The length of each of the first line and space pattern and the second line and space pattern is in the range of 5 micrometers to 35 micrometers, and A length of each of the third line and space pattern and the fourth line and space pattern is in a range of 3 micrometers to 20 micrometers.

19. The semiconductor device according to claim 16, wherein: The first overlapping pattern and the second overlapping pattern correspond to one overlapping pattern group, and The overlapping pattern group is located in the intra-cell area or on the scribe line.

20. The semiconductor device according to claim 16, wherein A horizontal area of ​​the first overlapping pattern is greater than a horizontal area of ​​the second overlapping pattern.

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