Semiconductor device and method of manufacturing the same
By providing a cover metal layer on the substrate of the semiconductor device, parasitic capacitances of the gate-drain and gate-source are suppressed, and the problem of deterioration in the prior art is solved, and the high-frequency characteristics of the semiconductor device are improved.
Patent Information
- Application Number
- CN202410812670.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-30
- Filing Date
- 2024-06-22
- Publication Date
- 2024-12-31
AI Technical Summary
Prior Art When configuring multiple unit FETs, electrical connection between the gate pad and the gate electrode far away from the gate pad will lead to an increase in parasitic capacitance and lead to deterioration of characteristics.
A semiconductor device is designed to suppress parasitic capacitances of the gate-drain and gate-source by providing the first and second transistor units on the substrate and setting up a cover metal layer between the source electrode and the gate wiring. Reduce characteristic deterioration.
The parasitic capacitances of the gate-drain and gate-source are effectively suppressed, and the high-frequency characteristics of the semiconductor device are improved, and characteristics are prevented from deteriorating.
Smart Images
Figure CN119230549A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] It is known that in a field effect transistor (FET) having a finger-shaped source electrode, a gate electrode, and a drain electrode, a plurality of unit FETs having a source electrode, a gate electrode, and a drain electrode are arranged in the extending direction of the electrodes (for example, Patent Document 1).
[0003] Prior art literature
[0004] Patent Literature
[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351
[0006] In Patent Document 1, by configuring a plurality of unit FETs in the extending direction of the electrode, the width of the gate electrode in the unit FET can be shortened. Thus, the gate resistance can be suppressed. However, the parasitic capacitance between the gate wiring that electrically connects the gate pad to the gate electrode away from the gate pad and the drain electrode increases, and the characteristics deteriorate. Summary of the invention
[0007] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of characteristics.
[0008] One embodiment of the present disclosure is a semiconductor device, comprising: a substrate; a first transistor unit, on which a first drain electrode, a first gate electrode, and a first source electrode are sequentially provided; a second transistor unit, on which a second source electrode arranged side by side along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode are sequentially provided, the second transistor unit being located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; a gate wiring arranged on the substrate between the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first covering metal layer arranged above the substrate between the first source electrode and the gate wiring, adjacent to the first source electrode and the gate wiring, the first covering metal layer being electrically connected to the first source electrode; and a second covering metal layer arranged above the substrate between the second source electrode and the gate wiring, adjacent to the second source electrode and the gate wiring, the second covering metal layer being electrically connected to the second source electrode.
[0009] One embodiment of the present disclosure is a method for manufacturing a semiconductor device, which includes the following steps: forming a first transistor unit and a second transistor unit on a substrate, wherein the first transistor unit is provided with a first drain electrode, a first gate electrode and a first source electrode in sequence, and the second transistor unit is provided with a second source electrode arranged side by side along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode in sequence, and the second transistor unit is located relative to the first transistor unit in the direction in which the first drain electrode, the first gate electrode and the first source electrode are arranged; between the first source electrode and the second source electrode, in the A gate wiring is formed on the substrate, and the gate wiring is electrically connected to the first gate electrode and the second gate electrode; and a first covering metal layer, a second covering metal layer and a field plate are formed simultaneously, wherein the first covering metal layer is between the first source electrode and the gate wiring, and is adjacent to the first source electrode and the gate wiring and is arranged above the substrate, the first covering metal layer is electrically connected to the first source electrode, the second covering metal layer is between the second source electrode and the gate wiring, and is adjacent to the second source electrode and the gate wiring and is arranged above the substrate, the second covering metal layer is electrically connected to the second source electrode, and the field plate is arranged above the substrate between the first gate electrode and the first drain electrode.
[0010] Effects of the Invention
[0011] According to the present disclosure, degradation of characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 This is a top view of the semiconductor device of Example 1.
[0013] Figure 2 yes Figure 1 An enlarged view of range E.
[0014] Figure 3 yes Figure 1 and Figure 2 A-A section view.
[0015] Figure 4 yes Figure 1 and Figure 2 B-B section view.
[0016] Figure 5 yes Figure 1 and Figure 2 C-C section view.
[0017] Figure 6 yes Figure 1 D-D section view.
[0018] Figure 7 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0019] Figure 8 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0020] Fig. 9 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0021] Fig.10 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0022] Fig.11A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0023] Fig. 11B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0024] Fig. 12A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0025] Fig. 12B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0026] Fig.13A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0027] Fig. 13B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0028] Fig.14A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0029] Fig. 14B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0030] Fig.15 is a cross-sectional view of a semiconductor device according to Comparative Example 1.
[0031] Fig.16 This is an enlarged top view of a semiconductor device according to Modification 1 of Embodiment 1.
[0032] Fig.17 yes Fig.16 A-A section view.
[0033] Fig.18 This is an enlarged top view of a semiconductor device according to a second variation of the first embodiment.
[0034] Fig.19 yes Fig.18 A-A section view.
[0035] Fig. 20 It is a top view of the semiconductor device of Example 2.
[0036] Fig.21 is a graph showing the K factor of semiconductor devices A and B versus frequency.
[0037] Fig. 22 Graph showing |S12| of semiconductor devices A and B with respect to frequency.
[0038] Description of Reference Numerals
[0039] 10, 10a: substrate;
[0040] 10b: semiconductor layer;
[0041] 11a, 11b, 11c: active region;
[0042] 12, 12a, 12b, 12c: source electrodes;
[0043] 13a, 13b: passive area;
[0044] 14, 14a, 14b, 14c, 14d: gate electrodes;
[0045] 15a, 15c: field plates;
[0046] 16a, 16b, 16c, 16d: drain electrodes;
[0047] 17: Wiring;
[0048] 18a, 18b: gate wiring;
[0049] 20: vias;
[0050] 22, 22a, 22b, 22c: source wiring;
[0051] 24: drain bus;
[0052] 25: Gate busbar;
[0053] 25a: gate metal layer;
[0054] 26a, 26c: drain wiring;
[0055] 28, 28a: metal layer;
[0056] 30, 30a, 30c: covering metal layer;
[0057] 32, 32a, 32b: insulating layer;
[0058] 35, 35a, 35b, 35c, 35d: unit FET (transistor unit);
[0059] 36a, 36b, 36c, 36d: FET group;
[0060] 38: gap;
[0061] 50, 53b: solid arrows;
[0062] 51, 52, 53a: dotted arrows;
[0063] 100 , 102 , 104 , 106 , 110 : semiconductor devices. DETAILED DESCRIPTION
[0064] [Description of Embodiments of the Present Disclosure]
[0065] First, the contents of the embodiments of the present disclosure will be listed and described.
[0066] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit, on which a first drain electrode, a first gate electrode, and a first source electrode are provided in sequence; a second transistor unit, on which a second source electrode arranged side by side along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode are provided in sequence, the second transistor unit being located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; a gate wiring provided on the substrate between the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first covering metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, the first covering metal layer being electrically connected to the first source electrode; and a second covering metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, the second covering metal layer being electrically connected to the second source electrode. This can suppress gate-drain parasitic capacitance and suppress degradation of characteristics.
[0067] (2) In the above (1), at least a portion of the first cover metal layer and at least a portion of the second cover metal layer may overlap the gate wiring in a non-contact manner when viewed from above. This can further suppress gate-drain parasitic capacitance and further suppress degradation of characteristics.
[0068] (3) In the above (1) or (2), the first cover metal layer and the second cover metal layer may be in contact with each other above the gate wiring. This can further suppress gate-drain parasitic capacitance and further suppress degradation of characteristics.
[0069] (4) In the above (1) or (2), the first cover metal layer and the second cover metal layer may not be in contact with each other above the gate wiring. This can suppress gate-source parasitic capacitance and further suppress degradation of characteristics.
[0070] (5) In the above (4), the end of the first covering metal layer may overlap with the gate wiring when viewed from above, and the end of the second covering metal layer may overlap with the gate wiring when viewed from above. In this way, gate-drain parasitic capacitance and gate-source parasitic capacitance can be suppressed, and degradation of characteristics can be further suppressed.
[0071] (6) In any of the above (1) to (5), the height of the upper surface of the first cover metal layer from the substrate may be greater than the height of the upper surface of the gate wiring from the substrate, and the height of the lower surface of the first cover metal layer located outside the gate wiring from the substrate may be less than the height of the upper surface of the gate wiring from the substrate. In this way, the gate-drain parasitic capacitance can be further suppressed, and the degradation of characteristics can be further suppressed.
[0072] (7) In any one of the above (1) to (6), the semiconductor device may include a source wiring provided on the first source electrode in an electrically contacting manner, and the height of the upper surface of the first cover metal layer from the substrate is smaller than the height of the upper surface of the source wiring from the substrate. In this way, gate-drain parasitic capacitance and gate-source parasitic capacitance can be suppressed, and degradation of characteristics can be further suppressed.
[0073] (8) In any one of the above (1) to (7), the semiconductor device may include a field plate provided above the substrate between the first gate electrode and the first drain electrode, the field plate being formed of the same material as the first cover metal layer. This can reduce the manufacturing process of forming the cover metal layer.
[0074] (9) In any one of the above (1) to (8), the semiconductor device may include: a third transistor unit, wherein a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode are sequentially provided on the substrate, and the third transistor unit is located in the direction in which the first gate electrode extends relative to the first transistor unit. In this way, the gate-drain parasitic capacitance can be further suppressed, and the degradation of characteristics can be further suppressed.
[0075] (10) One embodiment of the present disclosure is a method for manufacturing a semiconductor device, which includes the following steps: forming a first transistor unit and a second transistor unit on a substrate, wherein the first transistor unit is provided with a first drain electrode, a first gate electrode and a first source electrode in sequence, and the second transistor unit is provided with a second source electrode arranged side by side along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode in sequence, and the second transistor unit is located relative to the first transistor unit in the direction in which the first drain electrode, the first gate electrode and the first source electrode are arranged; between the first source electrode and the second source electrode, A gate wiring is formed on the substrate, the gate wiring is electrically connected to the first gate electrode and the second gate electrode; and a first covering metal layer, a second covering metal layer and a field plate are formed simultaneously, wherein the first covering metal layer is disposed above the substrate between the first source electrode and the gate wiring, adjacent to the first source electrode and the gate wiring, the first covering metal layer is electrically connected to the first source electrode, the second covering metal layer is disposed above the substrate between the second source electrode and the gate wiring, adjacent to the second source electrode and the gate wiring, the second covering metal layer is electrically connected to the second source electrode, and the field plate is disposed above the substrate between the first gate electrode and the first drain electrode. Thus, the degradation of the characteristics can be suppressed, and the manufacturing process of forming the covering metal layer can be reduced.
[0076] [Details of the embodiments of the present disclosure]
[0077] Hereinafter, specific examples of semiconductor devices and methods of manufacturing the same according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.
[0078] [Example 1]
[0079] A semiconductor device of an amplifier used for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a base station for mobile communications will be described as an example. Figure 1 This is a top view of the semiconductor device of Example 1.
[0080] Figure 2 yes Figure 1 A magnified view of range E, Figures 3 to 6 They are Figure 1 or Figure 2The A-A cross-sectional view, the B-B cross-sectional view, the C-C cross-sectional view, and the D-D cross-sectional view are shown in FIG. The thickness direction of the substrate 10 is set to the Z direction, the extension direction of each finger-shaped electrode is set to the Y direction (first direction), and the arrangement direction of each electrode is set to the X direction (second direction intersecting the first direction). Figure 1 In the figure, for simplicity, the field plates 15a and 15c are omitted.
[0081] In each figure, the source electrode 12, the gate electrode 14, the source wiring 22, and the unit FET 35 represent general elements, and the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the source wiring 22a to 22c, and the unit FETs 35a to 35d represent specific elements included in the general elements. Hereinafter, the unit FETs 35a to 35d will be described mainly using the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the drain electrode 16a, the drain electrode 16b, the source wiring 22a to 22c, the drain wiring 26a, and the drain wiring 26c.
[0082] like Figures 1 to 6 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the regions deactivated by ion implantation or the like of the semiconductor layer 10b are the inactive regions 13a and 13b, and the regions not deactivated are the active regions 11a to 11c.
[0083] The active region 11a and the active region 11b are arranged in the X direction. The active region 11c is provided in a region closer to the + direction in the Y direction than the active region 11a and the active region 11b. The region between the active region 11a and the active region 11b is the inactive region 13a. The region between the active region 11a and the active region 11b and the active region 11c is the inactive region 13b. A FET group 36a including a plurality of unit FETs 35a and 35c arranged in the X direction is provided on the active region 11a and the active region 11b. A FET group 36b including a plurality of unit FETs 35b and 35d arranged in the X direction is provided on the active region 11c. The gate bus 25 and the FET group 36b are separated by the FET group 36a. The drain bus 24 and the FET group 36a are separated by the FET group 36b.
[0084] The unit FET 35a (first transistor unit) has a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode) extending in the Y direction and respectively disposed on the substrate 10. The drain electrode 16a, the gate electrode 14a, and the source electrode 12a are disposed in sequence. The unit FET 35c (second transistor unit) is located in the direction in which the drain electrode 16a, the gate electrode 14a, and the source electrode 12a are arranged relative to the unit FET 35a. The unit FET 35c has a source electrode 12c (second source electrode), a gate electrode 14c (second gate electrode), and a drain electrode 16c (second drain electrode) extending in the Y direction and respectively disposed on the substrate 10. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are disposed in sequence. The source electrode 12c is disposed side by side along the source electrode 12a, and is electrically connected to the source electrode 12a via the source electrode 12b. The gate electrode 14c is electrically connected to the gate electrode 14a via the gate bus 25. The drain electrode 16 c is electrically connected to the drain electrode 16 a via a drain bus bar 24 .
[0085] A field plate 15a is provided on the substrate 10 between the gate electrode 14a and the drain electrode 16a and between the gate electrode 14b and the drain electrode 16b via an insulating layer 32a. A field plate 15c is provided on the substrate 10 between the gate electrode 14c and the drain electrode 16c and between the gate electrode 14d and the drain electrode 16d via an insulating layer 32a. At least a portion of the field plate 15a may overlap with the gate electrode 14a and the gate electrode 14b when viewed from the Z direction, or may not overlap. At least a portion of the field plate 15c may overlap with the gate electrode 14c and the gate electrode 14d when viewed from the Z direction, or may not overlap. The field plate 15a and the field plate 15c are electrically connected to the source wiring 22a and the source wiring 22c respectively via the wiring 17 and are short-circuited. The field plate 15a and the field plate 15c are provided to improve the drain withstand voltage and suppress the gate-drain parasitic capacitance. The field plate 15a and the field plate 15c may not be provided.
[0086] A gate wiring 18a extending in the Y direction is provided on the region of the substrate 10 located in the +X direction of the unit FET 35a. The gate wiring 18a is provided on the inactive region 13a between the unit FET 35a and the unit FET 35c. That is, in the unit FET 35a, the source electrode 12a is closer to the gate wiring 18a than the drain electrode 16a. In the unit FET 35c, the source electrode 12c is closer to the gate wiring 18a than the drain electrode 16c.
[0087] The unit FET 35b (third transistor unit) and the unit FET 35d are respectively provided in the region on the substrate 10 located in the direction in which the gate electrode 14a extends relative to the unit FET 35a and the unit FET 35c. The unit FET 35b has a source electrode 12b (third source electrode), a gate electrode 14b (third gate electrode), and a drain electrode 16b (third drain electrode) which extend in the Y direction and are respectively provided on the substrate 10. The drain electrode 16b, the gate electrode 14b, and the source electrode 12b are provided in sequence. The drain electrode 16b is electrically connected to the drain electrode 16a. The gate electrode 14b is electrically connected to the gate wiring 18a. The unit FET 35d has a source electrode 12b, a gate electrode 14d, and a drain electrode 16d which extend in the Y direction and are respectively provided on the substrate 10. The unit FET 35b and the unit FET 35d share the source electrode 12b. When viewed from the Y direction, the source electrode 12 a , the source electrode 12 c , and the gate wiring 18 a are provided so as to overlap with the source electrode 12 b and fall within the range where the source electrode 12 b is provided.
[0088] The gate wiring 18b extending in the X direction is provided on the inactive region 13b. The gate wiring 18b electrically connects the gate wiring 18a to the gate electrode 14b and the gate electrode 14d to short-circuit them. The gate wiring 18a, the gate electrode 14a and the gate electrode 14c are connected to a gate bus 25.
[0089] The cover metal layer 30 is provided to cover the gate wiring 18a via the insulating layer 32a. The width of the cover metal layer 30 in the X direction is larger than the width of the gate wiring 18a in the X direction. Figure 5 The cover metal layer 30 is sandwiched between the source electrode 12b and the source wiring 22b, thereby electrically connecting to the source electrode 12b and the source wiring 22b and short-circuiting. The cover metal layer 30 may also be connected to the source wiring 22a and the source wiring 22c. In this way, the cover metal layer 30 is connected to the source wiring 22a to the source wiring 22c at one or two or more locations.
[0090] The source wiring 22a (first source wiring), the source wiring 22b, and the source wiring 22c (second source wiring) are provided on the source electrode 12a, the source electrode 12b, and the source electrode 12c, respectively, in a contacting manner. The source wiring 22a and the source wiring 22c cross the gate wiring 18b in a non-contact manner via the insulating layer 32a, thereby connecting to the source electrode 12b. The drain wiring 26a (first drain wiring) is provided on the drain electrode 16a and the drain electrode 16b in a contacting manner, and the drain electrode 16a and the drain electrode 16b are electrically connected to the drain bus 24. The drain wiring 26c (second drain wiring) is provided on the drain electrode 16c and the drain electrode 16d in a contacting manner, and the drain electrode 16c and the drain electrode 16d are electrically connected to the drain bus 24.
[0091] The via hole 20 penetrates the substrate 10 and is connected to the source electrode 12b. A metal layer 28 is provided on the lower surface of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20. Thus, the metal layer 28 is electrically connected to the source electrode 12b via the via hole 20 to form a short circuit.
[0092] The source potential (for example, a reference potential such as a ground potential) is supplied from the metal layer 28 to the source electrode 12b via the metal layer 28a in the via 20. Furthermore, the source potential is supplied to the source electrode 12a, the source electrode 12c, the field plate 15a, the field plate 15c, and the cover metal layer 30 via the source wiring 22a to the source wiring 22c. The gate potential (for example, a high-frequency signal and a gate bias voltage) is supplied from the gate bus 25 to the gate electrode 14a and the gate electrode 14c. In addition, the gate potential is supplied from the gate bus 25 to the gate electrode 14b and the gate electrode 14d via the gate wiring 18a and the gate wiring 18b. The drain bias voltage is supplied from the drain bus 24 to the drain electrode 16a to the drain electrode 16d via the drain wiring 26a and the drain wiring 26c. The high-frequency signal amplified in each unit FET 35a to the unit FET 35d is output from the drain wiring 26a and the drain wiring 26c to the drain bus 24.
[0093] In the unit FET 35a and the unit FET 35c, a high-frequency signal is input from the - end in the Y direction of the gate electrode 14a and the gate electrode 14c. In the unit FET 35b and the unit FET 35d, a high-frequency signal is input from the - end in the Y direction of the gate electrode 14b and the gate electrode 14d. If a high-frequency signal is input to the gate electrode 14a and the gate electrode 14c from both ends of the + end and the - end in the Y direction of the gate electrode 14a and the gate electrode 14c, the high-frequency characteristics of the unit FET 35a and the unit FET 35c will deteriorate due to a phase difference, etc. In the first embodiment, the + end in the Y direction of the gate electrode 14a and the gate electrode 14c is not connected to the - end in the Y direction of the gate electrode 14b and the gate electrode 14d, so that the degradation of the high-frequency characteristics of the unit FET 35a and the unit FET 35c can be suppressed.
[0094] In the case where the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. In the case where the unit FETs 35a to 35d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. In the case where the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as a LDMOS (Laterally Diffused Metal Oxide Semiconductor).
[0095] The source electrodes 12a to 12c and the drain electrodes 16a to 16d are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d, the gate wiring 18a and the gate wiring 18b are metal films, for example, nickel films and gold films from the substrate 10 side. The field plates 15a, 15c and the cover metal layer 30 are, for example, titanium films or nickel films, and gold films or aluminum films from the insulating layer 32a side. The source wirings 22a to 22c, the drain wirings 26a and 26c are, for example, gold layers, copper layers or aluminum layers. The insulating layers 32a and 32b are, for example, inorganic insulating layers such as silicon nitride layers. The insulating layer 32 is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.
[0096] The width of the source electrode 12a and the source electrode 12c in the X direction is, for example, 5 μm to 20 μm. The width of the source electrode 12b in the X direction is, for example, 50 μm to 150 μm. The gate length of the gate electrodes 14a to 14d in the X direction is, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a and 16c in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 18a in the X direction is, for example, 5 μm to 20 μm. The width of the gate wiring 18b in the Y direction is, for example, 3 μm to 20 μm. The width of the field plates 15a and 15c in the X direction is, for example, 1 μm to 10 μm. The width of the cover metal layer 30 in the X direction is, for example, 7 μm to 25 μm. The gate width of the unit FETs 35a to 35d in the Y direction is, for example, 100 μm to 400 μm. The width of the via hole 20 in the X direction is, for example, 10 μm to 60 μm.
[0097] The widths of the source wirings 22a to 22c, the drain wirings 26a and 26c in the X direction are the same as or slightly smaller than the widths of the source electrodes 12a to 12c, the drain electrodes 16a and 16c in the X direction, respectively. The thicknesses of the source wirings 22a to 22c, the drain wirings 26a and 26c are, for example, 1 μm to 20 μm. The thicknesses of the field plates 15a, 15c and the cover metal layer 30 are, for example, 0.5 μm to 1 μm.
[0098] [Manufacturing method of Example 1]
[0099] Figures 7 to 10 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 11A to FIG. 14B is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1, which is equivalent to Figures 7 to 10 A-A section.
[0100] like Figure 7 and Fig.11A As shown, by performing ion implantation into the semiconductor layer 10b, an inactive region 13a and an inactive region 13b are formed in the semiconductor layer 10b. The region where the inactive region 13a and the inactive region 13b are not formed is the active region 11a to the active region 11c. The inactive region 13a is formed between the active region 11a and the inactive region 11b, and the inactive region 13b is formed between the active region 11a and the active region 11b and the active region 11c.
[0101] like Figure 7 and Fig. 11BAs shown, a source electrode 12a and a drain electrode 16a are formed on the active region 11a. A source electrode 12c and a drain electrode 16c are formed on the active region 11b. A source electrode 12b, a drain electrode 16b, and a drain electrode 16d are formed on the active region 11c. In the formation of the source electrodes 12a to 12c and the drain electrodes 16a to 16d, for example, a vacuum evaporation method and a lift-off method are used. Thereafter, a heat treatment is performed. Thus, the source electrodes 12a to 12c and the drain electrodes 16a to 16d are in ohmic contact with the active region 11a, the active region 11b, and the active region 11c.
[0102] like Figure 8 and Fig. 12A As shown, gate electrodes 14a to 14d, gate wirings 18a and 18b, and a gate metal layer 25a are formed on a substrate 10. The gate electrodes 14a to 14d, gate wirings 18a and 18b, and the gate metal layer 25a are formed by, for example, vacuum evaporation and lift-off.
[0103] like Fig. 12B As shown, an insulating layer 32a is formed on the substrate 10 to cover the source electrodes 12a to 12c, the drain electrodes 16a and 16c, the gate electrodes 14a to 14d, the gate wiring 18a and 18b, and the gate metal layer 25a. The insulating layer 32a is formed by, for example, using a CVD (Chemical Vapor Deposition) method.
[0104] like Fig. 9 and Fig.13A As shown, field plates 15a, 15c and a cover metal layer 30 are formed on the insulating layer 32a. For example, vacuum evaporation and lift-off methods are used to form the field plates 15a, 15c and the cover metal layer 30. The + end of the cover metal layer 30 in the Y direction contacts the source electrode 12b.
[0105] like Fig.10 and Fig. 13B As shown, an opening is formed in a desired region of the insulating layer 32a by etching. Source wirings 22a to 22c, drain wirings 26a and 26c are formed on the source electrodes 12a to 12c, and drain electrodes 16a and 16c, respectively, so as to be in contact with each other. A gate bus 25 and a drain bus 24 are formed. For example, a plating method is used to form the source wirings 22a to 22c, the gate bus 25 and the drain bus 24.
[0106] like Fig.14AAs shown, an insulating layer 32b is formed to cover the field plates 15a and 15c, the source wirings 22a to 22c, the drain wirings 26a and 26c, and the metal layer 30. The insulating layer 32b is formed by, for example, CVD.
[0107] like Fig. 14B As shown, the insulating layer 32 is formed on the insulating layer 32b. The insulating layer 32 is formed by applying a solvent containing a resin and performing a heat treatment. Openings (not shown) for exposing the gate bus bar 25 and the drain bus bar 24 are formed in the insulating layer 32 and the insulating layer 32b.
[0108] Then, the lower surface of the substrate 10 is ground or polished to make the substrate 10 thinner, and a via hole 20 is formed to penetrate the substrate 10. The metal layer 28 and the metal layer 28a are formed on the lower surface of the substrate 10 and the inner surface of the via hole 20. Thus, the semiconductor device of Example 1 is manufactured.
[0109] [Comparative Example 1]
[0110] Fig.15 is a cross-sectional view of a semiconductor device of Comparative Example 1. Fig.15 As shown, in the semiconductor device 110 of the comparative example 1, the cover metal layer 30 is not provided. The other structures are the same as those of the first embodiment.
[0111] The gate wiring 18a connects the gate electrode 14b and the gate electrode 14d (see Figure 2 ) is electrically connected to the gate bus 25. Thus, the unit FET 35b and the unit FET 35d (see Figure 2 ) gate resistance. However, as indicated by the solid arrow 50, the gate wiring 18a and the drain wiring 26a and the drain wiring 26c are capacitively coupled due to the electric lines passing through the source wiring 22a and the source wiring 22c. As a result, the gate-drain parasitic capacitance increases. If the gate-drain parasitic capacitance increases, the gain decreases. In addition, the K factor, which is a stability factor, decreases. In this way, the high-frequency characteristics of the semiconductor device 110 deteriorate.
[0112] [Description of Example 1]
[0113] like Figure 3As described above, according to Embodiment 1, a covering metal layer 30 is provided above the gate wiring 18a. Thus, as shown by the dotted arrow 52, the covering metal layer 30 shields the electric lines between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c. Thus, the capacitive coupling between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c is suppressed. Thus, the gate-drain parasitic capacitance can be suppressed, and the degradation of the high-frequency characteristics of the semiconductor device 100 can be suppressed. It should be noted that in Embodiment 1, the gate-source parasitic capacitance and the drain-source parasitic capacitance are increased. However, the gate-source capacitance and the drain-source capacitance are larger than the gate-drain capacitance. Therefore, the influence of the gate-source parasitic capacitance and the drain-source parasitic capacitance is small.
[0114] The two ends of the covering metal layer 30 in the X direction are located outside the gate wiring 18a in the X direction when viewed from the Z direction. The height H1 of the lower surface of the end of the covering metal layer 30 in the X direction from the substrate 10 is less than the height H3 of the upper surface of the gate wiring 18a from the substrate 10. As a result, the covering metal layer 30 can further shield the electric lines between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c, and can further suppress capacitive coupling. From the perspective of shielding effect, the height H1 can be set to less than 3 / 4 of the height H3, and can be set to less than 1 / 2. From the perspective of suppressing the contact between the covering metal layer 30 and the substrate 10, the height H1 is more than 1 / 10 of the height H3.
[0115] The height H2 of the upper surface of the cover metal layer 30 from the substrate 10 is smaller than the height H4 of the upper surface of the source wiring 22a and the source wiring 22c from the substrate 10. Thus, the source wiring 22a and the source wiring 22c can also shield the electric lines between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c, and can suppress capacitive coupling. From the perspective of the shielding effect, the height H2 can be set to less than 3 / 4 of the height H4, and can be set to less than 1 / 2. The height H2 is more than 1 / 10 of the height H4.
[0116] like Figure 4 In this way, in the passive region 13b, the cover metal layer 30 is provided on the center portion of the gate wiring 18b in the X direction via the insulating layer 32a. As a result, as indicated by the dotted arrow 51, the cover metal layer 30 shields a portion of the gate wiring 18b and the electric lines of force between the drain wiring 26a and the drain wiring 26c, thereby suppressing capacitive coupling. As a result, the parasitic capacitance between the gate and the drain can be suppressed, and the degradation of the high frequency characteristics of the semiconductor device 100 can be suppressed.
[0117] [Variation 1 of Example 1]
[0118] Fig.16 This is an enlarged top view of a semiconductor device according to Modification 1 of Embodiment 1. Fig.17yes Fig.16 A-A section view. Fig.16 and Fig.17 As shown, in the semiconductor device 102 of the first modification of the first embodiment, the cover metal layer 30 includes a cover metal layer 30a and a cover metal layer 30c. A gap 38 is provided between the cover metal layer 30a and the cover metal layer 30c. When viewed from the Z direction, the + side surface of the cover metal layer 30a in the X direction overlaps with the gate wiring 18a, and the - side surface of the cover metal layer 30c in the X direction overlaps with the gate wiring 18a. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.
[0119] like Fig.17 As shown by the dashed arrow 54, most of the electric lines of force between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c are shielded by the cover metal layer 30. There are not many electric lines of force passing through the gap 38. Thus, the gate-drain parasitic capacitance can be suppressed. On the other hand, a part of the area closest to the gate wiring 18a in the cover metal layer 30 is the gap 38. Thus, the gate-source parasitic capacitance can be suppressed.
[0120] The width W1 of the gap 38 in the X direction can be appropriately set depending on whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is emphasized. When the suppression of the gate-drain parasitic capacitance is emphasized, the width W1 can be set to 0.8 times or less, or 0.5 times or less, of the width W2 of the gate wiring 18a in the X direction. When the suppression of the gate-source parasitic capacitance is emphasized, the width W1 can be set to 0.25 times or more, or 0.5 times or more, of the width W2.
[0121] [Variation 2 of Example 1]
[0122] Fig.18 This is an enlarged top view of a semiconductor device according to a second variation of the first embodiment. Fig.19 yes Fig.18 A-A section view. Fig.18 and Fig.19 As shown, in the semiconductor device 104 of the second variation of the first embodiment, the cover metal layer 30 includes a cover metal layer 30a and a cover metal layer 30c. When viewed from the Z direction, the cover metal layer 30a and the cover metal layer 30c do not overlap with the gate wiring 18a. The other structures are the same as those of the first embodiment, and the description thereof is omitted.
[0123] like Fig.19As shown in the embodiment 1, the cover metal layer 30a and the cover metal layer 30c suppress a portion of the electric force lines between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c, as shown by the dotted arrow 53a. As shown by the solid arrow 53b, a portion of the electric force lines between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c is not shielded. As a result, the gate-drain parasitic capacitance is increased compared to the embodiment 1, and the gate-source parasitic capacitance is reduced.
[0124] From the perspective of suppressing the gate-drain parasitic capacitance, the height H2 of the upper surface of the covering metal layer 30a and the covering metal layer 30c from the upper surface of the substrate 10 can be set to be greater than the height H3 of the upper surface of the gate wiring 18a from the upper surface of the substrate 10, can be set to be greater than 1.2 times, and can be set to be greater than 1.5 times. The height H2 can also be greater than the height H4. From the perspective of the manufacturing process, the height H2 can be set to be less than 5 times the height H3.
[0125] According to Embodiment 1 and its Modification 1 and Modification 2, as Figure 3 , Fig.17 as well as Fig.19 In this way, the cover metal layer 30 or the cover metal layer 30a (first cover metal layer) is provided above the substrate 10 between the source electrode 12a and the gate wiring 18a, adjacent to the source electrode 12a and the gate wiring 18a, as shown in FIG. Figure 2 Thus, the cover metal layer 30 or the cover metal layer 30a suppresses the capacitive coupling between the gate wiring 18a and the drain wiring 26a. Thus, the gate-drain parasitic capacitance can be suppressed, and the degradation of the characteristics of the semiconductor device can be suppressed.
[0126] Furthermore, at least a portion of the cover metal layer 30 overlaps the gate wiring 18a in a non-contact manner when viewed from the Z direction. This can further suppress the gate-drain parasitic capacitance and further suppress the degradation of the characteristics of the semiconductor device.
[0127] The cover metal layer 30 or the cover metal layer 30c (second cover metal layer) is provided above the substrate 10 between the source electrode 12c and the gate wiring 18a, adjacent to the source electrode 12c and the gate wiring 18a, as shown in FIG. Figure 2 Thus, the cover metal layer 30 or the cover metal layer 30c suppresses the capacitive coupling between the gate wiring 18a and the drain wiring 26c. Thus, the gate-drain parasitic capacitance can be further suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0128] According to Example 1, Figure 3In this way, the cover metal layer 30a and the cover metal layer 30c included in the cover metal layer 30 are in contact above the gate wiring 18a. As a result, the gate-drain parasitic capacitance can be further suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed. When viewed from the X direction, the cover metal layers 30a and 30c are in contact at all locations. As a result, the gate-drain parasitic capacitance can be further suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0129] As in the variant 1 and the variant 2 of the embodiment 1 Fig.17 and Fig.19 Thus, the cover metal layer 30a and the cover metal layer 30c are not in contact with each other above the gate wiring 18a. This can suppress the gate-source parasitic capacitance and further suppress the degradation of the characteristics of the semiconductor device.
[0130] Furthermore, the ends of the cover metal layers 30a and 30c in the X direction overlap the gate wiring 18a when viewed from the Z direction. This can suppress gate-drain parasitic capacitance and gate-source parasitic capacitance, and further suppress degradation of the characteristics of the semiconductor device.
[0131] As in Example 1, its variant 1 and variant 2 Figure 3 , Fig.17 as well as Fig.19 In this way, the height H2 of the upper surface of the covering metal layer 30 from the substrate 10 is greater than the height H3 of the upper surface of the gate wiring 18a from the substrate 10. When viewed from the Z direction, the height H1 of the lower surface of the end of the covering metal layer 30 located on the outer side of the gate wiring 18a in the X direction from the substrate 10 is less than the height H3 of the upper surface of the gate wiring 18a from the substrate 10. Thus, the end of the covering metal layer 30 on the outer side of the gate wiring 18a in the X direction covers a part of the side of the gate wiring 18a. Thus, the capacitive coupling between the gate wiring 18a and the drain wiring 26a and the drain wiring 26c is suppressed. Thus, the gate-drain parasitic capacitance can be further suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0132] The height H2 of the upper surface of the cover metal layer 30 from the substrate 10 is smaller than the height H4 of the upper surfaces of the source wiring 22a and the source wiring 22c from the substrate 10. Thus, the gate-drain parasitic capacitance and the gate-source parasitic capacitance can be suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0133] like Fig. 9 and Fig.13AIn this way, the covering metal layer 30 and the field plates 15a and 15c are formed at the same time. As a result, the manufacturing process of forming the covering metal layer 30 can be reduced. The covering metal layer 30 and the field plates 15a and 15c are formed of the same material. In addition, the thickness of the covering metal layer 30 is equal to the thickness of the field plates 15a and 15c. It should be noted that at least a part of the field plates 15a and 15c may not be provided.
[0134] [Example 2]
[0135] Fig. 20 FIG. 2 is a top view of the semiconductor device of Example 2. Fig. 20 As shown, in the semiconductor device 106 of the second embodiment, a FET group 36c and a FET group 36d are provided between the FET group 36a and the FET group 36b. The source wiring 22a and the source wiring 22c are electrically connected to the source electrodes of the FET group 36a, the FET group 36c, and the FET group 36d. The drain wiring 26a and the drain wiring 26c are electrically connected to the drain electrodes of the FET group 36a to the FET group 36d. The gate wiring 18a and the gate wiring 18b are electrically connected to the gate electrodes 14 of the FET group 36b to the FET group 36d. A cover metal layer 30 is provided in the region between the source wiring 22a and the source wiring 22c of the FET group 36a, the FET group 36c, and the FET group 36d. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.
[0136] As in Example 2, the number of FET groups arranged in the Y direction may be four. In Example 1 and its variants, the number of FET groups arranged in the Y direction may be appropriately set. In Example 1, Example 2 and its variants, an example in which four unit FETs 35 are arranged in the X direction is described, but the number of unit FETs 35 in the X direction may be any one of one to three, five or more, and may be appropriately set.
[0137] [Measurement results]
[0138] GaN HEMTs having the structures of Comparative Example 1 and Example 1 were fabricated, and their high-frequency characteristics were measured. A high-frequency signal was input to the gate bus 25 , and an amplified high-frequency signal was output from the drain bus 24 . Fig.21 is a graph showing K factors of semiconductor device A and semiconductor device B with respect to frequency. Fig. 22 Graph showing |S12| of semiconductor device A and semiconductor device B with respect to frequency. Fig.21 The horizontal axis is the frequency, and the vertical axis is the K factor, which is the stability factor. The smaller the K factor, the less likely it is to oscillate, and the more stable it is. Fig. 22The horizontal axis is frequency, and the vertical axis is |S12|. |S12| is the absolute value of the S parameter S12 when the gate is set as port 1 and the drain is set as port 2. |S12| represents the power fed back from the drain to the gate. Semiconductor device A corresponds to Example 1, and semiconductor device B corresponds to Comparative Example 1.
[0139] like Fig.21 and Fig. 22 As shown in the figure, when the frequency increases, both the K factor and |S12| increase. Compared with semiconductor device B, semiconductor device A has smaller K factor and |S12|. The gate-drain capacitance is a feedback capacitance, and when the gate-drain capacitance increases, both the K factor and |S12| increase. Compared with semiconductor device B, semiconductor device A can reduce the gate-drain capacitance and suppress the K factor and |S12|.
[0140] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.
Claims
1. A semiconductor device comprising: substrate; A first transistor unit, wherein a first drain electrode, a first gate electrode and a first source electrode are sequentially provided on the substrate; a second transistor unit, wherein a second source electrode, a second gate electrode, and a second drain electrode are arranged in parallel along the first source electrode and electrically connected to the first source electrode, respectively, on the substrate, and the second transistor unit is located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; a gate wiring, provided on the substrate between the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer, disposed above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, the first cover metal layer being electrically connected to the first source electrode; as well as A second cover metal layer is provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring. The second cover metal layer is electrically connected to the second source electrode.
2. The semiconductor device according to claim 1, wherein At least a portion of the first cover metal layer and at least a portion of the second cover metal layer overlap the gate wiring in a non-contact manner in a plan view.
3. The semiconductor device according to claim 1 or 2, wherein: The first cover metal layer and the second cover metal layer are in contact with each other above the gate wiring.
4. The semiconductor device according to claim 1 or 2, wherein: The first cover metal layer and the second cover metal layer are not in contact with each other above the gate wiring.
5. The semiconductor device according to claim 4, wherein: The end of the first cover metal layer overlaps with the gate wiring when viewed from above, An end portion of the second cover metal layer overlaps with the gate wiring in a plan view.
6. The semiconductor device according to claim 1 or 2, wherein: The height of the upper surface of the first covering metal layer from the substrate is greater than the height of the upper surface of the gate wiring from the substrate, and the height of the lower surface of the first covering metal layer located outside the gate wiring from the substrate is less than the height of the upper surface of the gate wiring from the substrate.
7. The semiconductor device according to claim 1 or 2, wherein: A source wiring is provided on the first source electrode in an electrically contacting manner, A height of an upper surface of the first cover metal layer from the substrate is smaller than a height of an upper surface of the source wiring from the substrate.
8. The semiconductor device according to claim 1 or 2, comprising: A field plate is disposed above the substrate between the first gate electrode and the first drain electrode, and the field plate is formed of the same material as the first covering metal layer.
9. The semiconductor device according to claim 1 or 2, comprising: A third transistor unit, wherein a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode are sequentially arranged on the substrate, and the third transistor unit is located in the direction in which the first gate electrode extends relative to the first transistor unit.
10. A method for manufacturing a semiconductor device, comprising the following steps: A first transistor unit and a second transistor unit are formed on a substrate, wherein: The first transistor unit is provided with a first drain electrode, a first gate electrode and a first source electrode in sequence, the second transistor unit is provided with a second source electrode arranged side by side along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode and a second drain electrode electrically connected to the first drain electrode in sequence, and the second transistor unit is located in a direction in which the first drain electrode, the first gate electrode and the first source electrode are arranged relative to the first transistor unit; A gate wiring is formed on the substrate between the first source electrode and the second source electrode, and the gate wiring is electrically connected to the first gate electrode and the second gate electrode; as well as A first covering metal layer, a second covering metal layer and a field plate are formed at the same time, wherein the first covering metal layer is between the first source electrode and the gate wiring, and is adjacent to the first source electrode and the gate wiring and is arranged above the substrate, and the first covering metal layer is electrically connected to the first source electrode, the second covering metal layer is between the second source electrode and the gate wiring, and is adjacent to the second source electrode and the gate wiring and is arranged above the substrate, the second covering metal layer is electrically connected to the second source electrode, and the field plate is arranged above the substrate between the first gate electrode and the first drain electrode.