Semiconductor device

Abstract

There is provided a semiconductor device including: a substrate including an active pattern; a channel pattern on the active pattern, in which the channel pattern includes a plurality of semiconductor patterns; a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode extending in a first direction on the channel pattern, in which the gate electrode includes an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern among the plurality of semiconductor patterns; and an inner gate spacer between the inner gate electrode and the source / drain pattern, in which the inner gate spacer includes a central portion having a first thickness in the second direction and an edge portion having a second thickness in the second direction, the first thickness being greater than the second thickness, the first semiconductor pattern and the second semiconductor pattern are adjacent to each other in the third direction.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0084069 filed in the Korean Intellectual Property Office on June 29, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same. Background Art

[0003] A semiconductor device may include an integrated circuit that may include a metal oxide semiconductor field effect transistor (MOSFET). In order to meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOSFETs are being scaled down. Scaling down of MOSFETs may result in degradation of the operating properties of the semiconductor device. Various studies are being conducted to overcome technical limitations associated with scaling down of semiconductor devices and to achieve high performance semiconductor devices. Summary of the invention

[0004] The inventive concepts of the present disclosure may provide a semiconductor device having improved reliability and electrical characteristics.

[0005] According to some embodiments of the inventive concepts disclosed herein, a semiconductor device may include: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode extending along a first direction on the channel pattern, wherein the gate electrode includes an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern among the plurality of semiconductor patterns; and an inner gate spacer between the inner gate electrode and the source / drain pattern, wherein the inner gate spacer includes a central portion and an edge portion adjacent to a first side of the central portion in the first direction, wherein the central portion has a first thickness in a second direction, wherein the edge portion has a second thickness in the second direction, wherein the first thickness is greater than the second thickness, wherein the first semiconductor pattern and the second semiconductor pattern are adjacent to each other in a third direction, wherein the first direction is parallel to an upper surface of the substrate, wherein the second direction is parallel to the upper surface of the substrate and intersects the first direction, and wherein the third direction is perpendicular to the upper surface of the substrate.

[0006] According to some embodiments of the inventive concepts disclosed herein, a semiconductor device may include: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode extending along a first direction on the channel pattern, wherein the gate electrode includes an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern among the plurality of semiconductor patterns; an inner gate spacer between the inner gate electrode and the source / drain pattern; and an inner high-k dielectric layer between the inner gate electrode and the inner gate spacer, wherein the inner gate spacer includes a first portion and a second portion adjacent to a first side of the first portion in the first direction, wherein the first portion includes a first outer surface contacting the inner high-k dielectric layer, wherein the second portion includes a second outer surface contacting the inner high-k dielectric layer, wherein the first outer surface is closer to a central portion of the inner gate electrode than the second outer surface, and wherein the first direction is parallel to an upper surface of the substrate.

[0007] According to some embodiments of the inventive concepts of the present disclosure, a semiconductor device may include: a substrate including an active region; an active pattern on the active region; a device isolation layer adjacent to the active pattern; a channel pattern and a source / drain pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns spaced apart from each other and stacked in a second direction, and wherein the source / drain pattern is electrically connected to the plurality of semiconductor patterns; a gate electrode extending along a first direction on the channel pattern, wherein the gate electrode includes an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern among the plurality of semiconductor patterns; a gate insulating layer between the first semiconductor pattern and the second semiconductor pattern and the inner gate electrode, wherein the gate insulating layer includes an inner gate electrode between the inner gate electrode and the source / drain pattern; a gate spacer; an inner high-k dielectric layer between the inner gate electrode and the inner gate spacer; and a gate spacer on a sidewall of the gate electrode, wherein the first semiconductor pattern and the second semiconductor pattern are adjacent to each other in a second direction, wherein the inner gate spacer includes a first edge portion, a second edge portion spaced apart from the first edge portion in the first direction, and a center portion between the first edge portion and the second edge portion, wherein a thickness of the inner gate spacer in a third direction increases from the first edge portion toward the center portion, reaches a maximum value at the center portion, and decreases from the center portion toward the second edge portion, wherein the second direction is perpendicular to an upper surface of the substrate, wherein the first direction is parallel to the upper surface of the substrate, and wherein the third direction is parallel to the upper surface of the substrate and intersects with the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0009] Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to some example embodiments of the inventive concept.

[0010] Figure 4 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept.

[0011] FIG. 5A to FIG. 5D Along the Figure 4 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0012] Fig. 6A It is shown Figure 5A An enlarged view of an embodiment of region "M".

[0013] Figure 6B It is along Figure 5B A cross-sectional view taken along line XX'.

[0014] 7A to 17B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0015] Fig.18 and Fig.19 According to some exemplary embodiments of the present invention, Figure 5B A cross-sectional view taken along line XX'. DETAILED DESCRIPTION

[0016] Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to some example embodiments of the inventive concept.

[0017] Reference Figure 1 , a single height cell SHC may be provided. For example, a first power wiring M1_R1 and a second power wiring M1_R2 may be provided on the substrate 100. The first power wiring M1_R1 may be a channel through which a source voltage VSS (eg, a ground voltage) is provided. The second power wiring M1_R2 may be a channel through which a drain voltage VDD (eg, a power supply voltage) is provided.

[0018] The single height cell SHC may be defined between the first power wiring M1_R1 and the second power wiring M1_R2. The single height cell SHC may include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 may be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. That is, the single height cell SHC may have a CMOS structure disposed between the first power wiring M1_R1 and the second power wiring M1_R2. For example, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0019] Each of the first active region AR1 and the second active region AR2 may have a single width WI1 in the first direction D1. The first direction D1 may extend parallel to the upper surface of the substrate 100. The length of the single height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to a distance (e.g., a pitch) between the first power wiring M1_R1 and the second power wiring M1_R2.

[0020] The single height cell SHC may constitute a logic unit. In this specification, a logic unit may represent a logic element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic unit may include transistors that constitute the logic element and wiring that connects the transistors to each other (e.g., electrically connected). It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "bound to" another element or layer, the element or layer may be directly on the other element or layer, directly connected to or bound to another element or layer, or one or more intervening elements or layers may exist. In contrast, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive to" another element or "directly on" another element, there is no intervening element. In addition, "electrically connected" conceptually includes physical connection and physical disconnection.

[0021] Reference Figure 2 , a double height cell DHC may be provided. For example, a first power wiring M1_R1, a second power wiring M1_R2, and a third power wiring M1_R3 may be provided on the substrate 100. The first power wiring M1_R1 may be provided between the second power wiring M1_R2 and the third power wiring M1_R3. The third power wiring M1_R3 may be a channel through which a source voltage VSS is provided.

[0022] The double height cell DHC may be defined between the second power wiring M1_R2 and the third power wiring M1_R3 The double height cell DHC may include two first active regions AR1 and two second active regions AR2.

[0023] One of the two second active regions AR2 may be adjacent to the second power wiring M1_R2. The other of the two second active regions AR2 may be adjacent to the third power wiring M1_R3. The two first active regions AR1 may be adjacent to the first power wiring M1_R1. When viewed in a plan view, the first power wiring M1_R1 may be disposed between the two first active regions AR1.

[0024] The length of the double height unit DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be Figure 1 The two first active areas AR1 of the double height cell DHC may be grouped together to operate as one active area.

[0025] In the present invention, Figure 2 The double height cell DHC shown in FIG. 1 may be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple height cell, the cell height of which is Figure 1 The single-height cell in the SHC is approximately three times the cell height.

[0026] Reference Figure 3 , the first single height cell SHC1, the second single height cell SHC2, and the double height cell DHC may be two-dimensionally arranged on the substrate 100. The first single height cell SHC1 may be arranged between the first power wiring M1_R1 and the second power wiring M1_R2. The second single height cell SHC2 may be arranged between the first power wiring M1_R1 and the third power wiring M1_R3. The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1.

[0027] The double height cell DHC may be disposed between the second power wiring M1_R2 and the third power wiring M1_R3. The double height cell DHC may be adjacent to the first single height cell SHC1 and the second single height cell SHC2 in the second direction D2. The second direction D2 may extend parallel to the upper surface of the substrate 100. The first direction D1 and the second direction D2 may intersect each other (e.g., may be perpendicular to each other).

[0028] The separation structure DB may be disposed between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. The active region of the double height cell DHC may be electrically separated from the active region of each of the first single height cell SHC1 and the second single height cell SHC2 by the separation structure DB.

[0029] Figure 4 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept. Figure 5A , Figure 5B , Figure 5C and Figure 5D Along the Figure 4 Cross-sectional views taken along lines AA', BB', CC' and DD'. Fig. 6A It is shown Figure 5A An enlarged view of an embodiment of region "M". Figure 6B It is along Figure 5B A cross-sectional view taken along line XX'. Figure 4 and FIG. 5A to FIG. 5D The semiconductor device shown is Figure 1 A more detailed example of a single height unit SHC.

[0030] Reference Figure 4 and FIG. 5A to FIG. 5D , the single height cell SHC may be disposed on the substrate 100. The logic transistor constituting the logic circuit may be disposed on the single height cell SHC. The substrate 100 may be a semiconductor substrate including, for example, silicon, germanium, silicon germanium, etc., or a compound semiconductor substrate. For example, the substrate 100 may be a silicon substrate.

[0031] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in the second direction D2. As an example, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0032] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR (or a device isolation layer ST in the trench TR to be discussed below) formed on an upper portion (e.g., upper surface) of the substrate 100. For example, the trench TR (device isolation layer ST) may be adjacent to the first active pattern AP1 and / or the second active pattern AP2. The first active pattern AP1 may be disposed on the first active region AR1, and the second active pattern AP2 may be disposed on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be a part of the substrate 100 and may be a vertical protrusion of the substrate 100. For example, the first active pattern AP1 and the second active pattern AP2 may protrude in the third direction D3. The third direction D3 may extend perpendicular to the upper surface of the substrate 100. The third direction D3 may intersect the first direction D1 and the second direction D2 (e.g., perpendicular to the first direction D1 and the second direction D2). The third direction D3 may be referred to as a vertical direction.

[0033] A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may at least partially fill the trench TR. The device isolation layer ST may include, for example, a silicon oxide layer. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2 to be described later.

[0034] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction (e.g., in a third direction D3).

[0035] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include, for example, silicon (Si), germanium (Ge), and / or silicon germanium (SiGe). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon. In some embodiments of the inventive concept, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be stacked nanosheets.

[0036] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first recesses RS1 may be formed on the first active pattern AP1. The first source / drain pattern SD1 may be correspondingly disposed in the first recess RS1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., n-type). The first channel pattern CH1 may be disposed between a pair of first source / drain patterns SD1. Here, a pair of first source / drain patterns SD1 may refer to first source / drain patterns SD1 adjacent to each other in the second direction D2. That is, the stacked first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the first channel pattern CH1 may connect (e.g., electrically connect) the pair of first source / drain patterns SD1 to each other.

[0037] A plurality of second source / drain patterns SD2 may be disposed on the second active pattern AP2. A plurality of second recesses RS2 may be formed on the second active pattern AP2. The second source / drain pattern SD2 may be disposed in the second recess RS2 accordingly. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., p-type). The second channel pattern CH2 may be disposed between a pair of second source / drain patterns SD2. Here, a pair of second source / drain patterns SD2 may refer to second source / drain patterns SD2 that are adjacent to each other in the second direction D2. That is, the stacked first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the second channel pattern CH2 may connect the pair of second source / drain patterns SD2 to each other (e.g., electrically connect).

[0038] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the upper surface of the third semiconductor pattern SP3. In some embodiments, the upper surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be positioned at substantially the same level as the upper surface of the third semiconductor pattern SP3. Hereinafter, the terms high (higher), low (lower), etc. may refer to relative distances from the substrate 100. For example, element A being higher than element B may mean that element A is disposed farther from the upper surface of the substrate 100 than element B in the vertical direction. The term "horizontal" may refer to a distance from the substrate 100 in the vertical direction.

[0039] As an embodiment of the inventive concept, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element (e.g., Si) of the substrate 100. Therefore, the pair of second source / drain patterns SD2 may provide compressive stress to the second channel pattern CH2 therebetween.

[0040] The sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a convex embossed shape. That is, each sidewall of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a wavy (uneven) profile. The sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may protrude toward the first to third portions PO1, PO2, and PO3 of the gate electrode GE to be described below.

[0041] The gate electrode GE may be disposed to intersect the first channel pattern CH1 and the second channel pattern CH2 and extend in the first direction D1. The gate electrodes GE may be arranged in the second direction D2 at a first pitch. Each gate electrode GE may be vertically overlapped with the first channel pattern CH1 and the second channel pattern CH2 (e.g., overlapped in a third direction D3). As used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one line extending along the direction X and intersecting both elements A and B.

[0042] The gate electrode GE may include a first portion PO1 disposed between an active pattern (e.g., a first active pattern AP1 or a second active pattern AP2) and a first semiconductor pattern SP1, a second portion PO2 (or referred to as an "inner gate electrode") disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3 (the topmost semiconductor pattern).

[0043] Reference Figure 5D , the gate electrode GE may be disposed on the upper surface TS, the lower surface BS, and the two (opposite) side walls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. That is, the transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., a multi-bridge channel (MBC) FET or a gate all around (GAA) FET) in which the gate electrode GE extends in three dimensions to surround (e.g., surround) a channel (e.g., the first channel pattern CH1 and the second channel pattern CH2).

[0044] Reference Figure 4 and FIG. 5A to FIG. 5D , a pair of gate spacers GS may be respectively disposed on two (opposite) side walls of the fourth portion PO4 of the gate electrode GE. The gate spacer GS may extend in the first direction D1 along the gate electrode GE. The upper surface of the gate spacer GS may be higher than the upper surface of the gate electrode GE (e.g., the upper surface of the fourth portion PO4). The upper surface of the gate spacer GS may be coplanar with the upper surface of the first interlayer insulating layer 110 to be described later. In some embodiments, the gate spacer GS may include, for example, at least one of SiCN, SiCON, and SiN. In some embodiments, the gate spacer GS may include, for example, a multilayer formed of at least two of SiCN, SiCON, and SiN.

[0045] The gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend in the first direction D1 along the gate electrode GE. The gate capping pattern GP may include a material having an etching selectivity with respect to a first interlayer insulating layer 110 and a second interlayer insulating layer 120 to be described later. For example, the gate capping pattern GP may include SiON, SiCN, SiCON, and / or SiN.

[0046] The gate insulating layer GI may be disposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may be on the upper surface TS, the lower surface BS, and the two (opposite) side walls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 (e.g., covering the upper surface TS, the lower surface BS, and the two (opposite) side walls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 or overlapping the upper surface TS, the lower surface BS, and the two (opposite) side walls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3). The gate insulating layer GI may be on the upper surface of the device isolation layer ST below the gate electrode GE (e.g., covering the upper surface of the device isolation layer ST below the gate electrode GE or overlapping the upper surface of the device isolation layer ST below the gate electrode GE).

[0047] As an embodiment of the inventive concept, refer to Fig. 6A, the gate insulating layer GI may include an inner spacer IS and a high dielectric layer HK. Here, the high dielectric layer may refer to a high-k dielectric layer. In some embodiments, the inner spacer IS may include an inner gate spacer IGS and an outer gate spacer OGS. Each of the inner gate spacer IGS and the outer gate spacer OGS may include, for example, an insulating material containing silicon (Si). Each of the inner gate spacer IGS and the outer gate spacer OGS may include, for example, a silicon oxide layer, a silicon oxynitride layer, and / or a silicon nitride layer.

[0048] The high dielectric layer HK may include a high-k material having a dielectric constant higher than that of the silicon oxide layer. For example, the high dielectric layer HK may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0049] In some embodiments, the semiconductor device of the inventive concept may include a negative capacitance (NC) FET using a negative capacitor.For example, the high dielectric layer HK may include a ferroelectric material layer having ferroelectric characteristics, a paraelectric material layer having paraelectric characteristics, or a combination thereof.

[0050] The ferroelectric material layer may have a negative capacitance and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series (e.g., electrically connected in series) and the capacitance of each capacitor has a positive value, the total capacitance is less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series (e.g., electrically connected in series) has a negative value, the total capacitance may have a positive value and may be greater than the absolute value of each individual capacitor.

[0051] When a ferroelectric material layer having negative capacitance is connected in series (e.g., electrically connected in series) with a paraelectric material layer having positive capacitance, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series (e.g., electrically connected in series) can be increased. With the increase in the total capacitance value, a transistor including the ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0052] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide and / or lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material doped with zirconium (Zr) to form hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr) and oxygen (O).

[0053] The ferroelectric material layer may further include a dopant. For example, the dopant may include zirconium (Zr), aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca) and cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and / or tin (Sn). Depending on the type of ferroelectric material included in the ferroelectric material layer, the type of dopant (e.g., dopant) included in the ferroelectric material layer may be different.

[0054] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0055] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 to 8 atomic % (at %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0056] When the dopant is silicon (Si), the ferroelectric material layer may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50at% to 80at% zirconium.

[0057] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, silicon oxide and / or a metal oxide with a high dielectric constant (high-k metal oxide). The metal oxide included in the paraelectric material layer may include, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but is not limited thereto.

[0058] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0059] The ferroelectric material layer may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, 0.5 nm to 10 nm, but is not limited thereto. For each ferroelectric material, the critical thickness that indicates ferroelectric properties may be different, and thus the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0060] For example, the gate insulating layer GI may include one ferroelectric material layer. As another example, the gate insulating layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0061] Reference Figure 4 and FIG. 5A to FIG. 5D , the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal for adjusting the threshold voltage of the transistor. The desired threshold voltage of the transistor may be achieved by adjusting the thickness and composition of the first metal pattern. For example, the first to third portions PO1, PO2, and PO3 of the gate electrode GE may be formed by a first metal pattern as a work function metal (may include a first metal pattern as a work function metal).

[0062] The first metal pattern may include, for example, a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In addition, the first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0063] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include tungsten (W), aluminum (Al), titanium (Ti) and / or tantalum (Ta). For example, the fourth portion PO4 (e.g., the uppermost portion) of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0064] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may extend around the gate spacer GS and the first and second source / drain patterns SD1 and SD2 (e.g., cover the gate spacer GS and the first and second source / drain patterns SD1 and SD2 or overlap the gate spacer GS and the first and second source / drain patterns SD1 and SD2). The upper surface of the first interlayer insulating layer 110 may be substantially coplanar with the upper surface of the gate capping pattern GP and the upper surface of the gate spacer GS. The second interlayer insulating layer 120 covering the gate capping pattern GP (e.g., overlapping the gate capping pattern GP) may be disposed on the first interlayer insulating layer 110. The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. For example, the first to fourth interlayer insulating layers 110 to 140 may include a silicon oxide layer.

[0065] The single height cell SHC may have a first boundary BD1 and a second boundary BD2 facing each other (e.g., opposite) in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The single height cell SHC may have a third boundary BD3 and a fourth boundary BD4 facing each other (e.g., opposite) in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0066] A pair of separation structures DB facing each other in the second direction D2 may be disposed on two (opposite) sides of the single height cell SHC. Here, a pair of separation structures DB may refer to separation structures DB adjacent to each other in the second direction D2. For example, the pair of separation structures DB may be disposed on the first boundary BD1 and the second boundary BD2 of the single height cell SHC, respectively. The separation structure DB may extend parallel to the first gate electrode GE1 and the second gate electrode GE2 in the first direction D1. The pitch between the separation structure DB and the first gate electrode GE1 and the second gate electrode GE2 adjacent thereto may be the same as the first pitch.

[0067] The separation structure DB may pass through (e.g., penetrate or extend to) the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and extend (at least partially) into the first active pattern AP1 and the second active pattern AP2. The separation structure DB may pass through (e.g., penetrate or extend to) an upper portion of each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB may electrically separate the active region (e.g., the first active pattern AP1 and / or the second active pattern AP2) of the single height cell SHC from the active region of another cell adjacent thereto.

[0068] Active contacts AC electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 may be disposed to pass through (e.g., at least partially penetrate or extend to) the first interlayer insulating layer 110 and the second interlayer insulating layer 120, respectively. A pair of active contacts AC may be disposed at two (opposite) sides of the gate electrode GE, respectively. When viewed in a plan view, the active contacts AC may have a strip shape extending in the first direction D1.

[0069] The active contact AC may be a self-aligned contact. That is, the active contact AC may be formed in a self-aligned manner using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may be on at least a portion of the sidewall of the gate spacer GS (e.g., covering at least a portion of the sidewall of the gate spacer GS, or overlapping at least a portion of the sidewall of the gate spacer GS). Although not shown, the active contact AC may be on a portion of the upper surface of the gate capping pattern GP (e.g., covering a portion of the upper surface of the gate capping pattern GP, ​​or overlapping a portion of the upper surface of the gate capping pattern GP).

[0070] A metal-semiconductor compound layer SC (e.g., a silicide layer) may be disposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC may be electrically connected to the source / drain patterns SD1 and SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include titanium silicide, tantalum silicide, tungsten silicide, nickel silicon silicide, and / or cobalt silicide.

[0071] The gate contact GC may at least partially penetrate or extend into the second interlayer insulating layer 120 and the gate capping pattern GP to be connected (e.g., electrically connected) to the gate electrode GE. When viewed in a plan view, the gate contact GC may be disposed to overlap the first active region AR1 and the second active region AR2, respectively. For example, the gate contact GC may be disposed on the second active pattern AP2 (refer to Figure 5B ).

[0072] As an embodiment of the inventive concept, refer to Figure 5B , the upper portion of the active contact AC adjacent to the gate contact GC may be (at least partially) filled with the upper insulating pattern UIP. The lower surface of the upper insulating pattern UIP may be lower than the lower surface of the gate contact GC. That is, the upper surface of the active contact AC adjacent to the gate contact GC may be lowered below the lower surface of the gate contact GC (may be located below the lower surface of the gate contact GC) by the upper insulating pattern UIP. Therefore, the problem of short circuit due to contact between the gate contact GC and the active contact AC adjacent thereto can be prevented.

[0073] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM that extends around the conductive pattern FM (e.g., at least partially around the conductive pattern FM). For example, the conductive pattern FM may include aluminum, copper, tungsten, molybdenum and / or cobalt. The barrier pattern BM may be on the sidewalls and lower surface of the conductive pattern FM (e.g., covering the sidewalls and lower surface of the conductive pattern FM, or overlapping the sidewalls and lower surface of the conductive pattern FM). The barrier pattern BM may include, for example, a metal layer / metal nitride layer. The metal layer may include, for example, titanium, tantalum, tungsten, nickel, cobalt and / or platinum. The metal nitride layer may include, for example, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer and / or a platinum nitride (PtN) layer.

[0074] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. For example, the first metal layer M1 may include a first power wiring M1_R1, a second power wiring M1_R2, and a first wiring M1_I. Here, the first power wiring M1_R1, the second power wiring M1_R2, and the first wiring M1_I may be collectively referred to as wiring of the first metal layer M1. Each of the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

[0075] Specifically, the first power wiring M1_R1 and the second power wiring M1_R2 may be disposed on the third boundary BD3 and the fourth boundary BD4 of the single height cell SHC, respectively. The first power wiring M1_R1 may extend in the second direction D2 along the third boundary BD3. The second power wiring M1_R2 may extend in the second direction D2 along the fourth boundary BD4.

[0076] The first wiring M1_I of the first metal layer M1 may be disposed between the first power wiring M1_R1 and the second power wiring M1_R2. The first wiring M1_I of the first metal layer M1 may be arranged in the first direction D1 at a second pitch. The second pitch may be smaller than the first pitch. The line width of each of the first wirings M1_I (e.g., the line width in the first direction D1) may be smaller than the line width of each of the first power wiring M1_R1 and the second power wiring M1_R2 (e.g., the line width in the first direction D1).

[0077] The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed below the wiring M1_R1, M1_R2, and / or M1_I of the first metal layer M1, respectively. The active contact AC (e.g., the first active contact AC1 and the second active contact AC2) and the wiring of the first metal layer M1 may be electrically connected to each other through the first via VI1. The gate contact GC and the wiring of the first metal layer M1 may be electrically connected to each other through the first via VI1.

[0078] The wiring of the first metal layer M1 and the first via VI1 thereunder may be formed by separate processes. In some embodiments, each of the wiring of the first metal layer M1 and the first via VI1 may be formed by, for example, a single damascene process. The semiconductor device according to the present embodiment may be formed using, for example, a process less than 20 nm.

[0079] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second wirings M2_1. Each of the second wirings M2_I of the second metal layer M2 may have a linear shape or a bar shape extending in the first direction D1. That is, the second wirings M2_I may extend parallel to each other in the first direction D1.

[0080] The second metal layer M2 may further include second vias VI2 respectively disposed below the second wiring M2_1. The wiring of the first metal layer M1 and the wiring of the second metal layer M2 (e.g., the second wiring M2_1) may also be electrically connected to each other through the second vias VI2. For example, the wiring of the second metal layer M2 (e.g., the second wiring M2_1) and the second vias VI2 thereunder may be formed together through a dual damascene process.

[0081] The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include the same or different conductive materials. For example, the wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include at least one of metal materials such as aluminum, copper, tungsten, molybdenum, ruthenium and cobalt. Although not shown, a metal layer (e.g., M3, M4, M5, etc.) stacked on the fourth interlayer insulating layer 140 may be additionally provided. Each of the stacked metal layers may include wiring for layout between cells.

[0082] Reference Fig. 6A and Figure 6B , the gate electrode GE and the gate insulating layer GI will be described in more detail. Fig. 6A, the first source / drain pattern SD1 may include protrusions PRP protruding toward the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE, respectively. The protrusion PRP of the first source / drain pattern SD1 may have a protruding sidewall. For example, the protrusion PRP of the first source / drain pattern SD1 may include a protruding sidewall of the first source / drain pattern SD1. The protruding sidewall of the protrusion PRP may protrude toward a corresponding portion among the first portion PO1, the second portion PO2, and the third portion PO3.

[0083] According to an embodiment of the inventive concept, the first to third portions PO1, PO2, and PO3 may have different widths (in the second direction D2). For example, the maximum width of the first portion PO1 in the second direction D2 may be greater than the maximum width of the second portion PO2 in the second direction D2. The maximum width of the second portion PO2 in the second direction D2 may be greater than the maximum width of the third portion PO3 in the second direction D2.

[0084] The first source / drain pattern SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 on the first semiconductor layer SEL1. In an embodiment, when the first source / drain pattern SD1 is n-type (e.g., has n-type conductivity), the first semiconductor layer SEL1 may include the same semiconductor material as the second semiconductor layer SEL2, such as silicon (Si). However, the concentration of n-type impurities (e.g., phosphorus or arsenic) in the second semiconductor layer SEL2 may be greater than the concentration of n-type impurities in the first semiconductor layer SEL1.

[0085] In another embodiment, when the first source / drain pattern SD1 is p-type (e.g., has p-type conductivity), the first semiconductor layer SEL1 may include the same semiconductor material as the second semiconductor layer SEL2, e.g., silicon germanium (SiGe). However, the germanium concentration of the second semiconductor layer SEL2 may be greater than the germanium concentration of the first semiconductor layer SEL1. In addition, the concentration of p-type impurities (e.g., boron) in the second semiconductor layer SEL2 may be greater than the concentration of p-type impurities in the first semiconductor layer SEL1.

[0086] The first semiconductor layer SEL1 may be in direct contact with the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first semiconductor layer SEL1 may include the above-mentioned protrusion PRP. The inner gate spacer IGS to be described later may be on the first semiconductor layer SEL1 (e.g., covering the first semiconductor layer SEL1). For example, the inner gate spacer IGS may be in direct contact with the first semiconductor layer SEL1. The first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may be spaced apart from the first semiconductor layer SEL1 (and the protrusion PRP) by the inner spacer IS (e.g., the inner gate spacer IGS) interposed therebetween.

[0087] The inner region IRG may be disposed between a pair of first source / drain patterns SD1. The first to third portions PO1, PO2, PO3 of the gate electrode GE may be disposed in the inner region IRG, respectively. An inner spacer IS (eg, inner gate spacer IGS) and a high dielectric layer HK may be further disposed in each of the inner regions IRG.

[0088] The inner spacer IS (eg, inner gate spacer IGS) may partially fill the inner region IRG. The inner gate spacer IGS may set the inner gate space IGE. The corresponding portion of the high dielectric layer HK and the first portion PO1, the second portion PO2, and the third portion PO3 may be set in the inner gate space IGE.

[0089] Representatively, refer to Figure 6B , the second portion PO2 of the gate electrode GE and the gate insulating layer GI extending around (e.g., at least partially surrounding) the second portion PO2 will be described. The gate insulating layer GI may be interposed between the second portion PO2 and the first semiconductor pattern SP1, between the second portion PO2 and the second semiconductor pattern SP2, and between the second portion PO2 and the (adjacent) first source / drain pattern SD1.

[0090] The gate insulating layer GI may include an inner gate spacer IGS and a high dielectric layer HK. The inner gate spacer IGS may be directly on the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the first source / drain pattern SD1 (e.g., covering the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the first source / drain pattern SD1). The high dielectric layer HK may be between the inner gate spacer IGS and the second portion PO2. The high dielectric layer HK may be directly on the surface of the second portion PO2 of the gate electrode GE (e.g., covering the surface of the second portion PO2 of the gate electrode GE).

[0091] The inner gate spacer IGS may include a central portion (or referred to as a "first portion") CNT and an edge portion EG (or referred to as a "second portion") adjacent to one side of the central portion CNT in the first direction D1. In an embodiment, the central portion CNT and the first edge portion EG1 and the second edge portion EG2 on both (opposite) sides of the central portion CNT may be defined by dividing the inner gate spacer IGS into three parts having the same length in the first direction D1. For example, the first edge portion EG1 and the second edge portion EG2 may be opposite to each other relative to the central portion CNT in the first direction D1.

[0092] The center portion CNT may have a first thickness TK1 in the second direction D2. The edge portion EG (e.g., each of the first edge portion EG1 and the second edge portion EG2) may have a second thickness TK2 in the second direction D2. The first thickness TK1 may be greater than the second thickness TK2. A ratio of the second thickness TK2 to the first thickness TK1 may be in a range of 0.2 to 0.8. The thickness of the inner gate spacer IGS may decrease from the center portion CNT to the edge portion EG (e.g., each of the first edge portion EG1 and the second edge portion EG2).

[0093] The edge portion EG may include a first edge portion EG1 and a second edge portion EG2 spaced apart from the first edge portion EG1 in the first direction D1. The center portion CNT may be disposed between the first edge portion EG1 and the second edge portion EG2. The thickness of the inner gate spacer IGS (in the second direction D2) may increase from the first edge portion EG1 toward the center portion CNT and then reach a maximum value at the center portion CNT. Thereafter, the thickness of the inner gate spacer IGS (in the second direction D2) may decrease from the center portion CNT to the second edge portion EG2. That is, the thickness of the inner gate spacer IGS may vary in the first direction D1 (e.g., increase and then decrease).

[0094] The inner gate spacer IGS may include a first sidewall GSW1 adjacent to the second portion PO2 of the gate electrode GE. The first sidewall GSW1 may be a sidewall protruding toward the second portion PO2 of the gate electrode GE. The second portion PO2 of the gate electrode GE may include a recessed sidewall PSW1 corresponding to the first sidewall GSW1. The recessed sidewall PSW1 may be on (e.g., in contact with) the inner gate spacer IGS. The high dielectric layer HK may be disposed between the recessed sidewall PSW1 and the inner gate spacer IGS (e.g., the first sidewall GSW1).

[0095] The first side wall GSW1 may include a first outer surface GSWa and a second outer surface GSWb. The central portion CNT may include a first outer surface GSWa on the high dielectric layer HK (e.g., in contact with the high dielectric layer HK). The first edge portion EG1 may include a second outer surface GSWb on the high dielectric layer HK (e.g., in contact with the high dielectric layer HK). In this case, the first outer surface GSWa may be more recessed (recessed farther) toward the second portion PO2 (in the second direction D2) than the second outer surface GSWb. For example, the first outer surface GSWa may be closer to the central portion of the second portion PO2 in the second direction D2 than the second outer surface GSWb. That is, the inner gate spacer IGS may include a structure in which the central portion CNT is more recessed toward the second portion PO2 than the first edge portion EG1 (in the second direction D2). Compared with the second edge portion EG2, the central portion CNT may be more recessed toward the second portion PO2 (in the second direction D2). For example, the central portion CNT may be closer to the central portion of the second portion PO2 in the second direction D2 than the first edge portion EG1 and the second edge portion EG2.

[0096] According to the present embodiment, the thickness of the inner gate spacer IGS decreases from the central portion CNT to the edge portion EG. Therefore, when the gate electrode GE is (at least partially) filled in the inner gate space IGE, the entrance into which the metal is injected becomes wider. Therefore, the gate electrode GE can be formed uniformly without gaps. Therefore, according to the inventive concept, the thickness of the inner gate spacer IGS can be changed, thereby improving the electrical characteristics of the semiconductor device.

[0097] Reference Fig. 6A The first portion PO1, the second portion PO2 and the third portion PO3 and the inner gate spacer IGS described above can be similarly applied to Figure 5B The second active region AR2 shown in FIG. Figure 6B The first portion PO1, the second portion PO2 and the third portion PO3 and the inner gate spacer IGS described above can be similarly applied to Figure 5A The first active area AR1 is shown in FIG.

[0098] 7A to 17B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept. In detail, Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A and Fig. 12A is corresponding to Figure 4 Cross-sectional view along line AA'. Fig. 10B is corresponding to Figure 4 Cross-sectional view along line BB'. Fig. 9B , Fig. 10C , Fig. 11B and Fig. 12B is corresponding to Figure 4 Cross-sectional view along line CC'. Figure 7B , Figure 8B , Fig. 9C , Fig. 10D , Fig. 11C and Fig. 12C is corresponding to Figure 4 Cross-sectional view along line D-D'.

[0099] Reference Fig. 7A and Figure 7B , a substrate 100 including a first active region AR1 and a second active region AR2 may be provided. Active layers ACL and sacrificial layers SAL may be alternately stacked on the substrate 100. The active layer ACL may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layer SAL may include another of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0100] The sacrificial layer SAL may include a material having an etching selectivity relative to the active layer ACL. For example, the active layer ACL may include silicon (Si), and the sacrificial layer SAL may include silicon germanium (SiGe). The concentration of germanium (Ge) in each of the sacrificial layers SAL may be 10 at % to 30 at %.

[0101] Mask patterns may be respectively formed on the first active area AR1 and the second active area AR2 of the substrate 100. The mask pattern may have a linear shape or a bar shape extending in the second direction D2.

[0102] A patterning process may be performed using the mask pattern as an etching mask to form trenches TR defining first and second active patterns AP1 and AP2. The first active pattern AP1 may be formed on the first active area AR1. The second active pattern AP2 may be formed on the second active area AR2.

[0103] A stack pattern STP may be formed on each of the first and second active patterns AP1 and AP2. The stack pattern STP may include active layers ACL and sacrificial layers SAL alternately stacked on each other. The stack pattern STP may be formed together with the first and second active patterns AP1 and AP2 during a patterning process.

[0104] The device isolation layer ST may be formed to fill (e.g., at least partially fill) the trench TR. For example, an insulating layer may be formed on a surface (e.g., the entire upper surface and the side surface) of the substrate 100 to cover the first and second active patterns AP1 and AP2 and the stacked pattern STP. The insulating layer may be recessed until the stacked pattern STP is exposed to form the device isolation layer ST.

[0105] The device isolation layer ST may include an insulating material (eg, a silicon oxide layer). The stack pattern STP may be exposed on the device isolation layer ST. That is, the stack pattern STP may protrude vertically from the device isolation layer ST.

[0106] Reference Fig. 8A and Figure 8B , sacrificial patterns PP crossing the stacked patterns STP may be formed on the substrate 100. Each of the sacrificial patterns PP may be formed in a linear shape or a bar shape extending in the first direction D1. The sacrificial patterns PP may be arranged at a first pitch in the second direction D2.

[0107] For example, forming the sacrificial pattern PP may include forming a sacrificial layer on a surface (eg, the entire upper surface) of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may include, for example, polysilicon.

[0108] A pair of gate spacers GS may be formed on both (opposite) sidewalls of each of the sacrificial patterns PP. The formation of the gate spacers GS may include conformally forming a gate spacer layer on a surface (e.g., the entire upper surface) of the substrate 100, and anisotropically etching the gate spacer layer to form the gate spacers GS. In some embodiments of the inventive concept, the gate spacer GS may be a multilayer including at least two layers.

[0109] Reference Fig.9A , Fig. 9B and Fig. 9C , a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. While forming the first recess RS1 and the second recess RS2, the device isolation layer ST on both (opposite) sides of each of the first active pattern AP1 and the second active pattern AP2 may be further recessed (refer to Fig. 9B ).

[0110] For example, the stacked pattern STP on the first active pattern AP1 may be etched using the hard mask pattern MP and the gate spacer GS as an etching mask to form a first recess RS1. The first recess RS1 may be formed between a pair of sacrificial patterns PP (e.g., between adjacent sacrificial patterns PP). The formation of the first recess RS1 may include additionally performing a selective etching process on the exposed sacrificial layer SAL. Each of the sacrificial layers SAL may be indented by a selective etching process to form an indented area IDE. Therefore, the first recess RS1 may have a wavy (uneven) inner wall (e.g., a wavy (uneven) inner side wall). The second recess RS2 in the stacked pattern STP on the second active pattern AP2 may be formed in the same manner as the first recess RS1.

[0111] From the active layer ACL, first, second, and third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent first recesses RS1 may be formed, respectively. The first channel pattern CH1 may include the first, second, and third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1. The second channel pattern CH2 may include the first, second, and third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2.

[0112] Reference FIG. 10A to FIG. 10D , first source / drain patterns SD1 may be formed in the first recess RS1, respectively. For example, an epitaxial layer filling (e.g., at least partially filling) the first recess RS1 may be formed by performing a SEG process using an inner wall (e.g., an inner sidewall) of the first recess RS1 as a seed layer. The epitaxial layer may be grown using the substrate 100 and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 exposed by the first recess RS1 as seeds. For example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process, but is not limited thereto.

[0113] As an embodiment, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. While forming the first source / drain pattern SD1, (n-type) impurities (e.g., phosphorus, arsenic, and / or antimony) that allow the first source / drain pattern SD1 to have n-type (n-type conductivity) may be in-situ implanted. In some embodiments, impurities (e.g., n-type impurities) may be implanted into the first source / drain pattern SD1 after the first source / drain pattern SD1 is formed.

[0114] Second source / drain patterns SD2 may be respectively formed in the second recesses RS2 For example, the second source / drain patterns SD2 may be formed by performing a SEG process using inner walls (eg, inner sidewalls) of the second recesses RS2 as a seed layer.

[0115] As an embodiment, the second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element (e.g., Si) of the substrate 100. While forming the second source / drain pattern SD2, (p-type) impurities (e.g., boron, gallium, or indium) that allow the second source / drain pattern SD2 to have p-type (p-type conductivity) may be in-situ implanted. In some embodiments, impurities (e.g., p-type impurities) may be implanted into the second source / drain pattern SD2 after the second source / drain pattern SD2 is formed.

[0116] Reference FIG. 11A to FIG. 11C A first interlayer insulating layer 110 may be formed on the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS (e.g., the first interlayer insulating layer 110 may be formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS). For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0117] The first interlayer insulating layer 110 may be planarized until the upper surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask pattern MP may be removed. As a result, the upper surface of the first interlayer insulating layer 110 may be coplanar with the upper surface of the sacrificial pattern PP and the upper surface of the gate spacer GS.

[0118] The exposed sacrificial pattern PP may be selectively removed. By removing the sacrificial pattern PP, an outer region ORG (refer to Fig. 11C ). The removal of the sacrificial pattern PP may include, for example, wet etching using an etchant that selectively etches polysilicon.

[0119] The sacrificial layer SAL exposed by the outer region ORG may be selectively removed to form the inner region IRG (refer to Fig. 11C). For example, an etching process for selectively etching the sacrificial layer SAL may be performed to remove only the sacrificial layer SAL while leaving the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 intact. The etching process may have a high etching rate for silicon germanium having a relatively high germanium concentration. For example, the etching process may have a high etching rate for silicon germanium having a germanium concentration greater than 10 at %.

[0120] During the etching process, the sacrificial layer SAL on the first active region AR1 and the second active region AR2 (eg, the first active pattern AP1 and the second active pattern AP2) may be removed. The etching process may be wet etching. The etchant used in the etching process may quickly remove the sacrificial layer SAL having a relatively high germanium concentration.

[0121] Reference Fig. 11C , the sacrificial layer SAL may be selectively removed, and thus the first, second, and third semiconductor patterns SP1, SP2, and SP3 may remain. The first, second, and third inner regions IRG1, IRG2, and IRG3 may be formed by removing regions of the sacrificial layer SAL, respectively.

[0122] For example, a first inner region IRG1 may be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1 , a second inner region IRG2 may be formed between the first and second semiconductor patterns SP1 and SP2 , and a third inner region IRG3 may be formed between the second and third semiconductor patterns SP2 and SP3 .

[0123] Reference FIG. 11A to FIG. 11C , a gate insulating layer GI may be formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate insulating layer GI may be formed to extend around (e.g., at least partially around) each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI may be formed in each of the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3. The gate insulating layer GI may be formed in the outer region ORG.

[0124] Fig.13 , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B is a plan view for explaining a method of manufacturing an inner gate spacer IGS. Fig.14A , Fig.15A , Fig.16A and Fig.17A yes Fig.11A1 is an enlarged cross-sectional view of a region “M” of FIG. 1 , and is a view for explaining a method of manufacturing the inner gate spacer IGS.

[0125] Reference Fig.13 , Fig.14A and Fig. 14B As described above, the sacrificial pattern PP may be selectively removed to form the outer region ORG. The sacrificial layer SAL exposed by the outer region ORG may be selectively removed to form the first to third inner regions IRG1 to IRG3. Each of the first to third inner regions IRG1 to IRG3 may be disposed between a pair of (e.g., adjacent) first source / drain patterns SD1.

[0126] because Fig.9A As shown in the indented region IDE, the first source / drain pattern SD1 may include a protrusion PRP. The protrusion PRP may have a convex sidewall. The second inner region IRG2 may expose an upper surface of the first semiconductor pattern SP1 and a lower surface of the second semiconductor pattern SP2.

[0127] Reference Fig.15A and Fig. 15B , the first insulating layer IL1 may be conformally formed in the first to third inner regions IRG1 to IRG3 and the outer region ORG. The first insulating layer IL1 may be formed by a deposition process such as ALD or CVD. The first insulating layer IL1 may be formed to partially fill, rather than completely fill, the first to third inner regions IRG1 to IRG3. Therefore, an internal gate space IGE surrounded by the first insulating layer IL1 may be defined (formed) in the first to third inner regions IRG1 to IRG3. For example, the first insulating layer IL1 may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

[0128] Reference Fig.16A and Fig. 16B , the first insulating layer IL1 may be partially and selectively etched. The etching of the first insulating layer IL1 may include a wet etching process using an etching solution that selectively etches only the first insulating layer IL1. The etching process may be an isotropic etching process (isotropic etching). For example, an etchant may be provided through the internal gate space IGE to etch the first insulating layer IL1 to form an inner gate spacer IGS. An etchant may be provided through the outer region ORG to etch the first insulating layer IL1 to form an outer gate spacer OGS.

[0129] Reference Fig. 16B, after the etching process, the first insulating layer IL1 may remain on the surface of the first source / drain pattern SD1 to form the inner gate spacer IGS. Specifically, compared with the first insulating layer IL1 retained in the first edge portion EG1 and the second edge portion EG2 of the inner gate spacer IGS, relatively more of the first insulating layer IL1 may remain in the central portion CNT of the inner gate spacer IGS. That is, the thickness TK1 of the inner gate spacer IGS in the central portion CNT along the second direction D2 may be greater than the thickness TK2 of the inner gate spacer IGS in the first edge portion EG1 and the second edge portion EG2 along the second direction D2. The central portion CNT may be formed to be thicker than the first edge portion EG1 and the second edge portion EG2, and thus the inner gate spacer IGS may include a first sidewall GSW1 protruding toward the internal gate space IGE.

[0130] Reference Fig.17A and Fig. 17B , a high dielectric layer HK may be formed in the outer region ORG and the first to third inner regions IRG1 to IRG3. A high dielectric layer HK may be formed in the inner gate space IGE. The inner gate spacer IGS, the outer gate spacer OGS, and the high dielectric layer HK may form a gate insulating layer GI. In an embodiment of the inventive concept, the high dielectric layer HK may be conformally formed. The thickness of the high dielectric layer HK in the horizontal direction (e.g., the second direction D2) may be substantially the same as the thickness in the vertical direction (e.g., the third direction D3).

[0131] According to the inventive concept, the edge portion EG (e.g., the first edge portion EG1 and the second edge portion EG2) of the inner gate spacer IGS can be formed to be thinner than the central portion CNT of the inner gate spacer IGS, so a certain space (i.e., the inner gate space IGE) sufficient to fill the gate electrode GE in each of the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 can be ensured. As a process to be described later, when the gate electrode GE is filled in the inner gate space IGE, the gate electrode GE can be uniformly and stably formed without a gap. As a result, the electrical characteristics of the semiconductor device can be improved.

[0132] Reference FIG. 12A to FIG. 12C , a gate electrode GE may be formed on the gate insulating layer GI. A first portion PO1, a second portion PO2, and a third portion PO3 of the gate electrode GE may be formed in the first to third inner regions IRG1, IRG2, and IRG3, respectively, and a fourth portion PO4 of the gate electrode GE may be formed in the outer region ORG. Each of the first to third portions PO1, PO2, and PO3 may be filled Fig.17ASince the gate electrode GE is recessed, the height of the gate electrode GE can be reduced. A gate capping pattern GP can be formed on the recessed gate electrode GE.

[0133] Reference FIG. 5A to FIG. 5D , a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include, for example, a silicon oxide layer. An active contact AC electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 may be formed through (e.g., at least partially through) the second interlayer insulating layer 120 and the first interlayer insulating layer 110. A gate contact GC electrically connected to the gate electrode GE may be formed through (e.g., at least partially through) the second interlayer insulating layer 120 and the gate capping pattern GP.

[0134] The formation of each active contact AC and gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include, for example, a metal layer / metal nitride layer. The conductive pattern FM may include, for example, a low resistance metal.

[0135] Separation structures DB may be formed on first and second boundaries BD1 and BD2 of the single height cell SHC, respectively. Separation structures DB may extend from the second interlayer insulating layer 120 to the active pattern AP1 or AP2 through the gate electrode GE. Separation structures DB may include insulating materials such as silicon oxide layers or silicon nitride layers.

[0136] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0137] Hereinafter, various embodiments of the inventive concept will be described. In the embodiments of the inventive concept to be described later, the same reference numerals as previously described may be omitted. Figures 1 to 6B A detailed description of the overlapping technical features described will be given, and the differences will be described.

[0138] Fig.18 and Fig.19 According to some exemplary embodiments of the present invention, Figure 5B A cross-sectional view taken along line XX'.

[0139] Reference Fig.18, the inner gate spacer IGS may include a second sidewall GSW2 in contact with the second source / drain pattern SD2. The second sidewall GSW2 may be a concave sidewall that is recessed toward the second portion PO2. In this case, the curvature of the first sidewall GSW1 may be greater than the curvature of the second sidewall GSW2. Therefore, the thickness TK1 of the center portion CNT (in the second direction D2) may still be greater than the thickness TK2 of the first edge portion EG1 (in the second direction D2) and the thickness TK3 of the second edge portion EG2 (in the second direction D2).

[0140] Reference Fig.19 , the first side wall GSW1 of the inner gate spacer IGS may be a concave side wall recessed toward the second source / drain pattern SD2. Corresponding to the first side wall GSW1, the second portion PO2 may include a side wall PSW1 protruding toward the inner gate spacer IGS. The second side wall GSW2 of the inner gate spacer IGS may be a protruding side wall protruding toward the second source / drain pattern SD2. In this case, the curvature of the second side wall GSW2 may be greater than the curvature of the first side wall GSW1. Therefore, the thickness TK1 of the center portion CNT (in the second direction D2) may still be greater than the thickness TK2 of the first edge portion EG1 (in the second direction D2) and the thickness TK3 of the second edge portion EG2 (in the second direction D2).

[0141] The center portion CNT may include a third outer surface GSWc (of the second side wall GSW2). The first edge portion EG1 may include a fourth outer surface GSWd (of the second side wall GSW2). In this case, the third outer surface GSWc may be recessed toward the second source / drain pattern SD2 than the fourth outer surface GSWd. For example, the third outer surface GSWc may be closer to the center portion of the second source / drain pattern SD2 than the fourth outer surface GSWd in the second direction D2. That is, the inner gate spacer IGS may include a structure in which the center portion CNT is recessed toward the second source / drain pattern SD2 than the first edge portion EG1. The center portion CNT may be recessed toward the second source / drain pattern SD2 than the second edge portion EG2. For example, the center portion CNT may be closer to the center portion of the second source / drain pattern SD2 than the first edge portion EG1 and the second edge portion EG2 in the second direction D2.

[0142] In a three-dimensional field effect transistor according to the inventive concept, the gate insulating layer may include an inner gate spacer capable of preventing leakage current of the gate. When viewed in a plan view, the thickness of the inner gate spacer may decrease from the center portion to the edge portion. As a result, the inner gate electrode may be filled uniformly and stably. As a result, the electrical characteristics of the semiconductor device according to the inventive concept may be improved.

[0143] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims. Therefore, in the case where the scope of the inventive concept is indicated by the appended claims, the exemplary embodiments of the inventive concept should be considered in all aspects as illustrative and not restrictive.

Claims

1. A semiconductor device, comprising: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode extending along a first direction on the channel pattern, wherein the gate electrode comprises an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern among the plurality of semiconductor patterns; and an inner gate spacer between the inner gate electrode and the source / drain pattern, wherein the inner gate spacer includes a central portion and an edge portion adjacent to a first side of the central portion in a first direction, wherein the central portion has a first thickness in the second direction, wherein the edge portion has a second thickness in the second direction, wherein the first thickness is greater than the second thickness, wherein the first semiconductor pattern and the second semiconductor pattern are adjacent to each other in the third direction, Wherein, the first direction is parallel to the upper surface of the substrate, The second direction is parallel to the upper surface of the substrate and intersects with the first direction, and The third direction is perpendicular to the upper surface of the substrate.

2. The semiconductor device according to claim 1, wherein A ratio of the second thickness to the first thickness is 0.2 to 0.

8.

3. The semiconductor device according to claim 1, wherein The thickness of the inner gate spacer in the second direction decreases from the center portion to the edge portion.

4. The semiconductor device according to claim 1, further comprising: A high-k dielectric layer is between the inner gate spacer and the inner gate electrode.

5. The semiconductor device according to claim 1, wherein The inner gate spacer includes a first sidewall protruding toward the inner gate electrode.

6. The semiconductor device according to claim 5, wherein: The inner gate spacer includes a second sidewall contacting the source / drain pattern and recessed toward the inner gate electrode.

7. The semiconductor device according to claim 6, wherein: The curvature of the first side wall is greater than the curvature of the second side wall.

8. The semiconductor device according to claim 1, wherein The inner gate electrode includes a recessed sidewall on the inner gate spacer.

9. The semiconductor device according to claim 1, wherein: The inner gate spacer includes a first outer sidewall contacting the source / drain pattern and protruding toward the source / drain pattern, and a second outer sidewall being on the inner gate electrode and recessed toward the source / drain pattern.

10. A semiconductor device, comprising: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode extending along a first direction on the channel pattern, wherein the gate electrode comprises an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern among the plurality of semiconductor patterns; an inner gate spacer between the inner gate electrode and the source / drain pattern; and inner high-k dielectric layer, between the inner gate electrode and the inner gate spacer, wherein the inner gate spacer includes a first portion and a second portion adjacent to a first side of the first portion in a first direction, wherein the first portion includes a first outer surface in contact with the inner high-k dielectric layer, wherein the second portion includes a second outer surface in contact with the inner high-k dielectric layer, wherein the first outer surface is closer to a central portion of the inner gate electrode than the second outer surface, and The first direction is parallel to the upper surface of the substrate.

11. The semiconductor device according to claim 10, wherein The inner gate spacer has a thickness in the second direction, wherein the second direction is parallel to the upper surface of the substrate and intersects with the first direction, and Therein, the thickness increases in a first direction and then decreases.

12. The semiconductor device according to claim 10, wherein: A first thickness of the first portion in the second direction is greater than a second thickness of the second portion in the second direction, and The second direction is parallel to the upper surface of the substrate and intersects with the first direction.

13. The semiconductor device according to claim 10, wherein: The inner gate spacer includes a first sidewall protruding toward the inner gate electrode.

14. The semiconductor device according to claim 13, wherein: The inner gate spacer further includes: a second sidewall contacting the source / drain pattern and recessed toward the inner gate electrode, and The curvature of the first side wall is greater than the curvature of the second side wall.

15. The semiconductor device according to claim 10, wherein The inner gate electrode includes a recessed sidewall contacting the inner high-k dielectric layer.

16. A semiconductor device, comprising: a substrate, including the active region; active pattern, on the active area; a device isolation layer, adjacent to the active pattern; a channel pattern and a source / drain pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns spaced apart from each other and stacked in the second direction, and wherein the source / drain pattern is electrically connected to the plurality of semiconductor patterns; a gate electrode extending along a first direction on the channel pattern, wherein the gate electrode comprises an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern among the plurality of semiconductor patterns; a gate insulating layer between the first semiconductor pattern, the second semiconductor pattern and the inner gate electrode, wherein the gate insulating layer comprises an inner gate spacer between the inner gate electrode and the source / drain pattern; an inner high-k dielectric layer between the inner gate electrode and the inner gate spacer; and Gate spacers, on the sidewalls of the gate electrode, The first semiconductor pattern and the second semiconductor pattern are adjacent to each other in the second direction. wherein the inner gate spacer includes a first edge portion, a second edge portion spaced apart from the first edge portion in a first direction, and a center portion between the first edge portion and the second edge portion, wherein the thickness of the inner gate spacer in the third direction increases from the first edge portion toward the central portion, reaches a maximum value at the central portion, and decreases from the central portion toward the second edge portion, The second direction is perpendicular to the upper surface of the substrate. wherein the first direction is parallel to the upper surface of the substrate, and The third direction is parallel to the upper surface of the substrate and intersects with the first direction.

17. The semiconductor device according to claim 16, wherein: The inner gate spacer includes a first sidewall protruding toward the inner gate electrode.

18. The semiconductor device according to claim 17, wherein: The inner gate spacer further includes a second sidewall in contact with the source / drain pattern, The second side wall is recessed toward the inner gate electrode, and The curvature of the first side wall is greater than the curvature of the second side wall.

19. The semiconductor device according to claim 16, wherein: The inner gate electrode includes a recessed sidewall contacting the inner high-k dielectric layer.

20. The semiconductor device according to claim 16, wherein The inner gate spacer includes a first outer sidewall protruding toward the source / drain pattern, and a second outer sidewall contacting the inner high-k dielectric layer and recessed toward the source / drain pattern.

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