CMOS image sensor with vertical transmission buried gate structure and preparation method

Abstract

The invention provides a CMOS image sensor with a vertical transmission buried gate structure and a preparation method thereof, and the method comprises the steps: preparing the vertical transmission buried gate structure in a pixel, and preparing a first floating diffusion region in a first conductive type doped region surrounded by the vertical transmission buried gate structure to serve as a source-drain doped region of the vertical transmission buried gate structure; the vertical projection of the vertical transmission buried gate structure and the vertical projection of the reset gate structure are located in the region of the photodiode, so that the area ratio of the photodiode in the whole pixel can be increased, and the requirement of an image sensor for FWC is met in a limited space. And overlapping between the transmission gate and the floating diffusion region can be reduced through the vertical transmission buried gate structure, so that the problem of GIDL is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of image sensors and relates to a CMOS image sensor with a vertical transmission buried gate structure and a preparation method thereof. Background Art

[0002] Image sensors are functional devices that use the photoelectric conversion function of photoelectric devices to convert the light image on the photosensitive surface into an electrical signal that is proportional to the light image. Among them, image sensors can include two types of CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charged Coupled Device) image sensors based on the principles they adopt. CCD image sensors and CMOS image sensors have their own advantages in different application scenarios, but with the rapid development and continuous improvement of CMOS image sensor manufacturing processes and technologies, CMOS image sensors have occupied an increasingly important position.

[0003] Among them, CMOS image sensors have been widely used in people's daily lives, such as digital cameras, mobile phones, medical devices, automobiles and other applications. With the development of technology, the integration of CMOS image sensors is getting higher and higher, and the photosensitive pixels are getting smaller and smaller. How to meet the full-well capacity (FWC) requirements of the photodiode (PD) as the photosensitive area in the pixel of the CMOS image sensor has become an urgent problem to be solved in the current CMOS image sensor.

[0004] Therefore, it is necessary to provide a CMOS image sensor with a vertical transfer buried gate structure and a preparation method thereof. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a CMOS image sensor with a vertical transfer buried gate structure and a preparation method thereof, so as to solve the problem that the CMOS image sensor in the prior art is difficult to meet the demand for full sink capacity.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a CMOS image sensor with a vertical transmission buried gate structure, the CMOS image sensor comprising:

[0007] substrate;

[0008] A photodiode, the photodiode comprising a first conductive type doped region located on one side of the substrate and a second conductive type doped region located on the other side of the substrate;

[0009] A vertical transmission buried gate structure, wherein the vertical transmission buried gate structure is located in the first conductive type doping region, and a vertical projection of the vertical transmission buried gate structure is located in the region of the photodiode;

[0010] a reset gate structure, wherein the reset gate structure is located on the first conductive type doping region, and a vertical projection of the reset gate structure is located within the region of the photodiode;

[0011] A floating diffusion region, wherein the floating diffusion region is located in the first conductive type doping region, and the floating diffusion region at least includes a first floating diffusion region, and the first floating diffusion region is located in the first conductive type doping region surrounded by the vertical transmission buried gate structure to serve as a source and drain doping region of the vertical transmission buried gate structure.

[0012] Optionally, the floating diffusion region also includes a second floating diffusion region, which is located between the vertical transfer buried gate structure and the reset gate structure to serve as a source and drain doping region of the reset gate structure, wherein the first floating diffusion region and the second floating diffusion region are spaced apart and electrically connected.

[0013] Optionally, a cross-sectional shape of the vertical transmission buried gate structure along the lateral direction includes a circle, an ellipse or a square.

[0014] Optionally, a readout circuit gate structure is also provided on the first conductive type doping region, and the vertical projection of the readout circuit gate structure is located within the region of the photodiode; the readout circuit gate structure includes one or a combination of a source follower gate structure and a row selection gate structure.

[0015] Optionally, a second conductivity type doped protrusion is arranged in the second conductivity type doped region and is arranged corresponding to the first floating diffusion region.

[0016] Optionally, in the vertical direction, a distance between an edge of the gate conductive layer in the vertical transmission buried gate structure and an edge of the first floating diffusion region is 0-80 nm.

[0017] The present invention also provides a method for preparing a CMOS image sensor with a vertical transmission buried gate structure, comprising the following steps:

[0018] providing a substrate;

[0019] Performing ion implantation to form a photodiode in the substrate, wherein the photodiode includes a first conductive type doping region located on one side of the substrate and a second conductive type doping region located on the other side;

[0020] Patterning the first conductive type doped region to form a trench in the first conductive type doped region;

[0021] forming a vertical transmission buried gate structure in the trench, and forming a reset gate structure on the first conductive type doping region, wherein the vertical transmission buried gate structure and the reset gate structure have their vertical projections both located within the region of the photodiode;

[0022] Ion implantation is performed to form a floating diffusion region in the first conductive type doping region, wherein the floating diffusion region includes at least a first floating diffusion region, and the first floating diffusion region is located in the first conductive type doping region surrounded by the vertical transmission buried gate structure to serve as a source and drain doping region of the vertical transmission buried gate structure.

[0023] Optionally, the floating diffusion region formed also includes a second floating diffusion region, which is located between the vertical transfer buried gate structure and the reset gate structure to serve as a source and drain doping region of the reset gate structure, wherein the first floating diffusion region and the second floating diffusion region are spaced apart and electrically connected.

[0024] Optionally, the cross-sectional morphology of the formed vertical transmission buried gate structure along the lateral direction includes a circle, an ellipse or a square.

[0025] Optionally, in the vertical direction, a distance between an edge of the gate conductive layer in the formed vertical transmission buried gate structure and an edge of the first floating diffusion region is 0-80 nm.

[0026] As described above, the CMOS image sensor with a vertical transmission buried gate structure and the preparation method of the present invention prepare a vertical transmission buried gate structure (VTG) in a pixel (Pixel), and prepare a first floating diffusion region in a first conductive type doping region (FD) surrounded by the vertical transmission buried gate structure to serve as a source-drain doping region (SD) of the vertical transmission buried gate structure, so that the vertical projections of the vertical transmission buried gate structure and the reset gate structure (RST) are both located within the region of the photodiode (PD), thereby expanding the area ratio of the photodiode in the entire pixel to meet the image sensor's FWC (full well capacity) requirements within a limited space, and the vertical transmission buried gate structure can also reduce the overlap between the transmission gate and the floating diffusion region, thereby solving the problem of GIDL (gate induced leakage). BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a process flow chart of manufacturing a CMOS image sensor with a vertical transfer buried gate structure according to an embodiment of the present invention.

[0028] Figure 2 It is a schematic diagram showing the structure after a photodiode is formed in a substrate in an embodiment of the present invention.

[0029] Figure 3 It is a schematic diagram of the structure after the grooves are formed in an embodiment of the present invention.

[0030] Figure 4 Shown is a schematic diagram of the structure after the groove is filled in an embodiment of the present invention.

[0031] Figure 5 It is a schematic diagram of the structure after forming the reset gate structure and the readout circuit gate structure in the embodiment of the present invention.

[0032] Figure 6 It is a schematic diagram of the structure after forming a vertical transmission buried gate structure in an embodiment of the present invention.

[0033] Figure 7 It is a schematic diagram of the structure after forming a gate protection layer in an embodiment of the present invention.

[0034] Figure 8 It is a schematic diagram of the structure after the floating diffusion region and the source-drain doping region are formed in an embodiment of the present invention.

[0035] Fig. 9 Shown is a schematic diagram of the structure after metal interconnects are formed in an embodiment of the present invention.

[0036] Fig.10 Shown is a schematic diagram of a top-view structure of a pixel of a CMOS image sensor with a vertical transfer buried gate structure formed in an embodiment of the present invention.

[0037] Figure 11a to Figure 11d Shown is a schematic top view of the vertical transmission buried gate structure and the floating diffusion region formed in an embodiment of the present invention.

[0038] Component number description

[0039] 101 first conductive type doping region

[0040] 1011 Groove

[0041] 102 second conductivity type doping region

[0042] 1021 second conductive type doped protrusion

[0043] 201 Gate dielectric layer

[0044] 202 gate conductive layer

[0045] 301 Reset gate structure

[0046] 302 Source Follower Gate Structure

[0047] 303 Row selection gate structure

[0048] 304 Vertical Transfer Buried Gate Structure

[0049] 400 Grid protection layer

[0050] 401 First protection layer

[0051] 402 Second grid protection layer

[0052] 501 First floating diffusion region

[0053] 502 Second floating diffusion region

[0054] 503, 504, 505, 506 Source and drain doping regions

[0055] 600 Passivation layer

[0056] 700 Metal Interconnects

[0057] A Photodiode Area DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0060] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0061] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] See also Figure 1 This embodiment provides a method for preparing a CMOS image sensor with a vertical transmission buried gate structure, comprising the following steps:

[0063] S1: providing a substrate;

[0064] S2: performing ion implantation to form a photodiode in the substrate, wherein the photodiode includes a first conductive type doping region located on one side of the substrate and a second conductive type doping region located on the other side;

[0065] S3: patterning the first conductive type doped region to form a trench in the first conductive type doped region;

[0066] S4: forming a vertical transmission buried gate structure in the trench, and forming a reset gate structure on the first conductive type doping region, wherein the vertical transmission buried gate structure and the reset gate structure have their vertical projections both located within the region of the photodiode;

[0067] S5: Perform ion implantation to form a floating diffusion region in the first conductive type doping region, wherein the floating diffusion region at least includes a first floating diffusion region, and the first floating diffusion region is located in the first conductive type doping region surrounded by the vertical transmission buried gate structure to serve as a source and drain doping region of the vertical transmission buried gate structure.

[0068] See also Figure 2 to Figure 10 FIG. 1 is a schematic diagram of the structure of each step in preparing the CMOS image sensor in this embodiment, wherein: Figure 2 to Figure 9 for Fig.10 Schematic diagram of the cross-sectional structure obtained along C-C'.

[0069] The following combination Figures 1 to 10 The preparation and structure of the CMOS image sensor are described.

[0070] First, see Figure 1 and Figure 2 , execute step S1, provide a substrate (not shown), wherein the substrate can be a P-type silicon substrate, but is not limited to this, and the material, size and thickness of the substrate are not overly limited here.

[0071] Next, see Figure 1 and Figure 2 , execute step S2, perform ion implantation, and form a photodiode (PD) in the substrate, wherein the photodiode includes a first conductive type doping region 101 located on one side of the substrate and a second conductive type doping region 102 located on the other side.

[0072] Specifically, by performing ion implantation in the substrate, a doping region having a first conductivity type, such as a P-type doping region or an N-type doping region, and a doping region of a second conductivity type corresponding to the first conductivity type, such as an N-type doping region or a P-type doping region, can be formed in the substrate, so that a PN junction can be formed in the substrate to constitute the photodiode, and the received optical signal is converted into an electrical signal by the photodiode. In this embodiment, the first conductivity type doping region 101 is a P-type doping region, and the corresponding second conductivity type doping region 102 is an N-type doping region, but it is not limited to this. The first conductivity type doping region 101 can also be an N-type doping region, and the corresponding second conductivity type doping region 102 is a P-type doping region, which is not excessively limited here.

[0073] In order to improve the FWC (full well capacity) performance of the photodiode in a limited space, in this embodiment, the area ratio of the photodiode in the entire pixel is enlarged, such as Fig.10 In the figure, A indicates the area of ​​the photodiode in a single pixel. In the lateral direction, the area ratio of the photodiode to the entire pixel unit is preferably 80% to 90%, such as 80%, 85%, 90%, etc., so as to maximize the effective area of ​​the photodiode to improve FWC.

[0074] As an example, Figure 2 The second conductive type doped region 102 preferably has a second conductive type doped protrusion 1021 so as to be subsequently used as a source-drain doped region (SD) of the vertical transmission buried gate structure 304 (VTG).

[0075] Next, see Figure 1 and Figure 3 , perform step S3 to pattern the first conductive type doping region 101 and form a trench 1011 in the first conductive type doping region 101 .

[0076] Specifically, the groove 1011 may be formed by photolithography and etching steps, wherein the cross-sectional shape of the groove 1011 along the transverse direction may include, for example, a circle, an ellipse or a square, etc. Fig.10 In this embodiment, a closed square ring buried gate structure is taken as an example, so that the trench 1011 adopts a closed square ring morphology, but is not limited to this. Figure 11a to Figure 11c In another embodiment, the cross-sectional shape of the vertical transmission buried gate structure 304 along the transverse direction may also include a closed rectangular ring, a circular ring, an elliptical ring, etc.

[0077] Further, such as Fig.11dThe cross-sectional morphology of the vertical transmission buried gate structure 304 along the horizontal direction may also include a non-closed morphology, such as a non-closed circle, ellipse or square, etc. The morphology of the groove 1011 is not overly limited here.

[0078] The formed groove 1011 is arranged corresponding to the position of the second conductive type doped protrusion 1021, so that the second conductive type doped protrusion 1021 can be used as a source-drain doping region of the vertical transmission buried gate structure 304 prepared subsequently.

[0079] Next, see Figure 1 and Figures 4 to 6 , forming the vertical transmission buried gate structure 304 in the groove 1011, and forming a reset gate structure 301 (RST) on the first conductive type doping region 101, and the vertical projections of the vertical transmission buried gate structure 304 and the reset gate structure 301 are both located within the region of the photodiode.

[0080] Specifically, a gate dielectric layer 201 is formed first, such as a silicon oxide gate dielectric layer formed by ISSG or other processes, but the formation process and material of the gate dielectric layer 201 are not limited thereto, and then a gate conductive layer 202 is formed by a deposition process, such as a polysilicon gate conductive layer, and then the gate conductive layer 202 and the gate dielectric layer 201 are patterned by photolithography, etching and other processes to form the vertical transmission buried gate structure 304 and the reset gate structure 301.

[0081] For example, see Fig.10 , Figure 5 and Figure 6 In this embodiment, a readout circuit gate structure is also provided on the first conductive type doping region 101, and the vertical projection of the readout circuit gate structure is located in the region A of the photodiode; wherein the readout circuit gate structure includes a source follower gate structure 302 and a row selection gate structure 303, but is not limited thereto. In another embodiment, the readout circuit gate structure may also only include the source follower gate structure 302 or the row selection gate structure 303 as needed, which is not overly limited here.

[0082] Next, see Figure 1 , Figure 7 and Figure 8 , execute step S5, perform ion implantation, and form a floating diffusion region (FD) in the first conductive type doping region 101, wherein the floating diffusion region at least includes a first floating diffusion region 501, and the first floating diffusion region 501 is located in the first conductive type doping region 101 surrounded by the vertical transmission buried gate structure 304 to serve as another source and drain doping region of the vertical transmission buried gate structure 304.

[0083] Specifically, Figure 8 When ion implantation is used to form the first floating diffusion region 501, the first floating diffusion region 501 is arranged corresponding to the second conductive type doped protrusion 1021 to constitute two source-drain doped regions of the vertical transmission buried gate structure 304, thereby forming a vertical buried gate transmission transistor with a vertical channel in combination.

[0084] In this embodiment, in the vertical direction, the distance between the edge of the gate conductive layer 202 in the vertical transmission buried gate structure 304 and the edge of the first floating diffusion region 501 is preferably 0 to 80 nm, such as 0 nm, 20 nm, 50 nm, 80 nm, etc., that is, the first floating diffusion region 501 and the vertical transmission buried gate structure 304 preferably have no overlapping area in the vertical direction to reduce the problem of GIDL (gate induced leakage).

[0085] Wherein, while forming the first floating diffusion region 501 , source and drain doping regions 503 , 504 , 505 , and 506 of corresponding transistors are formed in the first conductive type doping region 101 .

[0086] In this embodiment, Fig.10 Since the cross-sectional morphology of the vertical transmission buried gate structure 304 along the transverse direction is a closed square ring, the floating diffusion region further includes a second floating diffusion region 502, and the second floating diffusion region 502 is located between the vertical transmission buried gate structure 304 and the reset gate structure 301 to serve as a source-drain doping region of the reset gate structure 301, wherein the first floating diffusion region 501 and the second floating diffusion region 502 are arranged at intervals and electrically connected, such as Fig. 9 The first floating diffusion region 501 and the second floating diffusion region 502 may be electrically connected via a metal interconnection 700 that is fabricated subsequently.

[0087] In another embodiment, if Fig.11d When the vertical transmission buried gate structure 304 is a non-enclosed morphology with an opening, the first floating diffusion region 501 and the second floating diffusion region 502 can be regarded as an interconnected whole.

[0088] See also Figure 7 Before ion implantation, the step of forming a gate protection layer 400 is also included. In this embodiment, the gate protection layer 400 adopts a stacked gate protection structure composed of a first gate protection layer 401 such as a silicon oxide layer and a second gate protection layer 402 such as a silicon nitride layer, but the structure and material of the gate protection layer 400 are not limited thereto.

[0089] See also Fig. 9After the floating diffusion region and the source-drain doped regions 503, 504, 505, 506 are prepared, a passivation layer 600 covering the transistor can be formed, and the metal interconnection 700 for electrical connection can be prepared by photolithography, etching, deposition, grinding, etc. The preparation process, material, size, etc. of the passivation layer 600 and the metal interconnection 700 are not limited here.

[0090] In which, other functional elements (not shown) of the CMOS image sensor, such as filters, microlenses, etc., can be prepared later according to the needs of the device structure to prepare a back-illuminated (BSI) CMOS image sensor or a front-illuminated (FSI) CMOS image sensor, which is not limited here. In this embodiment, the CMOS image sensor is preferably a back-illuminated (BSI) CMOS image sensor with high light efficiency.

[0091] See also Fig. 9 and Fig.10 This embodiment further provides a CMOS image sensor with a vertical transmission buried gate structure, the CMOS image sensor comprising:

[0092] a substrate (not shown);

[0093] A photodiode, the photodiode comprising a first conductive type doping region 101 located on one side of the substrate and a second conductive type doping region 102 located on the other side of the substrate;

[0094] A vertical transmission buried gate structure 304, wherein the vertical transmission buried gate structure 304 is located in the first conductive type doping region 101, and a vertical projection of the vertical transmission buried gate structure 304 is located in region A of the photodiode;

[0095] a reset gate structure 301, wherein the reset gate structure 301 is located on the first conductive type doping region 101, and a vertical projection of the reset gate structure 301 is located within a region A of the photodiode;

[0096] A floating diffusion region, wherein the floating diffusion region is located in the first conductive type doping region 101, and the floating diffusion region at least includes a first floating diffusion region 501, and the first floating diffusion region 501 is located in the first conductive type doping region 101 surrounded by the vertical transmission buried gate structure 304 to serve as a source and drain doping region of the vertical transmission buried gate structure 304.

[0097] As an example, the floating diffusion region also includes a second floating diffusion region 502, which is located between the vertical transfer buried gate structure 304 and the reset gate structure 301 to serve as a source and drain doping region of the reset gate structure 301, wherein the first floating diffusion region 501 and the second floating diffusion region 502 are spaced apart and electrically connected.

[0098] As an example, the cross-sectional shape of the vertical transfer buried gate structure 304 along the lateral direction includes a circle, an ellipse or a square.

[0099] As an example, a readout circuit gate structure is also provided on the first conductive type doping region 101 , and the vertical projection of the readout circuit gate structure is located within region A of the photodiode; the readout circuit gate structure includes one or a combination of a source follower gate structure 302 and a row selection gate structure 303 .

[0100] As an example, a second conductivity type doped protrusion 1021 is disposed in the second conductivity type doped region 102 and is disposed corresponding to the first floating diffusion region 501 .

[0101] As an example, in the vertical direction, the distance between the edge of the gate conductive layer in the vertical transmission buried gate structure 304 and the edge of the first floating diffusion region 501 is 0-80 nm.

[0102] Specifically, in this embodiment, the CMOS image sensor is manufactured by the above process, but is not limited thereto, so the material, structure and manufacturing process of the CMOS image sensor are not described in detail herein.

[0103] In summary, the CMOS image sensor with a vertical transmission buried gate structure and the preparation method of the present invention prepare a vertical transmission buried gate structure in a pixel, and prepare a first floating diffusion region in a first conductive type doping region surrounded by the vertical transmission buried gate structure to serve as a source-drain doping region of the vertical transmission buried gate structure, so that the vertical projections of the vertical transmission buried gate structure and the reset gate structure are both located within the region of the photodiode, thereby expanding the area ratio of the photodiode in the entire pixel to meet the image sensor's requirements for FWC within a limited space, and through the vertical transmission buried gate structure, the overlap between the transmission gate and the floating diffusion region can also be reduced, thereby solving the problem of GIDL.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A CMOS image sensor with a vertical transfer buried gate structure, characterized in that: The CMOS image sensor comprises: substrate; A photodiode, the photodiode comprising a first conductive type doped region located on one side of the substrate and a second conductive type doped region located on the other side of the substrate; A vertical transmission buried gate structure, wherein the vertical transmission buried gate structure is located in the first conductive type doping region, and a vertical projection of the vertical transmission buried gate structure is located in the region of the photodiode; a reset gate structure, wherein the reset gate structure is located on the first conductive type doping region, and a vertical projection of the reset gate structure is located within the region of the photodiode; A floating diffusion region, wherein the floating diffusion region is located in the first conductive type doping region, and the floating diffusion region at least includes a first floating diffusion region, and the first floating diffusion region is located in the first conductive type doping region surrounded by the vertical transmission buried gate structure to serve as a source and drain doping region of the vertical transmission buried gate structure.

2. The CMOS image sensor with a vertical transfer buried gate structure according to claim 1, characterized in that: The floating diffusion region also includes a second floating diffusion region, which is located between the vertical transfer buried gate structure and the reset gate structure to serve as a source and drain doping region of the reset gate structure, wherein the first floating diffusion region and the second floating diffusion region are spaced apart and electrically connected.

3. The CMOS image sensor with a vertical transfer buried gate structure according to claim 1, characterized in that: The cross-sectional shape of the vertical transmission buried gate structure along the transverse direction includes a circle, an ellipse or a square.

4. The CMOS image sensor with a vertical transfer buried gate structure according to claim 1, characterized in that: A readout circuit gate structure is also provided on the first conductive type doping region, and the vertical projection of the readout circuit gate structure is located within the region of the photodiode; the readout circuit gate structure includes one or a combination of a source follower gate structure and a row selection gate structure.

5. The CMOS image sensor with a vertical transfer buried gate structure according to claim 1, characterized in that: The second conductive type doped region is provided with a second conductive type doped protrusion corresponding to the first floating diffusion region.

6. The CMOS image sensor with a vertical transfer buried gate structure according to claim 1, characterized in that: In the vertical direction, the distance between the edge of the gate conductive layer in the vertical transmission buried gate structure and the edge of the first floating diffusion region is 0-80 nm.

7. A method for preparing a CMOS image sensor having a vertical transmission buried gate structure, characterized in that: The following steps are involved: providing a substrate; Performing ion implantation to form a photodiode in the substrate, wherein the photodiode includes a first conductive type doping region located on one side of the substrate and a second conductive type doping region located on the other side; Patterning the first conductive type doped region to form a trench in the first conductive type doped region; forming a vertical transmission buried gate structure in the trench, and forming a reset gate structure on the first conductive type doping region, wherein the vertical transmission buried gate structure and the reset gate structure have their vertical projections both located within the region of the photodiode; Ion implantation is performed to form a floating diffusion region in the first conductive type doping region, wherein the floating diffusion region includes at least a first floating diffusion region, and the first floating diffusion region is located in the first conductive type doping region surrounded by the vertical transmission buried gate structure to serve as a source and drain doping region of the vertical transmission buried gate structure.

8. The method for preparing a CMOS image sensor with a vertical transfer buried gate structure according to claim 7, characterized in that: The floating diffusion region formed also includes a second floating diffusion region, which is located between the vertical transfer buried gate structure and the reset gate structure to serve as a source and drain doping region of the reset gate structure, wherein the first floating diffusion region and the second floating diffusion region are spaced apart and electrically connected.

9. The method for preparing a CMOS image sensor with a vertical transfer buried gate structure according to claim 7, characterized in that: The cross-sectional shape of the formed vertical transmission buried gate structure along the lateral direction includes a circle, an ellipse or a square.

10. The method for preparing a CMOS image sensor with a vertical transfer buried gate structure according to claim 7, characterized in that: In the vertical direction, the distance between the edge of the gate conductive layer in the formed vertical transmission buried gate structure and the edge of the first floating diffusion region is 0-80 nm.

Images