Image sensor

Abstract

An image sensor is provided. The image sensor includes: a substrate including a plurality of pixel regions, in which the substrate includes a first surface and a second surface opposite to each other; and a device isolation pattern extending from the first surface and into the substrate, in which the device isolation pattern is located between the plurality of pixel regions, in which the device isolation pattern has an intermediate region and an intersection region and includes a first device isolation portion and a second device isolation portion, the intermediate region includes a first dielectric pattern, a conductive pad, and a second dielectric pattern, where the first dielectric pattern extends from the first device isolation portion and toward the second device isolation portion, and where the first device isolation portion includes the conductive pad and the second dielectric pattern.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0083429 filed in the Korean Intellectual Property Office on June 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to an image sensor and a method for manufacturing the same, and more particularly, to a complementary metal oxide semiconductor (CMOS) image sensor and a method for manufacturing the same. Background Art

[0003] Image sensor is a semiconductor device that converts optical images into electrical signals. The latest developments in the computer and communication industries have led to a strong demand for high-performance image sensors in various consumer electronic devices (such as digital cameras, video cameras, PCS (personal communication systems), gaming devices, security cameras, medical miniature cameras, etc.). Image sensors can be classified into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type. CMOS type image sensors can be abbreviated as CIS (CMOS image sensor). CIS has multiple pixels arranged in two dimensions. Each pixel includes a photodiode. The photodiode converts incident light into an electrical signal. Multiple pixels are defined by a deep device isolation pattern disposed therebetween. Summary of the invention

[0004] Some embodiments of the present disclosure provide an image sensor configured to minimize or suppress the occurrence of dark current and a method of manufacturing the same.

[0005] Some embodiments of the present disclosure provide a highly integrated image sensor and a method for manufacturing the same.

[0006] According to some embodiments of the present disclosure, an image sensor may include: a substrate including a plurality of pixel regions, wherein the substrate includes a first surface and a second surface opposite to each other; and a device isolation pattern extending from the first surface and into the substrate, wherein the device isolation pattern is located between the plurality of pixel regions, wherein the device isolation pattern includes an intermediate region, an intersection region, a first device isolation portion, and a second device isolation portion, wherein the intermediate region includes a first dielectric pattern, a conductive pad contacting a sidewall of the first dielectric pattern, and a second dielectric pattern contacting a sidewall of the conductive pad and a top surface of the conductive pad, wherein the first dielectric pattern extends from the first device isolation portion and toward the second device isolation portion, and wherein the first device isolation portion includes the conductive pad and the second dielectric pattern.

[0007] According to some embodiments of the present disclosure, an image sensor may include: a substrate including a plurality of pixel regions, wherein the substrate includes a first surface and a second surface opposite to each other; and a device isolation pattern extending from the first surface and into the substrate, wherein the device isolation pattern is located between the plurality of pixel regions, wherein the device isolation pattern includes an intermediate region, a cross region, a first device isolation portion, and a second device isolation portion, wherein the intermediate region includes an intermediate dielectric pattern, a conductive pad contacting the intermediate dielectric pattern, a first dielectric pattern contacting the conductive pad, and a second dielectric pattern located on the first dielectric pattern, wherein the first dielectric pattern extends from the first device isolation portion and toward the second device isolation portion, wherein the first device isolation portion includes the intermediate dielectric pattern, the conductive pad, and the second dielectric pattern, and wherein the first dielectric pattern includes a step shape located on the first device isolation portion.

[0008] According to some embodiments of the present disclosure, an image sensor may include: a substrate including a plurality of pixel regions, wherein the substrate includes a first surface and a second surface opposite to each other; a device isolation pattern extending from the first surface and into the substrate, wherein the device isolation pattern is located between the plurality of pixel regions; and a shallow device isolation pattern adjacent to the second surface of the substrate, wherein the device isolation pattern includes an intermediate region, an intersection region, a first device isolation portion, and a second device isolation portion, wherein in the intermediate region: a width of the first device isolation portion is smaller than a width of the shallow device isolation pattern, a width of the second device isolation portion is smaller than a width of the first device isolation portion, the first device isolation portion includes at least one dielectric material and at least one conductive material, and the second device isolation portion includes at least one dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A simplified block diagram of an image sensor according to some embodiments of the present disclosure is shown.

[0010] Figure 2 A circuit diagram of an active pixel sensor array of an image sensor according to some embodiments of the present disclosure is shown.

[0011] Figure 3 A plan view of an image sensor according to some embodiments of the present disclosure is shown.

[0012] Figure 4A Shown along Figure 3 A cross-sectional view taken along line AA'.

[0013] Figure 4B Shows the display Figure 4A An enlarged view of part M1.

[0014] Figure 4C Shown along Figure 3A cross-sectional view taken along line BB'.

[0015] Figure 4D Shows Figure 4C An enlarged view of part M2.

[0016] Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of a method of manufacturing an image sensor taken along line AA′ and line BB′.

[0017] Fig.15A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'.

[0018] Fig. 15B Shows the display Fig.15A Magnified view of part of M1a.

[0019] Fig. 15C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'.

[0020] Fig.15D Shows the display Fig. 15C Magnified view of a portion of M2a.

[0021] Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A and Fig.25B According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of a method of manufacturing an image sensor taken along line AA′ and line BB′.

[0022] Fig.26A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'.

[0023] Fig.26B Show Display Fig.26A Magnified view of part M1b.

[0024] Fig.26C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'.

[0025] Fig.26D Shows the display Fig.26C Magnified view of part M2b.

[0026] Fig.27A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'.

[0027] Fig.27B Shows the display Fig.27A Magnified view of part M1c.

[0028] Fig.27C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'.

[0029] Fig.27D Shows the display Fig.27C Magnified view of a portion of M2c.

[0030] Fig.28A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'.

[0031] Fig.28B Shows the display Fig.28A Magnified view of part M1d.

[0032] Fig.28C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'.

[0033] Fig.28D Shows the display Fig.28C A magnified view of part M2d.

[0034] Fig.29A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'.

[0035] Fig.29B Shows the display Fig.29A A magnified view of a portion of M1e.

[0036] Fig.29C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'.

[0037] Fig.29D Shows the display Fig.29C A magnified view of a portion of M2e.

[0038] Fig. 30A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'.

[0039] Fig. 30B Shows the display Fig. 30A A magnified view of part of M1f.

[0040] Fig. 30C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'.

[0041] Fig.30D Shows the display Fig. 30C A magnified view of part of M2f. DETAILED DESCRIPTION

[0042] In order to make the present disclosure clear, parts not related to the description will be omitted, and the same elements or equivalents are represented by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, plates, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively shown for better understanding and ease of description.

[0043] It will be understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, it can be directly on the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms such as "under...", "under...", "under...", "above...", "on", etc. can be used here to describe the relationship between an element or feature and another (other) element or feature as shown in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "under" or "under" other elements or features will then be oriented to "above" the other elements or features. Therefore, the term "below" can cover both above and below. The device can be oriented in addition (rotated 90 degrees or in other orientations), and the spatial relative descriptors used here can be interpreted accordingly.

[0044] In addition, unless explicitly described to the contrary, the word "include" and variations such as "comprise" or "contain" will be understood to imply the inclusion of the stated elements but not to exclude any other elements. As used herein, the phrase "at least one of A, B, and C" refers to the logic (A "or" B "or" C) using a non-exclusive logic "or", and should not be interpreted as meaning "at least one A, at least one B, and at least one C". As used herein, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)", and "the (described)" are intended to also include plural forms. It will also be understood that when the terms "include", "include" and / or variations thereof are used herein, the stated features, steps, operations, elements, and / or components are indicated, but the presence or addition of one or more other features, steps, operations, elements, components, and / or their groups is not excluded. The term "and / or" includes any combination and all combinations of one or more of the relevant listed items. The term "connected" may be used herein to refer to a physical connection and / or an electrical connection, and may refer to a direct or indirect physical connection and / or electrical connection. The phrase "element A surrounds element B" may refer to element A at least partially surrounding element B. The phrase "element A is filled with element B" or "element B fills element A" means that element B is at least partially located in the space defined by element A. As used herein, "element A is at the same level (same level) as element B" means that at least one surface of element A is coplanar with at least one surface of element B.

[0045] Some embodiments of the present disclosure will now be described in detail below with reference to the accompanying drawings.

[0046] Figure 1A simplified block diagram showing an image sensor according to some embodiments of the present disclosure is shown.

[0047] Reference Figure 1 , the image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog-to-digital converter (ADC) 1007 and an input / output (I / O) buffer 1008.

[0048] The active pixel sensor array 1001 may include a plurality of two-dimensionally arranged unit pixels, each unit pixel being configured to convert an optical signal into an electrical signal. The active pixel sensor array 1001 may be driven by a plurality of driving signals (such as a pixel selection signal, a reset signal, and a charge transfer signal) from a row driver 1003. The correlated double sampler 1006 may receive the converted electrical signal.

[0049] The row driver 1003 may provide a number of driving signals for driving a number of unit pixels to the active pixel sensor array 1001 according to the decoding result obtained from the row decoder 1002. When the unit pixels are arranged in a matrix shape, the driving signals may be provided for each row.

[0050] The timing generator 1005 may provide timing signals and control signals to the row decoder 1002 and the column decoder 1004 .

[0051] The correlated double sampler 1006 may receive the electrical signal generated by the active pixel sensor array 1001, and may hold and sample the received electrical signal. The correlated double sampler 1006 may perform a double sampling operation to sample a specific noise level and a signal level of the electrical signal, and may then output a difference level corresponding to the difference between the noise level and the signal level.

[0052] The analog-to-digital converter 1007 may convert an analog signal corresponding to the difference level received from the correlated double sampler 1006 into a digital signal and then output the converted digital signal.

[0053] The input / output buffer 1008 may latch the digital signal and then sequentially output the latched digital signal to an image signal processing unit (not shown) in response to a decoding result obtained from the column decoder 1004 .

[0054] Figure 2 A circuit diagram showing an active pixel sensor array of an image sensor according to some embodiments of the present disclosure is shown.

[0055] Reference Figure 1 and Figure 2, the active pixel sensor array 1001 may include a plurality of pixel regions PX, and the pixel regions PX may be arranged in a matrix shape. Each pixel region PX may include a transfer transistor TX. Each pixel region PX may also include logic transistors RX, SX, and DX. The logic transistors RX, SX, and DX may include a reset transistor RX, a selection transistor SX, and a source follower transistor DX. The transfer transistor TX may include a transfer gate TG. Each pixel region PX may also include a photoelectric conversion element PD and a floating diffusion region FD. The logic transistors RX, SX, and DX may be shared by a plurality of pixel regions PX.

[0056] The photoelectric conversion element PD can generate and accumulate photoelectric charges in proportion to the amount of external incident light. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX can transfer the charge generated in the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD can accumulate and store the charge generated and transferred from the photoelectric conversion element PD. The source follower transistor DX can be controlled by the amount of photoelectric charge accumulated in the floating diffusion region FD.

[0057] The reset transistor RX including the reset gate RG may periodically reset the charge accumulated in the floating diffusion region FD. The reset transistor RX may have a drain electrode connected to the floating diffusion region FD and a power supply voltage V DD When the reset transistor RX is turned on, the floating diffusion region FD can be supplied with a power supply voltage V connected to the source electrode of the reset transistor RX. DD Therefore, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion area FD may be exhausted (discharged), and thus the floating diffusion area FD may be reset.

[0058] The source follower transistor DX including the source follower gate SF may be used as a source follower buffer amplifier. The source follower transistor DX may amplify the change in the potential of the floating diffusion region FD and may output the amplified potential to the output line V OUT .

[0059] The selection transistor SX including the selection gate SEL can select each row of pixel regions PX to be read out. When the selection transistor SX is turned on, the power supply voltage V DD can be applied to the drain electrode of the source follower transistor DX.

[0060] Figure 3 A plan view of an image sensor according to some embodiments of the present disclosure is shown. Figure 4A Shown along Figure 3 A cross-sectional view taken along line AA'. Figure 4B Shows the display Figure 4A An enlarged view of part M1. Figure 4C Shown along Figure 3 A cross-sectional view taken along line BB'. Figure 4D Shows the display Figure 4C An enlarged view of part M2.

[0061] Reference Figure 3 and FIG. 4A to FIG. 4D , a substrate 100 may be provided. For example, the substrate 100 may be a single crystal silicon wafer, a silicon epitaxial layer, or a silicon on insulator (SOI) substrate. The substrate 100 may be doped with impurities to have a first conductivity type (e.g., p-type). The substrate 100 may have a first surface 100A and a second surface 100B opposite to each other. The first surface 100A may be spaced apart from the second surface 100B in a first direction D1, and the second surface 100B may be spaced apart from the first surface 100B in a second direction D2. The first direction D1 and the second direction D2 may be opposite to each other.

[0062] The substrate 100 may include a plurality of pixel regions PX. For example, when viewed in a plane, the substrate 100 may include a first pixel region PX1, a second pixel region PX2, a third pixel region PX3, and a fourth pixel region PX4 arranged in sequence in a clockwise direction. The first pixel region PX1 and the second pixel region PX2 may be adjacent to each other in a third direction D3 or arranged side by side along the third direction D3, and the third pixel region PX3 and the fourth pixel region PX4 may also be adjacent to each other in the third direction D3. The third direction D3 may be parallel to the second surface 100B of the substrate 100. The second pixel region PX2 and the third pixel region PX3 may be adjacent to each other in a fourth direction D4, and the first pixel region PX1 and the fourth pixel region PX4 may also be adjacent to each other in the fourth direction D4. The fourth direction D4 may be parallel to the second surface 100B of the substrate 100 and may intersect with the third direction D3.

[0063] The device isolation pattern PI may be located in the substrate 100. The device isolation pattern PI may confine the pixel regions PX and separate them from each other. The device isolation pattern PI may penetrate or extend through the substrate 100 between the pixel regions PX along the second direction D2.

[0064] The device isolation pattern PI may be disposed in an isolation trench ITR extending from the second surface 100B toward the first surface 100A. The isolation trench ITR may include a deep trench DTR and an extension trench ETR. When viewed in a plane, the device isolation pattern PI may have a mesh shape in which lines extending in the third direction D3 intersect lines extending in the fourth direction D4.

[0065] The device isolation pattern PI may extend from the second surface 100B and into the substrate 100, and may be interposed between the plurality of pixel regions PX. The device isolation pattern PI may include or have an intermediate region IR and a crossing region CR.

[0066] The intermediate region IR may be defined as a region indicating between two adjacent pixel regions PX. The intersection region CR may be defined as a region indicating between four adjacent pixel regions PX. The intermediate region IR and the intersection region CR may be continuous with each other.

[0067] The device isolation pattern PI may include a first device isolation portion DTI and a second device isolation portion ETI. The first device isolation portion DTI and the second device isolation portion ETI may have different widths from each other.

[0068] In the intermediate region IR, the device isolation pattern PI may include a first dielectric pattern 22 , a conductive pad 14 on the first dielectric pattern 22 , a second dielectric pattern 12 on the conductive pad 14 , and a buried dielectric pattern 16 .

[0069] In the crossing region CR, the device isolation pattern PI may include a first dielectric pattern 22 , a buried conductive pattern 18 under the first dielectric pattern 22 , a conductive pad 14 contacting the buried conductive pattern 18 , a second dielectric pattern 12 contacting the conductive pad 14 , and a buried dielectric pattern 16 .

[0070] In the intermediate region IR, the first dielectric pattern 22 may extend from the first device isolation portion DTI to the second device isolation portion ETI. The conductive pad 14 and the second dielectric pattern 12 may be disposed in the first device isolation portion DTI.

[0071] In the crossing region CR, the first dielectric pattern 22 may be disposed in the second device isolation portion ETI, and may extend from the second device isolation portion ETI to the first device isolation portion DTI. The buried conductive pattern 18 may be disposed in the first device isolation portion DTI.

[0072] The first dielectric pattern 22 or the second dielectric pattern 12 may include a dielectric such as SiO 2 、Al 2 O 3 The conductive pad 14 may include Si. The conductive pad 14 may include Si doped with B or P. The conductive pad 14 may include a metal such as one or more of Cu, W, Al, and Ti. The buried dielectric pattern 16 may include silicon oxide or silicon nitride.

[0073] The doped region DR may be further disposed on or in the substrate 100. The doped region DR may be adjacent to the first device isolation portion DTI. The doped region DR may include boron. In an embodiment, the doped region DR may be in contact with the first device isolation portion DTI. In this case, the doped region DR may be doped with boron to at least partially surround the second dielectric pattern 12.

[0074] In an embodiment, the doped region DR may contact the first and second device isolation portions DTI and ETI. In this case, the doped region DR may be doped with boron to at least partially surround the first and second dielectric patterns 22 and 12.

[0075] The photoelectric conversion element PD may be disposed in each pixel region PX. The photoelectric conversion element PD may be doped with impurities having a second conductivity type (e.g., n-type) opposite to the first conductivity type. The impurities doped into the photoelectric conversion element PD and the impurities having the first conductivity type in the substrate 100 may constitute a PN junction, thereby providing a photodiode.

[0076] The shallow device isolation trench STR may be recessed from the second surface 100B of the substrate 100 into the substrate 100 , and the shallow device isolation portion STI may be located in the shallow device isolation trench STR. The shallow device isolation portion STI may be disposed adjacent to the second surface 100B of the substrate 100 .

[0077] The shallow device isolation portion STI may include a first isolation portion 32 and a second isolation portion 34. The first isolation portion 32 may conformally cover the inner wall of the shallow device isolation trench STR or overlap with the inner wall of the shallow device isolation trench STR. The second isolation portion 34 may be located in the shallow device isolation trench STR. The first isolation portion 32 and the second isolation portion 34 may independently include at least one selected from silicon oxide (SiO), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN) and any combination thereof. The device isolation pattern PI may extend through the shallow device isolation portion STI in the second direction D2. In the pixel region PX, the shallow device isolation portion STI may limit an active area (not shown) adjacent to the second surface 100B of the substrate 100. It may be directed to Figure 2 The transistors TX, RX, DX and SX are provided with active regions.

[0078] The buried dielectric pattern 16 may extend into the shallow device isolation portion STI. The second dielectric pattern 12 may be disposed between the buried dielectric pattern 16 and the shallow device isolation portion STI. In an embodiment, the first dielectric pattern 22 and the second dielectric pattern 12 may be disposed between the buried dielectric pattern 16 and the shallow device isolation portion STI.

[0079] In each pixel region PX, the transmission gate TG may be disposed on the second surface 100B of the substrate 100. For example, a portion of the transmission gate TG may be buried in the substrate 100. The transmission gate TG may be a vertical type. Alternatively, the transmission gate TG may be a planar type that is flat on the second surface 100B of the substrate 100.

[0080] The gate dielectric pattern GI may be interposed between the transfer gate TG and the substrate 100. A floating diffusion region (not shown) may be disposed in the substrate 100 while being adjacent to one side of the transfer gate TG. For example, the floating diffusion region (not shown) may be implanted with impurities having a second conductivity type.

[0081] According to some embodiments of the present disclosure, light may enter the substrate 100 through the first surface 100A of the substrate 100. At the PN junction, electron-hole pairs may be generated by the incident light. These generated electrons may move toward the photoelectric conversion element PD. When a voltage is applied to the transmission gate TG, the electrons may move to the floating diffusion region (not shown).

[0082] The interlayer dielectric layer ILD may be disposed on the second surface 100B of the substrate 100 and cover the second surface 100B of the substrate 100 or overlap the second surface 100B of the substrate 100. The interlayer dielectric layer ILD may be a multilayer structure including at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a porous low-k dielectric layer, and a combination thereof. The interlayer dielectric layer ILD may have a wiring 60 disposed therein. A floating diffusion region (not shown) may be connected to the wiring 60.

[0083] The fixed charge layer 42 may be disposed on the first surface 100A of the substrate 100 and cover the first surface 100A of the substrate 100 or overlap with the first surface 100A of the substrate 100. The fixed charge layer 42 may be a single layer structure or a multilayer structure including at least one selected from a metal oxide layer having an oxygen ratio less than a stoichiometric ratio, a metal fluoride layer having a fluorine ratio less than a stoichiometric ratio, and a combination thereof. Therefore, the fixed charge layer may have a negative fixed charge. For example, the fixed charge layer 42 may include a metal oxide layer or a metal fluoride layer including at least one selected from hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), lanthanide elements, and any combination thereof. The fixed charge layer 42 may suppress or reduce dark current and white spots.

[0084] The protective layer 44 may be stacked on the fixed charge layer 42. The protective layer 44 may include at least one selected from silicon oxide (SiO), silicon oxycarbide (SiOC), silicon nitride (SiN), and any combination thereof. The protective layer 44 may function as an anti-reflection layer and a planarization layer.

[0085] The light shielding pattern 48 may be disposed on the protective layer 44. The low refraction pattern 50 may be disposed on the light shielding pattern 48 accordingly. The light shielding pattern 48 and the low refraction pattern 50 may overlap with the device isolation pattern PI and may have a grid shape when viewed in a plane. The light shielding pattern 48 may include, for example, titanium. The low refraction pattern 50 may have the same thickness and include an organic material. The low refraction pattern 50 may have a refractive index less than the refractive index of the color filters CF1 and CF2 discussed below. The light shielding pattern 48 and the low refraction pattern 50 may prevent crosstalk between adjacent pixel regions PX.

[0086] Color filters CF1 and CF2 may be disposed between the low refraction patterns 50. Color filters CF1 and CF2 may each have one of blue, green, and red. Optionally, color filters CF1 and CF2 may have different colors such as cyan, magenta, or yellow. In the image sensor according to the present embodiment, color filters CF1 and CF2 may be arranged in a Bayer pattern. Optionally, color filters CF1 and CF2 may be arranged in a 2×2 Tetra pattern, a 3×3 Nona pattern, and a 4×4 Hexadeca pattern.

[0087] The micro lenses ML may be disposed on the color filters CF1 and CF2. The micro lenses ML may have edges that are in contact and connected to each other.

[0088] Return to reference Figure 4B , the device isolation pattern PI and the shallow device isolation portion STI are located on the intermediate region IR.

[0089] The second surface 100B of the substrate 100 may be located at the same level as that of the bottom surface 12BS of the second dielectric pattern 12. The first device isolation portion DTI may be defined between the level of the bottom surface 12BS of the second dielectric pattern 12 and the level of the top surface 12TS of the second dielectric pattern 12. The second device isolation portion ETI may be defined between the level of the top surface 12TS of the second dielectric pattern 12 and the level of the top surface 22TS of the first dielectric pattern 22.

[0090] The second dielectric pattern 12 may be interposed between the buried dielectric pattern 16 and the shallow device isolation portion STI.

[0091] The first dielectric pattern 22 may have a width IRWE1 smaller than a width IRW12 of the second dielectric pattern 12. The conductive pad 14 may have a width IRW14 larger than the width IRWE1 of the first dielectric pattern 22. The width IRW14 of the conductive pad 14 may be smaller than a width IRW12 of the second dielectric pattern 12.

[0092] The buried dielectric pattern 16 may have a top surface 16TS having a level higher than that of a top surface 32TS of a first isolation portion 32 included in the shallow device isolation portion STI (e.g., a distance between the top surface 16TS and the second surface 100B of the substrate 100 in the first direction D1 is greater than a distance between the top surface 32TS and the second surface 100B of the substrate 100 in the first direction D1).

[0093] In the intermediate region 11R, a sidewall of the first dielectric pattern 22 may be in contact with the conductive pad 14. The second dielectric pattern 12 may be in contact with the top surface and the sidewall of the conductive pad 14. The top surface 16TS of the buried dielectric pattern 16 may be in contact with the conductive pad 14 and the first dielectric pattern 22. The conductive pad 14 may have a top surface 14TS located at a level lower than that of the top surface 12TS of the second dielectric pattern 12 (e.g., the distance of the top surface 12TS from the second surface 100B of the substrate 100 in the first direction D1 is greater than the distance of the top surface 14TS from the second surface 100B of the substrate 100 in the first direction D1).

[0094] In the intermediate region IR, the first device isolation part DTI may be provided with one or more dielectric materials and one or more conductive materials, and the second device isolation part ETI may be provided with one or more dielectric materials or one or more dielectric materials and one or more conductive materials.

[0095] Return to reference Figure 4D , the device isolation pattern PI and the shallow device isolation portion STI are located on the crossing region CR.

[0096] The second surface 100B of the substrate 100 may be located at the same level as that of the bottom surface 12BS of the second dielectric pattern 12. The first device isolation portion DTI may be defined between the level of the bottom surface 12BS of the second dielectric pattern 12 and the level of the top surface 12TS of the second dielectric pattern 12. The second device isolation portion ETI may be defined between the level of the top surface 12TS of the second dielectric pattern 12 and the level of the top surface 22TS of the first dielectric pattern 22.

[0097] The buried conductive pattern 18 may have a bottom surface 18BS coplanar with the bottom surface 14BS of the conductive pad 14. The bottom surface 18BS of the buried conductive pattern 18 may be located at the same level as the bottom surface 14BS of the conductive pad 14 (e.g., the bottom surface 18BS and the bottom surface 14BS are the same distance from the second surface 100B of the substrate 100).

[0098] The conductive pad 14 may be disposed between the second dielectric pattern 12 and the buried conductive pattern 18. A top surface 14TS of the conductive pad 14 may be in contact with the second dielectric pattern 12. The conductive pad 14 may have a sidewall in contact with the second dielectric pattern 12, the buried conductive pattern 18, and the first dielectric pattern 22. A top surface 14TS of the conductive pad 14 may be located at a level lower than that of a top surface 12TS of the second dielectric pattern 12. A top surface 14TS of the conductive pad 14 may be located at a level higher than that of a top surface 18TS of the buried conductive pattern 18. A top surface 12TS of the second dielectric pattern 12 may be located at a level higher than that of a top surface 18TS of the buried conductive pattern 18. A top surface 18TS of the buried conductive pattern 18 may be in contact with the first dielectric pattern 22.

[0099] The first dielectric pattern 22 may have a width CRWE1 that is the same as a width CRW18 of the buried conductive pattern 18. The second dielectric pattern 12 may have a width CRW12 greater than a width CRW14 of the conductive liner 14. The width CRW14 of the conductive liner 14 may be greater than a width CRW18 of the buried conductive pattern 18.

[0100] FIG. 5A to FIG. 14B According to some embodiments of the present disclosure, Figure 3 A cross-sectional view showing a method of manufacturing an image sensor taken along lines AA' and BB'. FIG. 5A to FIG. 14B , the following will discuss the manufacturing reference Figures 3 to 4D The method of the image sensor discussed in the present invention will be omitted for the sake of brevity of description.

[0101] Reference Figure 5A and Figure 5B , a substrate 100 may be prepared. A shallow device isolation trench STR recessed from the second surface 100B of the substrate 100 into the substrate 100 may be formed. The formation of the shallow device isolation trench STR may include forming a mask pattern on the second surface 100B of the substrate 100, and etching the substrate 100 using the mask pattern as an etching mask. Through the etching process, a portion of the mask pattern may or may not remain.

[0102] The first isolation layer 32p may be formed to cover the inner wall of the shallow device isolation trench STR and the second surface 100B of the substrate 100 or to overlap with the inner wall of the shallow device isolation trench STR and the second surface 100B of the substrate 100. The first isolation layer 32p may be a mask pattern retained after an etching process for forming the shallow device isolation trench STR. The second isolation layer 34p may be formed in an unoccupied portion of the device isolation trench STR and formed to cover the second surface 100B of the substrate 100 or to overlap with the second surface 100B of the substrate 100. The first isolation layer 32p and the second isolation layer 34p may independently include at least one selected from silicon oxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbon nitride (SiCON), and any combination thereof.

[0103] Reference Fig. 6A and Figure 6B , the first trench TR1 may be formed to extend into the first isolation layer 32p, the second isolation layer 34p, and a portion of the substrate 100. When viewed in a plane, the first trench TR1 may have a mesh shape in which lines extending in the third direction D3 intersect lines extending in the fourth direction D4. The first trench TR1 may expose the interior of the substrate 100. The first trench TR1 may limit the pixel area (see Figure 3 The middle area (see Figure 3 The width of the first trench TR1 on the IR) may be smaller than the cross region (see Figure 3 The width of the first trench TR1 on CR).

[0104] The doping region DR may be formed along the inner wall of the first trench TR1. The doping region DR may be formed by, for example, doping boron along the inner wall of the first trench TR1.

[0105] Reference Fig. 7A and Figure 7B , a dielectric liner layer 12p may be formed on the second surface 100B of the substrate 100. The dielectric liner layer 12p may conformally cover the inner wall of the first trench TR1 or overlap with the inner wall of the first trench TR1. The dielectric liner layer 12p may be formed in a portion of the first trench TR1. The dielectric liner layer 12p may include silicon oxide (SiO). For example, the dielectric liner layer 12p may also include materials other than silicon oxide, such as silicon nitride (SiN), silicon carbonitride (SiCN) or silicon oxycarbon nitride (SiCON). The dielectric liner layer 12p may be a single-layer structure or a multilayer structure including two or more layers. The second trench TR2 may be formed while the dielectric liner layer 12p conformally covers the inner wall of the first trench TR1 or overlaps with the inner wall of the first trench TR1.

[0106] Reference Fig. 8A and Figure 8B , the preliminary conductive liner 14p may conformally cover or overlap the inner wall of the second trench TR2. The preliminary conductive liner 14p may conformally cover or overlap the bottom surface of the second trench TR2, and may also conformally cover or overlap the sidewall of the second trench TR2. The preliminary conductive liner 14p on the sidewall of the second trench TR2 may extend to the same level as the top surface of the conductive liner 14 to be formed below. The formation of the preliminary conductive liner 14p may form a third trench TR3.

[0107] Reference Fig. 9A and Fig. 9B , an extension trench ETR may be formed to extend into the preliminary conductive pad 14p, the dielectric liner layer 12p, and a portion of the substrate 100. The extension trench ETR may expose the preliminary conductive pad 14p, the dielectric liner layer 12p, and a portion of the substrate 100. A portion of the preliminary conductive pad 14p may be removed while forming the extension trench ETR. A conductive pad 14 may be formed.

[0108] Reference Fig. 10A and Fig. 10B , a preliminary first dielectric pattern 22p may be formed in a portion of the second trench TR2, the extension trench ETR, and the third trench TR3. The preliminary first dielectric pattern 22p may be located in the extension trench ETR and the third trench TR3. The preliminary first dielectric pattern 22p may be conformally located on the second trench TR2, and thus a preliminary dielectric pattern trench 22TR may be formed.

[0109] Reference Fig.11A and Fig. 11B , an upper portion of the preliminary first dielectric pattern 22p may be removed.

[0110] In the intermediate region IR, removing the upper portion of the preliminary first dielectric pattern 22p may include removing the preliminary first dielectric pattern 22p until the top surface of the conductive pad 14 is exposed. In the intersection region CR, removing the upper portion of the preliminary first dielectric pattern 22p may include removing the preliminary first dielectric pattern 22p to expose a boundary between a buried conductive pattern 18 and a first dielectric pattern 22 to be formed below, the boundary between the buried conductive pattern 18 and the first dielectric pattern 22 being defined between the top surface and the bottom surface of the conductive pad 14.

[0111] Removing the upper portion of the preliminary first dielectric pattern 22p may include performing an etch-back process on the preliminary first dielectric pattern 22p. The first dielectric pattern 22 may include the preliminary first dielectric pattern 22p remaining after the removal process. Removing the upper portion of the preliminary first dielectric pattern 22p may expose a portion of the sidewall of the second trench TR2 on the intermediate region IR, and may also expose a portion of the sidewall of the third trench TR3 and the second trench TR2 on the intersection region CR.

[0112] Reference Fig. 12A and Fig. 12B , a preliminary buried conductive pattern 18p may be formed on the first dielectric pattern 22 and the conductive liner 14. The preliminary buried conductive pattern 18p may be formed to conformally cover or overlap the exposed portion of the second trench TR2.

[0113] In the intermediate region IR, the preliminary buried conductive pattern 18p may be formed to cover or overlap the top surface 14T of the conductive liner 14 and the top surface 22T of the first dielectric pattern 22. In the intersection region CR, the preliminary buried conductive pattern 18p may be formed in the third trench TR3 and formed to conformally cover or overlap the exposed portion of the second trench TR2. In the intersection region CR, the preliminary buried conductive pattern 18p may be formed to cover or overlap the first dielectric pattern 22.

[0114] Reference Fig.13A and Fig. 13B , the preliminary buried conductive pattern 18p may be removed in the intermediate region IR, and the upper portion of the preliminary buried conductive pattern 18p may be removed in the intersection region CR. Removing the upper portion of the preliminary buried conductive pattern 18p in the intersection region CR may include removing the preliminary buried conductive pattern 18p until the top surface 14T of the conductive liner 14 is exposed. The preliminary buried conductive pattern 18p may be formed (e.g., retained) in the third trench TR3 (e.g., the third trench TR3 in the intersection region CR). After the removal process, a portion of the second trench TR2 may be exposed. The buried conductive pattern 18 may include the preliminary buried conductive pattern 18p retained after the removal process.

[0115] A preliminary buried dielectric pattern 16p may be formed on the first dielectric pattern 22 and the conductive liner 14 on the intermediate region IR and on the conductive liner 14 and the buried conductive pattern 18 in the intersection region CR. In the intersection region CR, the preliminary buried dielectric pattern 16p may be formed to cover or overlap the top surface 18T of the buried conductive pattern 18 and the top surface 14T of the conductive liner 14. The preliminary buried dielectric pattern 16p may be formed to conformally cover or overlap the exposed portion of the second trench TR2. According to some embodiments, an annealing process may be additionally performed after forming the preliminary buried dielectric pattern 16p.

[0116] Reference Fig.14A and Fig. 14B , a planarization process may be performed. The planarization process may include a chemical mechanical polishing (CMP) process. The planarization process may remove the upper portion of the dielectric liner layer 12p, the upper portion of the preliminary buried dielectric pattern 16p, and the upper portion of the second isolation layer 34p, thereby forming the second dielectric pattern 12, the buried dielectric pattern 16, and the second isolation portion 34. The planarization process may expose the top surface 34T of the second isolation portion 34, the top surface 12T of the second dielectric pattern 12, and the top surface 16T of the buried dielectric pattern 16. In addition, during the planarization process, a portion of the first isolation layer 32p may be exposed and may be used as a polishing stop layer. The retained first isolation layer 32p may constitute the first isolation portion 32, and the planarization process may expose the top surface 32T of the first isolation portion 32.

[0117] Fig.15A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the display image sensor taken along line AA′. Fig. 15B Shows the display Fig.15A Magnified view of part of M1a. Fig. 15C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'. Fig.15D Shows the display Fig. 15C For the sake of brevity, repeated description will be omitted.

[0118] Reference Figure 3 , Fig.15A and Fig. 15B , showing in detail the device isolation pattern PIa and the shallow device isolation portion STI on the intermediate region IR.

[0119] The device isolation pattern PIa may be disposed on the intermediate region IR. In the intermediate region IR, the device isolation pattern PIa may include an intermediate dielectric pattern 24a, a conductive pad 14a on the intermediate dielectric pattern 24a, a first dielectric pattern 22a on the conductive pad 14a, a second dielectric pattern 12a on the first dielectric pattern 22a, and a buried dielectric pattern 16a in contact with the first dielectric pattern 22a.

[0120] The shallow device isolation portion STI may include a first isolation portion 32 and a second isolation portion 34. The first isolation portion 32 and the second isolation portion 34 may be in contact with the second dielectric pattern 12a.

[0121] The device isolation pattern PIa may be formed to fill the extension trench ETR and the deep trench DTR. The device isolation pattern PIa may include a first device isolation portion DTI and a second device isolation portion ETI.

[0122] The first device isolation portion DTI may be defined between the level of the bottom surface 12BS of the second dielectric pattern 12a and the level of the top surface 12aTS of the second dielectric pattern 12a. The second device isolation portion ETI may be defined between the level of the top surface 12aTS of the second dielectric pattern 12a and the level of the top surface 22aTS of the first dielectric pattern 22a.

[0123] In the first device isolation portion DTI, the device isolation pattern PIa may include an intermediate dielectric pattern 24a, a conductive pad 14a, a first dielectric pattern 22a, a second dielectric pattern 12a, and a buried dielectric pattern 16a. In the second device isolation portion ETI, the device isolation pattern PIa may include a first dielectric pattern 22a.

[0124] The first dielectric pattern 22 a may extend from the first device isolation portion DTI to the second device isolation portion ETI.

[0125] A portion of the substrate 100 adjacent to the deep trench DTR may be doped to form a first doped region DR1. The first doped region DR1 may be doped, for example, with boron. A portion of the substrate 100 adjacent to the extension trench ETR may be doped to form a second doped region DR2. The second doped region DR2 may be doped, for example, with boron. The first doped region DR1 may contact the second dielectric pattern 12a. The second doped region DR2 may contact the first dielectric pattern 22a.

[0126] The conductive pad 14 a may have a top surface 14 aTS having a level lower than that of the top surface 12 aTS of the second dielectric pattern 12 a .

[0127] The first dielectric pattern 22a may have a first dielectric step difference 22STP. The first dielectric step difference 22STP may have, for example, a step shape. The first dielectric step difference 22STP may be defined to indicate, for example, a step shape between the top surface 14aTS of the conductive pad 14a and the top surface 12aTS of the second dielectric pattern 12a.

[0128] The conductive liner 14 a may at least partially surround the side surface 24 aSS and the top surface 24 aTS of the intermediate dielectric pattern 24 a .

[0129] The conductive pad 14a may include a flat conductive portion 14aF and an extended conductive portion 14aE. The flat conductive portion 14aF may be parallel to the substrate 100. The flat conductive portion 14aF may extend in a third direction D3 parallel to the extension direction of the substrate 100. The extended conductive portion 14aE may extend in a first direction D1 intersecting the extension direction of the substrate 100. The extended conductive portion 14aE may extend from the flat conductive portion 14aF toward the second surface 100B of the substrate 100. The top surface 24aTS of the intermediate dielectric pattern 24a may contact the flat conductive portion 14aF. The side surface 24aSS of the intermediate dielectric pattern 24a may contact the extended conductive portion 14aE. The extended conductive portion 14aE may be disposed between the intermediate dielectric pattern 24a and the first dielectric pattern 22a.

[0130] Reference Figure 3 , Fig. 15C and Fig.15D , showing in detail the device isolation pattern PIa and the shallow device isolation portion STI on the crossing region CR.

[0131] On the intersection region CR, a device isolation pattern PIa may be provided. In the intersection region CR, the device isolation pattern PIa may include a buried conductive pattern 18a, a conductive pad 14a on the buried conductive pattern 18a, a first dielectric pattern 22a on the conductive pad 14a, a second dielectric pattern 12a on the first dielectric pattern 22a, and a buried dielectric pattern 16a in contact with the first dielectric pattern 22a.

[0132] The shallow device isolation portion STI may be disposed adjacent to the second surface 100B of the substrate 100. The shallow device isolation portion STI may include a first isolation portion 32 and a second isolation portion 34. The first isolation portion 32 and the second isolation portion 34 may contact the second dielectric pattern 12a.

[0133] The device isolation pattern PIa may be formed to fill the extension trench ETR and the deep trench DTR. The device isolation pattern PIa may include a first device isolation portion DTI and a second device isolation portion ETI.

[0134] The first device isolation portion DTI may be defined between the level of the bottom surface 12BS of the second dielectric pattern 12a and the level of the top surface 12aTS of the second dielectric pattern 12a. The second device isolation portion ETI may be defined between the level of the top surface 12aTS of the second dielectric pattern 12a and the level of the top surface 22aTS of the first dielectric pattern 22a.

[0135] In the first device isolation portion DTI, the device isolation pattern PIa may include a buried conductive pattern 18a, a conductive pad 14a, a first dielectric pattern 22a, a second dielectric pattern 12a, and a buried dielectric pattern 16a. In the second device isolation portion ETI, the device isolation pattern PIa may include a first dielectric pattern 22a, a conductive pad 14a, and a buried conductive pattern 18a.

[0136] The first dielectric pattern 22 a , the conductive liner 14 a , and the buried conductive pattern 18 a may extend from the first device isolation portion DTI to the second device isolation portion ETI.

[0137] The width EW18a of the buried conductive pattern 18a in the second device isolation portion ETI may be smaller than the width DW18a of the buried conductive pattern 18a in the first device isolation portion DTI.

[0138] The conductive pad 14a may have a pad outer surface 14aOS in contact with the first dielectric pattern 22a. The pad outer surface 14aOS may include a first pad outer surface 14aOS1, a second pad outer surface 14aOS2 in contact with (or in contact with) the first pad outer surface 14aOS1, and a third pad outer surface 14aOS3 in contact with (or in contact with) the second pad outer surface 14aOS2. The first pad outer surface 14aOS1 may be spaced apart from the third pad outer surface 14aOS3 and may extend in a first direction D1, and the third pad outer surface 14aOS3 may extend in a second direction D2 opposite to the first direction D1. The second pad outer surface 14aOS2 may extend in a direction (e.g., a third direction D3 or a fourth direction D4) intersecting the first direction D1 and / or the second direction D2.

[0139] The first dielectric pattern 22a may include a pattern outer surface 22aOS in contact with the substrate 100 and the second dielectric pattern 12a. The pattern outer surface 22aOS may include a first pattern outer surface 22aOS1, a second pattern outer surface 22aOS2 in contact with (or in contact with) the first pattern outer surface 22aOS1, and a third pattern outer surface 22aOS3 in contact with (or in contact with) the second pattern outer surface 22aOS2. The first pattern outer surface 22aOS1 may be spaced apart from the third pattern outer surface 22aOS3.

[0140] The first pattern outer surface 22aOS1 may be in contact with the substrate 100 and the second dielectric pattern 12a. The second pattern outer surface 22aOS2 and the third pattern outer surface 22aOS3 may be in contact with the second dielectric pattern 12a.

[0141] FIG. 16A to FIG. 25B According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of a method of manufacturing an image sensor taken along line AA' and line BB' of FIG. For the sake of brevity of description, repeated description will be omitted.

[0142] Reference Fig.16A and Fig. 16B , a substrate 100 , a first trench TR1 , a dielectric liner layer 12 p conformally covering or overlapping the first trench TR1 , a second trench TR2 , a first isolation layer 32 p , and a second isolation layer 34 p may be formed.

[0143] Shallow device isolation trenches STR, first isolation layers 32p and second isolation layers 34p may be formed on substrate 100, and then first trenches TR1 may be formed. Dielectric liner layer 12p may be formed to conformally cover or overlap inner walls of first trenches TR1.

[0144] Reference Fig.17A and Fig. 17B , the extension trench ETR may be formed to extend into a portion of the substrate 100 and the dielectric liner layer 12p. The extension trench ETR may be formed to extend from the second trench TR2.

[0145] The first doped region DR1 may be formed adjacent to the dielectric liner layer 12p. The second doped region DR2 may be formed adjacent to the extension trench ETR. The first doped region DR1 and the second doped region DR2 may be doped with boron.

[0146] Reference Fig.18A and Fig.18B , a preliminary first dielectric pattern 22p may be formed on the dielectric liner layer 12p and the extension trench ETR. While forming the preliminary first dielectric pattern 22p, a portion of the dielectric liner layer 12p may be etched. In this case, a portion of the dielectric liner layer 12p may be etched, and then the preliminary first dielectric pattern 22p may be formed, and as a result, a first dielectric step difference 22STP may be formed.

[0147] In the intermediate region IR, the preliminary first dielectric pattern 22p may be formed to fill the extension trench ETR and to conformally cover or overlap the dielectric liner layer 12p. In the crossing region CR, the preliminary first dielectric pattern 22p may be formed, and thus a preliminary dielectric pattern trench 22TR may be formed.

[0148] In the intersection region CR, the preliminary first dielectric pattern 22p may be formed to conformally cover the dielectric liner layer 12p and the extension trench ETR or overlap with the dielectric liner layer 12p and the extension trench ETR. In the intersection region CR, the preliminary dielectric pattern trench 22TR may include an upper preliminary dielectric pattern trench 22TRu and a lower preliminary dielectric trench 22TRl. The upper preliminary dielectric pattern trench 22TRu and the lower preliminary dielectric trench 22TRl may be divided across the first dielectric step difference 22STP. The trench above the first dielectric step difference 22STP may be defined as an upper preliminary dielectric pattern trench 22TRu. The trench below the first dielectric step difference 22STP may be defined as a lower preliminary dielectric trench 22TRl.

[0149] Reference Fig.19A and Fig.19B , a conductive liner 14a may be formed on the preliminary first dielectric pattern 22p. The conductive liner 14a may conformally cover the inner wall of the preliminary dielectric pattern trench 22TR or overlap with the inner wall of the preliminary dielectric pattern trench 22TR. The conductive liner 14a may conformally cover the bottom surface of the preliminary dielectric pattern trench 22TR and a portion of the sidewall of the preliminary dielectric pattern trench 22TR or overlap with the bottom surface of the preliminary dielectric pattern trench 22TR and a portion of the sidewall of the preliminary dielectric pattern trench 22TR. The formation of the conductive liner 14a may form a conductive liner trench 14aTR.

[0150] In the intersection region CR, the preliminary dielectric pattern groove 22TR may include an upper preliminary dielectric pattern groove 22TRu and a lower preliminary dielectric groove 22TRl, and when the conductive pad 14a is conformally formed along the preliminary dielectric pattern groove 22TR, the conductive pad groove 14aTR may include an upper conductive pad groove 14aTRu and a lower conductive pad groove 14aTRl.

[0151] Reference Fig. 20A and Fig. 20B , a preliminary intermediate dielectric pattern 24p may be formed in a portion of the conductive liner trench 14aTR and the preliminary dielectric pattern trench 22TR.

[0152] On the intermediate region IR, a preliminary intermediate dielectric pattern 24p may be formed in the conductive liner trench 14aTR. The preliminary intermediate dielectric pattern 24p may be conformally formed on the preliminary first dielectric pattern 22p.

[0153] In the crossing region CR, the preliminary interlayer dielectric pattern 24 p may be conformally formed along the conductive pad trench 14 aTR.

[0154] Reference Fig.21A and Fig. 21BIn the intermediate region IR, the upper portion of the preliminary intermediate dielectric pattern 24p may be removed. In the crossing region CR, the preliminary intermediate dielectric pattern 24p may be removed. The removal process may form an intermediate dielectric pattern 24a.

[0155] Removing the upper portion of the preliminary intermediate dielectric pattern 24p of the intermediate region IR may include, for example, removing the preliminary intermediate dielectric pattern 24p until the top surface 14aT of the conductive pad 14a is exposed. In this case, the top surface 14aT of the conductive pad 14a may be located at the same level as the top surface 24aT of the intermediate dielectric pattern 24a.

[0156] Removing the preliminary interlayer dielectric pattern 24p of the crossing region CR may include removing the preliminary interlayer dielectric pattern 24p conformally formed along the conductive pad trench 14aTR In this case, the removal process may expose the preliminary dielectric pattern trench 22TR and the conductive pad trench 14aTR.

[0157] Reference Fig.22A and Fig. 22B A preliminary buried conductive pattern 18p may be formed on the preliminary first dielectric pattern 22p, the intermediate dielectric pattern 24a, and the conductive pad 14a. The preliminary buried conductive pattern 18p may be formed to conformally cover or overlap the exposed portion of the preliminary dielectric pattern trench 22TR and the exposed portion of the conductive pad trench 14aTR.

[0158] In the intermediate region IR, the forming of the preliminary buried conductive pattern 18 p may include conformally forming the preliminary buried conductive pattern 18 p along the exposed preliminary dielectric pattern trenches 22TR.

[0159] In the crossing region CR, the forming of the preliminary buried conductive pattern 18 p may include conformally forming the preliminary buried conductive pattern 18 p along the exposed preliminary dielectric pattern trench 22TR to completely fill the conductive liner trench 14 aTR.

[0160] Reference Fig.23A and Fig. 23B , the upper portion of the preliminary buried conductive pattern 18p may be removed to form the buried conductive pattern 18a.

[0161] Removing the upper portion of the preliminary buried conductive pattern 18p of the intermediate region IR may include removing the preliminary buried conductive pattern 18p. In this case, the top surface 14aT of the conductive pad 14a may be exposed, and likewise, the top surface 24aT of the intermediate dielectric pattern 24a may be exposed.

[0162] Removing the upper portion of the preliminary buried conductive pattern 18p on the intersection region CR may include removing the preliminary buried conductive pattern 18p until the top surface 14aT of the conductive pad 14 is exposed. The removal process may form the buried conductive pattern 18a. In this case, the top surface 14aT of the conductive pad 14a may be located at the same level as the top surface 18aT of the buried conductive pattern 18a.

[0163] Reference Fig.24A and Fig. 24B A preliminary buried dielectric pattern 16p may be formed on the preliminary first dielectric pattern 22p, the conductive pad 14a and the intermediate dielectric pattern 24a on the intermediate region IR, and a preliminary buried dielectric pattern 16p may also be formed on the preliminary first dielectric pattern 22p, the conductive pad 14a and the buried conductive pattern 18a of the intersection region CR.

[0164] In the crossing region CR, the preliminary buried dielectric pattern 16p may be formed to cover or overlap top surfaces 18aT of the buried conductive pattern 18a and the conductive pad 14a.

[0165] In the intermediate region IR, the preliminary buried dielectric pattern 16p may be formed to cover or overlap a top surface 24aT of the intermediate dielectric pattern 24a and a top surface 14aT of the conductive pad 14a.

[0166] Reference Fig.25A and Fig.25B In the planarization process, the upper portion of the dielectric liner layer 12p, the upper portion of the preliminary buried dielectric pattern 16p, and the upper portion of the second isolation layer 34p may be removed to form the second dielectric pattern 12a, the buried dielectric pattern 16a, and the second isolation portion 34.

[0167] Fig.26A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'. Fig.26B Show Display Fig.26A Magnified view of part M1b. Fig.26C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'. Fig.26D Shows the display Fig.26C For the sake of simplicity, the following will mainly describe the Figures 3 to 4D Discuss the differences between image sensors.

[0168] Reference Figure 3 and FIG. 26A to FIG. 26D The device isolation pattern PIb may extend from the first surface 100A into the substrate 100 and may be disposed between the plurality of pixel regions PX. The device isolation pattern PIb may include or have an intermediate region IR and a crossing region CR. The device isolation pattern PIb may include a first device isolation portion DTI and a second device isolation portion ETI.

[0169] In the intermediate region IR, the device isolation pattern PIb may include an intermediate dielectric pattern 24b, a conductive pad 14b on the intermediate dielectric pattern 24b, a first dielectric pattern 22b on the conductive pad 14b, a second dielectric pattern 12b on the first dielectric pattern 22b, and a buried dielectric pattern 16b.

[0170] In the intermediate region IR, the first dielectric pattern 22b may have a first dielectric step difference 22STPb. The first dielectric step difference 22STPb may have, for example, a step shape. The first dielectric step difference 22STPb may be defined as indicating, for example, a step shape near the interface between the first device isolation portion DTI and the second device isolation portion ETI of the first dielectric pattern 22b.

[0171] In the intermediate region IR, the conductive pad 14b may have a pad step difference 14STPb. The pad step difference 14STPb may have, for example, a step shape. The pad step difference 14STPb may be defined to indicate, for example, a step shape of the conductive pad 14b near the interface between the first device isolation portion DTI and the second device isolation portion ETI.

[0172] In the intermediate region IR, the intermediate dielectric pattern 24b may have an intermediate dielectric step difference 24STPb. The intermediate dielectric step difference 24STPb may have, for example, a step shape. The intermediate dielectric step difference 24STPb may be defined as indicating, for example, a step shape near the interface between the first device isolation portion DTI and the second device isolation portion ETI of the intermediate dielectric pattern 24b.

[0173] In the intersection region CR, the device isolation pattern PIb may include a buried conductive pattern 18b, an intermediate dielectric pattern 24b on the buried conductive pattern 18b, a conductive pad 14b in contact with the buried conductive pattern 18b and the intermediate dielectric pattern 24b, a first dielectric pattern 22b on the conductive pad 14b, a second dielectric pattern 12b on the first dielectric pattern 22b, and a buried dielectric pattern 16b.

[0174] In the crossing region CR, the buried conductive pattern 18b may have a top surface 18bT in contact with the intermediate dielectric pattern 24b. The top surface of the buried conductive pattern 18b may be located at a level lower than that of the top surface 12bT of the second dielectric pattern 12b.

[0175] Fig.27A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'. Fig.27B Shows the display Fig.27A Magnified view of part M1c. Fig.27C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'. Fig.27D Shows the display Fig.27C For the sake of simplicity, the following will mainly describe the Figures 3 to 4D Discuss the differences between image sensors.

[0176] Reference Figure 3 and FIG. 27A to FIG. 27D The device isolation pattern PIc may extend from the first surface 100A into the substrate 100 and may be disposed between the plurality of pixel regions PX. The device isolation pattern PIc may include or have an intermediate region IR and a crossing region CR. The device isolation pattern PIc may include a first device isolation portion DTI and a second device isolation portion ETI.

[0177] In the intermediate region IR, the device isolation pattern PIc may include a first dielectric pattern 22c, a conductive pad 14c on the first dielectric pattern 22c, a second dielectric pattern 12c on the conductive pad 14c, and a buried dielectric pattern 16c.

[0178] The first dielectric pattern 22c may extend from the first device isolation portion DTI to the second device isolation portion ETI. The first dielectric pattern 22c may extend from the top surface of the buried dielectric pattern 16c to the first surface 100A of the substrate 100. A sidewall of the first dielectric pattern 22c may contact the conductive pad 14c.

[0179] The first device isolation portion DTI may include a first dielectric pattern 22c, a conductive pad 14c, a second dielectric pattern 12c, and a buried dielectric pattern 16c. The second device isolation portion ETI may include a first dielectric pattern 22c.

[0180] In the crossing region CR, the device isolation pattern PIc may include a buried conductive pattern 18c, a conductive pad 14c contacting the buried conductive pattern 18c, a first dielectric pattern 22c contacting the buried conductive pattern 18c and the conductive pad 14c, a second dielectric pattern 12c on the conductive pad 14c, and a buried dielectric pattern 16c.

[0181] In the intersection region CR, the top surface of the buried conductive pattern 18c may include a first buried conductive top surface 18cT1 in contact with the bottom surface 22cB of the first dielectric pattern 22c and a second buried conductive top surface 18cT2 in contact with the first surface 100A of the substrate 100. The first buried conductive top surface 18cT1 and the second buried conductive top surface 18cT2 may be spaced apart from each other. The first buried conductive top surface 18cT1 may be located at a level lower than that of the second buried conductive top surface 18cT2.

[0182] The first buried conductive top surface 18cT1 may be at a level lower than that of the top surface 14cT of the conductive pad 14c.

[0183] Fig.28A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'. Fig.28B Shows the display Fig.28A Magnified view of part M1d. Fig.28C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'. Fig.28D Shows the display Fig.28C For the sake of simplicity, the following will mainly describe the Figures 3 to 4D Discuss the differences between image sensors.

[0184] Reference Figure 3 and FIG. 28A to FIG. 28D The device isolation pattern PId may extend from the first surface 100A into the substrate 100 and may be disposed between the plurality of pixel regions PX. The device isolation pattern PId may include or have an intermediate region IR and a crossing region CR. The device isolation pattern PId may include a first device isolation portion DTI and a second device isolation portion ETI.

[0185] In the intermediate region IR, the device isolation pattern PId may include a buried conductive pattern 18d, a first dielectric pattern 22d on the buried conductive pattern 18d, a second dielectric pattern 12d on the first dielectric pattern 22d, and a buried dielectric pattern 16d.

[0186] The first device isolation portion DTI may include a first dielectric pattern 22d, a buried conductive pattern 18d, a second dielectric pattern 12d, and a buried dielectric pattern 16d. The second device isolation portion ETI may include a first dielectric pattern 22d.

[0187] The buried conductive pattern 18d may have a top surface 18dT located at a lower level than the top surface 22dT of the first dielectric pattern 22d. The first dielectric pattern 22d may surround the top surface 18dT and side surfaces of the buried conductive pattern 18d.

[0188] In the cross region CR, the device isolation pattern PId may include a buried conductive pattern 18d, a first dielectric pattern 22d on the buried conductive pattern 18d, a second dielectric pattern 12d on the first dielectric pattern 22d, and a buried dielectric pattern 16d. The buried conductive pattern 18d and the first dielectric pattern 22d may extend from the first device isolation portion DTI to the second device isolation portion ETI.

[0189] In the intersection region CR, the first dielectric pattern 22d may have a first dielectric step difference 22STPd. The first dielectric step difference 22STPd may have, for example, a step shape. The first dielectric step difference 22STPd may be defined to indicate, for example, a step shape near the interface between the first device isolation portion DTI and the second device isolation portion ETI.

[0190] In the intersection region CR, the buried conductive pattern 18d may have a buried conductive step difference 18STPd. The buried conductive step difference 18STPd may have, for example, a step shape. The buried conductive step difference 18STPd may be defined to indicate, for example, a step shape near the interface between the first device isolation portion DTI and the second device isolation portion ETI.

[0191] The first dielectric step difference 22STPd may be closer to the interface between the first device isolation portion DTI and the second device isolation portion ETI than the buried conductive step difference 18STPd.

[0192] Fig.29A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'. Fig.29B Shows the display Fig.29A A magnified view of a portion of M1e. Fig.29C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'. Fig.29D Shows the display Fig.29CFor the sake of simplicity, the following will mainly describe the Figures 3 to 4D Discuss the differences between image sensors.

[0193] Reference Figure 3 and FIG. 29A to FIG. 29D The device isolation pattern Pie may extend from the first surface 100A into the substrate 100 and may be disposed between the plurality of pixel regions PX. The device isolation pattern Pie may include or have an intermediate region IR and a crossing region CR. The device isolation pattern Pie may include a first device isolation portion DTI and a second device isolation portion ETI.

[0194] The device isolation pattern PIE may include a buried conductive pattern 18e, a conductive pad 14e contacting the buried conductive pattern 18e, an intermediate dielectric pattern 24e on the buried conductive pattern 18e, a first dielectric pattern 22e on the conductive pad 14e, a second dielectric pattern 12e on the first dielectric pattern 22e, and a buried dielectric pattern 16e.

[0195] The first dielectric pattern 22e and the conductive pad 14e may extend from the first device isolation portion DTI to the second device isolation portion ETI.

[0196] The first device isolation portion DTI may include a first dielectric pattern 22e, a conductive pad 14e, a buried conductive pattern 18e, a second dielectric pattern 12e, an intermediate dielectric pattern 24e, and a buried dielectric pattern 16e. The second device isolation portion ETI may include a first dielectric pattern 22e, a conductive pad 14e, and an intermediate dielectric pattern 24e.

[0197] The conductive pad 14e may have a pad step difference 14STPe. The pad step difference 14STPe may have, for example, a step shape. The pad step difference 14STPe may be defined to indicate, for example, a step shape of the conductive pad 14e near the interface between the first device isolation portion DTI and the second device isolation portion ETI.

[0198] The pad step difference 14STPe may include a top surface 14STPeT of the pad step difference 14STPe and a bottom surface 14STPeB of the pad step difference 14STPe.

[0199] The first dielectric pattern 22e may have a first dielectric step difference 22STPe. The first dielectric step difference 22STPe may have, for example, a step shape. The first dielectric step difference 22STPe may be defined to indicate, for example, a step shape near the interface between the first device isolation portion DTI and the second device isolation portion ETI of the first dielectric pattern 22e.

[0200] The buried conductive pattern 18e may have a top surface 18eT located at a level lower than that of the top surface 14STPeT of the pad step difference 14STPe. The level of the top surface 18eT of the buried conductive pattern 18e may be the same as that of the bottom surface 14STPeB of the pad step difference 14STPe. The top surface 18eT of the buried conductive pattern 18e may be coplanar with the bottom surface 14STPeB of the pad step difference 14STPe.

[0201] Fig. 30A According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line AA'. Fig. 30B Show Display Fig. 30A A magnified view of part of M1f. Fig. 30C According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of the image sensor taken along line BB'. Fig.30D Shows the display Fig. 30C For the sake of simplicity, the following will mainly describe the Figures 3 to 4D Discuss the differences between image sensors.

[0202] Reference Figure 3 and FIG. 30A to FIG. 30D The device isolation pattern PIf may extend from the first surface 100A into the substrate 100 and may be disposed between the plurality of pixel regions PX. The device isolation pattern PIf may include or have an intermediate region IR and a crossing region CR. The device isolation pattern PIf may include a first device isolation portion DTI and a second device isolation portion ETI.

[0203] The device isolation pattern PIf may include a buried conductive pattern 18f, a conductive pad 14f on the buried conductive pattern 18f, a first dielectric pattern 22f on the conductive pad 14f, a second dielectric pattern 12f on the first dielectric pattern 22f, and a buried dielectric pattern 16f.

[0204] The first dielectric pattern 22f, the conductive liner 14f, and the buried conductive pattern 18f may extend from the first device isolation portion DTI to the second device isolation portion ETI.

[0205] The first device isolation portion DTI may include a first dielectric pattern 22f, a buried conductive pattern 18f, a second dielectric pattern 12f, a conductive pad 14f, and a buried dielectric pattern 16f. The second device isolation portion ETI may include a first dielectric pattern 22f, a conductive pad 14f, and a buried conductive pattern 18f.

[0206] The conductive pad 14f may have a pad step difference 14STPf. The pad step difference 14STPf may have, for example, a step shape. The pad step difference 14STPf may be defined to indicate, for example, a step shape of the conductive pad 14f near an interface between the first device isolation portion DTI and the second device isolation portion ETI.

[0207] The buried conductive pattern 18f may have a buried conductive step difference 18STPf. The buried conductive step difference 18STPf may have, for example, a step shape. The buried conductive step difference 18STPf may be defined to indicate, for example, a step shape near the interface between the first device isolation portion DTI and the second device isolation portion ETI of the buried conductive pattern 18f.

[0208] The first dielectric pattern 22f may have a first dielectric step difference 22STPf. The first dielectric step difference 22STPf may have, for example, a step shape. The first dielectric step difference 22STPf may be defined to indicate, for example, a step shape near the interface between the first device isolation portion DTI and the second device isolation portion ETI.

[0209] According to the present disclosure, an image sensor may have a deep device isolation pattern formed by a multi-step trench, and the deep device isolation pattern may have a first device isolation portion and a second device isolation portion.

[0210] The first device isolation portion and the second device isolation portion may have different materials disposed therein. In addition, boron may be doped in a sidewall of the multi-step trench.

[0211] Thus, the extension of the light receiving area may be increased, sensitivity may be improved, optical absorption may be reduced, and total reflection may be improved. Furthermore, the embodiments described herein provide improved control of dark current and white point.

[0212] The foregoing description provides some embodiments for explaining the present disclosure. Therefore, the present disclosure is not limited to the above embodiments, and it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the present disclosure.

Claims

1. An image sensor, comprising: a substrate including a plurality of pixel regions, wherein the substrate includes a first surface and a second surface opposite to each other; and a device isolation pattern extending from the first surface and extending into the substrate, wherein the device isolation pattern is located between the plurality of pixel regions, wherein the device isolation pattern has a middle region and a cross region and includes a first device isolation portion and a second device isolation portion, The middle region includes: a first dielectric pattern; a conductive pad contacting a sidewall of the first dielectric pattern; and a second dielectric pattern contacting a sidewall of the conductive pad and a top surface of the conductive pad. wherein the first dielectric pattern extends from the first device isolation portion and extends toward the second device isolation portion, and The first device isolation portion includes a conductive pad and a second dielectric pattern.

2. The image sensor according to claim 1, wherein: A width of the first dielectric pattern is smaller than a width of the second dielectric pattern.

3. The image sensor according to claim 1, wherein: The width of the conductive pad is greater than the width of the first dielectric pattern.

4. The image sensor according to claim 1, further comprising a doped region located on the substrate, wherein: The doped region contacts the first device isolation portion and is doped with boron.

5. The image sensor according to claim 1, wherein: The intersection region includes a buried conductive pattern contacting the conductive pad, wherein the buried conductive pattern is located in the first device isolation portion.

6. The image sensor according to claim 5, wherein: A top surface of the buried conductive pattern is a first distance from the second surface of the substrate, wherein a top surface of the conductive pad is a second distance from the second surface of the substrate, wherein the first distance is smaller than the second distance.

7. The image sensor according to claim 5, further comprising: a shallow device isolation pattern adjacent to the second surface of the substrate; as well as buried dielectric pattern, extending into the shallow device isolation pattern, The second dielectric pattern is also located between the buried dielectric pattern and the shallow device isolation pattern.

8. The image sensor according to claim 7, wherein: A top surface of the buried dielectric pattern contacts the conductive pad and the buried conductive pattern.

9. The image sensor according to claim 5, wherein: A width of the buried conductive pattern is greater than a width of the first dielectric pattern.

10. An image sensor, comprising: a substrate including a plurality of pixel regions, wherein the substrate includes a first surface and a second surface opposite to each other; and a device isolation pattern extending from the first surface and extending into the substrate, wherein the device isolation pattern is located between the plurality of pixel regions, wherein the device isolation pattern has a middle region and a cross region and includes a first device isolation portion and a second device isolation portion, The middle region includes: a middle dielectric pattern; a conductive pad contacting the middle dielectric pattern; a first dielectric pattern contacting the conductive pad; and a second dielectric pattern located on the first dielectric pattern. wherein the first dielectric pattern extends from the first device isolation portion and extends toward the second device isolation portion, wherein the first device isolation portion comprises an intermediate dielectric pattern, a conductive pad and a second dielectric pattern, and The first dielectric pattern includes a step shape located on the first device isolation portion.

11. The image sensor according to claim 10, wherein: Conductive pads also include: a flat conductive portion parallel to the substrate; and an extended conductive portion extending from the planar conductive portion and extending toward the second surface of the substrate, The extended conductive portion contacts the intermediate dielectric pattern.

12. The image sensor according to claim 11, wherein: The extended conductive portion is located between the intermediate dielectric pattern and the first dielectric pattern.

13. The image sensor according to claim 10, further comprising a doped region located on the substrate, wherein: The doped region is doped with boron and contacts the first device isolation portion and the second device isolation portion.

14. The image sensor according to claim 10, wherein: The conductive pad at least partially surrounds a side surface of the intermediate dielectric pattern and a top surface of the intermediate dielectric pattern.

15. The image sensor according to claim 10, wherein: In the intersection region, the device isolation pattern further includes a buried conductive pattern contacting the conductive pad, wherein the buried conductive pattern extends from the first device isolation portion and extends toward the second device isolation portion.

16. The image sensor according to claim 15, wherein: The first dielectric pattern further includes: a first pattern outer surface; a second pattern outer surface contacting the first pattern outer surface; and The third pattern outer surface contacts the second pattern outer surface, The first pattern outer surface is spaced apart from the third pattern outer surface.

17. The image sensor according to claim 15, wherein: Conductive pads also include: a first liner outer surface; a second gasket outer surface contacting the first gasket outer surface; and The third pad outer surface contacts the second pad outer surface, wherein the first liner outer surface is spaced apart from the third liner outer surface, The outer surface of the first liner extends along a first direction, and The outer surface of the second pad extends along a second direction intersecting with the first direction.

18. The image sensor according to claim 15, wherein: A width of the buried conductive pattern in the second device isolation portion is smaller than a width of the buried conductive pattern in the first device isolation portion.

19. The image sensor according to claim 10, further comprising: a shallow device isolation pattern adjacent to the second surface of the substrate; as well as buried dielectric pattern, extending into the shallow device isolation pattern, The second dielectric pattern and the first dielectric pattern are also located between the buried dielectric pattern and the shallow device isolation pattern.

20. An image sensor, comprising: A substrate including a plurality of pixel regions, wherein the substrate includes a first surface and a second surface opposite to each other; a device isolation pattern extending from the first surface and extending into the substrate, wherein the device isolation pattern is located between the plurality of pixel regions; and A shallow device isolation pattern adjacent to the second surface of the substrate, wherein the device isolation pattern has a middle region and a cross region and includes a first device isolation portion and a second device isolation portion, Among them, in the middle area: The width of the first device isolation portion is smaller than the width of the shallow device isolation pattern, The width of the second device isolation portion is smaller than the width of the first device isolation portion, The first device isolation portion includes at least one dielectric material and at least one conductive material, and The second device isolation portion includes at least one dielectric material.

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