Fet-type igbt device and method of manufacturing the same

Abstract

The application discloses an FS-IGBT device, which comprises a drift region, a well region formed on the surface of the drift region, a gate structure, and an emitter region formed on the surface of the well region and self-aligned with the gate structure. A first epitaxial layer for forming a field stop layer and a second semiconductor material layer for forming a collector region are formed on the back surface of the drift region, and the band gap of the second semiconductor material layer is lower than that of the semiconductor substrate. The top surface of the field stop layer is in contact with the bottom surface of the drift region. The collector region is heavily doped with a second conductive type, and the top surface of the collector region is in contact with the bottom surface of the field stop layer and forms a back surface PN junction. The top surface of the collector region is flush with or below the top surface of the second semiconductor material layer. The application also discloses a manufacturing method of the FS-IGBT device. The application improves the collector region material, and can reduce the opening voltage of the back surface PN junction, the conduction voltage drop of the whole device, and the conduction loss.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor power devices, in particular to a field stop (FS) Insulated Gate Bipolar Transistor (IGBT) device; the present application also relates to a FS-IGBT device and a manufacturing method thereof. BACKGROUND

[0002] An IGBT device is a voltage-driven device composed of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar transistor (BJT). The MOSFET has high input impedance, fast switching speed, but low carrier density and high on-resistance; the BJT has large current density and low on-resistance, but large driving current; the IGBT combines the advantages of the two, has low driving loss and fast switching speed, and has low on-resistance, and is therefore widely used in medium and high voltage fields such as household appliances, photovoltaic, industrial control, new energy vehicles, and rail transit.

[0003] The FS-IGBT device has a field blocking layer (field stop layer) and a transparent anode structure. The field blocking layer can appropriately reduce the thickness of the drift region, accelerate the switching speed of the device, and reduce the on-state loss. The transparent anode structure regulates the injection efficiency of the collector region, and the on-state loss and switching speed of the IGBT device are well balanced.

[0004] The collector region side of the FS-IGBT device has a PN junction diode structure. When the device is turned on, the channel on the front surface of the device is opened, and electrons are injected from the emitter region to the drift region; at the same time, the PN junction on the collector region side is opened, and a large number of holes are injected from the collector region to the drift region, so that a large number of carriers are accumulated in the drift region, forming a conductivity modulation effect. This greatly reduces the on-resistance of the IGBT, and further reduces the on-state loss.

[0005] In the prior art, the IGBT device is formed on a silicon substrate. Since the band gap of Si is about 1.12 eV, the opening voltage of the silicon-based PN junction diode is 0.7 V, which is almost half of the on-state voltage of the existing IGBT. This means that 50% of the on-state loss of the IGBT is caused by the PN junction diode on the collector region side. Therefore, if the structure of the collector region is further improved to reduce the opening voltage of the PN junction diode on the collector region side, the on-state loss of the device will be greatly reduced.

[0006] As shown in FIG. 1, it is a structural schematic diagram of the existing FS-IGBT device; the existing FS-IGBT device usually adopts an N-type device, taking the N-type device as an example, the existing FS-IGBT device includes: Figure 1

[0007] ​Drift region 103, consisting of N-type lightly doped region formed on the surface of silicon substrate.

[0008] P-type doped well region 105, formed on the surface of the drift region 103.

[0009] Gate structure, including gate oxide layer 104 and polysilicon gate 106 stacked in sequence. Figure 1 In one embodiment, the gate structure is trench gate, the gate oxide layer 104 is formed on the inner surface of the gate trench, the polysilicon gate 106 is filled in the gate trench, the gate trench longitudinally passes through the well region 105, the surface of the well region 105 covered by the side of the gate structure is the channel region. The gate structure can also be planar gate.

[0010] N-type heavily doped emitter region 107, formed on the surface of the well region 105 and self-aligned with the gate structure.

[0011] N-type doped field stop layer 102 is formed on the back surface of the drift region 103, the field stop layer 102 is usually formed by back surface injection, the doping concentration of the field stop layer 102 is greater than the doping concentration of the drift region 103.

[0012] P-type heavily doped collector region 101 is formed on the back surface of the field stop layer 102.

[0013] The top surface of the collector region 101 and the bottom surface of the field stop layer 102 are in contact and form a back surface PN junction.

[0014] The turn-on voltage of the back surface PN junction is mainly determined by the band gap of silicon material, the band gap of silicon is about 1.12eV, the turn-on voltage of the back surface PN junction is about 0.7V.

[0015] After the front metal layer 109 is patterned, the gate and the emitter are formed. Figure 1 In one embodiment, only the emitter is shown, the gate composed of the front metal layer 109 is not shown in the cross section. Figure 1 The gate will be connected with the bottom polysilicon gate 106, the emitter will be connected with the bottom emitter region 107. The well contact region 108 is also formed on the surface of the well region 105, the well contact region 108 is heavily doped of the second conductivity type, the emitter is also connected with the well contact region 108.

[0016] The collector composed of the back metal layer 110 is formed on the back surface of the collector region 101. SUMMARY

[0017] The technical problem solved by the present application is to provide a FS-IGBT device, which can improve the material of the collector region, thereby reducing the opening voltage of the back PN junction and further reducing the on-state voltage drop and on-state loss of the whole device.

[0018] To solve the above technical problem, the present application provides a FS-IGBT device, which comprises:

[0019] A drift region composed of a first-conductivity-type lightly doped region formed on the surface of a semiconductor substrate.

[0020] A well region doped with a second conductivity type formed on the surface of the drift region.

[0021] A gate structure comprising a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0022] A first-conductivity-type heavily doped emitter region formed on the surface of the well region and self-aligned with the gate structure; the surface of the well region between the emitter region and the drift region serves as a channel region and is covered by the gate structure.

[0023] A first epitaxial layer doped with the first conductivity type formed on the back surface of the drift region, the semiconductor substrate on the back surface of the drift region is thinned and removed, the top surface of the first epitaxial layer directly contacts the bottom surface of the drift region, the material of the first epitaxial layer is the same as that of the semiconductor substrate, and the doping concentration of the first epitaxial layer is greater than that of the drift region.

[0024] A second semiconductor material layer formed on the back surface of the first epitaxial layer, the band gap of the second semiconductor material layer is lower than that of the semiconductor substrate.

[0025] A second-conductivity-type heavily doped collector region, the top surface of the collector region is flush with or below the top surface of the second semiconductor material layer; a field stop layer composed of the first epitaxial layer or the first epitaxial layer plus the second semiconductor material layer above the top surface of the collector region, the doping impurities of the field stop layer are formed by diffusion of the first-conductivity-type doped impurities of the first epitaxial layer.

[0026] The top surface of the collector region and the bottom surface of the field stop layer are in contact with each other to form a back PN junction. The interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer. The turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower band gap width of the second semiconductor material layer is used to reduce the turn-on voltage of the back PN junction.

[0027] A further improvement is that the material of the semiconductor substrate includes Si.

[0028] A further improvement is that the material of the second semiconductor material layer includes Ge and GeSi.

[0029] A further improvement is that the second semiconductor material layer is a deposition layer formed on the back side of the semiconductor substrate.

[0030] Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the second semiconductor material layer is a GeSi layer formed by backside Ge implantation into Si.

[0031] A further improvement is that the second semiconductor material layer has undergone annealing treatment, and the field stop layer and the collector region have undergone backside laser annealing treatment.

[0032] The second semiconductor material layer is annealed by furnace annealing or backside laser annealing.

[0033] A further improvement is that the doping impurities in the collector region are back-implanted impurities heavily doped with the second conductivity type or in-situ doping impurities in the second semiconductor material layer;

[0034] The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer;

[0035] The junction depth of the collector region is less than 0.5 μm;

[0036] The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

[0037] A further improvement is that the gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region;

[0038] Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, and the gate conductive material layer is stacked on the top surface of the gate dielectric layer, and the well region surface covered by the gate structure from the top side of the well region serves as the channel region.

[0039] Further improvement is that the thickness of the first epitaxial layer is 5-15 mu m, and the doping concentration is 1E15 cm -3 -1E17 cm -3 .

[0040] To solve the above technical problems, the manufacturing method of the FS-IGBT device provided by the application comprises the following steps:

[0041] Step one, complete the front process to form the front process structure of the FS-IGBT device.

[0042] The front process structure of the FS-IGBT device comprises:

[0043] The drift region is composed of a first conductive type lightly doped region formed on the surface of the semiconductor substrate.

[0044] The well region doped with a second conductive type is formed on the surface of the drift region.

[0045] The gate structure comprises a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0046] The emitter region doped with a first conductive type is formed on the surface of the well region and is self-aligned with the gate structure; the well region surface between the emitter region and the drift region serves as the channel region and is covered by the gate structure.

[0047] Step two, thin the back of the semiconductor substrate, and the semiconductor substrate on the back of the drift region is removed.

[0048] Step three, form a first epitaxial layer doped with a first conductive type on the back of the drift region by epitaxial growth process, the top surface of the first epitaxial layer is in direct contact with the bottom surface of the drift region, the material of the first epitaxial layer is the same as that of the semiconductor substrate, and the doping concentration of the first epitaxial layer is greater than that of the drift region.

[0049] Step four, form a second semiconductor material layer on the back of the thinned semiconductor substrate; the band gap of the second semiconductor material layer is lower than that of the semiconductor substrate.

[0050] Step five, forming a second conductivity type heavily doped collector region, the top surface of the collector region is level with or below the top surface of the second semiconductor material layer.

[0051] The first epitaxial layer above the top surface of the collector region or the first epitaxial layer plus the second semiconductor material layer forms a field stop layer, the doped impurities of the field stop layer are formed by the diffusion of the first conductivity type doped impurities of the first epitaxial layer.

[0052] The top surface of the collector region and the bottom surface of the field stop layer are in contact and form a backside PN junction, the interface of the backside PN junction is inside the second semiconductor material layer or part or all of the built-in space charge region of the backside PN junction is inside the second semiconductor material layer, the turn-on voltage of the backside PN junction is determined by the second semiconductor material layer and the lower band gap of the second semiconductor material layer is used to lower the turn-on voltage of the backside PN junction.

[0053] Further improvement is that the material of the semiconductor substrate includes Si.

[0054] Further improvement is that the material of the second semiconductor material layer includes Ge, GeSi.

[0055] Further improvement is that in step three, a deposition process is used to form the second semiconductor material layer on the backside of the thinned semiconductor substrate.

[0056] Or, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the process of forming the second semiconductor material layer in step three includes: performing a backside Ge implant, the Ge of the backside Ge implant and the Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer.

[0057] Further improvement is that the second semiconductor material layer has undergone annealing treatment, and the field stop layer and the collector region have undergone backside laser annealing treatment.

[0058] The annealing of the second semiconductor material layer uses a furnace tube annealing or the backside laser annealing.

[0059] Further improvement is that when the annealing of the second semiconductor material layer includes the furnace tube annealing, the furnace tube annealing of the second semiconductor material layer is placed after step three and before step four and step five.

[0060] The backside laser annealing is performed after step four and step five are completed.

[0061] Steps four and five can be interchanged in sequence.

[0062] Further improvement is that in step five, the backside ion implantation with the second conductivity type heavy doping forms the collector region.

[0063] Or, when the deposition process is used in step three to form the second semiconductor material layer, step five is omitted, and in step three, the second semiconductor material layer is in-situ doped with impurities, which are used as the doping impurities of the collector region.

[0064] The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer.

[0065] The junction depth of the collector region is less than 0.5 μm.

[0066] The thickness of the second semiconductor material layer is greater than the junction depth of the collector region, and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

[0067] Further improvement is that the gate structure is a trench gate, the gate dielectric layer is formed on the inner side surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench longitudinally passes through the well region, and the well region surface covered by the side surface of the gate structure is the channel region.

[0068] Or, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, and the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the well region surface covered by the top side surface of the well region from the gate structure is the channel region.

[0069] Further improvement is that the thickness of the first epitaxial layer is 5 μm to 15 μm, the doping concentration is 1E15 cm -3 to 1E17 cm -3 .

[0070] The collector region of the FS-IGBT device is directly formed by implantation on the back surface of the thinned semiconductor substrate in the prior art. In the present application, after the back surface of the semiconductor substrate is thinned, a second semiconductor material layer with a lower band gap is formed on the back surface of the semiconductor substrate. The collector region is formed on the basis of the second semiconductor material layer, and the top surface of the collector region is lowered to be below the top surface of the second semiconductor material layer. The interface of the back surface PN junction formed between the collector region and the field stop layer on the top of the collector region is located in the second semiconductor material layer, and part or all of the built-in space charge region is located in the second semiconductor material layer. Therefore, the turn-on voltage of the back surface PN junction in the present application is determined by the second semiconductor material layer, while the turn-on voltage of the back surface PN junction in the prior art FS-IGBT device is determined by the material of the semiconductor substrate. Since the lower the band gap of the material forming the PN junction, the lower the turn-on voltage of the PN junction, the present application can reduce the band gap of the material forming the back surface PN junction, thereby reducing the turn-on voltage of the back surface PN junction. That is, the present application reduces the turn-on voltage of the back surface PN junction by using the lower band gap of the second semiconductor material layer. In summary, the present application improves the material of the collector region, so that the collector region is located in the second semiconductor material layer with a lower band gap than the semiconductor substrate, thereby reducing the turn-on voltage of the back surface PN junction, and further reducing the on-state voltage drop and on-state loss of the entire device.

[0071] In addition, the field stop layer in the present application is mainly formed by the first epitaxial layer formed by back surface epitaxy. The epitaxial process can more accurately control the thickness, doping concentration and impurity distribution of the field stop layer, thereby further improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0072] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0073] Figure 1 is a structural schematic diagram of a prior FS-IGBT device;

[0074] Figure 2 is a structural schematic diagram of a first embodiment of the FS-IGBT device of the present application;

[0075] Figure 3 is a structural schematic diagram of a third embodiment of the FS-IGBT device of the present application;

[0076] Figure 4 is a flowchart of the manufacturing method of the first embodiment of the FS-IGBT device of the present application;

[0077] Figure 5 is a flowchart of the manufacturing method of the second embodiment of the FS-IGBT device of the present application. DETAILED DESCRIPTION

[0078] The FS-IGBT device of the first embodiment of the present invention:

[0079] like Figure 2 FIG. 1 is a schematic structural diagram of an FS-IGBT device according to a first embodiment of the present invention. The FS-IGBT device according to the first embodiment of the present invention includes:

[0080] The drift region 203 is composed of a lightly doped region of the first conductivity type formed on the surface of the semiconductor substrate.

[0081] A well region 205 doped with the second conductivity type is formed on the surface of the drift region 203 .

[0082] The gate structure includes a gate dielectric layer 204 and a gate conductive material layer 206 stacked in sequence.

[0083] An emitter region 207 heavily doped with the first conductivity type is formed on the surface of the well region 205 and is self-aligned with the gate structure. The surface of the well region 205 between the emitter region 207 and the drift region 203 serves as a channel region and is covered by the gate structure.

[0084] In the first embodiment of the present invention, the gate structure is a trench gate. The gate dielectric layer 204 is formed on the inner surface of the gate trench, and the gate conductive material layer 206 fills the gate trench. The gate trench vertically passes through the well region 205, and the surface of the well region 205 covered by the side of the gate structure serves as the channel region. In some embodiments, the gate dielectric layer 204 is a gate oxide layer, and the gate conductive material 206 is a polysilicon gate.

[0085] A first epitaxial layer 301 doped with a first conductivity type is formed on the back side of the drift region 203. The semiconductor substrate on the back side of the drift region 203 is thinned and removed. The top surface of the first epitaxial layer 301 is in direct contact with the bottom surface of the drift region 203. The material of the first epitaxial layer 301 is the same as that of the semiconductor substrate, and the doping concentration of the first epitaxial layer 301 is greater than the doping concentration of the drift region 203. A second semiconductor material layer 302 is formed on the back side of the first epitaxial layer 301. The bandgap of the second semiconductor material layer 302 is lower than the bandgap of the semiconductor substrate. Figure 2 In FIG, the back surface of the first epitaxial layer 301 is separately marked with a mark 304 , and the surface 304 is also the top surface of the second semiconductor material layer 302 .

[0086] A second conductive type heavily doped collector region 201, a top surface of the collector region 201 is flush with or below a top surface of the second semiconductor material layer 302; a field stop layer 202 is composed of the first epitaxial layer 301 above the top surface of the collector region 201 or the first epitaxial layer 301 plus the second semiconductor material layer 302, a doped impurity of the field stop layer 202 is formed by diffusion of the first conductive type doped impurity of the first epitaxial layer 301.

[0087] The top surface of the collector region 201 and a bottom surface of the field stop layer 202 are in contact and form a back surface PN junction. The collector region 201 is located in an area indicated by a pair of braces corresponding to the mark 201, and the field stop layer 202 is located in an area indicated by a pair of braces corresponding to the mark 202. An interface of the back surface PN junction is located inside the second semiconductor material layer 302, or part or all of a built-in space charge region of the back surface PN junction is located inside the second semiconductor material layer 302, so that an opening voltage of the back surface PN junction is determined by the second semiconductor material layer 302 and the opening voltage of the back surface PN junction is reduced by using the lower band gap of the second semiconductor material layer 302. Figure 2 In the case, the interface of the back surface PN junction is indicated by a mark 303, and it can be seen that the interface 302 is located below the surface 303.

[0088] In the first embodiment of the present application, the material of the semiconductor substrate includes Si.

[0089] In some embodiments, a second epitaxial layer is further formed on a surface of the semiconductor substrate, the drift region 203 is formed in the second epitaxial layer, and the semiconductor substrate is completely removed after being thinned on the back surface. The material of the second semiconductor material layer 302 includes Ge. Since the band gap of Si is about 1.12 eV and the band gap of Ge is about 0.67 eV, when the space charge region of the back surface PN junction is located inside Ge, the opening voltage will be reduced to about 0.3 V, which is lower than the opening voltage of about 0.7 V of a PN junction in Si material. In other embodiments, the material of the second semiconductor material layer 302 can also use GeSi or other semiconductor materials with a lower band gap than Si.

[0090] The second semiconductor material layer 302 is a deposited layer formed on the back surface of the semiconductor substrate. In some embodiments, the deposition process of the second semiconductor material layer 302 includes molecular beam epitaxy, organic chemical vapor deposition, pulsed laser deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, low-temperature germanium buffer layer deposition, etc.

[0091] In the first embodiment of the present invention, the second semiconductor material layer 302 undergoes an annealing treatment, and the field stop layer 202 and the collector region 201 undergo a backside laser annealing treatment. The second semiconductor material layer 302 can repair Ge crystallization after annealing; and the field stop layer 202 and the collector region 201 can achieve impurity activation after the backside laser annealing treatment.

[0092] In some embodiments, the second semiconductor material layer 302 is annealed using furnace annealing or backside laser annealing. The furnace annealing process conditions include an annealing temperature of 400°C to 500°C and an annealing time of 40 minutes. In other embodiments, the second semiconductor material layer 302 may be annealed using only backside laser annealing, without furnace annealing. In this way, both crystallization repair of the second semiconductor material layer 302 and impurity activation of the field stop layer 202 and the collector region 201 are achieved through the same backside laser annealing.

[0093] In some embodiments, the doping impurities in the collector region 201 are back-implanted impurities heavily doped with the second conductivity type. In other embodiments, the doping impurities in the collector region 201 can also be in-situ doping impurities in the second semiconductor material layer 302 .

[0094] The bottom surface of the collector region 201 is flush with the bottom surface of the second semiconductor material layer 302 .

[0095] The first embodiment of the present invention further includes: a front metal layer 209 , wherein the front metal layer 209 is patterned to form a gate and an emitter. Figure 2 Only the emitter is shown in FIG. 2 , and the gate composed of the front metal layer 209 is not shown in FIG. Figure 2 The gate is connected to the gate conductive material layer 206 at the bottom, and the emitter is connected to the emitter region 207 at the bottom. A well contact region 208 is also formed on the surface of the well region 205. The well contact region 208 is heavily doped with the second conductivity type, and the emitter is also connected to the well contact region 208. In some embodiments, the front metal layer 209 includes multiple layers, and each layer of the front metal layer 209 is isolated by an interlayer film and connected by vias passing through the interlayer film.

[0096] A collector electrode composed of a back metal layer 210 is formed on the back side of the collector region 201 .

[0097] In some embodiments, the junction depth of the collector region 201 is less than 0.5 μm. The thickness of the second semiconductor material layer 302 is greater than the junction depth of the collector region 201 and is 0.3 μm to 1 μm.

[0098] The thickness of the first epitaxial layer 301 is 5-15 μm, and the doping concentration is 1E15 cm -3 ~1E17 cm -3 .

[0099] In the first embodiment of the present application, the FS-IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. The FS-IGBT device being an N-type device means that the carriers of the conductive channel formed by the surface inversion of the channel region controlled by the gate structure are electrons. The doping impurities of the collector region 201 include boron, and the doping concentration is 1E16 cm -3 ~1E18 cm -3 .

[0100] In other embodiments, the FS-IGBT device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0101] In the prior art, the collector region 201 of the FS-IGBT device is directly formed by implantation on the back surface of the thinned semiconductor substrate. In the first embodiment of the present application, after the back surface of the semiconductor substrate is thinned, a second semiconductor material layer 302 with a lower band gap is formed on the back surface of the semiconductor substrate. The collector region 201 is formed on the basis of the second semiconductor material layer 302, and the top surface of the collector region 201 is set to be below the top surface of the second semiconductor material layer 302. This can make the interface of the back surface PN junction formed between the collector region 201 and the field stop layer 202 on the top of the collector region 201 located inside the second semiconductor material layer 302, and part or all of the built-in space charge region located inside the second semiconductor material layer 302. Therefore, the turn-on voltage of the back surface PN junction of the first embodiment of the present application is determined by the second semiconductor material layer 302, while the turn-on voltage of the back surface PN junction in the prior art FS-IGBT device is determined by the material of the semiconductor substrate. Since the lower the band gap of the material forming the PN junction, the lower the turn-on voltage of the PN junction, the first embodiment of the present application can reduce the band gap of the material forming the back surface PN junction, thereby reducing the turn-on voltage of the back surface PN junction. That is, the first embodiment of the present application uses the lower band gap of the second semiconductor material layer 302 to reduce the turn-on voltage of the back surface PN junction. In summary, the first embodiment of the present application can improve the material of the collector region 201, so that the collector region 201 is located inside the second semiconductor material layer 302 with a lower band gap than the semiconductor substrate, thereby reducing the turn-on voltage of the back surface PN junction and further reducing the on-state voltage drop and on-state loss of the entire device.

[0102] In addition, the field stop layer 202 of the second embodiment of the present application is mainly formed by the first epitaxial layer 301 formed by backside epitaxy. The epitaxial process can more accurately control the thickness and doping concentration and impurity distribution of the field stop layer 202, thereby further improving the performance of the device. The FS-IGBT device of the second embodiment of the present application:

[0103] The difference between the FS-IGBT device of the second embodiment of the present application and the FS-IGBT device of the first embodiment of the present application is that:

[0104] In the FS-IGBT device of the second embodiment of the present application, the material of the semiconductor substrate is Si, the material of the second semiconductor material layer 302 is GeSi, and the second semiconductor material layer 302 is a GeSi layer formed by backside Ge injection into Si. The GeSi layer formed by backside Ge injection can be well crystallized by combining with annealing treatment.

[0105] The FS-IGBT device of the third embodiment of the present application:

[0106] The difference between the FS-IGBT device of the third embodiment of the present application and the FS-IGBT device of the first embodiment of the present application is that:

[0107] In the FS-IGBT device of the third embodiment of the present application, as shown in Figure 3 , the gate structure is a planar gate, the gate dielectric layer 204a covers the top surface of the well region 205 and extends to the top surface of the drift region 203 adjacent to the well region 205, and the gate conductive material layer 206a is superimposed on the top surface of the gate dielectric layer 204. The surface of the well region 205 covered by the gate structure from the top side of the well region 205 serves as the channel region. Figure 3 In the FS-IGBT device of the third embodiment of the present application, the gate dielectric layer is separately denoted by the mark 204a, and the gate conductive material layer is separately denoted by the mark 206a. The surface of other structures is unchanged.

[0108] The manufacturing method of the FS-IGBT device of the first embodiment of the present application:

[0109] As shown in Figure 4 , it is a manufacturing method of the FS-IGBT device of the first embodiment of the present application. The manufacturing method of the FS-IGBT device of the first embodiment of the present application can manufacture Figure 2 the FS-IGBT device of the first embodiment of the present application and Figure 3 the FS-IGBT device of the third embodiment of the present application, and also can obtain the FS-IGBT device of the second embodiment of the present application. Hereinafter, the structure shown in Figure 2 will be taken as an example for description. The manufacturing method of the FS-IGBT device of the first embodiment of the present application comprises the following steps:

[0110] Step one, the front side process is completed to form a front side process structure of the FS-IGBT device. Step one corresponds to Figure 4 the step S101 in the front side process is completed.

[0111] The front side process structure of the FS-IGBT device includes:

[0112] A drift region 203, which is composed of a first conductive type lightly doped region formed on a surface of a semiconductor substrate.

[0113] A well region 205 doped with a second conductive type, which is formed on a surface of the drift region 203.

[0114] A gate structure, which includes a gate dielectric layer 204 and a gate conductive material layer 206 stacked in sequence.

[0115] A first conductive type heavily doped emitter region 207, which is formed on a surface of the well region 205 and self-aligned with the gate structure; a surface of the well region 205 between the emitter region 207 and the drift region 203 serves as a channel region and is covered by the gate structure.

[0116] In the method of the first embodiment of the present application, the material of the semiconductor substrate includes Si.

[0117] In some embodiments, an epitaxial layer is further formed on the surface of the semiconductor substrate, and the drift region 203 is formed in the epitaxial layer. The semiconductor substrate will be completely removed in a subsequent back side thinning process, and a subsequent field stop layer 202 is formed in a back side region of the epitaxial layer.

[0118] The gate structure is a trench gate, the gate dielectric layer 204 is formed on an inner side surface of a gate trench, the gate conductive material layer 206 is filled in the gate trench, the gate trench longitudinally passes through the well region 205, and a surface of the well region 205 covered by a side surface of the gate structure serves as the channel region.

[0119] When used for manufacturing Figure 3 the FS-IGBT device of the third embodiment of the present application shown in FIG. 3, the gate structure is a planar gate, the gate dielectric layer 204 covers a top surface of the well region 205 and extends to a top surface of the drift region 203 adjacent to the well region 205, and the gate conductive material layer 206 is stacked on a top surface of the gate dielectric layer 204, a surface of the well region 205 covered by a top side surface of the gate structure from the well region 205 serves as the channel region.

[0120] The FS-IGBT device of the first embodiment of the present application further comprises a front metal layer 209, which forms a gate and an emitter after being patterned. Figure 2 The gate formed by the front metal layer 209 is not shown in the cross section of the FS-IGBT device. Figure 2 The gate is connected with the gate conductive material layer 206 at the bottom, and the emitter is connected with the emitter region 207 at the bottom. A well contact region 208 is further formed on the surface of the well region 205, which is heavily doped with the second conductive type, and the emitter is also connected with the well contact region 208. In some embodiments, the front metal layer 209 comprises multiple layers, which are separated by interlayer films and connected by through-holes penetrating the interlayer films.

[0121] Step two: back-thinning the semiconductor substrate. The back-thinning removes the semiconductor substrate on the back of the drift region 203.

[0122] Step two corresponds to step S102 of the method in Figure 4 , i.e., back-thinning.

[0123] Step three: forming a first epitaxial layer 301 of the first conductive type on the back of the drift region 203 by an epitaxial growth process, the top surface of the first epitaxial layer 301 directly contacts the bottom surface of the drift region 203, the material of the first epitaxial layer 301 is the same as that of the semiconductor substrate, and the doping concentration of the first epitaxial layer 301 is greater than that of the drift region 203. Step three corresponds to step S103 of the method in Figure 4 , i.e., field stop layer epitaxy. The field stop layer is the field stop layer 202, i.e., the first epitaxial layer 301 is an epitaxial layer for forming the field stop layer 202.

[0124] Step four: forming a second semiconductor material layer 302 on the back of the thinned semiconductor substrate; the band gap of the second semiconductor material layer 302 is lower than that of the semiconductor substrate.

[0125] In the first embodiment of the present application, the material of the second semiconductor material layer 302 is Ge, and a Ge layer is formed by a deposition process. Step four corresponds to step S104 of the method in Figure 4 , i.e., Ge layer deposition.

[0126] In other embodiments, the material of the second semiconductor material layer 302 can also be GeSi or other semiconductor materials with a band gap lower than that of Si.

[0127] In some embodiments, the deposition process of the second semiconductor material layer 302 includes molecular beam epitaxy, organic chemical vapor deposition, pulsed laser deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, low-temperature germanium buffer deposition, etc.

[0128] In other embodiments, the semiconductor substrate is made of Si and the second semiconductor material layer 302 is made of GeSi, and the process of forming the second semiconductor material layer 302 includes backside Ge implantation, in which Ge and Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer 302. The device formed at this time corresponds to the FS-IGBT device of the second embodiment of the present application.

[0129] In the first embodiment of the present application, after step four is completed, the method further includes:

[0130] The second semiconductor material layer 302 is subjected to furnace tube annealing to repair the crystal of the Ge layer, which corresponds to step S104 in Figure 4 The process conditions of the furnace tube annealing include an annealing temperature of 400-500°C and an annealing time of 40 min.

[0131] Step five: forming a second-conductivity-type heavily doped collector region 201, the top surface of the collector region 201 being flush with or below the top surface of the second semiconductor material layer 302.

[0132] The field stop layer 202 is composed of the first epitaxial layer 301 above the top surface of the collector region 201 or the first epitaxial layer 301 plus the second semiconductor material layer 302, and the doping impurities of the field stop layer 202 are formed by diffusion of the first-conductivity-type doping impurities of the first epitaxial layer 301.

[0133] Generally, the collector region 201 is heavily doped, and the doping concentration of the first epitaxial layer 301 is lower than that of the collector region 201, for example, the first epitaxial layer has a thickness of 5-15 μm and a doping concentration of 1E15 cm -3 -1E17 cm -3 ; the collector region 201 has a doping concentration of 1E16 cm -3 -1E18 cm -3 Therefore, in the region above the top surface of the collector region 201, i.e., the region where the collector region 201 does not diffuse, the doping impurities are determined by diffusion of the first epitaxial layer 301, thereby determining the field stop layer 202.

[0134] The top surface of the collector region 201 and the bottom surface of the field stop layer 202 are in contact and form a back PN junction. The interface of the back PN junction is inside the second semiconductor material layer 302 or part or all of the built-in space charge region of the back PN junction is inside the second semiconductor material layer 302, so that the opening voltage of the back PN junction is determined by the second semiconductor material layer 302 and the opening voltage of the back PN junction is reduced by the lower band gap of the second semiconductor material layer 302.

[0135] In the method of the first embodiment of the present application, the collector region 201 is formed by back ion implantation of the second conductivity type heavy doping. The second conductivity type is P type and the second conductivity type heavy doping is P type heavy doping. Step five corresponds to step S106, back Pplus implantation, Pplus representing P type heavy doping implantation, i.e. second conductivity type heavy doping implantation, in Figure 4

[0136] In other embodiment methods, when the second semiconductor material layer 302 is formed by deposition process in step four, step five is omitted and in situ doping is performed on the second semiconductor material layer 302 in step four, and the in situ doping impurities of the second semiconductor material layer 302 are used as the doping impurities of the collector region 201. The step of omitting step five is described in the brackets of step S106 in Figure 4

[0137] In the method of the first embodiment of the present application, the bottom surface of the collector region 201 is flat with the bottom surface of the second semiconductor material layer 302.

[0138] In some embodiment methods, the junction depth of the collector region 201 is less than 0.5 μm.

[0139] The thickness of the second semiconductor material layer 302 is greater than the junction depth of the collector region 201 and the thickness of the second semiconductor material layer 302 is 0.3 μm to 1 μm.

[0140] After step five, the method further comprises:

[0141] Back laser annealing is performed to activate the impurities of the collector region 201. This step corresponds to step S107, laser annealing, in Figure 4

[0142] Subsequently, the method further comprises:

[0143] A back metal layer 210 is formed on the back of the collector region 201 to form a collector electrode. The back metal layer 210 is usually formed by metal sputtering process. This step corresponds to step S108, back metal layer 210 formation, in Figure 4 ​​​Step S108, metal sputtering.

[0144] In the method of the first embodiment of the present invention, the order of the above-mentioned step 4 and step 5 can be interchanged.

[0145] A method for manufacturing a FS-IGBT device according to a second embodiment of the present invention:

[0146] like Figure 5 FIG. 1 shows a method for manufacturing a FS-IGBT device according to a second embodiment of the present invention. The differences between the method for manufacturing a FS-IGBT device according to the second embodiment of the present invention and the method for manufacturing a FS-IGBT device according to the first embodiment of the present invention are as follows:

[0147] In the manufacturing method of the FS-IGBT device according to the second embodiment of the present invention, the annealing of the second semiconductor material layer 302 does not include the furnace annealing. Figure 5 Omitted Figure 4 In this way, the annealing for crystallization repair of the second semiconductor material layer 302 directly adopts the back laser annealing for activating the field stop layer 202 and the collector region 201 .

[0148] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A FS-IGBT device, characterized in that: include: A drift region comprising a lightly doped region of a first conductivity type formed on a surface of a semiconductor substrate; A well region doped with a second conductivity type is formed on the surface of the drift region; A gate structure comprising a gate dielectric layer and a gate conductive material layer stacked in sequence; An emitter region heavily doped with a first conductivity type is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region located between the emitter region and the drift region serves as a channel region and is covered by the gate structure; A first epitaxial layer doped with a first conductivity type is formed on the back side of the drift region, the semiconductor substrate on the back side of the drift region is thinned and removed, a top surface of the first epitaxial layer is in direct contact with a bottom surface of the drift region, the material of the first epitaxial layer is the same as that of the semiconductor substrate, and the doping concentration of the first epitaxial layer is greater than the doping concentration of the drift region; a second semiconductor material layer formed on the back side of the first epitaxial layer, wherein the band gap of the second semiconductor material layer is lower than the band gap of the semiconductor substrate; A collector region heavily doped with the second conductivity type, wherein a top surface of the collector region is located below a top surface of the second semiconductor material layer; A field stop layer is formed by the first epitaxial layer or the first epitaxial layer plus the second semiconductor material layer on the top surface of the collector region, wherein the doping impurities of the field stop layer are formed by diffusing impurities doped with the first conductivity type in the first epitaxial layer; The top surface of the collector region and the bottom surface of the field stop layer are in contact with each other to form a back PN junction, and the interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer; The doping impurities in the collector region are back-implanted impurities heavily doped with the second conductivity type or in-situ doping impurities in the second semiconductor material layer; The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer; The junction depth of the collector region is less than 0.5 μm; The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

2. The FS-IGBT device according to claim 1, wherein: The material of the semiconductor substrate includes Si.

3. The FS-IGBT device according to claim 2, wherein: The material of the second semiconductor material layer includes Ge and GeSi.

4. The FS-IGBT device according to claim 3, wherein: The second semiconductor material layer is a deposition layer formed on the back side of the semiconductor substrate; Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the second semiconductor material layer is a GeSi layer formed by backside Ge implantation into Si.

5. The FS-IGBT device according to claim 1, wherein: The turn-on voltage of the back PN junction is determined by the second semiconductor material layer, and the turn-on voltage of the back PN junction is reduced by utilizing the characteristic of the second semiconductor material layer having a lower band gap.

6. The FS-IGBT device according to claim 1, wherein: The gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region; Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

7. The FS-IGBT device according to claim 1, wherein: The thickness of the first epitaxial layer is 5 μm to 15 μm, and the doping concentration is 1E15 cm -3 ~1E17cm -3 .

8. A method for manufacturing a FS-IGBT device, characterized in that: The steps include: Step 1: Complete the front side process to form the front side process structure of the FS-IGBT device; The front process structure of the FS-IGBT device includes: a drift region, consisting of a lightly doped region of the first conductivity type formed on the surface of the semiconductor substrate; A well region doped with a second conductivity type is formed on the surface of the drift region; A gate structure comprising a gate dielectric layer and a gate conductive material layer stacked in sequence; An emitter region heavily doped with a first conductivity type is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region located between the emitter region and the drift region serves as a channel region and is covered by the gate structure; Step 2: thinning the back side of the semiconductor substrate, wherein the back side thinning removes the semiconductor substrate on the back side of the drift region; Step 3: forming a first epitaxial layer doped with a first conductivity type on the back side of the drift region by an epitaxial growth process, wherein a top surface of the first epitaxial layer is in direct contact with a bottom surface of the drift region, a material of the first epitaxial layer is the same as a material of the semiconductor substrate, and a doping concentration of the first epitaxial layer is greater than a doping concentration of the drift region; Step 4: forming a second semiconductor material layer on the back side of the thinned semiconductor substrate; the band gap width of the second semiconductor material layer is lower than the band gap width of the semiconductor substrate; Step 5: forming a collector region heavily doped with the second conductivity type, wherein the top surface of the collector region is located below the top surface of the second semiconductor material layer; A field stop layer is formed by the first epitaxial layer or the first epitaxial layer plus the second semiconductor material layer on the top surface of the collector region, wherein the doping impurities of the field stop layer are formed by diffusing impurities doped with the first conductivity type in the first epitaxial layer; The top surface of the collector region and the bottom surface of the field stop layer are in contact with each other to form a back PN junction, the interface of the back PN junction is located inside the second semiconductor material layer, or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer, the turn-on voltage of the back PN junction is determined by the second semiconductor material layer, and the lower band gap width of the second semiconductor material layer is utilized to reduce the turn-on voltage of the back PN junction; In step five, the collector region is formed by back ion implantation with heavy doping of the second conductivity type; Alternatively, when the second semiconductor material layer is formed by a deposition process in step 3, step 5 is omitted, and in step 3, the second semiconductor material layer is in-situ doped with impurities, and the in-situ doped impurities of the second semiconductor material layer serve as doping impurities for the collector region; The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer; The junction depth of the collector region is less than 0.5 μm; The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

9. The method for manufacturing a FS-IGBT device according to claim 8, wherein: The material of the semiconductor substrate includes Si.

10. The method for manufacturing a FS-IGBT device according to claim 9, wherein: The material of the second semiconductor material layer includes Ge and GeSi.

11. The method for manufacturing a FS-IGBT device according to claim 10, wherein: In step three, a deposition process is used to form the second semiconductor material layer on the back side of the thinned semiconductor substrate; Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the process of forming the second semiconductor material layer in step three includes: performing back-side Ge injection, the Ge injected from the back-side Ge and the Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer.

12. The method for manufacturing a FS-IGBT device according to claim 11, wherein: The second semiconductor material layer has been subjected to an annealing process, and the field stop layer and the collector region have been subjected to a backside laser annealing process; The second semiconductor material layer is annealed by furnace annealing or backside laser annealing.

13. The method for manufacturing a FS-IGBT device according to claim 12, wherein: When the annealing of the second semiconductor material layer includes the furnace tube annealing, the furnace tube annealing of the second semiconductor material layer is performed after step 3 and before step 4 and step 5; The backside laser annealing is performed after step 4 and step 5 are completed; The order of steps 4 and 5 can be interchanged.

14. The method for manufacturing a FS-IGBT device according to claim 8, wherein: The gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region; Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

15. The method for manufacturing a FS-IGBT device according to claim 8, wherein: The thickness of the first epitaxial layer is 5 μm to 15 μm, and the doping concentration is 1E15 cm -3 ~1E17cm -3 .

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