Semiconductor device

Abstract

A semiconductor device. A semiconductor device (100) is provided with a diode section (20) disposed on a semiconductor substrate (101), and an IGBT section (10) disposed around the diode section. The IGBT section is provided with a first semiconductor region (6) of a first conductivity type, a second semiconductor region (7) of a second conductivity type provided on the first semiconductor region, and a trench (14) penetrating the second semiconductor region in the depth direction. The diode part is provided with a first semiconductor region, a second conductivity-type third semiconductor region (12) provided on the first semiconductor region, and a second trench (16) penetrating the third semiconductor region in the depth direction. A second conductivity-type fourth semiconductor region (70) having a junction depth deeper than that of the second semiconductor region of the IGBT portion is provided between a first end (14EG) of the IGBT portion in the first direction in which the first trench extends and a second end (16EG) of the second trench of the diode portion in the first direction.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Conventionally, there has been proposed a semiconductor device in which an insulated gate bipolar transistor (IGBT) and a reflux diode are formed on a single semiconductor substrate, namely a reverse conducting IGBT (RC-IGBT). In addition, there is also an example in which a region called a surface drop field (RESURF) region is provided in the peripheral region of the semiconductor device to improve the withstand voltage.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2022-56498

[0004] Patent Document 2: Japanese Patent Application Publication No. 2018-46187

[0005] Patent Document 3: Japanese Patent Application Publication No. 2004-349556 Summary of the invention

[0006] An object of the embodiment is to provide a semiconductor device that alleviates electric field concentration in a boundary region between an IGBT and a diode and reduces breakdown.

[0007] The semiconductor device of the embodiment includes a semiconductor substrate, a diode portion arranged on the semiconductor substrate, and an IGBT portion arranged around the diode portion on the semiconductor substrate. The IGBT portion includes a first semiconductor region of a first conductivity type arranged on the semiconductor substrate, a second semiconductor region of a second conductivity type arranged on the first semiconductor region, and a first trench provided in a manner penetrating the second semiconductor region in a depth direction. The diode portion includes a first semiconductor region, a third semiconductor region of a second conductivity type arranged on the first semiconductor region, and a second trench provided in a manner penetrating the third semiconductor region in a depth direction. A fourth semiconductor region of a second conductivity type having a junction depth deeper than the junction depth of the second semiconductor region of the IGBT portion is provided between a first end in a first direction in which the first trench of the IGBT portion extends and a second end in a first direction in which the second trench of the diode portion extends.

[0008] According to the embodiment of the present invention, it is possible to provide a semiconductor device that alleviates electric field concentration in a boundary region between an IGBT and a diode and reduces breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a plan view of the overall structure of the semiconductor device according to the embodiment.

[0010] Figure 2 yes Figure 1 An enlarged top view of a portion of the

[0011] Figure 3 It is along Figure 2 Cross-sectional view of line II.

[0012] Figure 4 It is along Figure 2 Cross-sectional view along line II-II.

[0013] Figure 5 It is along Figure 2 Cross-sectional view along line III-III.

[0014] Figure 6 It is along Figure 2 A cross-sectional view taken along line IV-IV.

[0015] Figure 7 It is along Figure 1 A cross-sectional view of line VV.

[0016] Figure 8 It is a cross-sectional view of a semiconductor device according to a modification of the embodiment.

[0017] Fig. 9 It is a top view of a part of an IGBT of the semiconductor device according to the embodiment.

[0018] Description of symbols

[0019] 1: back electrode (collector, cathode electrode); 2: collector region; 3: cathode region; 4: buffer region; 5: drift region; 6: storage region; 7: base region; 8: emitter region; 9A: anode contact region; 9B: base contact region; 9D: dummy contact region; 9E: emitter contact region; 10: IGBT part; 11: emitter electrode (upper electrode); 12: anode region; 13: interlayer insulating layer; 14: first trench; 14a, 15a, 16a: trench electrodes; 14b, 15b, 16b: insulating film; 14EG: first end ; 15: the third groove (dummy groove); 16: the second groove; 16EG: the second end; 14C1, 16C2: connecting groove; 20: the diode part; 30: the boundary area (dummy part); 33: the N-type semiconductor region; 40: the terminal area; 51, 52, 53, 54: the pad; 70: the fourth semiconductor region; 100, 102, 103: the semiconductor device; 101: the semiconductor substrate; 130: the termination electrode; 220, 230: the surface field reduction area; 240, 250: the floating limiting ring diffusion layer; 260: the termination layer; 500: the control pad part. DETAILED DESCRIPTION

[0020] Next, the embodiments of the present invention are described with reference to the accompanying drawings. In the following description of the accompanying drawings, the same or similar parts are marked with the same or similar reference numerals. However, it should be noted that the accompanying drawings are schematic, and the relationship between the thickness and the plane size, the ratio of the length of each part, etc. are different from the actual. Therefore, the specific dimensions should be determined with reference to the following description. In addition, of course, the drawings also include parts with different relationship and ratio of each other's dimensions.

[0021] In addition, the embodiments shown below illustrate devices for concretizing the technical concept of the present invention, and the technical concept of the present invention does not limit the shape, structure, configuration, etc. of the structural components to the following contents. The embodiments of the present invention can be modified in various ways in the claims. In addition, in the present invention, the terms "upper" and "lower" and the like for determining upper and lower are used for the convenience of recording. Even in the case of being arranged on the side, as long as they are substantially the same as the structural elements of the present invention, they belong to the scope of rights of the present invention. In addition, "upper" includes not only the case of being formed in contact with the object, but also the case of being formed through other layers. In addition, in the present invention, "connection" is not limited to direct connection. Even in the case of connecting with a resistor or the like interposed therebetween, as long as they are substantially the same as the structural elements of the present invention, they belong to the scope of rights of the present invention.

[0022] In the following description, the direction of the semiconductor device is defined by the XYZ axis. In the cross-sectional view, the left-right direction is set as the X-axis direction, the direction perpendicular to the paper is set as the Y-axis direction, and the direction perpendicular to the XY plane is set as the Z-axis direction. In addition, these directions are an example. Depending on the configuration of the pattern, it can be appropriately changed. In addition, in the following description, the semiconductor device is described as centered on the IGBT, but as long as it is a semiconductor device in which a reflux diode is formed on a semiconductor substrate, a MOSFET can be used instead of the IGBT. In addition, it can also be an element with other insulating gate structures such as an electron injection enhanced insulated gate transistor (IEGT: Injection Enhanced Gate Transistor). In addition, it can also be a super junction MOSFET (Super Junction MOSFET) and a complementary metal oxide semiconductor field effect transistor (CMOSFET: Complementary Metal Oxide Semiconductor Field Effect Transistor).

[0023] (Implementation Method)

[0024] Figure 1 It is a plan view of the overall structure of the semiconductor device 100 according to the embodiment.

[0025] like Figure 1As shown, the semiconductor device 100 of the embodiment includes a semiconductor substrate 101, a diode portion 20 arranged on the semiconductor substrate 101, and an IGBT portion 10 arranged around the diode portion 20 on the semiconductor substrate 101. The semiconductor device 100 of the embodiment constitutes a reverse conducting IGBT (RC-IGBT) in which the IGBT portion 10 and the reflux diode portion 20 are formed on one semiconductor substrate 101. A region for improving the withstand voltage, which is called a surface field reduction region, is provided in a terminal region 40 at the peripheral portion of the semiconductor device 100. The IGBT portion 10 is arranged around the diode portion 20 arranged in an island shape on the semiconductor substrate 101. A boundary region 30 is provided around the diode portion 20. The boundary region 30 is also called a dummy region. In addition, Figure 1 In the example shown in FIG. 1 , a control pad portion 500 is further provided on the semiconductor substrate 101. Figure 1 Although not shown in the drawings, an emitter pad 51 is provided on the IGBT unit 10 and / or the diode unit 20 .

[0026] The control pad unit 500 includes, for example, a current sensing pad 50 , a gate pad 52 , and temperature sensing pads 53 and 54 . The current sensing pad 50 is a control pad for detecting a current flowing through a cell region of the semiconductor device 100 .

[0027] The gate pad 52 is a control pad to which a gate driving voltage is applied for on-off control of the semiconductor device 100. The temperature sensing pads 53 and 54 are control pads electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100, for example.

[0028] Figure 2 yes Figure 1 FIG. 1 is an enlarged top view of a portion of the semiconductor device 102. Figure 2 , a diode unit 20, a boundary region (dummy portion) 30 surrounding the diode unit 20, and an IGBT unit 10 surrounding the boundary region 30 are shown. The inside of the dotted line FLR indicates a region where a fourth semiconductor region (FLR region) described later is provided (with or without a boundary line of the fourth semiconductor region). The dotted line DMY1 indicates a boundary line between the diode unit 20 and the boundary region 30. In addition, the dotted line DMY2 indicates a boundary line between the IGBT unit 10 and the boundary region 30.

[0029] In the IGBT unit 10 , a plurality of trenches 14 extend in a first direction (longitudinal direction, Y direction) and are arranged in parallel in a second direction (shortitudinal direction, X direction). Some trenches 14 are connected to trenches 15 in the boundary region 30 in the Y direction.

[0030] A connection groove 16C2 extending in the second direction perpendicular to the Y direction is provided at the end of the groove 16 in the diode portion 20. The plurality of grooves 16 extend in the Y direction, are arranged in parallel in the second direction (short side direction, X direction), and terminate in a T-shaped structure in the connection groove 16C2.

[0031] In the portion of the boundary region 30 between the diode portion 20 and the IGBT portion 10 viewed from the diode portion 20 in the Y direction, the trench 15 is provided with an end portion separated from the trench 16 and the connection trench 16C2 of the diode portion 20 located on the extension line in the Y direction. A connection trench 15C1 extending in the X direction is provided at the end portion in the Y direction of the trench 15 in the boundary region 30. In the boundary region 30, the plurality of trenches 15 extend in the Y direction and terminate in a T-shaped structure in the connection trench 15C1.

[0032] The first end 15EG in the Y direction extending from the groove 15 is connected to the first end 15EG in the Y direction extending from the adjacent groove 15 via the connecting groove 15C1.

[0033] The second end 16EG in the Y direction extending from the groove 16 is connected to the second end 16EG in the Y direction extending from the adjacent groove 16 via the connecting groove 16C2.

[0034] A distance Y1 between a first end 15EG in the Y direction extending from the groove 15 and a second end 16EG in the Y direction extending from the groove 16 is equal to or smaller than a distance X1 between adjacent grooves 15 in the X direction of the grooves 15 in the boundary region 30. That is, Y1≤X1 holds.

[0035] In addition, if Figure 2 As shown, in the portion of the boundary region 30 between the diode portion 20 and the IGBT portion 10 viewed from the diode portion 20 along the X direction, the plurality of trenches 15 extend in the Y direction and are arranged in parallel in the second direction (short side direction, X direction). Furthermore, the plurality of trenches 15 in the boundary region 30 are respectively connected to the plurality of trenches 14 of the IGBT portion 10 existing in the Y direction, and the trenches 15 and the trenches 14 are continuous.

[0036] The distance from the P-type fourth semiconductor region 70 with a lower impurity concentration in the boundary region 30 to the emitter region 8 of the IGBT portion 10 on the diode portion 20 side is formed such that the distance WL in the long side direction (Y direction) of the groove 14 is longer than the distance WS in the short side direction (X direction) of the groove 14 of the IGBT portion 10. That is, WL>WS holds. When viewed from the diode portion 20, the emitter region 8 in the X direction (WS) has a plurality of grooves 15 between the diode portion 20, and the grooves 15 can prevent electrons from diffusing from the emitter region to the diode portion 20 side, and can make the distance WS shorter than the distance WL.

[0037] In the IGBT part 10, a hole is provided in the P base region 7 sandwiched by the trenches 14 in the X direction, and the hole extends in the Y direction. A P-type emitter contact region 9E is formed below the bottom of the hole and in the Z direction of the P base region 7. The n emitter region 8 is formed in the opening of the trench 14, and the n emitter region 8 is exposed on the side of the hole. Figure 2 As shown, the n emitter regions 8 are adjacent to the trench 14 and are discretely arranged in the Y direction. The n emitter regions 8 are arranged at regular intervals in the Y direction, but they do not necessarily need to be arranged regularly in the Y direction. The n emitter regions 8 may also be arranged intermittently. In this way, the IGBT portion 10 may also include a region where the n emitter regions 8 are arranged and a region where the n emitter regions 8 are not arranged. In the IGBT portion 10, the n emitter regions 8 are intermittently arranged, thereby suppressing excessive electron injection and shortening the switching time.

[0038] Figure 3 It is along Figure 2 A cross-sectional view of line II. Figure 3 , a cross-sectional structure along the XZ plane that spans the diode unit 20, the boundary region 30, and the IGBT unit 10 is shown. Figure 3 In FIG. 1 , a dotted line DMY1 extending in the Z direction indicates a boundary line between the diode unit 20 and the boundary region 30. In addition, a dotted line DMY2 extending in the Z direction indicates a boundary line between the IGBT unit 10 and the boundary region 30. Figure 2 In FIG. 1 , a portion of the groove 14 along the II line is omitted, but in FIG. Figure 3 5 are shown.

[0039] like Figure 3 As shown, the semiconductor substrate 101 has, for example, an N-type high-resistance drift region 5, an N-type accumulation region 6 formed along the Z direction on the drift region 5 and having a higher impurity concentration than the drift region 5, a P-type base region 7 and an anode region 12 formed along the Z direction on the accumulation region 6, an N-type buffer region 4 formed below the drift region 5 (negative Z direction), and a P-type collector region 2 and an N-type cathode region 3 formed below the buffer region 4 (negative Z direction).

[0040] The diode portion 20 includes an N-type high-resistance drift region 5, an N-type storage region 6 arranged on the drift region 5, a P-type anode region 12 provided on the storage region 6, and a groove 16 provided so as to penetrate the anode region 12 in the depth direction (Z direction).

[0041] In the diode part 20, the anode region 12 is sandwiched by the groove 16 extending in the Y direction and extends in the Y direction. In addition, a hole is formed in the Z direction of the anode region 12, and a P-type anode contact region 9A is provided at the bottom. An emitter electrode (upper electrode) 11 is provided inside the hole, and the anode contact region 9A is connected to the emitter electrode (upper electrode) 11. The groove 16 has an in-groove electrode 16a and an insulating film 16b. The in-groove electrode 16a is connected to the emitter electrode (upper electrode) 11. In addition, the groove 16 penetrates the anode region 12, but does not penetrate the storage region 6.

[0042] In the boundary region 30, an N-type accumulation region 6 is arranged on the drift region 5, and the base region 7 is sandwiched by the groove 15 extending in the Y direction and extends in the Y direction. In addition, a P-type dummy contact region 9D is arranged in the Z direction of the base region 7. The dummy contact region 9D connected to the base region 7 is connected to the emitter electrode (upper electrode) 11. The groove 15 has an intra-groove electrode 15a and an insulating film 15b. The intra-groove electrode 15a is electrically connected to the intra-groove electrode 14a of the IGBT part 10. In the Z direction of the base region 7, unlike the IGBT part 10, there is no emitter region 8 connected to the groove 15. The groove 15 penetrates the base region 7, but does not penetrate the accumulation region 6.

[0043] The IGBT portion 10 includes an N-type drift region 5, an N-type accumulation region 6 disposed on the drift region 5, a P-type base region 7 disposed on the accumulation region 6, and a trench 14 disposed so as to penetrate the base region 7 in the depth direction (Z direction). Here, the trench 14 does not penetrate the accumulation region 6.

[0044] In the IGBT portion 10, the base region 7 is sandwiched by the grooves 14 extending in the Y direction and extends in the Y direction. In addition, in the Z direction of the base region 7, the emitter region 8 is provided in contact with the groove 14. In addition, a hole is engraved in the Z direction of the base region 7, and a P-type emitter contact region 9E is arranged at the bottom. The emitter contact region 9E extends in the Y direction on the base region 7 sandwiched by the grooves 14. The emitter region 8 and the emitter contact region 9E are connected to the emitter electrode (upper electrode) 11. The groove 14 has an intra-trench electrode 14a and an insulating film 14b. The intra-trench electrode 14a and Figure 2 The gate pad 52 is electrically connected.

[0045] An N-type emitter region 8 and a P-type emitter contact region 9E are formed in the base region 7 sandwiched by the trenches 14 in the X direction. Fig. 9 This will be described later.

[0046] The back electrode 1 provided in the negative Z direction of the semiconductor substrate 101 becomes a collector electrode connected to the P-type collector region 2 in the IGBT portion 10, and becomes a cathode electrode connected to the N-type cathode region 3 in the diode portion 20. Figure 3 In the example of , the boundary line BL between the collector region 2 and the cathode region 3 is set on the boundary line between the diode portion 20 and the boundary region 30. The boundary line between the diode portion 20 and the boundary region 30 is indicated by a dotted line DMY1. In addition, as indicated by a dotted line BLC1, the boundary line BL between the collector region 2 and the cathode region 3 may also be set in the boundary region 30. In addition, as indicated by a dotted line BLC2, the boundary line BL between the collector region 2 and the cathode region 3 may also be set in the IGBT portion 10. In addition, as indicated by a dotted line BLA, the boundary line BL between the collector region 2 and the cathode region 3 may also be set in the diode portion 20. In this way, the relative area between the P-type collector region 2 and the N-type cathode region 3 changes according to the position of the boundary line BL between the collector region 2 and the cathode region 3. Therefore, the amount of carrier injection changes, and therefore, the switching characteristics of the semiconductor device 100 as an RC-IGBT can be appropriately changed according to the application.

[0047] Figure 4 It is along Figure 1 The cross-sectional view of the II-II line. Figure 4 , a cross-sectional structure along the YZ plane is shown, which spans the diode portion 20, the boundary region (dummy portion) 30, and the region where the emitter electrode 11 of the IGBT portion 10 is connected to the P-type emitter contact region 9E. Figure 4 In FIG. 1 , a dotted line DMY1 extending in the Z direction indicates a boundary line between the diode unit 20 and the boundary region 30 . In addition, a dotted line DMY2 extending in the Z direction indicates a boundary line between the IGBT unit 10 and the boundary region 30 . Figure 4 In the figure, the dotted line FLR extending in the Z direction represents the boundary of the fourth semiconductor region 70. The fourth semiconductor region 70 is formed on the inner side of the region divided by the dotted line FLR. That is, the fourth semiconductor region 70 is formed not only directly below the base region 7 of the boundary region 30 sandwiched between the connecting groove 15C1 and the connecting groove 16C2, but also extends a portion directly below the base region 7 of the boundary region 30 closer to the negative Y direction than the side wall of the connecting groove 15C1, and also extends a portion directly below the anode region 12 of the diode portion 20 closer to the Y direction than the side wall of the connecting groove 16C2. In addition, the dotted line DL schematically represents the depletion layer in a thermal equilibrium state extending in the N-type semiconductor region 6. The connecting groove 15C1 of the boundary region 30 has an in-groove electrode 15a and an insulating film 15b. The connecting groove 16C2 of the diode portion 20 has an in-groove electrode 16a and an insulating film 16b. As shown in FIG. Figure 4As shown, it can be seen that the provision of the fourth semiconductor region 70 reduces the penetration of the depletion layer in the Z direction into the region sandwiched between the connection trench 15C1 and the connection trench 16C2.

[0048] Furthermore, an anode contact region 9A is formed in the base region 7 between the connection trench 15C1 and the connection trench 16C2 , and the anode contact region 9A is electrically connected to the emitter electrode 11 .

[0049] Figure 5 It is along Figure 1 The cross-sectional view of the III-III line. Figure 5 , a cross-sectional structure spanning the diode portion 20, the dummy portion 30, and the IGBT portion 10 is shown. That is, a cross-sectional structure along the YZ plane of the trench 14 and the trench 16 is shown. Figure 5 In FIG. 1 , a dotted line DMY1 extending in the Z direction indicates a boundary line between the diode unit 20 and the boundary region 30 . In addition, a dotted line DMY2 extending in the Z direction indicates a boundary line between the IGBT unit 10 and the boundary region 30 . Figure 5 In FIG. 1 , a dotted line FLR extending in the Z direction indicates a boundary of the fourth semiconductor region 70. In addition, a dotted line DL schematically indicates a depletion layer in a thermal equilibrium state extending in the N-type semiconductor region 6.

[0050] like Figure 5 As shown, a second conductive type fourth semiconductor region 70 having a junction depth deeper than the junction depth of the P anode region 12 of the diode portion 20 is provided between the first end 15EG in the Y direction of the trench 15 extending in the boundary region 30 and the second end 16EG in the Y direction of the trench 16 extending in the diode portion 20. Figure 5 As shown, it can be seen that the fourth semiconductor region 70 is provided to reduce the penetration of the depletion layer in the Z direction into the region where the trench is not formed between the longitudinal direction of the trench 15 and the longitudinal direction of the trench 16 .

[0051] Figure 6 It is along Figure 1 A cross-sectional view of the IV-IV line. Figure 6 , a cross-sectional structure spanning the diode portion 20, the boundary region 30, and the IGBT portion 10 is shown. That is, a cross-sectional structure along the YZ plane along the anode region 12, the fourth semiconductor region 70, and the P base region 7 is shown. In addition, the dotted line DL schematically represents a depletion layer in a thermal equilibrium state extending in the N-type semiconductor region 6. Figure 6 As shown, it can be seen that the provision of the fourth semiconductor region 70 reduces the penetration of the depletion layer in the Z direction into the region sandwiched between the connection trench 15C1 and the connection trench 16C2.

[0052] The impurity concentration NP(70) of the fourth semiconductor region 70 is lower than the impurity concentration NP(7) of the second semiconductor region (base region) 7. That is, NP(70) < NP(7) holds. In addition, the impurity concentration NP(70) of the fourth semiconductor region 70 is lower than the impurity concentration NP(12) of the third semiconductor region 12. That is, NP(70) < NP(12) holds.

[0053] In addition, as Figure 6 shown, the junction depth Z4 of the fourth semiconductor region 70 is deeper than the junction depth Z3 of the third semiconductor region 12.

[0054] In addition, the junction depth Z4 of the fourth semiconductor region 70 is shallower than the depth ZT1 of the trench 14 of the IGBT section 10.

[0055] In addition, the junction depth Z4 of the fourth semiconductor region 70 is shallower than the depth ZT2 of the trench 16 of the diode section 20.

[0056] In the semiconductor device 100 of the embodiment, the diode section 20 is formed in an island shape, and the IGBT section 10 is formed around the diode section 20. In addition, the portion of the dummy section 30 extending from the IGBT section 10 having the trench 15 is continuous from the trench 14. Therefore, in the following description, the trench 14 of the IGBT section (including the dummy section) 10 will be described. The trench 14 of the dummy section 30 does not have an emitter region 8, but the trench 14 of the IGBT section 10 has an emitter region 8.

[0057] The long side direction of the trench 14 of the IGBT section (including the dummy section) 10 in which the trench electrode 14a is buried inside with the insulating film 14b interposed therebetween and the long side direction of the trench 16 of the diode section 20 in which the trench electrode 16a having the same potential as the emitter electrode 11 is buried with the insulating film 16b interposed therebetween are formed in the same Y direction, but the two trenches are separated from each other. Preferably, the trench 16 of the diode section 20 is arranged on the extension line of the long side direction of the trench 14 of the IGBT section (including the dummy section) 10. Thereby, when viewed from above, the electric field concentration in the boundary region 30 can be alleviated, and the expansion of the depletion layer can be made gentle.

[0058] In addition, the distance Y1 between the first end 14EG in the long side direction of the trench 14 of the IGBT section (including the dummy section) 10 and the second end 16EG in the long side direction of the trench 16 of the diode section 20 is preferably equal to or less than the distance (trench pitch of the IGBT section 10) X1 between adjacent trenches in the short side direction (X direction) of the same trench 14 of the IGBT section (including the dummy section) 10.

[0059] A P-type semiconductor region (FLR region: fourth semiconductor region 70) having an impurity concentration lower than that of the P base region 7 of the IGBT portion 10 is formed in the N-type drift region 5 in the boundary region 30 between the first end 14EG in the long side direction of the groove 14 of the IGBT portion (including the dummy portion) 10 and the second end 16EG in the long side direction of the groove 16 of the diode portion 20.

[0060] As a result, the depletion layer is reduced from entering the storage region 6 in the Z direction under the base region 7 reaching the first end 14EG in the long-side direction of the trench 14 and the second end 16EG in the long-side direction of the trench 16. Furthermore, the depletion layer of the semiconductor region including the fourth semiconductor region 70 in the boundary region 30 between the first end 14EG in the long-side direction of the trench 14 of the IGBT portion (including the dummy portion) 10 and the second end 16EG in the long-side direction of the trench 16 of the diode portion 20 can be more easily expanded.

[0061] In addition, it is preferable that the junction depth of the P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 is deeper than the junction depth of the base region 7 of the IGBT unit 10, and deeper than the junction depth of the anode region 12 of the diode unit 20. However, the P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 does not have to be deep enough to reach the bottom (trench depth) of the trenches of the IGBT unit 10 and the diode unit 20. This is to shift the breakdown point from the boundary region 30 to the IGBT unit 10 side.

[0062] The P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 is formed to a position closer to the inside (toward the IGBT portion 10 side, i.e., in the negative Y direction) than the first end 14EG of the trench 14 in such a manner as to include the first end 14EG of the trench 14 of the IGBT portion (including the dummy portion) 10. Similarly, the fourth semiconductor region 70 is formed to a position closer to the inside (in the Y direction) of the diode portion 20 than the second end 16EG of the trench 16 in such a manner as to include the second end 16EG of the trench 16 of the diode portion 20.

[0063] The first end 15EG of the groove 15 is connected to the first end 15EG of the adjacent groove 15 through the connecting groove 15C1. That is, the first end 15EG of the groove 15 is T-shaped. Moreover, the adjacent groove electrode 14a in the IGBT part 10 is connected via the groove electrode 15a in the groove 15 and the groove electrode 15a in the connecting groove 15C1. As a result, it is also possible not to form a gate bus on the semiconductor substrate 101 in the boundary area 30, and when the upper electrode 11 on the semiconductor substrate 101 is continuously formed from the IGBT part 10 to the diode part 20, it will not be hindered by the gate bus. In addition, the groove electrode 15a and the groove electrode 16a extend in the X direction, thereby making it possible to make the electric field distribution in the X direction of the area sandwiched by the connecting groove 15C1 and the connecting groove 16C2 more uniform.

[0064] like Figure 2 As shown, when observed from the dotted line FLR (the fourth semiconductor region 70), in the short side direction (X direction) of the groove 14 of the IGBT portion 10, a dummy trench 15 in which the emitter region 8 is not formed is arranged parallel to the groove 14 of the IGBT portion 10 between the P-type fourth semiconductor region 70 with a lower impurity concentration in the boundary region 30 and the emitter region 8 in such a manner that the P-type fourth semiconductor region 70 with a lower impurity concentration in the boundary region 30 is not connected to (does not reach) the emitter region 8.

[0065] The boundary BL between the P collector region 2 and the N cathode region 3 is formed in the approximate Z direction of the boundary region 30, but the boundary BL between the P collector region 2 and the N cathode region 3 may not be formed directly below the boundary region 30, and may be offset. For example, the boundary BL between the P collector region 2 and the N cathode region 3 may be located closer to the diode portion 20 than directly below the boundary region 30. Alternatively, it may be located on the IGBT portion 10 side.

[0066] The P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 is connected to the upper electrode (emitter electrode) 11 .

[0067] (Surface field structure)

[0068] Figure 7 It is along Figure 1 A cross-sectional view of line EE.

[0069] The semiconductor device 100 of the embodiment has a first surface field reduction region 220 and a second surface field reduction region 230 in the terminal region 40. The first surface field reduction region 220 is connected to the P base region 7 to improve the withstand voltage. The second surface field reduction region 230 is connected to the first surface field reduction region 220 via a depletion layer. The dotted line BLL extending in the Z direction represents the boundary line between the IGBT portion 10 and the terminal region 40. The back electrode 1 is connected to the P-type collector region 2 of the IGBT portion 10. In addition, the back electrode 1 is connected to the N-type semiconductor region 33 of the terminal region 40. The N-type semiconductor region 33 and the cathode region 3 of the diode portion 20 are at the same potential. In addition, the N-type semiconductor region 33 and the N-type stopper layer 260 of the terminal portion are at the same potential. The boundary between the P-type collector region 2 of the IGBT portion 10 and the N-type semiconductor region 33 is represented by BL3.

[0070] The semiconductor substrate 101 has an N-type drift region 5 constituting one surface thereof. A plurality of surface field reduction regions 220 and 230 are formed of a P-type semiconductor region having a lower impurity concentration than the P-base region 7, and are formed in the surface region of the drift region 5 so as to surround the IGBT portion 10. The surface field reduction regions 220 and 230 are formed simultaneously with the P-type fourth semiconductor region 70 having a lower impurity concentration in the boundary region 30, and therefore, the junction depth is formed to be shallower than the trench 14 and deeper than the P-base region 7.

[0071] Floating limiting ring diffusion layers 240 and 250 are arranged on the outer periphery of the second surface field lowering region 230. In addition, an N-type stopper layer 260 is arranged at the terminal portion. The stopper layer 260 is connected to a stopper electrode 130.

[0072] The floating limiting ring diffusion layers 240 and 250 are provided to smooth the shape of the depletion layer and alleviate the electric field concentration. The floating limiting ring diffusion layers 240 and 250 are formed of a P-type diffusion layer that is equal to or shallower than the surface field reduction regions 220 and 230. In addition, the impurity concentration of the floating limiting ring diffusion layers 240 and 250 is set to be equal to or higher than the impurity concentration of the surface field reduction regions 220 and 230.

[0073] The fourth P-type semiconductor region 70 having a low impurity concentration in the boundary region 30 can be formed simultaneously with the first surface field reduction region 220 and the second surface field reduction region 230. Therefore, even if the fourth P-type semiconductor region 70 having a low impurity concentration in the boundary region 30 is additionally formed, the increase in man-hours caused thereby can be suppressed.

[0074] The semiconductor device 100 according to the embodiment includes the surface field reduction regions 220 and 230 , and thus can relatively easily achieve a high withstand voltage.

[0075] (Variation Example)

[0076] Figure 8 The semiconductor device 103 of the modified example of the embodiment Figure 3 Corresponding cross-sectional view. In the semiconductor device 103 of the modified example of the embodiment, the P base region 7 of the boundary region 30 and the upper electrode (emitter electrode) 11 may be connected via a resistor R. In addition, the P base region 7 of the IGBT portion 10 near the boundary region 30 and the upper electrode (emitter electrode) 11 may also be connected via a resistor R. In addition, the P anode region 12 of the diode portion 20 near the boundary region 30 and the upper electrode (emitter electrode) 11 may also be connected via a resistor R.

[0077] The P-type fourth semiconductor region 70 with a low impurity concentration in the boundary region 30 can be connected to the upper electrode (emitter electrode) 11 via a resistor. For example, the P-type fourth semiconductor region 70 has a low impurity concentration and is connected to the upper electrode 11 with a relatively large contact resistance. Therefore, when the diode portion 20 is turned on, the amount of holes injected from the P-type fourth semiconductor region 70 in the boundary region 30 to the N-type drift region 5 can be reduced, thereby shortening the reverse recovery time of the diode portion 20.

[0078] (Emitter contact structure)

[0079] Fig. 9 It is a top view of a part of the semiconductor device according to the embodiment.

[0080] In the IGBT portion 10, the P base region 7 is sandwiched by the trenches 14 extending in the Y direction and extends in the Y direction. In addition, the n emitter region 8 is arranged in contact with the trenches 14 in the Z direction of the P base region 7. In addition, there is a hole between the adjacent trenches 14, and a P-type emitter contact region 9E is arranged under the bottom of the hole and in the Z direction of the P base region 7. The P-type emitter contact region 9E extends in the Y direction on the P base region 7 sandwiched by the trenches 14. The n emitter region 8 exposed on the side of the hole and the emitter contact region 9E at the bottom of the hole are connected to the emitter electrode (upper electrode) 11 buried in the hole.

[0081] A structure consisting of n emitter region 8 / base region 7 / n emitter region 8 exposed on the side of the hole in the Y direction where the P-type emitter contact region 9E is formed is formed. This structure is arranged on the ZY plane of the hole. The n emitter region 8 does not necessarily need to be arranged regularly in the Y direction. By intermittently arranging the n emitter region 8 in the IGBT unit 10, it is possible to suppress excessive electron injection and shorten the switching time.

[0082] (Other embodiments)

[0083] As described above, the present invention is described through the embodiments, but it should not be understood that the discussion and drawings that constitute a part of this disclosure limit the present invention. Based on the present disclosure, a person skilled in the art can clearly identify various alternative embodiments, examples, and application technologies. In this way, the present invention certainly includes various embodiments and the like that are not described herein. Therefore, the technical scope of the present invention is determined only by the specific matters of the invention of the appropriate claims according to the above description. For example, an example in which the grooves 14, 15, and 16 do not penetrate the accumulation region 6 is shown, but it is also possible that at least one groove penetrates the accumulation region 6, and the accumulation region 6 may not be provided in any of the IGBT portion 10, the diode portion 20, and the dummy portion 30.

Claims

1. A semiconductor device, wherein: The semiconductor device has: Semiconductor substrate; a diode portion disposed on the semiconductor substrate; and an IGBT portion disposed around the diode portion on the semiconductor substrate, The IGBT unit has: a first semiconductor region of a first conductivity type, disposed on the semiconductor substrate; a second semiconductor region of a second conductivity type, disposed on the first semiconductor region; as well as a first trench provided so as to penetrate the second semiconductor region in a depth direction; The diode unit has: the first semiconductor region; a third semiconductor region of the second conductivity type, disposed on the first semiconductor region; and a second trench provided so as to penetrate the third semiconductor region in a depth direction, A second conductivity type fourth semiconductor region having a junction depth deeper than that of the second semiconductor region of the IGBT portion is provided between a first end in a first direction in which the first trench of the IGBT portion extends and a second end in the first direction of the second trench of the diode portion.

2. The semiconductor device according to claim 1, wherein The impurity concentration of the fourth semiconductor region is lower than the impurity concentration of the second semiconductor region.

3. The semiconductor device according to claim 1, wherein The impurity concentration of the fourth semiconductor region is lower than the impurity concentration of the third semiconductor region.

4. The semiconductor device according to claim 1, wherein The junction depth of the fourth semiconductor region is deeper than the junction depth of the third semiconductor region.

5. The semiconductor device according to claim 1, wherein The second trench of the diode portion is arranged on an extension line of the first trench of the IGBT portion in the first direction.

6. The semiconductor device according to claim 1, wherein A distance between the first end of the IGBT portion in the first direction extending from the first trench and the second end of the second trench of the diode portion in the first direction is equal to or smaller than a distance between adjacent first trenches of the same IGBT portion in the second direction.

7. The semiconductor device according to claim 1, wherein A junction depth of the fourth semiconductor region is shallower than a depth of the first trench of the IGBT portion.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The semiconductor device includes a first connection trench extending in a second direction perpendicular to the first direction. The first end of the IGBT portion extending from the first trench in the first direction is connected to the first end extending from the adjacent first trench in the first direction via the first connection trench. The semiconductor device includes a second connection trench extending in the second direction. The second end of the diode portion extending from the second trench in the first direction is connected to the second end extending from the adjacent second trench in the first direction via the second connection trench.

9. The semiconductor device according to claim 1, wherein: The semiconductor device includes a fifth semiconductor region disposed on the second semiconductor region.

10. The semiconductor device according to claim 9, wherein When viewed from the diode portion side, a distance between the fourth semiconductor region and the fifth semiconductor region in the first direction along the first trench is longer than a distance between the fourth semiconductor region and the fifth semiconductor region in a second direction perpendicular to the first direction.

11. The semiconductor device according to claim 9, wherein The fifth semiconductor region is intermittently arranged on the second semiconductor region extending in the first direction.

12. The semiconductor device according to claim 9, wherein: When viewed from the diode portion side, a third trench provided in parallel with the first trench is provided between the fourth semiconductor region and the fifth semiconductor region.

13. The semiconductor device according to claim 1, wherein The semiconductor device comprises: a fifth semiconductor region disposed on the second semiconductor region; and an upper electrode electrically connected to the fifth semiconductor region, The fourth semiconductor region is electrically connected to the upper electrode via a resistor.

14. The semiconductor device according to claim 1, wherein The semiconductor device includes a surface field reduction region at the peripheral portion. The fourth semiconductor region can be formed simultaneously with the surface field reduction region.

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