Superlattice cap layer gallium nitride high electron mobility transistor and preparation method thereof

Abstract

The present invention belongs to the field of microelectronics research, and provides a superlattice cap layer gallium nitride high electron mobility transistor and a preparation method thereof, comprising a substrate, a nucleation layer and a GaN buffer layer arranged in sequence from bottom to top, a source electrode and a drain electrode arranged on the GaN buffer layer, and an AlN insertion layer, an AlGaN barrier layer and a superlattice cap layer arranged in sequence from bottom to top between the source electrode and the drain electrode; the GaN buffer layer, the AlN insertion layer and the AlGaN barrier layer form a heterojunction, the superlattice cap layer comprises a plurality of groups of overlappingly grown GaN cap layers and SiN cap layers, the superlattice cap layer is provided with a gate electrode, and the gate electrode is located between the source electrode and the drain electrode, and a SiO2 passivation layer is arranged between the gate electrode and the source electrode and the drain electrode. Based on the superlattice cap layer technology, the present invention can solve the problem that crystalline SiN cannot grow too thick, can reduce device leakage and increase breakdown voltage, thereby improving device performance.

Description

Technical Field

[0001] The invention belongs to the field of microelectronics research, and in particular relates to a superlattice cap layer gallium nitride high electron mobility transistor and a preparation method thereof. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] GaN high electron mobility transistor (HEMT) devices have broad prospects in high-frequency and high-power applications, and their excellent performance characteristics make them one of the main candidates for the next generation of RF and power electronic devices. However, there are still some problems in practical applications, such as leakage current, breakdown voltage and reliability.

[0004] By growing a gate dielectric layer such as SiO2, Al2O3 and Si3N4, the gate electrode leakage current can be effectively reduced and the breakdown voltage can be increased. However, the introduction of the gate dielectric layer often introduces new interface states, affecting the interface quality. In addition, the gate dielectric layer requires atomic layer deposition ALD coating equipment, plasma enhanced chemical vapor deposition equipment PECVD, etc. for growth, which increases the process cost. In-situ growth technology refers to continuous growth without changing equipment and growth chambers during the experiment, which avoids contact with the atmospheric environment during the sample growth process, thereby avoiding oxidation and contamination of the sample.

[0005] For GaN HEMT, in-situ SiN growth technology has been widely used in the preparation of dielectric layers and passivation layers, but most in-situ SiN films are amorphous, so it is impossible to continue to grow single crystal films on them. By optimizing the in-situ SiN growth process, it has been reported that in-situ SiN crystalline growth can be achieved on AlGaN barrier layers. Limited by the lattice mismatch between SiN and GaN-based materials, crystalline SiN cannot grow too thick (less than 2 nm) and the growth rate is slow. Summary of the invention

[0006] In order to solve the above problems, the present invention proposes a superlattice cap layer gallium nitride high electron mobility transistor and a preparation method thereof. The present invention is based on superlattice cap layer technology, which can solve the problem that crystalline SiN cannot grow too thick, can reduce device leakage and increase breakdown voltage, thereby improving device performance.

[0007] According to some embodiments, the present invention adopts the following technical solutions:

[0008] A superlattice cap layer gallium nitride high electron mobility transistor, comprising: a substrate, a nucleation layer and a GaN buffer layer arranged in sequence from bottom to top;

[0009] A source electrode and a drain electrode are arranged on the GaN buffer layer, and an AlN insertion layer, an AlGaN barrier layer and a superlattice cap layer are arranged in sequence from bottom to top between the source electrode and the drain electrode;

[0010] The GaN buffer layer, the AlN insertion layer and the AlGaN barrier layer form a heterojunction, and the superlattice cap layer includes a plurality of groups of overlappingly grown GaN cap layers and SiN cap layers;

[0011] The superlattice cap layer is provided with a gate electrode, and the gate electrode is located between the source electrode and the drain electrode, and a SiO2 passivation layer is provided between the gate electrode and the source electrode and the drain electrode.

[0012] As an optional implementation, the material of the substrate is SiC, Si or sapphire.

[0013] As an optional implementation, the nucleation layer is AlN or AlGaN, and the thickness of the nucleation layer is 50-5000 nm.

[0014] As an optional implementation manner, the thickness of the GaN buffer layer is 1-10 μm, and the GaN buffer layer is not doped.

[0015] As an optional embodiment, the thickness of the AlN insertion layer is 0.5 ~ 5 nm.

[0016] As an optional implementation manner, the thickness of the AlGaN barrier layer is 10-50 nm, and the molar ratio of Al is 15-25%.

[0017] As an optional implementation manner, the number of groups of the superlattice cap layer is 1 to 10, wherein the thickness of the GaN cap layer is 0.2 to 100 nm, and the thickness of the SiN cap layer is 0.2 to 100 nm.

[0018] As an optional implementation, the SiO2 passivation layer has a thickness of 100-1000 nm.

[0019] As an optional implementation manner, the distance between the source electrode and the drain electrode ranges from 3 to 100 μm.

[0020] As an optional implementation, the length of the gate electrode is 1-100 μm, the distance between the gate electrode and the source electrode is in the range of 1-100 μm, and the distance between the gate electrode and the drain electrode is in the range of 1-100 μm.

[0021] The method for preparing the superlattice cap layer gallium nitride high electron mobility transistor comprises the following steps:

[0022] (1) growing a nucleation layer, a GaN buffer layer, an AlN insertion layer, an AlGaN barrier layer and a superlattice cap layer on a substrate in sequence, wherein the superlattice cap layer is grown in situ;

[0023] (2) Etching away the superlattice cap layer in the area where the source electrode and drain electrode need to be grown;

[0024] (3) growing a source electrode and a drain electrode on the etched area and performing annealing;

[0025] (4) After the ohmic contact device is prepared, the gate electrode is prepared;

[0026] (5) A SiO2 passivation layer is grown on the surface of the device with the gate electrode prepared, and holes are etched in the electrode area to obtain a superlattice cap layer gallium nitride high electron mobility transistor.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention can increase the Schottky barrier height of the device gate electrode through the superlattice cap layer structure. The increase in the Schottky barrier height reduces the tunneling probability of electrons, thereby reducing the gate electrode leakage current;

[0029] The present invention sets an in-situ superlattice cap layer, and performs single crystal epitaxial growth on the basis of the AlGaN barrier layer. The interface of coherent growth will significantly reduce the interface state density and greatly improve the interface quality. Simulation results show that the superlattice cap layer provided by the present invention has a good voltage division effect, and the formed device has good transfer characteristics.

[0030] The present invention can significantly improve the breakdown characteristics of the device through the superlattice cap layer structure, and the superlattice cap layer structure is in-situ grown, thereby reducing the process cost.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0033] Figure 1 A schematic diagram of a superlattice cap layer (GaN / SiN×3) structure device according to an embodiment;

[0034] Figure 2 A comparison diagram of energy band simulation of a superlattice cap layer (GaN / SiN×3) structure and a traditional GaN cap layer structure device in one embodiment;

[0035] Figure 3 A transfer curve simulation comparison diagram of a superlattice cap layer (GaN / SiN×3) structure and a traditional GaN cap layer structure device in one embodiment;

[0036] Figure 4 A comparison diagram of the breakdown characteristics of a superlattice cap layer (GaN / SiN×3) structure and a conventional GaN cap layer structure device according to an embodiment;

[0037] Figure 5 The electric field distribution (V) of the channel cross section of a superlattice cap layer (GaN / SiN×3) structure and a conventional GaN cap layer structure device in an embodiment is shown in FIG. DS = 400 V) simulation comparison diagram.

[0038] Among them, 1. substrate, 2. nucleation layer, 3. GaN buffer layer, 4. AlN insertion layer, 5. AlGaN barrier layer, 6. GaN cap layer, 7. SiN cap layer, 8. SiO2 passivation layer, 9. superlattice cap layer, 10. source electrode, 11. drain electrode, 12. gate electrode. DETAILED DESCRIPTION

[0039] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0040] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0041] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0042] In the absence of conflict, the embodiments in this application and the features in the embodiments may be combined with each other.

[0043] Embodiment 1

[0044] A superlattice cap layer gallium nitride high electron mobility transistor device, such as Figure 1As shown, it includes, from bottom to top, a substrate 1, a nucleation layer 2, a GaN buffer layer 3, an AlN insertion layer 4, an AlGaN barrier layer 5, a GaN cap layer 6, a SiN cap layer 7 and a SiO2 passivation layer 8, wherein the GaN buffer layer, the AlN insertion layer and the AlGaN barrier layer form a heterojunction, and the multiple groups of overlappingly grown GaN cap layers 6 and SiN cap layers 7 form a superlattice cap layer 9; a source electrode 10 and a drain electrode 11 are arranged on the GaN channel layer; a gate electrode 12 is arranged on the GaN cap layer 6, and the gate electrode 12 is located between the source electrode 10 and the drain electrode 11.

[0045] In this embodiment, the number of stacked groups of GaN cap layer 6 and SiN cap layer 7 is 3, referred to as GaN / SiN×3.

[0046] In some preferred embodiments, the material of the substrate 1 includes SiC, Si and sapphire. In this embodiment, the substrate material is SiC.

[0047] In some preferred embodiments, the nucleation layer 2 is made of AlN or AlGaN, and the thickness of the nucleation layer is 50-5000 nm. In this embodiment, the nucleation layer 2 is 100 nm AlN.

[0048] In some preferred embodiments, the thickness of the GaN buffer layer 3 is 1 to 10 μm, and the GaN buffer layer 3 is not doped; in this embodiment, the thickness of the GaN buffer layer 3 is 1.5 μm.

[0049] In some preferred embodiments, the thickness of the AlN insertion layer 4 is 0.5-5 nm; in this embodiment, the thickness of the AlN insertion layer 4 is 1 nm.

[0050] In some preferred embodiments, the thickness of the AlGaN barrier layer 5 is 10-50 nm, and the molar ratio of Al is 15-25%; in this embodiment, the thickness of the AlGaN barrier layer 5 is 20 nm, and the molar ratio of Al is 20%.

[0051] In some preferred embodiments, the number of groups of the superlattice cap layer 9 is 1 to 10, wherein the thickness of the GaN cap layer 6 is 0.2 to 100 nm, and the thickness of the SiN cap layer 7 is 0.2 to 100 nm; in this embodiment, the number of groups of the superlattice cap layer is 3, wherein the thickness of the GaN cap layer is 2 nm, and the thickness of the SiN cap layer is 2 nm.

[0052] In some preferred embodiments, the thickness of the SiO 2 passivation layer 8 is 100-1000 nm; in this embodiment, the thickness of the SiO 2 passivation layer 8 is 250 nm.

[0053] In some preferred embodiments, the distance L between the source electrode 10 and the drain electrode 11 is SD In this embodiment, the distance L between the source electrode 10 and the drain electrode 11 is 3 to 100 μm. SD is 20 μm.

[0054] In some preferred embodiments, the gate electrode 12 has a length L G The distance L between the gate electrode 12 and the source electrode 10 is 1 - 100 μm. GS The distance L between the gate electrode 12 and the drain electrode 11 is 1 - 100 μm. GD In this embodiment, the length L of the gate electrode 12 is 1 - 100 μm. G , the distance L between the gate electrode 12 and the source electrode 10 GS , the distance L between the gate electrode 12 and the drain electrode 11 GD They are 2 μm, 5 μm and 13 μm respectively.

[0055] Embodiment 2

[0056] The method for preparing a superlattice cap layer gallium nitride high electron mobility transistor device as described in the first embodiment comprises the following steps:

[0057] (1) A nucleation layer 2, a GaN buffer layer 3, an AlN insertion layer 4, an AlGaN barrier layer 5 and a superlattice cap layer 9 are sequentially grown on a substrate 1;

[0058] (2) etching away the superlattice cap layer 9 in the region where the source electrode 10 and the drain electrode 11 are to be grown;

[0059] (3) growing a source electrode 10 and a drain electrode 11 on the etched area and performing annealing treatment;

[0060] (4) After the ohmic contact device is prepared, the gate electrode 12 is prepared;

[0061] (5) A SiO2 passivation layer 8 is grown on the surface of the device with the gate electrode 12 prepared, and the electrode region is etched to open a hole, thereby obtaining a superlattice cap layer gallium nitride high electron mobility transistor.

[0062] Embodiment 3

[0063] As a verification of the performance of the superlattice cap layer gallium nitride high electron mobility transistor device provided in the above embodiment, Figure 2As shown, the conventional GaN cap layer (2 nm) structure and the superlattice cap layer (GaN / SiN×3) structure provided in the above embodiment are respectively simulated by TCAD simulation software. As can be seen from the figure, the Schottky barrier height of the conventional GaN cap layer structure at zero bias is 1.24 eV, and the Schottky barrier height of the superlattice cap layer (GaN / SiN×3) structure of the present invention at zero bias is 1.6 eV, which is significantly higher than the conventional cap layer. The increase in the Schottky barrier height reduces the tunneling probability of electrons, thereby reducing the gate leakage current.

[0064] In addition, in order to reduce gate leakage and improve gate withstand voltage, the conventional method is to grow a layer of gate dielectric, such as SiO2, Al2O3 and Si3N4, before the gate metal is grown. However, the non-in-situ growth method will inevitably introduce new interface states, thereby affecting device performance, while the in-situ superlattice cap layer of the present invention is a single crystal epitaxial growth on the basis of the AlGaN barrier layer, and the interface of the coherent growth will significantly reduce the interface state density, greatly improving the interface quality.

[0065] Figure 3 The simulation results of the transfer curves of the conventional GaN cap layer (2 nm) structure and the superlattice cap layer (GaN / SiN×3) structure device of the present invention using TCAD software show that the superlattice cap layer device has good transfer characteristics. The threshold voltage of the conventional GaN cap layer structure device is -3.15 V, and the output voltage of the superlattice cap layer device is -4.81 V, indicating that the superlattice cap layer has a voltage-dividing effect similar to that of the conventional dielectric layer.

[0066] The present invention can significantly improve the device breakdown characteristics through the superlattice cap layer structure. Figure 4 As shown in the figure, the breakdown characteristics of different cap layer devices with a gate-drain spacing of 13 μm were simulated using TCAD simulation software. The results showed that the breakdown voltage of the conventional GaN cap layer (2 nm) structure was 444 V, and the breakdown voltage of the superlattice cap layer (GaN / SiN×3) structure of the present invention was 1145 V, where the device breakdown criterion was the critical breakdown electric field of the GaN material of 3.3 MV / cm (shown by the dotted line in the figure). The superlattice cap layer structure had a significantly improved breakdown voltage (158%) compared to the traditional GaN cap layer.

[0067] Figure 5 This is a comparison diagram of the electric field distribution simulation of the channel cross section of the superlattice cap layer (GaN / SiN×3) structure and the traditional GaN cap layer structure device (V DS = 400 V), it can be seen from the figure that due to the voltage-dividing effect of the superlattice cap layer, under the same drain voltage, the electric field borne by the channel in the superlattice cap layer device is significantly smaller than the electric field borne by the channel in the traditional GaN cap layer device.

[0068] The dielectric layer in the traditional metal-insulator-semiconductor MIS-HEMT needs to be grown using equipment such as vapor phase chemical deposition PECVD and atomic layer deposition ALD, while the superlattice cap layer in the present invention is grown in situ in an organic metal chemical vapor deposition MOCVD device, which greatly reduces the process cost.

[0069] In summary, the solution provided by the present invention has the advantages of increasing the gate Schottky barrier height, reducing gate leakage, reducing interface state density, improving interface quality, increasing breakdown voltage, and reducing process costs.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principle of the present invention without creative labor shall be included in the protection scope of the present invention.

Claims

1. A superlattice cap layer gallium nitride high electron mobility transistor, characterized in that: It includes a substrate, a nucleation layer and a GaN buffer layer which are sequentially arranged from bottom to top; A source electrode and a drain electrode are arranged on the GaN buffer layer, and an AlN insertion layer, an AlGaN barrier layer and a superlattice cap layer are arranged in sequence from bottom to top between the source electrode and the drain electrode; The GaN buffer layer, the AlN insertion layer and the AlGaN barrier layer form a heterojunction, and the superlattice cap layer includes a plurality of groups of overlappingly grown GaN cap layers and SiN cap layers; A gate electrode is arranged on the superlattice cap layer, and the gate electrode is located between the source electrode and the drain electrode, and a SiO2 passivation layer is arranged between the gate electrode and the source electrode and the drain electrode; The number of groups of the superlattice cap layer is 1-10, wherein the thickness of the GaN cap layer is 0.2-100 nm, and the thickness of the SiN cap layer is 0.2-100 nm.

2. A superlattice cap layer gallium nitride high electron mobility transistor as claimed in claim 1, characterized in that: The material of the substrate is SiC, Si or sapphire.

3. The superlattice cap layer gallium nitride high electron mobility transistor according to claim 1, characterized in that: The nucleation layer is AlN or AlGaN, and the thickness of the nucleation layer is 50-5000 nm.

4. The superlattice cap layer gallium nitride high electron mobility transistor according to claim 1, characterized in that: The thickness of the GaN buffer layer is 1-10 μm, and the GaN buffer layer is not doped.

5. The superlattice cap layer gallium nitride high electron mobility transistor according to claim 1, characterized in that: The thickness of the AlN insertion layer is 0.5-5 nm.

6. The superlattice cap layer gallium nitride high electron mobility transistor according to claim 1, characterized in that: The thickness of the AlGaN barrier layer is 10-50 nm, and the molar ratio of Al is 15-25%.

7. The superlattice cap layer gallium nitride high electron mobility transistor according to claim 1, characterized in that: The thickness of the SiO2 passivation layer is 100-1000 nm.

8. The superlattice cap layer gallium nitride high electron mobility transistor according to claim 1, characterized in that: The distance between the source electrode and the drain electrode ranges from 3 to 100 μm; The length of the gate electrode is 1-100 μm, the distance between the gate electrode and the source electrode is in the range of 1-100 μm, and the distance between the gate electrode and the drain electrode is in the range of 1-100 μm.

9. The method for preparing a superlattice cap layer gallium nitride high electron mobility transistor according to any one of claims 1 to 8, characterized in that: The following steps are involved: (1) growing a nucleation layer, a GaN buffer layer, an AlN insertion layer, an AlGaN barrier layer and a superlattice cap layer on a substrate in sequence, wherein the superlattice cap layer is grown in situ; (2) Etching away the superlattice cap layer in the area where the source electrode and drain electrode need to be grown; (3) growing a source electrode and a drain electrode on the etched area and performing annealing; (4) After the ohmic contact device is prepared, the gate electrode is prepared; (5) A SiO2 passivation layer is grown on the surface of the device with the gate electrode prepared, and holes are etched in the electrode area to obtain a superlattice cap layer gallium nitride high electron mobility transistor.

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