Transistor and image sensing device

Abstract

A transistor and an image sensing apparatus are provided. The transistor may be a dual vertical pass transistor. In some embodiments, a gate of a dual vertical pass transistor may include a pair of poles extending to an n-type region of a photodiode and a connection portion connecting the pair of poles to each other. A first insulating pattern may be disposed between the poles and on the substrate.

Description

[0001] This patent application claims the priority of Korean Patent Application No. 10-2023-0084207 filed on June 29, 2023, and Korean Patent Application No. 10-2023-0162743 filed on November 21, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a complementary metal oxide semiconductor (CMOS) image sensing device, and more particularly to a circuit including a transistor having a vertical channel gate and a CMOS image sensing device using the circuit as a unit pixel circuit. In addition, the present disclosure relates to a method for manufacturing a unit pixel circuit having a vertical channel gate and a CMOS image sensing device having the unit pixel circuit. Background Art

[0003] An image sensing device or image sensor is a semiconductor device for converting an optical signal into an electrical signal. The image sensing device may include a wafer and an imaging circuit (eg, a complementary metal oxide semiconductor (CMOS) device or a charge coupled device (CCD)) integrated on the wafer.

[0004] Until the 1990s, CCD image sensors were widely used because their optical characteristics were superior to those of CMOS image sensors (CIS). However, after the introduction of pinned photodiodes (PPDs) and the development of circuit noise reduction technology, CIS devices with simpler structures and easier manufacturing processes are now more widely used. Summary of the invention

[0005] Aspects of the present disclosure provide an image sensing device including a photodiode (PD) having a relatively large charge capacity even when the device size is reduced due to an increased demand for high-density devices.

[0006] Some aspects of the present inventive concept provide a transistor having a gate having a three-dimensional shape, which can improve transfer efficiency of negative charges.

[0007] Some embodiments of the inventive concept provide an image sensing device that prevents a potential hump problem, in which the transfer of negative charges from an inter-pole region to a floating diffusion (FD) region is hindered by an electric field concentrated in the inter-pole region between a pair of poles, and a backflow problem, in which negative charges are transferred from the FD region to the inter-pole region.

[0008] According to some embodiments of the inventive concept, a transistor may include: a first n-type region below a gate; a gate including a pair of gates extending to the n-type region and a connection portion connecting the paired electrodes to each other; a second n-type region adjacent to the gate; and a first insulating pattern arranged between the electrodes and on a substrate. In some embodiments, the first insulating pattern may include a silicon nitride (Si x N y ), silicon oxide (SiO 2 ), a composite layer formed of at least one of silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), and silicon oxycarbon nitride (SiOCN). In some embodiments, the first insulating pattern may include a void.

[0009] According to some embodiments of the inventive concept, a transistor may include: an n-type region of a photodiode, arranged below a gate; a gate, including a pair of poles extending to the n-type region and a connecting portion connecting the pair of poles to each other; a floating diffusion region adjacent to the gate; and a first insulating pattern arranged between the poles and on a substrate.

[0010] According to some embodiments of the inventive concept, a unit circuit may include a first transistor in a first substrate and a second transistor on a second substrate, the first transistor including: a first n-type region; a gate including a pair of poles extending to the first n-type region and a connection portion connecting the paired poles to each other; a second n-type region adjacent to the gate; and a first insulating pattern arranged between the poles and on the first substrate. Here, the second n-type region of the first substrate may be connected to the gate of the second transistor of the second substrate.

[0011] According to some embodiments of the inventive concept, a unit circuit may include a transfer transistor in a first substrate and a source follower transistor on a second substrate, the transfer transistor including: a PD region; a gate including a pair of poles extending to an n-type region of the PD region and a connection portion connecting the paired poles; an FD region adjacent to the gate; and a first insulating pattern arranged between the paired poles and on the first substrate. Here, the FD region of the first substrate may be connected to the gate of the source follower transistor of the second substrate.

[0012] According to some embodiments of the inventive concept, an image sensing device may include: a first substrate including a PD region, a gate, a first insulating pattern, and an FD region, the gate including a pair of poles extending to an n-type region of the PD region and a connecting portion connecting the paired poles, the first insulating pattern being between the poles; a second substrate including a source follower transistor; and a third substrate including a logic circuit. Here, the FD region of the first substrate may be connected to the gate of the source follower transistor of the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view illustrating a 2-stacked CMOS image sensing (CIS) device according to some embodiments of the inventive concept.

[0014] Figure 2 is a cross-sectional view illustrating a 2-stacked CIS device according to some embodiments of the inventive concept.

[0015] Figure 3 is a cross-sectional view of a 3-stack CIS device according to some embodiments of the inventive concept.

[0016] Figure 4 is a cross-sectional view illustrating a 3-stack CIS device according to some embodiments of the inventive concept.

[0017] Figure 5 is a cross-sectional view illustrating a 3-stack CIS device according to some embodiments of the inventive concept.

[0018] Figure 6 is a cross-sectional view illustrating a 3-stack CIS device according to some embodiments of the inventive concept.

[0019] Fig. 7A and Figure 7B is a circuit diagram showing a structure in which a photodiode PD is configured to share a unit pixel processing circuit.

[0020] Fig. 8A , Figure 8B and Figure 8C is a circuit diagram showing a first substrate and a second substrate which are bonded to each other and respectively include a photodiode and a unit pixel processing circuit, wherein the unit pixel processing circuit is shared by the photodiode.

[0021] Fig. 9A and Fig. 9B is a layout showing a 2-PD shared pixel configured to include two photodiodes.

[0022] Fig. 10A and Fig. 10B is a layout showing a 4-PD shared pixel configured to include four photodiodes.

[0023] FIG. 11A to FIG. 11F is a side view illustrating a dual vertical transfer gate (dVTG) according to some embodiments of the inventive concept.

[0024] Fig. 12A and Fig. 12B A side view is provided that defines the terms and dimensions of the dual vertical transfer gates when viewed in two different directions.

[0025] Fig.13A and Fig. 13Bis a side view showing a double vertical transfer gate according to a comparative example.

[0026] FIG. 14A to FIG. 14I is a diagram illustrating a process of manufacturing a first substrate including a unit pixel circuit according to some embodiments of the inventive concept.

[0027] FIG. 15A to FIG. 15E is a diagram illustrating a process of manufacturing a CIS device including a unit pixel circuit and a logic circuit according to some embodiments of the inventive concept.

[0028] FIG. 16A to FIG. 16G is a diagram illustrating a process of manufacturing a first pixel substrate including a dual vertical transfer gate according to some embodiments of the inventive concept.

[0029] FIG. 17A to FIG. 17F is a diagram illustrating a process of manufacturing a CIS device including a unit pixel circuit and a logic circuit according to some embodiments of the inventive concept.

[0030] Fig.18 is a diagram illustrating a process of manufacturing a CIS device including a unit pixel circuit and a logic circuit according to some embodiments of the inventive concept.

[0031] FIG. 19A to FIG. 19D is a diagram illustrating a process of manufacturing a CIS device including a unit pixel circuit and a logic circuit according to some embodiments of the inventive concept.

[0032] Fig. 20 is a diagram illustrating a process of manufacturing a CIS device including a unit pixel circuit and a logic circuit according to some embodiments of the inventive concept.

[0033] Fig.21 is a flowchart illustrating a process of manufacturing a CIS device according to some embodiments of the inventive concept.

[0034] Fig. 22 is a flowchart illustrating a process of manufacturing a first pixel substrate including a dual vertical transfer gate according to some embodiments of the inventive concept.

[0035] Fig.23 is a flow chart illustrating a substrate bonding method according to some embodiments of the inventive concept.

[0036] Fig.24 is a flow chart showing a process flow depending on the location of an I / O pad and a method of forming the I / O pad. DETAILED DESCRIPTION

[0037] As the demand for high-resolution video increases, high-density image sensors are increasingly needed. The increase in the integration of image sensors leads to a decrease in the size of the devices included in the image sensors. That is, as the number of pixels in the image sensor increases, the size of the device in each pixel and the occupied area of ​​the photodiode (PD) in each pixel also decrease.

[0038] To implement a full well capacitance photodiode in a pixel of reduced size, the photodiode may include an n-type region extending from a level that may be spaced apart from the front surface of the substrate by a certain distance to a level that may be adjacent to the rear surface of the substrate. Such a photodiode may be referred to as a "deep photodiode".

[0039] The deep photodiode may include an n-type region (n-PD) that may be surrounded by an isolation structure (eg, a p-type region and / or a deep trench isolation (DTI)) to be electrically isolated from each other. Hereinafter, for the sake of brevity, the n-type region n-PD may be referred to as an “n-PD region”.

[0040] A vertical transfer gate (VTG) can be used to efficiently collect negative charges from an n-type region having a large vertical depth. The vertical transfer gate may include one or two extensions (hereinafter referred to as a monopole or a bipole), which may extend to an n-type region of a photodiode formed in a substrate. According to some embodiments, the vertical transfer gate may be configured to have a bipole (e.g., two extensions), in which case the charge transfer efficiency of the image sensor may be improved, as described below.

[0041] Reference Fig. 12A , the vertical transfer gate 120 may include a pair of poles P1 and P2, which may be disposed in the substrate 100 and may extend from the substrate surface 100a of the substrate 100 to the n-type region n-PD of the photodiode. The gate insulating layer 122 may be disposed between the vertical transfer gate 120 and the substrate 100. When measured at the level of the substrate surface 100a, the poles P1 and P2 may extend from the substrate surface 100a to a depth L and may have a width W. In addition, the vertical transfer gate 120 may include a connection portion C and a gate extension portion E (or a first gate extension portion E and a second gate extension portion E located on the left and right sides of the connection portion C, respectively), the connection portion C being disposed on the substrate 100 to connect the paired poles P1 and P2 to each other, and the gate extension portion E being disposed on the substrate 100 and may extend outward from the connection portion C in a horizontal direction. The poles P1 and P2 may be spaced apart from each other by a gap G (e.g., a specific distance or a predetermined gap).

[0042] Fig. 12B is with Fig. 12A A cross-sectional view of the vertical transfer gate 120 taken in a direction perpendicular to the cross section of FIG. Fig. 12B In the cross-sectional view of FIG. 1 , the paired poles P1 and P2 are shown as one pole because the paired poles P1 and P2 overlap each other. A floating diffusion region FD may be formed near the paired poles P1 and P2, and a device isolation region STI may be formed to isolate several regions in the substrate 100 from each other.

[0043] like Fig.13A As shown in , in the case where the vertical transfer gate 1320 is set to have a pair of electrodes P1 and P2 extending to the n-PD region of the photodiode, the electric field is concentrated in the region between the pair of electrodes (hereinafter, the inter-electrode region) to generate an electric field that will hinder the transfer of negative charges from the inter-electrode region to the floating diffusion region FD ( Fig.13A The potential energy hump (not shown) will occur, and a backflow phenomenon of negative charge flowing from the floating diffusion region FD to the inter-electrode region (ie, in an undesirable direction) will occur. Here, Fig.13A The comparative example is shown. Fig. 12A and Fig. 12B An embodiment of a similar image sensor, in Fig.13A The intermediate substrate and gate insulating layer are identified by reference numerals 100 and 1322 .

[0044] like Fig. 13B As shown in FIG. 1 , the transfer gate may be configured to include vertical transfer gates 1320 and 1321 each having a single pole and contacts 1340 and 1341 and an interconnection line 1345 for connecting the vertical transfer gates 1320 and 1321 to each other, instead of Fig. 12A In this case, technical problems (i.e., potential energy hump and backflow phenomenon) can be prevented or suppressed, but other problems (such as complex interconnection structure and misalignment when forming contacts 1340 and 1341) may exist. Therefore, as the pixel size decreases, it becomes disadvantageous in terms of manufacturing process. Here, Fig. 13B An image sensor according to a comparative example is illustrated, and each of reference numerals 1320 and 1321 may denote a single vertical transfer gate.

[0045] In some embodiments, Fig. 12A and Fig. 12B As shown in , the first insulating pattern 125 can be placed between the vertical transfer gate 120 and the substrate 100, and in this case, the electric field concentration effect between the poles P1 and P2 can be reduced. In addition, since the first insulating pattern 125 can be arranged in a region located between the poles and having a strong field concentration effect, the charge transfer efficiency can be improved. The first insulating pattern 125 will be described in more detail below.

[0046] Hereinafter, some examples of embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0047] Fig.11A 1 is a side view of a transfer gate having a dual vertical transfer gate (dVTG) structure. The vertical transfer gate 120 may include a pair of electrodes P1 and P2, which may be disposed in the substrate 100 and may extend to the n-type region n-PD, and a connection portion C, which may be disposed to connect the paired electrodes P1 and P2. Fig.11A is not shown, but when in conjunction with Fig.11A When viewed in a direction orthogonal to the cross section, Fig. 12B A floating diffusion region FD (eg, of n type) shown in FIG. 1 may be disposed in the substrate 100 adjacent to the transfer gate 120 .

[0048] The substrate 100 may be a base structure on which a photodiode, a transistor, and a device having an electrode node are formed. The substrate 100 may be a semiconductor wafer and may be divided into IC chips by a sawing process. The substrate 100 may be formed of or include a pure semiconductor material or a compound semiconductor material (e.g., silicon or GaN), and in some embodiments, the substrate 100 may be configured as an n-type or p-type substrate doped with n-type or p-type impurities. FIG. 11A to FIG. 11E An example of an n-type MOS FET device is shown, which can be manufactured by providing a p-type substrate and forming an n-type gate and n-type source / drain regions on and in the p-type substrate. The n-type region n-PD of the photodiode can be used as a source region (or referred to as an "n-type source region"), and the floating diffusion region FD can be used as a drain region (or referred to as an "n-type drain region").

[0049] A portion of the p-type region of the substrate 100 together with the n-type region n-PD may constitute a PN junction used as a photodiode. In an embodiment, a p-doping process may be additionally performed on the p-type region to change the doping concentration of the p-type region, and the p-type region may be provided to surround the n-PD region and the n-PD region may be used to separate pixels from each other together with the isolation structure 130.

[0050] Further references Fig.11A, the first insulating layer 126 may be formed on the substrate 100 and at least in the inter-electrode region between the first pole P1 and the second pole P2. At least a portion of the first insulating layer 126 may be disposed between the substrate 100 and the vertical transfer gate 120, and may vertically separate the connection portion C of the vertical transfer gate 120 from the substrate 100. For example, the first insulating layer 126 may include a first insulating pattern 125 that may be between the connection portion C and the substrate 100. In this case, the intensity of the electric field generated by a portion (e.g., the connection portion C) of the vertical transfer gate 120 laid out on the substrate 100 may be reduced, thereby preventing or suppressing an undesirable phenomenon that may occur when the electric field is concentrated to the region between the paired poles P1 and P2.

[0051] In some embodiments, a natural oxide layer may be formed between the first insulating layer 126 and the substrate 100, between the poles P1 and P2, and between the first insulating pattern 125 and the substrate 100. The first insulating layer 126 includes silicon nitride (eg, Si x N y , where x and y are real numbers greater than 0), the first insulating layer 126 may further include a thin oxide layer.

[0052] like Fig.11A As shown in FIG. 1 , the first insulating layer 126 may be disposed below the vertical transfer gate 120 and on the substrate 100, and may cover a portion or the entirety of the substrate 100. In some embodiments, the first insulating layer 126 may serve as an etch stop layer.

[0053] The gate insulating layer 122 may be disposed between the vertical transfer gate 120 and the substrate 100. In addition, the pixels may be separated from each other by the isolation structure 130, and the photodiode may be formed between the isolation structures 130. The isolation structure 130 may be used to electrically isolate adjacent pixels from each other, and may include a single layer or a composite layer, which may be made of a material selected from SiO 2 、Si x N y , SiON, and SiOC. In some embodiments, the isolation structure 130 may include a first insulating layer 132 and a second insulating layer 131. The first insulating layer 132 may be an oxide insulating layer (e.g., SiO 2 ), the second insulating layer 131 may be a nitride insulating layer (eg, Si x N y). In addition, the isolation structure 130 may further include a conductive layer 136, which may be disposed in the isolation structure 130 and may be used to apply a bias voltage. The conductive layer 136 may be formed of, for example, at least one of doped polysilicon and tungsten (W), or include, for example, at least one of doped polysilicon and tungsten (W).

[0054] Fig. 11B A structure according to some embodiments of the inventive concept is shown, in which the gate insulating layer 122 is partially exposed and removed by a patterning process.

[0055] Fig. 11C 1 shows a gate extension E according to some embodiments of the inventive concept, which may extend horizontally on the substrate 100. Fig. 11C When the gate extension E is shown in FIG. 1 , the electric field generated by the gate extension E can also be weakened, and this structure can have several advantages of increasing the freedom of designing the gate and the process margin during the manufacturing process.

[0056] Fig.11D A gate insulating layer 122 according to an embodiment of the inventive concept is shown, which can be partially formed in the substrate 100 to cover the side surfaces and bottom surfaces of the poles P1 and P2. The gate insulating layer 122 can be cut between the poles P1 and P2. The gate insulating layer 122 of this structure can be formed by oxidizing the exposed surface of the substrate 100, and in this case, the gate insulating layer 122 can be formed of silicon oxide. In some embodiments, the process can be modified to improve the quality of the gate insulating layer 122 and change the energy band gap of the gate insulating layer 122. For example, the gate insulating layer 122 can be doped with an element such as nitrogen, or can be formed to include another layer.

[0057] Fig.11E Shows Fig. 11B In more detail, refer to Fig.11E , the first insulating pattern 125 may exist between the paired poles P1 and P2, but the first insulating layer 126 on the substrate 100 may be removed. Fig. 11B The difference between the embodiments of the present invention is that, in some embodiments, the first insulating layer 126 may not exist. The structure may be formed by performing a dry etching process on the entire substrate to remove the exposed portion of the first insulating layer 126 and leave the first insulating pattern 125 covered by the gate connection portion.

[0058] Fig.11FA structure including a void 127 according to some embodiments of the inventive concept is shown, which may be partially or completely formed on the substrate 100 and between the poles P1 and P2. In the case where the void 127 is formed, the effective dielectric constant of the first insulating pattern 125 may be further reduced, and this may enable the electric field between the poles P1 and P2 to be weakened (e.g., effectively weakened). The void 127 may be an empty or solid-free region that may be defined by at least one of the first insulating pattern 125, the substrate 100, and the gate insulating layer 122.

[0059] Fig. 12A is a side view showing a dual vertical transfer gate according to some embodiments of the inventive concept, for showing a pair of poles P1 and P2. Fig. 12B is with Fig. 12A A side view taken in a direction orthogonal to the cross section.

[0060] In the following, reference will be made to Fig. 12A and Fig. 12B The structure and geometric features of the gate are described. The vertical transfer gate 120 may include a pair of poles P1 and P2 that may extend toward the lower portion of the substrate 100. Each of the pair of poles P1 and P2 may be disposed to have a width W at the level of the substrate surface 100a, and may be spaced apart from each other by a gap G (e.g., a specific distance or a predetermined gap) at the level of the substrate surface 100a.

[0061] In addition, the paired poles P1 and P2 may have substantially the same size and shape, but in some embodiments, depending on the shape and position of the gate, the paired poles P1 and P2 may have different sizes from each other. However, for ease of illustration, a drawing is provided to show an example of an embodiment in which multiple poles have substantially the same features. Each of the poles P1 and P2 may be configured to have a width that decreases as the distance from the substrate surface 100a increases in a downward vertical direction. In addition, each of the poles P1 and P2 may have a bottom end that may be arranged in the substrate 100 and may be in contact with the n-type region n-PD of the photodiode. Here, the bottom end of each pole may have a curved surface or a rounded (smooth) shape, and this shape of the bottom end may prevent the formation of a potential barrier.

[0062] The vertical transfer gate 120 may include a connection portion C that may connect the paired poles P1 and P2 to each other, and in some embodiments, the vertical transfer gate 120 may further include a gate extension E that may extend in the horizontal direction. The connection portion C may be used to connect the paired poles to each other and provide a bonding position for a contact plug of an interconnection structure thereon.

[0063] Reference Fig. 12B, each of the poles P1 and P2 may be formed (e.g., formed relatively deeply) to extend into the n-type region n-PD of the photodiode, and may be arranged near the floating diffusion region FD (e.g., relatively close to the floating diffusion region FD). In addition, each of the poles P1 and P2 may be adjacent to a device isolation region STI that may be formed near the substrate surface 100a. If the vertical transfer gate 120 is an NMOS-FET having an n-type doped region, a channel region may be formed around the poles P1 and P2 when the transistor is turned on by a voltage higher than an operating voltage. In this case, negative charges generated in the n-type region n-PD may be transferred to the floating diffusion region FD through the channel region.

[0064] Reference Fig. 12A , the first insulating pattern 125 may be formed on the substrate 100 to have a substantially constant thickness d. The thickness d of the first insulating pattern 125 may be in the range of 5 nm to 50 nm, specifically, in the range of 10 nm to 50 nm.

[0065] The first insulating pattern 125 may be made of silicon nitride (Si x N y ) is formed of or includes silicon nitride (Si x N y ). Optionally, the first insulating pattern 125 may be a single layer or a composite layer, and may be made of SiON, SiONC, SiO 2 In some embodiments, the first insulating pattern 125 may be provided with a gap, in which case an electric field concentration effect may be suppressed.

[0066] In some embodiments, when the electric field is concentrated (e.g., relatively strongly concentrated) on the area between the poles P1 and P2 (i.e., the size of the device is reduced), the first insulating pattern 125 can more effectively reduce the intensity of the electric field. In some embodiments, the width W of the pole P1 or the pole P2 can be in the range of 50nm to 200nm, and the depth L of the poles P1 and P2 can be in the range of 200nm to 500nm. The aspect ratio (i.e., L / W) of the poles P1 and P2 can be in the range of 1 to 10, preferably in the range of 1.5 to 10, and more preferably in the range of 3 to 10. In addition, at the level of the substrate surface 100a, the gap G (e.g., a specific distance or a predetermined gap) between the poles P1 and P2 can be in the range of 10nm to 80nm. As the gap G between the poles P1 and P2 decreases, the intensity of the electric field increases, and when the first insulating pattern 125 is formed, the intensity of the electric field can be more effectively reduced by the first insulating pattern 125. The gap G between the poles P1 and P2 may be substantially equal to or less than the pole width W. For example, the gap G between the poles P1 and P2 may be less than the pole width W, and may be 1 / 2 to 1 / 5 of the width W in some embodiments.

[0067] As described above, the smaller the device, the more effectively the electric field concentration can be reduced (especially for devices with a pixel size of less than 1.5 μm, preferably less than 1.2 μm, and more preferably less than 1.0 μm). Here, the pixel size may be the larger of the longitudinal length and the lateral length of the unit pixel in a plan view.

[0068] In some embodiments, the image sensing device according to some embodiments of the inventive concept may be configured to include a vertical transfer gate, which may include a first insulating pattern 125, which is arranged on the substrate 100 and at least between the first pole P1 and the second pole P2 of the vertical transfer gate 120. As image sensing devices become more high-performance and miniaturized, a stacked image sensing device with improved optical efficiency and high pixel density may be manufactured using a substrate bonding process of forming and bonding additional substrates.

[0069] Figure 1 is a cross-sectional view showing a 2-stacked CMOS image sensing (CIS) device according to some embodiments of the inventive concept. Figure 1, the pixel substrate 100 and the logic / peripheral substrate 300 may be separately provided. Here, the pixel substrate 100 may include an analog circuit configured to drive a pixel, and the logic / peripheral substrate 300 may include a peripheral circuit and a logic circuit (e.g., an ISP block), the peripheral circuit may be used to supply power and generate various control signals, and the logic circuit may be used to process an image signal. Then, a stacked image sensing device may be formed by bonding the pixel substrate 100 to the logic / peripheral substrate 300 by making the front surfaces of the pixel substrate 100 and the logic / peripheral substrate 300 face each other.

[0070] Reference Figure 1 , the isolation structure 130 may be formed in the pixel substrate 100 and may define the pixels in the pixel substrate 100. The isolation structure 130 may be a deep trench isolation (DTI) extending from the front surface to the rear surface of the pixel substrate 100. In some embodiments, a method of applying a bias voltage may be used to reduce the loss of optically generated negative charges and improve optical efficiency, and for this purpose, a conductive layer 136 may be further provided in the isolation structure 130.

[0071] The photodiode may be disposed between the isolation structures 130 in the pixel substrate 100, and the n-type region n-PD or 110 of the photodiode may be disposed in the pixel substrate 100 and below the device placed on the pixel substrate 100. Depending on the design and location of the pixel, the isolation structures 130 may have the same size or may have at least two different thicknesses (e.g., see isolation structure 134).

[0072] The pixel substrate 100 may have a front surface and a rear surface. Devices (e.g., transistors) and nodes may be formed on the front surface of the pixel substrate 100. A device isolation region may be formed in the front surface of the pixel substrate 100 and may define an active region of the pixel substrate 100, and a vertical transfer gate 120 may be formed on the active region of the pixel substrate 100. The vertical transfer gate 120 may include a pair of poles P1 and P2 and a connection portion C, which may extend toward the bottom of the pixel substrate 100 to the n-type region n-PD of the photodiode, and the connection portion C may be provided on the pixel substrate 100 and may connect the paired poles P1 and P2 to each other. A gate insulating layer 122 may be placed between the paired poles P1 and P2 and the pixel substrate 100.

[0073] A first insulating pattern 125 having a thickness of d (refer to FIG. 12 ) may be disposed on the front surface of the pixel substrate 100. The first insulating pattern 125 may be arranged on the pixel substrate 100 and at least between the poles P1 and P2. In some embodiments, a gap may be formed between the poles P1 and P2. When the gap is formed, the first insulating pattern 125 may be partially retained between the poles, or may be completely removed.

[0074] In addition to the vertical transfer gate 120, analog devices for driving pixels may also be disposed on the front surface of the substrate 100. Fig. 7A and Figure 7B As shown in , the image sensing device may include a reset transistor RG, a source follower transistor SF, a select transistor SEL, and a ground node.

[0075] A plurality of interconnection lines 145 and a plurality of contacts 140 may be formed in an interlayer insulating layer 150, and the interlayer insulating layer 150 may be disposed on the pixel substrate 100. Figure 1 In the embodiment of the present invention, the contact 140 may be connected to the connection portion C of the vertical transfer gate 120 and may be electrically connected to the bonding pad 180 through the interconnection line 145. The bonding pad 180 may include a copper pad and may be bonded and electrically connected to a bonding pad of a substrate paired therewith. The bonding pad 180 may be electrically connected to a bonding pad of a substrate paired therewith, and in some embodiments, a dummy pad may be additionally provided for substrate bonding.

[0076] Meanwhile, in a backside illumination (BSI) image sensing device, various optical elements may be formed on a rear surface of the substrate 100 to which light may be incident. Figure 1 , a microlens 175, an RGB color filter 170, and a grid 172 may be formed in a pixel region of a rear surface of the substrate 100. The microlens 175 may be provided to adjust a focal length in each pixel.

[0077] The pixel substrate 100 may be thinned by, for example, chemical mechanical polishing (CMP) to improve light receiving efficiency of light incident through the rear surface of the pixel substrate 100. The second insulating layer 178 may be formed to suppress the negative charge consumption problem. The second insulating layer 178 may be made of hafnium oxide (HfO 2 )、Alumina(Al 2 O 3 ) and tantalum oxide (TaO x ) or includes at least one of hafnium oxide (HfO 2 )、Alumina(Al 2 O 3 ) and tantalum oxide (TaO x ) at least one of. In addition, the anti-reflection layer 179 may be disposed on the second insulating layer 178, and the optical efficiency of the image sensing device may be improved. In the chemical formula symbols indicating the composition of the inorganic material here, x and y may represent a stoichiometric ratio and may be a real number (eg, a natural number) greater than 0. For example, silicon nitride may be represented as Si x N y , where each of x and y is a real number greater than 0.

[0078] The light blocking member 173 may be formed in an optical black body region surrounding the pixel array, and may be used to observe a reference signal.

[0079] Further references Figure 1 , various devices may be formed on the front surface of the logic / peripheral substrate 300. For example, a device isolation region 330 may be formed in the logic / peripheral substrate 300 to define an active region, and a transistor may be formed by forming a gate 320 on the active region. In addition, an interconnection line 345 and a contact 340 may be formed on the logic / peripheral substrate 300 and may be electrically connected to the transistor. In an example embodiment, although not shown, the interconnection line 345 and the contact 340 may be electrically disconnected from each other by an interlayer insulating layer 350. In the present application, the contact 340 may be a conductive element that may be used for vertical interconnection. The contact 340 may include a via that may be used to connect the substrate to the interconnection line and to connect the interconnections to each other.

[0080] As described above, the pixel substrate 100 and the logic / peripheral substrate 300 may be bonded to each other through a bonding process. The bonding process may include, for example, a wafer bonding process of bonding wafers to each other, and as a result of bonding between bonding pads, an electrical connection path may be formed. Figure 1 As shown in , the bonding pad 180 of the pixel substrate 100 can be bonded to the bonding pad 380 of the logic / peripheral substrate 300, and a dummy pad can be additionally provided to bond the substrates to each other. The bonding pads 180 and 380 can be formed of or include copper (Cu) and can form a Cu-Cu bonding structure.

[0081] According to some embodiments of the inventive concept, the image sensing device may include an I / O pad that may be used to send and receive signals to and from the outside of the image sensing device and to receive control signals and power. In some embodiments, since the pixel substrate 100 may be configured to have a thin rear portion for a 2-stack backside illumination structure, the I / O pad may be formed on the rear surface of the pixel substrate 100. Figure 1, a through electrode 194 (e.g., a through silicon via (TSV)) may be provided, and the through electrode 194 may penetrate the pixel substrate 100 through the rear surface of the pixel substrate 100. Here, the through electrode 194 may be connected to the interconnection line 147 and the landing pad 347, the interconnection line 147 may be provided in the interlayer insulating layer 150 of the pixel substrate 100, and the landing pad 347 may be provided in the interlayer insulating layer 350 of the logic / peripheral substrate 300. The insulating layer 195 may be provided between the through electrode 194 and the substrate 100, and may electrically separate the substrate 100 from the through electrode 194. The I / O pad 192 may be provided on the through electrode 194, and the insulating layer 178 and / or the passivation layer 176 may be provided on the rear surface of the substrate and may protect the substrate. In some embodiments, the insulating layer 178 and / or the passivation layer 176 may be formed of or include the same material as the microlens 175.

[0082] Figure 2 is a cross-sectional view illustrating a 2-stacked CIS device according to some embodiments of the inventive concept. Figure 2 An embodiment may be similar to Figure 1 but with Figure 1 The embodiment of the present invention is different in that the through electrode 194 penetrating the pixel substrate 100 may be directly connected to the landing pad 347 in the interlayer insulating layer 350 of the logic / peripheral substrate 300. The through electrode 194 may not be connected to the interconnection line in the interlayer insulating layer 150 of the pixel substrate 100.

[0083] Figure 2 1 shows a stacked structure in which the pixel substrate 100 and the logic / peripheral substrate 300 are bonded to each other, similar to Figure 1 As shown in . A substrate bonding process may be performed on the front surface of the pixel substrate 100, and a substrate removal process may be performed on the rear surface of the pixel substrate 100 to increase the amount of light incident on the photodiode. As a result, the thickness of the pixel substrate 100 may be less than the thickness of the logic / peripheral substrate 300. Therefore, a method of forming an I / O pad structure including a through electrode 194 to penetrate the rear surface of the pixel substrate 100 may be used to facilitate the manufacturing process.

[0084] In some embodiments, a 2-stack pixel substrate can be manufactured by forming pixel circuits on two substrates respectively and bonding the two substrates to each other. Then, a 3-stack image sensing device can be manufactured by bonding the 2-stack pixel substrate to a logic / peripheral substrate.

[0085] FIG. 7A to FIG. 7B : is a circuit diagram of a unit pixel processing circuit shared by the photodiodes PD. Fig. 7A shows the structure of two photodiodes PD sharing a unit pixel processing circuit, Figure 7B The structure in which four photodiodes PD share a unit pixel processing circuit is shown.

[0086] Reference Fig. 7A Each photodiode PD may include a p-node that may be connected to ground and an n-node that may be connected to the source of the transfer transistor TG. The drain of the transfer transistor TG may be connected to the floating diffusion region FD ( Fig. 7A ). The photodiode PD can be connected to the floating diffusion region FD through the corresponding transfer transistor TG to share the floating diffusion region FD. If the gate of the transfer transistor TG is turned on, the negative charge in the corresponding photodiode PD can be transferred to the floating diffusion region FD. The floating diffusion region FD can also be connected to the source of the reset transistor RG and the gate of the source follower transistor SF. If the reset transistor RG is turned on, the charge can be removed from the floating diffusion region FD, and this operation can be performed to set a reference point for the potential. When the reset transistor RG is turned off, the source follower transistor SF can be used as a common drain amplifier that generates a gate voltage based on the amount of charge in the floating diffusion region FD and transmits the corresponding analog signal to the bit line VOUT. The drain regions of the reset transistor RG and the source follower transistor SF can be connected to the VDD node. When the selection transistor SEL is turned on, one of the pixels sharing the bit line can be selected. In this specification, unless the context clearly indicates otherwise, the transistor may be an nMOS transistor.

[0087] Reference Fig. 7A and Fig. 8A In the embodiment, the photodiode PD, the transfer transistor TG, the floating diffusion region FD ( Fig. 7A and Fig. 8A ) and a ground node may be formed in or on a first pixel substrate, and a shared unit pixel circuit may be formed on an additional substrate (ie, a second pixel substrate).

[0088] Fig. 8A It is a circuit diagram of a structure that can be formed by bonding a first pixel substrate to a second pixel substrate in a wafer bonding process (e.g., a Cu-Cu bonding process), in which a photodiode PD, a transfer transistor TG, a floating diffusion region FD, and a ground node are formed, and in which a unit pixel circuit including a reset transistor RG, a source follower transistor SF, and a selection transistor SEL is formed. In this case, an analog device of a sufficiently large size can be realized within a small pixel size, thereby manufacturing a high-precision, high-performance image sensing device.

[0089] In addition, according to Fig. 8AIn the embodiment of the present invention, the interconnection structure of the image sensing device can be simplified. For example, the bit line can be omitted from the first pixel substrate having the photodiode PD, the transfer transistor TG, the floating diffusion region FD and the ground node (GND), so the number of interconnection lines can be reduced. In some embodiments, the interconnection lines of the first pixel substrate can be arranged to form a double-layer structure, but in some embodiments, if the number of Cu bonding pads is not counted, the interconnection lines can be arranged to form a single-layer structure.

[0090] Figure 7B is a circuit diagram showing a structure in which four photodiodes PD are provided and can share one floating diffusion region (not shown) and a unit pixel circuit (including transistors RG, SF, and SEL). However, the number of photodiodes PD sharing the unit pixel circuit is not limited to two or four, and as Figure 8C As shown in , eight photodiodes PD can be set to share the unit pixel circuit. According to the circuit structure, the number of shared photodiodes PD can be increased to 16 or more.

[0091] In addition, if Fig. 10A and Fig. 10B As shown in , the four photodiodes PD can be operated independently. Fig. 9A and Fig. 9B As shown in , two photodiodes PD can be operated in a paired manner. In the paired operation method, the photodiodes can be used as a single photodiode in a high brightness mode, and the two photodiodes can be used as a single photodiode in a low brightness mode. Figure 8B , can be modified Figure 7B The embodiment of the invention is to use the Fig. 8A A plurality of pixel bases are described.

[0092] Fig. 9A , Fig. 9B , Fig. 10A and Fig. 10B are plan views of some embodiments according to the inventive concept, each plan view showing a Fig. 8A The photodiode PD, the transfer transistor TG, the floating diffusion region FD and the first pixel substrate of the ground node are described.

[0093] Reference Fig. 9A and Fig. 9B When the first pixel substrate is viewed from above, the unit pixel may be defined by the isolation structure 930. The unit pixel may include at least one active region that may be defined by another isolation structure 940, such as a device isolation region STI.

[0094] The transmission gate 920 may be disposed between the n-type region n-PD of the photodiode and the floating diffusion region FD or 950 to open or close a conductive path from the n-type region n-PD to the floating diffusion region FD. The transmission gate 920 may include a pair of poles P1 and P2 that may extend toward the bottom of the substrate (e.g., extend deeply). The transmission gate 920 may also include a connection portion C that is disposed on the substrate and may electrically connect the paired poles P1 and P2 to each other. Fig. 9A In the embodiment of the present invention, when viewed in a plan view, the gate may have a rectangular shape, and the paired poles P1 and P2 may be arranged in a symmetrical manner and have the same characteristics. However, the shape of the gate may be changed according to the arrangement of the devices in the pixel. Although not shown, the paired poles P1 and P2 may be arranged in an asymmetrical manner or have different characteristics. In some embodiments, a first insulating pattern may be formed on the substrate and between the poles instead of a gate insulating layer.

[0095] The floating diffusion region FD or 950 may be shared by the n-type regions n-PD of the two photodiodes, and a contact that may be connected to the second pixel substrate may be laid out on the floating diffusion region FD.

[0096] The ground node 970 may be spaced apart from the n-PD region. The ground node 970 may be used to apply a ground voltage to the p-type region of the photodiode.

[0097] Further references Fig. 9A , two photodiodes PD can be operated in pairs, and two adjacent pixels can share one of the lenses. Two adjacent pixels can be operated as separate pixels in high brightness mode, and can be used as a single (or one) pixel in low brightness mode.

[0098] Fig. 9B shows (including two adjacent pixels) Fig. 9A A floating diffusion region (not shown) of the first shared pixel PX1 may be arranged to face a floating diffusion region (not shown) of the second shared pixel PX2, and the floating diffusion region of the second shared pixel PX2 may be placed below the floating diffusion region of the first shared pixel PX1 in the vertical direction. In the case where the pixels are arranged to face each other, the floating diffusion region of the first shared pixel PX1 may be connected (e.g., relatively easily connected) to the floating diffusion region of the second shared pixel PX2.

[0099] At the same time, two 2-PD shared pixels (e.g., shared pixels PX1 and PX2 or shared pixels PX3 and PX4) can share an analog circuit in one pixel even when they are connected to a circuit formed on a second pixel substrate (e.g., the circuit includes a source follower transistor SF, a reset transistor RG, and a selection transistor SEL). In this case, the integration of the device can be increased (e.g., effectively increased) under the limitation of a small pixel size and the size of the analog circuit can be increased. As a result, the characteristics of the device can be improved.

[0100] according to Fig. 9B An embodiment of may include an embodiment in which a 2-PD shared pixel of a first pixel substrate is connected to a pixel analog unit circuit of a second pixel substrate, and such an embodiment may correspond to Fig. 8A Another embodiment in which two 2-PD shared pixels are arranged may correspond to Figure 8B circuit connections.

[0101] The analog circuit formed on the second pixel substrate can be manufactured by a process different from the process used for the first pixel substrate. In some embodiments, the transfer gate of the first pixel substrate can be provided in the form of a dual vertical transfer gate having a pair of poles, and the first insulating pattern can be provided on the substrate. In contrast, for the second pixel substrate, the first insulating pattern may not be formed on the substrate, and a planar gate or a FinFET type gate may be formed on the substrate. In addition, depending on the type of device on the second pixel substrate, the gate may be formed by different processes or in different shapes.

[0102] Fig. 10A and Fig. 10B : is a plan view showing a 4-PD shared pixel in which four photodiodes PD are provided to form one pixel. Fig. 10A yes Fig. 10B An enlarged view of the first sub-pixel Px1.

[0103] Reference Fig. 10A When the first pixel substrate is viewed from above, the unit pixel may be defined by the isolation structure 1030. The unit pixel may include at least one active region that may be defined by another isolation structure 1040 such as a device isolation region STI.

[0104] The transfer gate 1020 may be disposed between the n-type region n-PD of the photodiode and the floating diffusion region FD or 1050 to open or close a conductive path from the n-type region n-PD to the floating diffusion region 1050. The transfer gate 1020 may include a pair of poles P1 and P2 that may extend (e.g., deeply extend) toward the bottom of the substrate to the n-type region n-PD.

[0105] In addition, the gate may extend in an oblique direction and may be formed to have a shape suitable for the shape of the n-PD region exposed on the surface of the substrate. For example, the gate may be formed to have a polygonal or rectangular shape. A connection portion C may be provided on the transmission gate 1020 to electrically connect the paired poles P1 and P2 to each other.

[0106] In accordance with Fig. 10A In an embodiment of the present invention, when viewed in a plan view, the gate may have a polygonal shape, and the paired poles P1 and P2 may be arranged in a symmetrical manner and have the same features. However, the shape of the gate may be changed according to the arrangement of the devices in the pixel. The paired poles P1 and P2 may be arranged in an asymmetrical manner or have different features. In an embodiment, a first insulating pattern 125 may be formed on the substrate instead of a gate insulating layer and between the paired poles P1 and P2.

[0107] like Fig. 10B As shown in the figure, the isolation structure 1030 may not extend to the central portion of the 4-PD shared pixel and may have an open shape, the four sub-pixels Px1, Px2, Px3 and Px4 may share the floating diffusion area FD or 1050, and a contact connected to the second pixel substrate may be set on the floating diffusion area 1050.

[0108] Reference Fig. 10A , the ground node 1070 may be spaced apart from the n-PD region. A ground voltage may be applied to the p-type region of the photodiode through the ground node 1070.

[0109] Reference Fig. 10B , the four photodiodes PD of the 4-PD shared pixel can operate together, and the four sub-pixels Px1, Px2, Px3 and Px4 can share one lens. In high brightness mode, each of the photodiodes PD can be operated separately as a separate pixel, while in low brightness mode, at least two of the photodiodes PD can be constructed to function as a single (or one) pixel. Fig. 10B The construction of the 4-PD shared pixel shown in can correspond to Figure 8B In this case, Fig. 10B Each photodiode PD can represent a photodiode of a sub-pixel. Even in this 4-PD shared pixel configuration, by connecting the pixel analog circuit of the second pixel substrate to the 4-PD shared pixel, a configuration such as Figure 8C The circuit shown in FIG. 1 shares eight sub-pixels, or the circuit can be expanded to a structure sharing sixteen or more sub-pixels.

[0110] In addition, similar to Fig. 9A and Fig. 9B An embodiment of Fig. 10Aand Fig. 10B The second pixel substrate in the embodiment may be manufactured by a process different from that of the devices of the first pixel substrate, and the devices of the second pixel substrate may be formed to have gates having shapes or sizes different from each other.

[0111] According to some embodiments of the inventive concept, a 3-stack CIS device may be configured to include two pixel substrates and one logic / peripheral substrate.

[0112] Figure 3 is a cross-sectional view showing a 3-stack CIS device including two pixel substrates and one logic / peripheral substrate. Figure 3 , a stacked image sensing device may be configured to include a first pixel substrate 100, a second pixel substrate 200, and a logic / peripheral substrate 300 that may be bonded to each other. Here, the first pixel substrate 100 may include a light receiving element, a photodiode, and a transmission gate, and the second pixel substrate 200 may include a pixel analog circuit that converts an optical signal generated in the photodiode into an analog signal. The logic / peripheral substrate 300 may include a peripheral circuit for supplying power and generating various control signals, and a logic circuit (e.g., an ISP block) for processing an image signal.

[0113] Figure 3 It shows that along Fig. 9A AA' section taken from the first pixel substrate 100. The isolation structure 130 may be formed in the first pixel substrate 100 and may define the pixel. The isolation structure 130 may be a deep trench isolation (DTI) that may extend from the front surface toward the rear surface of the first pixel substrate 100. Other features (e.g., a conductive layer 136 disposed in the isolation structure and used to apply a bias, a change in the thickness of the isolation structure, and features of the device isolation region) may be different from those of FIG. Figure 1 The features in the embodiments are basically the same.

[0114] The photodiode may be disposed in the first pixel substrate 100 and between the isolation structures 130 , and an n-type region n-PD or 110 of the photodiode may be disposed in the first pixel substrate 100 and may be located under devices disposed on the first pixel substrate 100 .

[0115] The first pixel substrate 100 may have a front surface and a rear surface. The vertical transfer gate 120 may be formed on the front surface of the first pixel substrate 100. The vertical transfer gate 120 may include a pair of poles P1 and P2, which may extend toward the bottom of the first pixel substrate 100 to the n-PD region, and a connection portion C, which may be provided on the first pixel substrate 100 and may connect the paired poles P1 and P2 to each other. The gate insulating layer 122 may be interposed between the paired poles P1 and P2 and the first pixel substrate 100.

[0116] The first insulating pattern 125 may be on the front surface of the substrate 100. The first insulating pattern 125 may be arranged on the first pixel substrate 100 and at least between the pole P1 and the pole P2. In some embodiments, a gap may be formed between the pole P1 and the pole P2. When the gap is formed, the first insulating pattern 125 may be partially retained between the poles, or may be completely removed.

[0117] A single pixel (eg, an n-type region n-PD of a photodiode PD, a vertical transfer gate 120, and a ground node (GND, not shown)) may be provided in a manner of providing a single pixel or a pair of pixels sharing a 2-PD (eg, Fig. 9A and Fig. 9B ) or by sharing four sub-pixels (as shown in Fig. 10A and Fig. 10B ) is located on the first pixel substrate.

[0118] Figure 3 Shows Fig. 9A and Fig. 9B An example of a pixel is shown in . Fig. 9A When viewed in a cross section taken along line AA' of FIG. 1 , a floating diffusion region (not shown) may be formed in a region of the first pixel substrate 100 that may be located near a front surface of the first pixel substrate 100, between vertical transfer gates 120, and behind the isolation structure 130. A contact may be formed on the floating diffusion region FD and may be connected to the gate 220 of the source follower transistor through pads 180 and 280 bonded to each other.

[0119] Various interconnection lines 145 and various contacts 140 may be disposed in the interlayer insulating layer 150 on the first pixel substrate 100. Figure 3In an embodiment of the present invention, the contact 140 may be disposed on the connection portion C of the vertical transfer gate 120, and may be electrically connected to the bonding pad 180 via the interconnection line 145. The bonding pad 180 may include a copper pad, and may be bonded and electrically connected to a corresponding one of the bonding pads 280 on the second pixel substrate 200. The bonding pads 180 and 280 may be electrically connected to other conductive structures, but in some embodiments, a dummy pad for substrate bonding may be further provided.

[0120] At the same time, Figure 3 In the backside illumination (BSI) image sensing device shown in , various optical elements may be formed on the rear surface of the substrate 100 to which light may be incident. Figure 3 , microlenses 175, RGB color filters 170, and grids 172 may be formed in the pixel region of the rear surface of the first pixel substrate 100. The offset layout of the microlenses 175, chemical mechanical polishing, formation of the backside insulating layer, and the optical black region may be similar to Figure 1 The embodiments are substantially the same as those in the embodiments.

[0121] like Figure 3 As shown in , a second pixel substrate 200 including a pixel analog circuit may be formed. Fig. 7A As shown in the circuit diagram of , the pixel analog circuit may include a source follower transistor SF, a reset transistor RG, and a selection transistor SEL. The pixel analog circuit formed on the second pixel substrate 200 may be used to convert the light signal generated in the photodiode into an analog signal. The pixel analog circuit may be formed on an active area defined by a device isolation region STI.

[0122] The first pixel substrate 100 may be bonded to the second pixel substrate 200. Figure 3 In the embodiment of the present invention, the first pixel substrate 100 and the second pixel substrate 200 may be bonded to each other in a face-to-face bonding manner. The interlayer insulating layer 150 of the first pixel substrate 100 may be bonded to the interlayer insulating layer 250 of the second pixel substrate 200 to form a bonding interface between the interlayer insulating layer 150 of the first pixel substrate 100 and the interlayer insulating layer 250 of the second pixel substrate 200.

[0123] In addition, due to the bonding of the bonding pad at the bonding interface, the devices or circuits of the two pixel substrates can be electrically connected to each other. The gate 220 of the source follower transistor SF can be connected to the floating diffusion region FD of the first pixel substrate 100. The bonding pad 180 of the first pixel substrate 100 and the bonding pad 280 of the second pixel substrate 200 can be copper-containing bonding pads.

[0124] The pixel analog circuit of the second pixel substrate 200 may be connected to one of the pixels on the first pixel substrate 100 or to a plurality of pixels on the first pixel substrate 100. Figure 3 As shown in , when the pixel unit circuit is separated and laid out on two substrates, the device can be effectively placed in a small pixel area. If part of the analog circuit is placed on the second substrate, the size of the analog circuit can be increased, thereby improving the signal characteristics of the CIS device (e.g., signal-to-noise ratio (SNR)).

[0125] Reference Figure 3 , the second pixel substrate 200 may be placed between the first pixel substrate 100 and the third logic / peripheral substrate 300, and a through electrode 260 may be provided, which may penetrate the second pixel substrate 200 and connect the device of the first pixel substrate 100 to the device of the third logic / peripheral substrate 300. An opening may be formed, and the opening may penetrate the second pixel substrate 200, and then an insulating layer may be formed in the opening or on the exposed surface of the second pixel substrate 200, and the through electrode 260 may be electrically separated from the second pixel substrate 200. In some embodiments, the through electrode 260 may be formed by a substrate etching process (including a dry etching process and / or a wet etching process). In addition, a chemical mechanical polishing (CMP) process may be performed on the second pixel substrate 200 to thin the second pixel substrate 200. In the case where a TSV (Through-Silicon Via) process is performed after the second pixel substrate 200 is thinned, the aspect ratio of the through electrode 260 may be reduced. The through electrode 260 may be formed to penetrate the second pixel substrate 200 through the rear surface of the second pixel substrate 200 .

[0126] Further references Figure 3 , various devices may be formed on the front surface of the logic / peripheral substrate 300. For example, a transistor may be formed by forming a device isolation region STI in the logic / peripheral substrate 300 to define an active region and forming a gate 320 on the active region. In addition, various interconnection lines 345 and contacts 340 electrically connected to the transistor may be formed on the logic / peripheral substrate 300. The interconnection lines 345 and the contacts 340 may be electrically isolated from each other by an interlayer insulating layer 350.

[0127] There may be a bonding interface between the logic / peripheral substrate 300 and the second pixel substrate 200. In some embodiments, the logic / peripheral substrate 300 and the second pixel substrate 200 may be bonded to each other in such a way that the front surface of the logic / peripheral substrate 300 is bonded to the rear surface of the second pixel substrate 200. The second pixel substrate 200 and the logic / peripheral substrate 300 may be bonded to each other through a bonding process. The bonding process may include, for example, a wafer bonding process in which wafers are bonded to each other, and as a result of bonding between bonding pads, an electrical connection path may be formed between the logic / peripheral substrate 300 and the second pixel substrate 200. In this case, an additional process may be further performed on the rear surface of the second pixel substrate 200 to form an insulating layer, a contact plug / via plug and / or a bonding pad, and then the second pixel substrate 200 may be bonded to the front surface of the logic / peripheral substrate 300 on which the contact plug / via plug and / or the bonding pad are formed by a substrate bonding process.

[0128] In addition, the image sensing device may include an I / O pad that may be used to transmit and receive signals to and from the outside of the image sensing device and to receive control signals and power. For a 3-stack BSI image sensing device (i.e., having two pixel substrates and one logic / peripheral substrate), since the rear portion of the first pixel substrate 100 has a small thickness, the I / O pad 192 may be formed on the rear surface of the first pixel substrate 100. Figure 3 A through electrode 194 may be provided, and the through electrode 194 may penetrate the pixel substrate 100 through the rear surface of the pixel substrate 100 , and may be connected to a landing pad 247 that may be arranged on the second pixel substrate 200 .

[0129] An insulating layer 195 may be provided between the through-electrode 194 and the substrate 100 to electrically isolate the substrate 100 from the through-electrode 194. The through-electrode 194 may be a via. The I / O pad 192 may be provided on the through-electrode 194, and the rear surface of the first pixel substrate 100 may be protected by the second insulating layer 178 and / or the passivation layer 176. In some embodiments, the second insulating layer 178 and / or the passivation layer 176 may be formed of or include the same material as a layer of a microlens.

[0130] In addition, the I / O pad 192 may be connected to a device of the logic / peripheral substrate 300 through the through electrode 260, the vertical line 249, and the horizontal line 248 that may be formed in the second pixel substrate 200. In some embodiments, in order to reduce resistance and increase signal transmission speed, a plurality of vertical lines and horizontal lines that may be connected to each other may be provided.

[0131] Figure 3A stacked image sensing device is shown in which two pixel substrates are bonded to each other in a face-to-face manner and one logic / peripheral substrate is bonded to each other in a front-to-back manner. In some embodiments, due to the use of a dual vertical transfer gate 120 including a first insulating pattern 125 located between the poles P1 and P2, the interconnection structure can be simplified and the negative charge transfer efficiency can be improved. In some embodiments, the number of interconnection lines of the first pixel substrate 100 can be one, and the number of interconnection lines of the second pixel substrate 200 can be two.

[0132] Figure 4 is a cross-sectional view illustrating a 3-stack CIS device according to some embodiments of the inventive concept.

[0133] Reference Figure 4 , similar to Figure 3 In some embodiments, the first pixel substrate 100 and the second pixel substrate 200 may be bonded to each other in a face-to-face wafer bonding manner, and in such embodiments, a bonding interface may be formed between the first pixel substrate 100 and the second pixel substrate 200. The second pixel substrate 200 may be bonded to the logic / peripheral substrate 300 in a manner that a front surface of the logic / peripheral substrate 300 is bonded to a rear surface of the second pixel substrate 200, and in this case, another bonding interface may be formed between the second pixel substrate 200 and the logic / peripheral substrate 300.

[0134] In addition, a rear surface of the first pixel substrate 100 having the photodiode and the transfer gate 120 may be used as a light receiving portion, and various optical elements such as a color filter and a microlens may be disposed on the rear surface of the first pixel substrate 100 .

[0135] A transmission gate 120 including a pair of electrodes P1 and P2 that may extend to an n-type region n-PD or 110 of a photodiode may be formed in the first pixel substrate 100, and a first insulating pattern 125 may be formed on the first pixel substrate 100 and between the pair of electrodes P1 and P2. In addition to the above features, the isolation structure, the interconnection structure, and the bonding pad 180 may have the same Figure 3 Basically the same features.

[0136] Analog pixel circuits such as a source follower transistor, a reset transistor, and a select transistor may be formed on the second pixel substrate 200 and may be connected to devices of the first pixel substrate 100 through the bonding pads 280 and 180. For example, a floating diffusion region of the first pixel substrate 100 may be connected to a gate 220 of a source follower transistor of the second pixel substrate 200. The analog devices of the second pixel substrate 200 may be connected to one or more pixels on the first pixel substrate 100.

[0137] In addition, the second pixel substrate 200 may include a through electrode 260, which may extend through the second pixel substrate 200 and may be used to connect the first pixel substrate 100 to the logic / peripheral substrate 300. The interconnection structure on the second pixel substrate 200, the formation of the through electrode 260, and the wafer bonding process with the first pixel substrate 100 may be similar to the above. Figure 3 The embodiments are basically the same.

[0138] The logic / peripheral substrate 300 may include a peripheral circuit and a logic circuit. The peripheral circuit may be used to drive the pixel circuit, and the logic circuit may be used to process an image signal.

[0139] According to Figure 3 Compared with the embodiment of Figure 4 The logic / peripheral substrate 300 in the embodiments may include a pad area. More specifically, in some embodiments, an opening may be formed and the opening may penetrate the logic / peripheral substrate 300 through the rear surface of the logic / peripheral substrate 300, an insulating layer for electrical isolation of the logic / peripheral substrate 300 may be formed in the opening, and then, a through electrode 394 may be formed to fill the opening. A passivation layer 376 may be formed on the rear surface of the logic / peripheral substrate 300, a portion of the passivation layer 376 may be removed to expose the through electrode 394, after which an I / O pad 392 may be formed to cover the through electrode 394. In some embodiments, in order to facilitate the formation of the through electrode 394 of the logic / peripheral substrate 300, the logic / peripheral substrate 300 may be thinned, and then a process of forming the through electrode may be performed.

[0140] In such Figure 4 In the embodiment shown in , the pad area is formed on the rear surface of the logic / peripheral substrate 300, the pad area can be directly connected to the power supply component that can be arranged on the logic / peripheral substrate 300 through the landing pad 347, and the image signal can be processed by the image processing unit (ISP) and can be directly sent to the application program (AP) or the central processing unit (CPU). As described above, since the interconnection or wiring structure can be relatively simple and a large area of ​​the pixel substrate can be used, the integration of the device can be increased (e.g., easily increased).

[0141] Figure 4 Other features of the logic / peripheral substrate 300 (e.g., features involving forming devices on the substrate, forming interconnects and contact plugs / via plugs, and bonding to the second pixel substrate 200 in a front-to-back bonding manner) may be the same as those of the second pixel substrate 200 according to the present invention. Figure 3 Those are basically the same.

[0142] In accordance with Figure 4In the embodiment of the present invention, the number of layers of the interconnection lines formed on the first pixel substrate 100 may be one layer or two layers, and the number of layers of the interconnection lines formed on the second pixel substrate 200 may be two layers or three layers.

[0143] Figure 5 is a cross-sectional view illustrating a 3-stack CIS device according to some embodiments of the inventive concept.

[0144] In accordance with Figure 5 In the embodiment of the present invention, the first pixel substrate 100, the second pixel substrate 200 and the logic / peripheral substrate 300 may be bonded to each other to form a Figure 5 The two bonding interfaces are shown. A transmission gate 120 including a pair of poles P1 and P2 of an n-type region n-PD or 110 of a photodiode extending into the first pixel substrate 100 may be formed on the front surface of the first pixel substrate 100, and a first insulating pattern 125 may be formed on the first pixel substrate 100 and between the pair of poles P1 and P2.

[0145] Light may be incident into the rear surface of the first pixel substrate 100 , and light receiving elements such as a color filter and a microlens may be formed on the rear surface of the first pixel substrate 100 .

[0146] Analog pixel circuits such as source follower transistors, reset transistors, and select transistors may be formed on the second pixel substrate 200. The analog pixel circuits may be connected to devices of the first pixel substrate 100 through bonding pads 280 and 180. For example, a floating diffusion region in the first pixel substrate 100 may be connected to a gate 220 of a source follower transistor of the second pixel substrate 200. The analog devices of the second pixel substrate 200 may be connected to one or more pixels on the first pixel substrate 100. In addition, the second pixel substrate 200 may include a through electrode 260, which may penetrate or extend through the second pixel substrate 200 and may be used to connect the first pixel substrate 100 to a logic / peripheral substrate 300.

[0147] According to Figure 4 The embodiments are different, according to Figure 5 The front surface of the first pixel substrate 100 and the rear surface of the second pixel substrate 200 in the embodiment may be bonded to each other to form a bonding interface. The second pixel substrate 200 and the logic / peripheral substrate 300 may be bonded to each other in a face-to-face manner to form a bonding interface.

[0148] In accordance with Figure 5In some embodiments, the pad region may be disposed on the rear surface of the logic / peripheral substrate 300. An opening may be formed to penetrate the logic / peripheral substrate 300, an insulating layer 395 may be formed to cover the inner surface of the opening, and then a through electrode 394 may be formed to fill the opening. In some embodiments, chemical mechanical polishing (CMP) may be performed to thin the logic / peripheral substrate 300, and then a through electrode 394 may be formed in the thinned logic / peripheral substrate 300.

[0149] Other features (e.g., features related to the arrangement of interconnection lines in the first pixel substrate 100 and the second pixel substrate 200, the formation of the through-electrode 260 of the second pixel substrate 200, the formation of an insulating layer on the substrate surface, and the connection and sharing of the pixels of the first pixel substrate 100 and the analog circuits of the second pixel substrate 200) may be the same as those described above. Figure 3 and Figure 4 The features in the embodiments are basically the same.

[0150] at the same time, Figure 5 An example is shown in which the interconnection lines on the first pixel substrate 100 are formed to have a double-layer structure, but in some embodiments, the interconnection lines may be formed to have a single-layer structure.

[0151] Figure 6 1 is a cross-sectional view showing a 3-stack CIS device according to some embodiments of the inventive concept. The devices disposed on the first pixel substrate 100, the second pixel substrate 200, and the logic / peripheral substrate 300 and their interconnection structures may be the same as those according to Figure 5 The devices and their interconnection structures in the embodiments are basically the same.

[0152] according to Figure 6 Embodiments and basis Figure 5 The embodiment of the present invention is different in that the pad region may be formed on the rear surface of the first pixel substrate 100. To this end, an opening may be formed and the opening may penetrate the first pixel substrate 100 through the rear surface of the first pixel substrate 100, an insulating layer 195 may be formed to cover the opening, and then a through electrode 194 may be formed in the opening having the insulating layer 195. In this case, the through electrode 194 may be connected to the device of the logic / peripheral substrate 300 through the interconnection line 147 and the through electrode 260 formed in the second pixel substrate 200.

[0153] Hereinafter, a device including a first insulating pattern and a vertical transfer gate, a substrate having the device, and a method of manufacturing a stacked image sensing device having the device will be described below.

[0154] Fig.21is a flow chart showing a process of manufacturing a CIS device according to some embodiments of the inventive concept. The process of manufacturing a CIS device may include: setting a substrate structure including a pixel substrate and a logic / peripheral substrate (in S100); bonding the substrates to each other (in S200); forming an optical element on a light receiving surface (in S300); and forming an I / O pad (in S400).

[0155] Fig. 22 is a flow chart showing a process of manufacturing a substrate including a dual vertical transfer gate and a first insulating pattern according to some embodiments of the inventive concept. The process can be used as Fig.21 The process of manufacturing a substrate including a dual vertical transfer gate and a first insulating pattern may be performed as part of operation S100. In some embodiments, the process of manufacturing a substrate including a dual vertical transfer gate and a first insulating pattern may include: forming an isolation structure (e.g., a shallow trench isolation (STI) or a deep trench isolation (DTI) structure) in the substrate to define an active region (in S110); forming a well region, an n-type region n-PD, a p-type region, and a floating diffusion region using an ion doping process (e.g., an ion implantation process) (in S120); forming a first insulating layer on the surface of the substrate (in S130); forming a dual vertical transfer gate (dVTG) in the substrate (in S140); and forming interconnects and contact plugs / via plugs (in S150). The operation of S150 may include forming a bonding pad and an interlayer insulating layer.

[0156] The bonding of substrates (in S200 ) may be classified into a method of bonding one pixel substrate to one logic / peripheral substrate (hereinafter, 2-substrate stacking method) and a method of bonding two pixel substrates to one logic / peripheral substrate (hereinafter, 3-substrate stacking method).

[0157] Reference Fig.23 , the 3-substrate stacking method shown in the first column may include: an operation of bonding a first pixel substrate to a second pixel substrate in a front-to-front bonding manner (S220); an operation of forming a through electrode (e.g., TSV) in the second pixel substrate (S222); and an operation of bonding a rear surface of the second pixel substrate to a logic / peripheral substrate (S224). When performing operation (S222), a CMP process may be performed on the second pixel substrate to reduce the thickness of the substrate, and then a process of forming a through electrode may be performed.

[0158] exist Fig.23 The 3-substrate stacking method shown in the second column may include: an operation of forming a through electrode (e.g., TSV) in a second pixel substrate (S222); an operation of bonding a rear surface of the second pixel substrate to a logic / peripheral substrate (S224); and an operation of bonding the first pixel substrate to the second pixel substrate in a front-to-front bonding manner (S220).

[0159] exist Fig.23 The 3-substrate stacking method shown in the third column of may include: an operation of bonding the second pixel substrate to the logic / peripheral substrate in a front-to-front bonding manner (S230); an operation of forming a through electrode (e.g., TSV) in the second pixel substrate (S232); and an operation of bonding the first pixel substrate to the second pixel substrate in a front-to-back bonding manner (S234). When performing operation (S232), a CMP process may be performed on the second pixel substrate to reduce the thickness of the substrate, and then a process of forming the through electrode may be performed.

[0160] exist Fig.23 The 3-substrate stacking method shown in the fourth column of may include: an operation of forming a through electrode (e.g., TSV) in a second pixel substrate (S232); an operation of bonding the first pixel substrate to the second pixel substrate in a front-to-back bonding manner (S234); and an operation of bonding the second pixel substrate to a logic / peripheral substrate in a face-to-face bonding manner (S230).

[0161] exist Fig.23 The 2-substrate stacking method shown in the fifth column may include an operation of bonding a pixel substrate to a logic / periphery substrate in a face-to-face bonding manner ( S240 ).

[0162] Fig.24 is a flowchart showing a process flow depending on the position of the I / O pad and a method of forming the I / O pad. In the operation (S400) of forming the I / O pad, the method of forming the I / O pad may be determined according to which side of the outermost substrate in the stacked substrate the I / O pad is formed. Fig.24 , the method of forming an I / O pad (S400) may include: a method of forming a pad region on a logic / peripheral substrate (S410) and a method of forming a pad region on a rear surface of a first pixel substrate (S420). In the case where the pad region is formed in the logic / peripheral substrate (S410), a through electrode (e.g., TSV) may be formed through the rear surface of the logic / peripheral substrate. In the case where the pad region is formed in the first pixel substrate (S420), a through electrode (e.g., TSV) may be formed through the rear surface of the first pixel substrate.

[0163] Next, a method of manufacturing a 2-stack image sensing device that can be formed by bonding one pixel substrate to one logic / peripheral substrate will be described below.

[0164] FIG. 14A to FIG. 14I is a cross-sectional view illustrating a process of manufacturing a first pixel substrate including a photodiode, a first insulating layer, and a vertical transfer gate according to an embodiment of the inventive concept. FIG. 14A to FIG. 14I is along with Fig. 12BHere, the first insulating layer may include a first insulating pattern formed on the substrate and between the poles P1 and P2 of the dual vertical transfer gate.

[0165] Reference Fig.14A , an isolation structure 137 may be formed in the substrate 100 to define an active region. The substrate 100 may be a silicon substrate or a compound semiconductor substrate, and the compound semiconductor substrate may be formed of, for example, indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (SiGe), indium arsenide (InAs), silicon carbide (SiC) or other suitable compound semiconductor materials. The silicon substrate may include a bulk silicon layer or a layer configured to have a silicon-on-insulator (SOI) structure.

[0166] The substrate 100 may be an n-type or p-type substrate that may include one or more dopants. In some embodiments, the substrate 100 may be a p-type substrate into which a dopant of boron (B), aluminum (Al), or indium (In) is implanted.

[0167] The isolation structure 137 may include a shallow trench isolation (STI) pattern, and may be formed by forming an opening through a photolithography technique and using an insulating material (eg, SiO 2 、Si x N y and composite materials) to fill the openings to form.

[0168] like Fig. 14B As shown in , deep trenches can be formed by, for example, a dry etching process, and the deep trenches can be filled with an insulating material to form an isolation structure 130 that separates pixel areas from each other. In some embodiments, a conductive layer 136 can be formed, and the conductive layer 136 can apply a bias to the isolation structure 130. The conductive material may include polysilicon or tungsten. In order to electrically isolate the conductive material, a second insulating layer 131 can be formed in the deep trench.

[0169] like Fig. 14C As shown in , the well region 960, the floating diffusion region FD or 950, and the n-type region n-PD of the photodiode can be formed by implanting ions into the substrate 100. In addition, a p-dopant (e.g., N, P, or As) can be implanted into the p-type region to produce a positional variation in the doping concentration of the p-type region. For example, a p-dopant can be implanted into the region around the isolation structure 130 to increase the doping concentration of the p-type dopant in the region around the n-type region n-PD. In some embodiments, a pin-type photodiode can be formed by increasing the doping concentration of the p-type dopant at the surface of the substrate 100, and a ground node (GND) can be formed by a similar method.

[0170] like Fig.14DAs shown in FIG. 1 , a first insulating layer 126 may be formed on the substrate 100. The first insulating layer 126 may include Si x N y 、SiON、SiONC、SiO 2 and SiOC. In some embodiments, the first insulating layer 126 may be made of aluminum oxide (Al 2 O 3 )、HfO 2 ), Tantalum pentoxide (Ta 2 O 5 ) and titanium oxide (TiO 2 ) or includes aluminum oxide (Al 2 O 3 )、HfO 2 ), Tantalum pentoxide (Ta 2 O 5 ) and titanium oxide (TiO 2 ) at least one of the following.

[0171] In some embodiments, a deposition process may be used to form the first insulating layer 126 on the substrate 100. The deposition process may include, for example, a chemical vapor deposition (CVD) process.

[0172] In the case of using a silicon nitride layer as the first insulating layer 126, a liner 129 may be deposited in advance to prevent delamination problems. In some embodiments, a silicon oxide layer may be used as the liner 129.

[0173] Reference Fig.14E , an opening 121 may be formed in the substrate 100. In some embodiments, the number of openings 121 per gate may be two. The formation of the opening may include: forming a photoresist pattern on the substrate; and performing a dry etching process on the substrate using the photoresist pattern. In some embodiments, a plasma-assisted dry etching process may be used to increase anisotropy in the dry etching process.

[0174] Reference Fig.14F , a gate insulating layer 122 may be formed in the opening 121. The gate insulating layer 122 may be a silicon oxide layer, a silicon nitride layer, or a composite layer thereof, and may be formed by atomic layer deposition (ALD) or by oxidizing an exposed surface of the opening. In this case, even when the gate insulating layer 122 has a small thickness, the gate insulating layer 122 may have excellent quality (e.g., density).

[0175] In some embodiments, the process may be modified to improve the quality of the gate insulating layer 122 and to change the energy bandgap of the gate insulating layer 122. For example, the gate insulating layer 122 may be doped with an element such as nitrogen, or may be formed to further include another deposition layer.

[0176] In some embodiments, an annealing process may be further performed before or after at least one of the deposition and ion implantation processes, and the annealing process may be performed as a part of the manufacturing process.

[0177] After forming the gate insulating layer 122 , a first polysilicon 120 a may be formed to fill the opening 121 .

[0178] Reference Figure 14G , a photomask 160 may be formed, and the first insulating layer 126 may be partially removed using the photomask 160 as a patterning mask.

[0179] Reference Fig.14H , a gate insulating layer 123 may be formed on the region exposed by the patterning process using the photomask 160, and then a second polysilicon layer may be formed on the gate insulating layer 123. Then, the second polysilicon layer and the gate insulating layer 123 may be patterned to form a gate. The gate may include a dual vertical transfer gate 120 and gates of other analog circuits such as a source follower transistor SF and a reset transistor RG.

[0180] In some embodiments, spacers 124 may optionally be formed around and on the gate.

[0181] Reference Fig.14I PDs and transistors may be formed in and on the substrate 100 , contacts 140 and interconnection lines 145 may be formed on the substrate 100 , and an interlayer insulating layer 150 for electrical isolation may be formed to protect the conductive layer. A bonding pad 180 may be formed on the interlayer insulating layer 150 .

[0182] FIG. 15A to FIG. 15E A method of manufacturing a 2-stack image sensing device according to some embodiments of the inventive concept is illustrated, and in particular, a process of bonding a pixel substrate 100 and a logic / peripheral substrate 300 and forming an I / O pad is illustrated.

[0183] Reference Fig.15A , the pixel substrate 100 and the logic / periphery substrate 300 may be provided separately. The logic / periphery substrate 300 may include a gate 320 , a contact 340 , and an interconnection line 345 , and may further include a bonding pad 380 provided on the interlayer insulating layer 350 .

[0184] The logic / periphery substrate 300 may be formed separately by a different process from the pixel substrate 100. In some embodiments, a silicon gate transistor or a metal gate transistor, which may be a planar transistor or a FinFET transistor, may be formed on the logic / periphery substrate 300.

[0185] Reference Fig. 15B , the pixel substrate 100 and the logic / peripheral substrate 300 may be laid out or aligned in such a manner that the front surface of the pixel substrate 100 faces the front surface of the logic / peripheral substrate 300. Then, the pixel substrate 100 and the logic / peripheral substrate 300 may be bonded to each other through a wafer bonding process. At the bonding interface between the pixel substrate 100 and the logic / peripheral substrate 300, the bonding pads 180 and 380 may be aligned and bonded to each other.

[0186] Reference Fig. 15C , the rear portion of the pixel substrate 100 may be partially removed, and then a second insulating layer 178 may be formed on the rear surface of the pixel substrate 100. The second insulating layer 178 may include a hafnium oxide layer, a tantalum oxide layer, and / or an aluminum oxide layer, and may be used to prevent negative charges generated in the photodiode from being captured or lost on the removed substrate. An anti-reflection layer 179 may be formed on the second insulating layer 178.

[0187] In some embodiments, the pixel substrate 100 may be thinned by performing chemical mechanical polishing (CMP) on a rear surface of the pixel substrate 100. The process of thinning the pixel substrate 100 may be performed to expose the isolation structure 130.

[0188] Reference Fig.15D , an insulating layer may be formed on the rear surface of the pixel substrate 100, and then a grid 172, a color filter 170, a light blocking member 173, and a microlens 175 may be formed on the rear surface of the pixel substrate 100. The grid 172 may be formed in the pixel array, and the grid 172 may prevent a crosstalk problem from occurring between adjacent pixels. The light blocking member 173 may be formed in the optical black area OB. In the pixel array, the grid 172 and the light blocking member 173 may be formed of or include the same material, and may be formed together through a single process.

[0189] Reference Fig.15E, an opening may be formed, and the opening may pass through the pixel substrate 100 through the rear surface of the pixel substrate 100 and extend to the landing pad 347 on the logic / peripheral substrate 300. Next, an insulating layer 195 may be deposited to cover the opening, and then a through electrode 194 may be formed by filling the opening with a conductive material, and the through electrode 194 may be electrically disconnected from the pixel substrate 100 by the insulating layer 195. The conductive material may include polysilicon or tungsten. An opening may be formed and pass through the passivation layer 176 on the rear surface of the pixel substrate 100, and the passivation layer 176 may be formed of or include the same material as the layer of the microlens 175. An I / O 192 pad may be formed on the exposed surface of the through electrode 194.

[0190] FIG. 16A to FIG. 16G is a cross-sectional view showing a process of manufacturing the first pixel substrate 100 according to some embodiments of the inventive concept. For example, FIG. 16A to FIG. 16G Shows the manufacturing Figure 8B or Figure 8C The photodiode PD and the transfer transistor TG in the structure are formed on the front surface of the first pixel substrate 100. The source follower transistor SF, the reset transistor RG and the selection transistor SEL may be formed on the second pixel substrate, which may be provided separately from the first pixel substrate 100. FIG. 16A to FIG. 16G is along with Fig. 12B Cross-sectional views taken in the same direction.

[0191] Reference Fig.16A , a substrate 100 may be provided, and an isolation structure 137 may be formed in the substrate 100 to define an active region. The substrate 100 may be a silicon substrate or a compound semiconductor substrate, and the compound semiconductor substrate may be formed of, for example, indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (SiGe), indium arsenide (InAs), silicon carbide (SiC) or other suitable compound semiconductor materials. The silicon substrate may include a bulk silicon layer or a layer provided with a silicon-on-insulator (SOI) structure. The dopant implantation into the substrate 100 may be performed in a manner similar to that of the substrate 100. Fig.14A Execute in the same way.

[0192] The isolation structure 137 may include a shallow trench isolation (STI) pattern, and may be formed by forming an opening through a photolithography technique and using an insulating material (eg, SiO 2 、Si x N y and composite materials) to fill the openings to form.

[0193] Reference Fig. 16B, a deep trench may be formed by, for example, a dry etching process, and then the isolation structure 130 may be formed by filling the deep trench with an insulating material including silicon oxide and / or silicon nitride. Pixel regions separated from each other may be defined by the isolation structure 130. In some embodiments, a conductive layer 136 may be formed, and the conductive layer 136 may apply a bias voltage to the isolation structure 139. In some embodiments, the isolation structure 139 may be formed by referring to Fig. 14B The described method forms the conductive layer 136 and the insulating material.

[0194] like Fig. 16C As shown in , the well region 960, the floating diffusion region FD or 950, and the n-type region n-PD of the photodiode can be formed by implanting ions into the substrate 100. In addition, a p-dopant (e.g., N, P, or As) can be implanted into the p-type region to produce a positional variation in the doping concentration of the p-type region. For example, the p-dopant can be implanted into the region around the isolation structure 130 to increase the doping concentration of the p-type dopant in the region around the n-type region n-PD. In some embodiments, a pin-type photodiode can be formed by increasing the doping concentration of the p-type dopant at the surface of the substrate 100, and a ground node (GND) can be formed by a similar method.

[0195] like Fig.16D As shown in FIG. 1 , a first insulating layer 126 may be deposited on the surface of the substrate 100. The first insulating layer 126 may include a Si x N y 、SiON、SiONC、SiO 2 and SiOC. In some embodiments, the first insulating layer 126 may be made of aluminum oxide (Al 2 O 3 )、HfO 2 ), Tantalum pentoxide (Ta 2 O 5 ) and titanium oxide (TiO 2 ) or includes aluminum oxide (Al 2 O 3 )、HfO 2 ), Tantalum pentoxide (Ta 2 O 5 ) and titanium oxide (TiO 2 ) at least one of the following.

[0196] In some embodiments, a deposition process may be used to form the first insulating layer 126 on the substrate 100. The deposition process may include, for example, a chemical vapor deposition (CVD) process.

[0197] In the case of using a silicon nitride layer as the first insulating layer 126, a liner 129 may be deposited in advance to prevent delamination problems. In some embodiments, a silicon oxide layer may be used as the liner 129.

[0198] Reference Fig.16E , an opening 121 may be formed in the substrate 100. In some embodiments, the number of openings 121 per gate may be two. The formation of the opening may include: forming a photoresist pattern on the substrate; and performing a dry etching process on the substrate using the photoresist pattern. In some embodiments, a plasma-assisted dry etching process may be used to increase anisotropy in the dry etching process. The opening may be formed to extend to an n-type region n-PD of the photodiode, which may be formed in the substrate.

[0199] Reference Fig.16F , a gate insulating layer 122 may be formed in the opening 121. The gate insulating layer 122 may be a silicon oxide layer, a silicon nitride layer, and a composite layer thereof, and may be formed by atomic layer deposition (ALD) or by oxidizing the exposed surface of the opening. In this case, even when the gate insulating layer 122 has a small thickness, the gate insulating layer 122 may have relatively excellent quality (e.g., density). After forming the gate insulating layer 122, a polysilicon layer may be formed and fill the opening 121, and the polysilicon layer may be patterned to form the vertical transfer gate 120. The process of forming the vertical transfer gate 120 may be performed in a 2-step manner: by filling the opening 121 with a first polysilicon, and then forming a second polysilicon and patterning the second polysilicon. During the patterning process, a spacer 124 may be optionally formed around and on the gate.

[0200] In this embodiment, the first insulating layer 126 formed on the substrate 100 may be retained, in which case the remaining portion of the first insulating layer 126 may serve as an etching barrier in a subsequent patterning process. Meanwhile, in some embodiments, the first insulating layer 126 exposed by the patterning process using the photomask 160 may be removed.

[0201] Reference Figure 16G , PDs and transistors may be formed in and on the substrate 100, contacts 140 and interconnects 145 may be formed on the substrate 100, and an interlayer insulating layer for electrical isolation may be formed to protect the conductive layer. The pad 180 may be formed on the interlayer insulating layer. The number of interconnect layers may be one or two. The bonding pad 180 may be formed of or include copper.

[0202] FIG. 17A to FIG. 17Fis a cross-sectional view showing a process of manufacturing an image sensing device by stacking two pixel substrates and a logic / peripheral substrate. FIG. 17A to FIG. 17F A process of bonding the first pixel substrate 100 , the second pixel substrate 200 , and the logic / peripheral substrate 300 to form an optical element and an I / O pad is described.

[0203] Reference Fig.17A , the second pixel substrate 200 may be provided independently of the first pixel substrate 100. The second pixel substrate 200 may include an active region that may be defined by a device isolation region 237, and a source follower transistor SF, a reset transistor RG, and a selection transistor SEL may be formed on the active region of the second pixel substrate 200.

[0204] In some embodiments, a process that may be different from the process for the first pixel substrate 100 may be performed on the second pixel substrate 200 , in which case a planar transistor or a FinFET transistor may be formed on the second pixel substrate 200 .

[0205] Contacts 240 , interconnection lines 245 , and bonding pads 280 , which may serve as interconnection structures, may be formed on the second pixel substrate 200 , and at least one interlayer insulating layer 250 may be formed to surround the contacts 240 , the interconnection lines 245 , and the bonding pads 280 .

[0206] Reference Fig. 17B The first pixel substrate 100 and the second pixel substrate 200 may be aligned with each other in such a manner that the front surface of the first pixel substrate 100 faces the front surface of the second pixel substrate 200, and then they may be bonded to each other through a wafer bonding process. At the interface of the bonded substrates, the bonding pads 180 and 280 may also be aligned and bonded to each other.

[0207] Reference Fig. 17C , an opening may be formed, and the opening may penetrate the second pixel substrate 200 through the rear surface of the second pixel substrate 200 and may extend to the interconnection line on the front surface of the second pixel substrate 200. Next, an insulating layer may be deposited to cover the opening, and then a through electrode 260 may be formed by filling the opening with a conductive material, and the through electrode 260 may be electrically disconnected from the second pixel substrate 200 by the insulating layer. The conductive material may include polysilicon or tungsten. In the process of forming the opening, a passivation layer may be formed on the rear surface of the second pixel substrate 200, and a portion of the passivation layer may be removed. In this case, the through electrode 260 may have a shape protruding from the rear surface of the second pixel substrate 200.

[0208] Reference Fig.17D , the logic / peripheral substrate 300 can be provided by a separate process. Fig.15AThe method is described to perform the manufacturing process of the logic / periphery substrate 300 .

[0209] The logic / peripheral substrate 300 may be aligned with the second pixel substrate 200 such that a front surface of the logic / peripheral substrate 300 faces a rear surface of the second pixel substrate 200 , and they may be joined to form a three-layer stack.

[0210] Reference Fig.17E , the rear surface of the first pixel substrate 100 may be partially removed, and then a second insulating layer 178 and an anti-reflective layer 179 may be formed on the rear surface of the first pixel substrate 100. The second insulating layer 178 and the anti-reflective layer 179 may be formed to have the same thickness as the reference layer. Fig. 15C and Fig.15D The features of the second insulating layer 178 and the anti-reflection layer 179 in the described embodiment are substantially the same features.

[0211] In some embodiments, the first pixel substrate 100 may be thinned by performing chemical mechanical polishing (CMP) on a rear surface of the first pixel substrate 100. The process of thinning the pixel substrate 100 may be performed to expose the isolation structure 130.

[0212] Next, an insulating layer may be formed on the rear surface of the pixel substrate 100, and then optical elements such as the grid 172, the color filter 170, the light blocking member 173, and the microlens 175 may be formed. Fig.15D A method is described to fabricate an optical element.

[0213] Reference Fig.17F , an opening may be formed to penetrate the logic / peripheral substrate 300 and may extend from the rear surface of the logic / peripheral substrate 300 to the landing pad 347 on the logic / peripheral substrate 300. Next, an insulating layer 395 may be formed to cover the opening, and then a conductive material may be formed and the conductive material may fill the opening covered by the insulating layer 395. As a result, a through electrode 394 may be formed in the opening, and the through electrode 394 may be electrically disconnected from the logic / peripheral substrate 300 by the insulating layer 395. The conductive material may include polysilicon or tungsten. The opening may extend to penetrate the logic / peripheral substrate 300 and the passivation layer 376. An I / O pad 392 may be formed on the exposed through electrode 394.

[0214] Fig.18 is a cross-sectional view of a CIS device, which may include a unit pixel circuit and a logic circuit and may be manufactured by a method according to some embodiments of the inventive concept. Fig.18, an opening may be formed, and the opening may penetrate the first pixel substrate 100 from the rear surface of the first pixel substrate 100, an insulating layer 195 may be formed to cover the opening, and a through electrode 194 may be formed in the opening. In some embodiments, the through electrode 194, the passivation layer 176, and the I / O pad 192 may be provided to have substantially the same features as those of the through electrode 194, the passivation layer 176, and the I / O pad 192 in the embodiment described with reference to FIG. 15 .

[0215] FIG. 19A to FIG. 19D A method of manufacturing an image sensing device by bonding a front surface of a first pixel substrate 100 to a rear surface of a second pixel substrate 200 according to some embodiments of the inventive concept is illustrated.

[0216] Reference Fig.19A , the second pixel substrate 200 and the logic / peripheral substrate 300 may be separately provided. For example, by referring to Fig.17A The second pixel substrate 200 is prepared by the method described with reference to FIG. 15 , and the logic / peripheral substrate 300 may be prepared by the method described with reference to FIG. 15 .

[0217] Reference Fig.19B , the second pixel substrate 200 and the logic / peripheral substrate 300 may be bonded to each other through a wafer bonding process, wherein the front surface of the second pixel substrate 200 is arranged to face the front surface of the logic / peripheral substrate 300. At the bonding interface between the second pixel substrate 200 and the logic / peripheral substrate 300, the bonding pad 281 of the second pixel substrate 200 may be aligned and bonded with the bonding pad 380 of the logic / peripheral substrate 300.

[0218] Reference Fig.19B , in such Fig.19A After the logic / peripheral substrate 300 is bonded to the second pixel substrate 200 in a front-to-front (FF) bonding manner as shown, an opening may be formed to penetrate the second pixel substrate 200 through the rear surface of the second pixel substrate 200. Next, an insulator may be formed in the opening, and then the through electrode 260 may be formed by filling the opening with a conductive material. In some embodiments, a removal process may be performed on the rear surface of the second pixel substrate 200, and then a process of forming the through electrode may be performed.

[0219] Next, the substrates may be bonded to each other in such a manner that the rear surface of the second pixel substrate 200 faces the front surface of the first pixel substrate 100. At the bonding interface of the substrates, the bonding pad 280 of the second pixel substrate 200 may be aligned and bonded to the bonding pad 180 of the first pixel substrate 100.

[0220] Reference Fig.19C, the rear portion of the first pixel substrate 100 may be partially removed, an insulating layer may be formed on the rear surface of the first pixel substrate 100, and an optical element may be formed on the insulating layer. Fig. 15C and Fig.15D The method described performs the process.

[0221] Reference Fig.19D , a passivation layer 376 may be formed on the rear surface of the logic / periphery substrate 300, and an opening may be formed, and the opening may pass through the rear surface of the logic / periphery substrate 300. Then, an insulating layer 395 may be formed in the opening, and a through electrode 394 may be formed by filling the opening with a conductive material. In some embodiments, the through electrode 394 may be connected to a landing pad 347 of the logic / periphery substrate 300.

[0222] Fig. 20 is a cross-sectional view of a CIS device, which may include a unit pixel circuit and a logic circuit and may be manufactured by a method according to some embodiments of the inventive concept. Fig. 20 The embodiment of FIG. 19 is different from the embodiment according to FIG. 19 in that Fig. 20 A pad region may be defined on the rear surface of the first pixel substrate 100 , and the through-electrode 194 may be formed by forming an opening in a backside etching manner.

[0223] For example, an embodiment may relate to a dual vertical transfer gate, and further to a CIS device including a dual vertical transfer gate, the dual vertical transfer gate including a pair of poles that can extend to the n-type region of the photodiode, and including a first insulating pattern that can be formed on the substrate and between the poles. The CIS device may include a stacked image sensing device in which one or two pixel substrates and a logic / peripheral substrate are stacked. The stacked image sensing device can be manufactured using wafer bonding technology. In some embodiments, the CIS device can be manufactured by stacking the second pixel substrate 200 on the pixel substrate 100 so that the front surface of the logic / peripheral substrate 300 and the front surface of the second pixel substrate 200 face each other.

[0224] Some embodiments of the inventive concept can be implemented using integrated circuit technology that forms semiconductor devices on a substrate. In addition, the inventive concept can be applied to substrate stacking technology without complex processes or additional complex processes. As the performance and integration of image sensing devices improve, it is expected that the applicability and technical effects of the inventive concept can be further improved.

[0225] The inventive concept may relate to an image sensing apparatus including a semiconductor device. However, some embodiments based on the inventive concept may be applied not only to electrical and electronic products in a directly applicable manner or in an integrated manner, but also to medical, health, construction, machinery and automotive electronics.

[0226] According to some embodiments of the inventive concept, a gate may be provided, which may include a pair of poles, the gate to transfer negative charge from a photodiode (PD) that may be formed deeper in a substrate to a floating diffusion (FD) region, and which may prevent negative charge backflow problems that may occur in the structure (e.g., caused by a strong electric field generated by a pair of poles and a connection portion). A transistor according to some embodiments and a device having the transistor may exhibit relatively good negative charge mobility and relatively high light conversion efficiency.

[0227] As image sensing devices become more integrated, unit pixel circuits may become smaller, photodiodes PD may become deeper, gates may become thinner, and the distance between poles may become narrower. According to some embodiments of the inventive concept, backflow problems that may be caused by device shrinkage or electric field increase can be prevented. In addition, the electric field can be prevented from increasing not only between the poles of the gate but also in the area outside the poles. This means that the effect of the inventive concept can be more effective for small-sized devices and scaled-down manufacturing processes.

[0228] In addition, the paired electrodes of the gate can be connected to each other without additional interconnection lines. Therefore, the interconnection structure can be simplified and the misalignment problem that occurs when forming contacts to connect the interconnection lines to the gate can be prevented. That is, the design and manufacturing margin of the image sensing device can be increased.

[0229] Pixel size is decreasing to increase the integration and performance of image sensing devices. In order to achieve reduced pixel size, high performance and efficient arrangement, substrate stacking technology can be used to manufacture stacked image sensing devices. According to some embodiments of the inventive concept, a pixel substrate manufacturing process can be performed to form pixel circuits separately on two pixel substrates, and then the pixel substrates can be joined to each other. Therefore, the image sensing device can be manufactured using substrate stacking technology without complex or large amounts of additional processes. The inventive concept can be relatively easily integrated with advanced processes that can be used to improve the performance and integration of image sensing devices. Therefore, as image sensing devices become more miniaturized, it is expected that the inventive concept will be more widely used.

[0230] According to some embodiments of the inventive concept, a first insulating pattern can be formed between the substrate surface and the paired poles to weaken the electric field between the paired poles. Therefore, the potential energy hump that hinders the transfer of negative charges from the region between the paired poles to the FD region and the backflow problem of negative charges flowing in the opposite direction from the FD region to the region between the poles can be prevented.

[0231] While some examples of embodiments of the inventive concept have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A transistor, comprising: Gate; An n-type source region, below the gate; an n-type drain region in the substrate adjacent to the gate; A gate insulating layer, between the gate and the substrate; as well as a first insulating pattern, between the gate insulating layer and the substrate, The gate includes a pair of electrodes extending to the n-type source region and a connecting portion connecting the pair of electrodes, and Wherein, the first insulating pattern is between the pair of poles.

2. The transistor according to claim 1, wherein The thickness of the first insulating pattern is in the range of 5 nm to 50 nm.

3. The transistor according to claim 1, wherein The first insulating pattern includes Si x N y , where x and y are real numbers greater than 0.

4. The transistor according to claim 1, wherein: The width of the poles in the pair of poles is in the range of 50 nm to 200 nm when measured at the surface level of the substrate.

5. The transistor according to claim 1, wherein The depth of the poles in the pair of poles is in the range of 200 nm to 500 nm when measured from the surface of the substrate.

6. The transistor according to claim 5, wherein: The aspect ratio of the poles in the pair of poles is in the range of 1 to 10.

7. The transistor according to claim 4, wherein: The distance between the pair of poles is in the range of 10 nm to 80 nm when measured at the level of the surface of the substrate.

8. The transistor according to claim 1, wherein The first insulating pattern is a single layer or a composite layer formed of at least one of SiON, SiONC, SiO 2 , and SiOC.

9. The transistor according to claim 3, wherein: The first insulating pattern includes a gap.

10. The transistor according to claim 3, further comprising: An etch stop layer is disposed on the substrate adjacent to the gate and at the same level as the first insulating pattern.

11. An image sensing device, comprising: A first substrate includes a photodiode region, a transfer transistor and a floating diffusion region, the transfer transistor includes a gate and a first insulating pattern, the gate includes a pair of electrodes extending to an n-type region of the photodiode region and a connecting portion connecting the pair of electrodes to each other, and the first insulating pattern is between the pair of electrodes; a second substrate including a source follower transistor; as well as The third substrate includes a logic circuit, The floating diffusion region of the first substrate is electrically connected to the gate of the source follower transistor of the second substrate.

12. The image sensing device according to claim 11, wherein: The floating diffusion region of the first substrate is connected to the gate of the source follower transistor of the second substrate by Cu-Cu bonding.

13. The image sensing device according to claim 12, wherein: The front surface of the third substrate is connected to the rear surface of the second substrate.

14. The image sensing device according to claim 12, further comprising: a via hole penetrating through the rear surface of the third substrate; as well as I / O pads, connected to vias.

15. The image sensing device according to claim 11, wherein: The floating diffusion region of the first substrate is connected to the gate of the source follower transistor of the second substrate through a via hole penetrating the second substrate.

16. The image sensing device according to claim 15, wherein: The front surface of the third substrate is connected to the front surface of the second substrate.

17. The image sensing device according to claim 15, further comprising: a via hole penetrating through the rear surface of the third substrate; as well as I / O pads, connected to vias.

18. The image sensing device according to claim 16, wherein: The second substrate and the third substrate are connected to each other in a Cu-Cu bonding manner.

19. The image sensing device according to claim 15, wherein: The first substrate includes metal lines arranged in a double-layer structure.

20. The image sensing device according to claim 12, further comprising: The dummy bonding pads are used to connect the first substrate to the second substrate.

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