Trench gate SiC MOSFET chip and manufacturing method thereof

Abstract

The present invention discloses a trench-gate SiC MOSFET chip and a method for manufacturing the same. The trench-gate SiC MOSFET chip of the present invention uses a composite trench gate structure. The gate oxide thickness at the trench bottom and sidewalls can be controlled separately. The gate oxide layer at the trench bottom, where the electric field intensity is greater, is thickened, thereby improving the long-term reliability of the device during use. The gate oxide layer is retained thinner in the sidewall trench portion, helping to reduce the channel resistance and conduction loss of the device. This shows that the present invention can effectively reduce the channel resistance and conduction loss while ensuring high device reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a trench gate SiC MOSFET chip and a manufacturing method thereof. Background Art

[0002] As a third-generation semiconductor material, SiC (silicon carbide, a semiconductor material that can be used to make semiconductor devices and integrated circuits) has the characteristics of large bandgap, high breakdown field strength, high saturated electron drift rate, high thermal conductivity, and stable chemical properties. This makes SiC-based power devices have great application prospects in high voltage, high temperature, high frequency, high power, and strong radiation, and is particularly suitable for the production of high-voltage and high-power power electronic devices.

[0003] SiC MOSFET (metal oxide field-effect transistor) devices have the advantages of fast switching speed, simple control (voltage control type), and low on-resistance. They are widely used in application fields requiring high-power devices such as wind power generation, solar power generation, smart grid, rail transportation, and military industry.

[0004] Compared to planar-gate SiC MOSFET device structures, trench-gate SiC MOSFETs offer smaller cell sizes and higher integration density. Furthermore, by eliminating the influence of the JFET region resistance effect in the on-state, they can further reduce on-resistance and increase current density, offering greater development potential in the context of the trend toward miniaturization and high-density integration of power electronic devices. However, the structural evolution from planar gate to trench gate also introduces new challenges. For example, when the gate oxide layer shifts from the chip surface to the trench surface within the chip, the electric field strength within the chip in the blocking state is much higher than that of traditional silicon-based devices. Furthermore, from a material perspective, the maximum electric field strength that the gate oxide layer can withstand is lower than that of the SiC in the chip body. This makes the gate oxide region at the bottom of the trench, where the Pwell depletion layer has been removed for protection, more susceptible to breakdown, thus affecting the long-term reliability of the device during use. One possible solution is to increase the thickness of the gate oxide layer to improve gate oxide reliability, but this will also increase channel resistance and increase conduction losses. Another possible solution is to add a deeper Pwell injection on one side of the strip trench. In this way, when the device is in the blocked state, the Pwell depletion layer can expand to completely protect the bottom of the channel. However, when the device is in the on state, half of the conductive channel area is lost, which is not conducive to reducing the device's on-resistance. Summary of the Invention

[0005] The purpose of the present invention is to provide a trench gate SiC MOSFET chip and a manufacturing method thereof, which can effectively reduce the channel resistance and conduction loss while ensuring the high reliability of the device.

[0006] A trench-gate SiC MOSFET chip comprises a cell region comprising a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer, and a second gate oxide layer, and a transition region comprising a gate metal, a source metal, and a plurality of contact holes. The first polysilicon gate is located at the bottom of the trench, the first gate oxide layer is located at the outer surface of the first polysilicon gate, the second polysilicon gate is located at the upper portion of the trench, the second gate oxide layer is located at the outer surface of the second polysilicon gate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the first polysilicon gate is connected to the source metal via corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal via corresponding contact holes in the transition region.

[0007] In one embodiment, the cell region further includes an N+ doped region, a P+ contact region and a substrate, and the transition region further includes a drain metal; wherein, the number of N+ doped regions and trenches is two, the two N+ doped regions are located between the two trenches, and are respectively in contact with the two first gate oxide layers, the P+ contact region is sandwiched between the two N+ doped regions and is respectively in contact with the two N+ doped regions, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0008] In one embodiment, the cell region also includes a back metal, a buffer layer, an epitaxial layer, a SiO2 dielectric layer, a front metal and a PI glue passivation layer; wherein, the back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer are stacked in sequence from bottom to top, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0009] In one embodiment, the cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region, and the P+ contact region.

[0010] A method for manufacturing a trench gate SiC MOSFET chip, used to manufacture the above chip, the method comprising:

[0011] A substrate is provided, and a buffer layer and an epitaxial layer are grown upward in sequence on the substrate;

[0012] Pwell ions, Source ions and Pplus ions are sequentially implanted into the epitaxial layer to form the corresponding Pwell layer, N+ doping region and P+ contact region respectively;

[0013] Depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a trench on the SiO2 etching hard mask layer, growing a sacrificial oxide layer on the inner surface of the trench, removing the sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the trench, growing polysilicon deposits in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a first polysilicon gate;

[0014] Wet etching the first gate oxide layer located on the inner surface of the upper portion of the trench, growing a second gate oxide layer on the inner surface of the upper portion of the trench, growing polysilicon deposits in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a second polysilicon gate;

[0015] The dummy gate contact hole area is defined by photolithography, the upper polysilicon layer in the trench is removed by etching, and a SiO2 dielectric layer is deposited and grown on the upper surface of the epitaxial layer. The SiO2 dielectric layer is densified and etched to form a source contact hole and a gate contact hole including a dummy gate and a real gate;

[0016] Sputtering nickel metal on a portion of the SiO2 dielectric layer and a portion of the epitaxial layer, performing a thermal annealing treatment to form an ohmic contact, wet-etching the unreacted nickel metal, and continuously sputtering aluminum metal and wet-etching it for patterning to obtain a front metal layer, and covering a portion of the front metal layer and a portion of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer;

[0017] The lower surface of the substrate is ground to remove silicon oxide, and metal nickel is sputtered, and thermal annealing is performed to form an ohmic contact, and metal titanium, nickel or silver is further sputtered to obtain a back metal layer.

[0018] A trench-gate SiC MOSFET chip comprises a cell region comprising a first trench, a second trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer, and a second gate oxide layer, and a transition region comprising a gate metal, a source metal, and a plurality of contact holes. The first polysilicon gate is located in the first trench, the first gate oxide layer is located on the outer surface of the first polysilicon gate, the second polysilicon gate is located in the second trench, the second gate oxide layer is located on the outer surface of the second polysilicon gate, there are two second trenches, one on each side of the first trench, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the depth of the first trench is greater than the depth of the second trench, the first polysilicon gate is connected to the source metal via corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal via corresponding contact holes in the transition region.

[0019] In one embodiment, the cell region further includes an N+ doped region, a P+ contact region and a substrate, and the transition region further includes a drain metal; wherein, the number of the N+ doped region and the P+ contact region are both two, the two N+ doped regions are respectively located on the outside of the two second trenches relative to the first trench, the two P+ contact regions are respectively located on the outside of the two N+ doped regions relative to the second trench, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0020] In one embodiment, the cell region also includes a back metal, a buffer layer, an epitaxial layer, a SiO2 dielectric layer, a front metal and a PI glue passivation layer; wherein, the back metal, the substrate, the buffer layer, the epitaxial layer, the SiO2 dielectric layer, the front metal and the PI glue passivation layer are stacked in sequence from bottom to top, the first trench, the second trench, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0021] In one embodiment, the cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region, and the P+ contact region.

[0022] A method for manufacturing a trench gate SiC MOSFET chip, used to manufacture the above chip, the manufacturing method comprising:

[0023] A substrate is provided, and a buffer layer and an epitaxial layer are grown upward in sequence on the substrate;

[0024] Pwell ions, Source ions and Pplus ions are sequentially implanted into the epitaxial layer to form the corresponding Pwell layer, N+ doping region and P+ contact region respectively;

[0025] Depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a first trench on the SiO2 etching hard mask layer, growing a first sacrificial oxide layer on the inner surface of the first trench, removing the first sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the first trench, growing polysilicon deposits in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a first polysilicon gate;

[0026] Etching a second trench on the SiO2 etching hard mask layer, growing a second sacrificial oxide layer on the inner surface of the second trench, removing the second sacrificial oxide layer and growing a second gate oxide layer on the inner surface of the second trench, growing polysilicon deposits in the second gate oxide layer and etching the polysilicon entirely to obtain a second polysilicon gate;

[0027] A SiO2 dielectric layer is deposited and grown on the upper surface of the epitaxial layer, the SiO2 dielectric layer is densified, and the SiO2 dielectric layer is etched to form a source contact hole and a gate contact hole including a dummy gate and a real gate;

[0028] Sputtering nickel metal on a portion of the SiO2 dielectric layer and a portion of the epitaxial layer, performing a thermal annealing treatment to form an ohmic contact, wet-etching the unreacted nickel metal, and continuously sputtering aluminum metal and wet-etching it for patterning to obtain a front metal layer, and covering a portion of the front metal layer and a portion of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer;

[0029] The lower surface of the substrate is ground to remove silicon oxide, metal nickel is sputtered, and thermal annealing is performed to form an ohmic contact, and metal titanium, nickel or silver is continuously sputtered to obtain a back metal layer.

[0030] The trench-gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure. The gate oxide thickness at the trench bottom and sidewalls can be controlled separately. The gate oxide layer at the trench bottom, where the electric field intensity is greater, is thickened, thereby improving the long-term reliability of the device during use. The gate oxide layer is retained thinner in the sidewall trench, helping to reduce the device's channel resistance and conduction losses. This shows that the present invention can effectively reduce channel resistance and conduction losses while ensuring high device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0032] Figure 1 A schematic diagram of a first structure of a trench-gate SiC MOSFET chip provided in the first embodiment of the present invention;

[0033] Figure 2 A schematic diagram of a second structure of a trench gate SiC MOSFET chip provided in the first embodiment of the present invention;

[0034] Figure 3 A flowchart of a method for manufacturing a trench-gate SiC MOSFET chip provided in the first embodiment of the present invention;

[0035] Figure 4 A schematic diagram of a first structure of a trench gate SiC MOSFET chip provided in the second embodiment of the present invention;

[0036] Figure 5 A schematic diagram of a second structure of a trench gate SiC MOSFET chip provided in the second embodiment of the present invention;

[0037] Figure 6 A flowchart of a method for manufacturing a trench-gate SiC MOSFET chip provided in the second embodiment of the present invention;

[0038] Among them, PI represents the PI glue passivation layer, M1 represents the back metal layer, M2 represents the front metal layer, Si represents the SiO2 dielectric layer, N represents the N+ doping region, P represents the P+ contact region, L represents the Pwell layer, P1 represents the first polysilicon gate, P2 represents the second polysilicon gate, S1 represents the first gate oxide layer, S2 represents the second gate oxide layer, E represents the epitaxial layer, B represents the buffer layer, and S represents the substrate. DETAILED DESCRIPTION

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0040] A trench gate SiC MOSFET chip and a method for manufacturing the same provided by the embodiment of the present invention can be found in Figures 1 to 6 , where PI represents the PI glue passivation layer, M1 represents the back metal layer, M2 represents the front metal layer, Si represents the SiO2 dielectric layer, N represents the N+ doped region, P represents the P+ contact region, L represents the Pwell layer, P1 represents the first polysilicon gate, P2 represents the second polysilicon gate, S1 represents the first gate oxide layer, S2 represents the second gate oxide layer, E represents the epitaxial layer, B represents the buffer layer, and S represents the substrate. The technical solution provided by the embodiment of the present invention is described in detail below.

[0041] See also Figure 1, which shows a structural schematic diagram of a trench gate SiC MOSFET chip provided by Example 1 of the present invention, wherein the cell region includes a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and the transition region includes a gate metal, a source metal and a plurality of contact holes; wherein, the first polysilicon gate is located at the bottom of the trench, the first gate oxide layer is located on the outer surface of the first polysilicon gate, the second polysilicon gate is located at the upper part of the trench, the second gate oxide layer is located on the outer surface of the second polysilicon gate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the first polysilicon gate is connected to the source metal through corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal through corresponding contact holes in the transition region.

[0042] Embodiment 1 of the present invention provides a high-reliability trench-gate SiC MOSFET chip, wherein a basic cell (cell region) includes a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer, and a second gate oxide layer, and a transition region includes a gate metal, a source metal, and a plurality of contact holes; wherein the first polysilicon gate and the first gate oxide layer are located at the bottom of the trench, the first gate oxide layer is between the first polysilicon gate and the inner surface of the trench, and covers the outer surface of the first polysilicon gate; the second polysilicon gate and the second gate oxide layer are located at the upper portion of the trench, the second gate oxide layer is located between the second polysilicon gate and the inner surface of the trench, and between the first gate oxide layer and the second polysilicon gate, and covers the outer surface of the second polysilicon gate; the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; the first polysilicon gate is connected to the source metal through a contact hole in the chip transition region, and the second polysilicon gate is connected to the gate metal through another contact hole in the chip transition region. Therefore, when the device is in the blocking state, the first gate oxide layer at the bottom of the trench will be subjected to a larger electric field strength. The larger thickness of the first gate oxide layer can improve the long-term reliability of the device during use. At the same time, the capacitance of this part of the gate oxide layer is not included in the Miller capacitance, which can reduce the Miller capacitance of the device, improve the switching speed, and reduce the overall loss of the device; when the device is in the on state, the second gate oxide layer on the upper sidewall of the trench has a thinner thickness, which can reduce the channel resistance and conduction loss of the device.

[0043] The trench-gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure. The gate oxide thickness at the trench bottom and sidewalls can be controlled separately. The gate oxide layer at the trench bottom, where the electric field intensity is greater, is thickened, thereby improving the long-term reliability of the device during use. The gate oxide layer is retained thinner in the sidewall trench, helping to reduce the device's channel resistance and conduction losses. This shows that the present invention can effectively reduce channel resistance and conduction losses while ensuring high device reliability.

[0044] In a trench gate SiC MOSFET chip provided in a first embodiment of the present invention, the cell region further includes an N+ doped region, a P+ contact region, and a substrate, and the transition region further includes a drain metal; wherein, the number of N+ doped regions and the number of trenches are both two, the two N+ doped regions are located between the two trenches and respectively contact the two first gate oxide layers, the P+ contact region is sandwiched between the two N+ doped regions and respectively contact the two N+ doped regions, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0045] The cell area also includes back metal, Buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer; among them, the back metal, substrate, Buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer are stacked in sequence from bottom to top, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0046] The cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

[0047] It should be noted that, in the first embodiment of the present invention, two or more trenches may be provided in parallel. Accordingly, in the transition region of the chip, the first polysilicon gate and the second polysilicon gate may be connected to the gate metal and the source metal by means of two or more trenches in parallel. Thus, there is no need to excessively reduce the size of the contact hole. When the size of the cell region is reduced, the size of the contact hole will not be restricted by the photolithography process capability, thereby improving the process compatibility during the chip manufacturing process.

[0048] In a specific implementation of the first embodiment of the present invention, the number of trenches is 2 for specific description. The structure of the basic cell of the chip may include a substrate, a buffer layer, an epitaxial layer, a Pwell layer, an N+ doping region, a P+ contact region, a first polysilicon gate, a first gate oxide layer, a second polysilicon gate, a second gate oxide layer, a SiO2 dielectric layer, a front metal, a PI glue passivation layer, a trench, and a back metal. The transition region includes a gate metal, a drain metal, a source metal, and a plurality of contact holes, such as Figure 2 shown.

[0049] The number of N+ doped regions is 2, each located between two parallel trenches, and in one-to-one contact with the two second gate oxide layers. The depth of the N+ doped region is less than the depth of the second gate oxide layer, and the depths of the two N+ doped regions may be the same. The P+ contact region is located between the two N+ doped regions, and in contact with the two N+ doped regions, and the depth may be the same as the depth of the N+ doped region. The N+ doped region and the P+ contact region are connected to the source metal in the transition region. The Pwell layer may include three sub-regions, two of which are located outside the two trenches relative to the N+ doped region, and in contact with the two second gate oxide layers respectively. Another sub-region is located between the two trenches, and in contact with the N+ doped region, the P+ contact region, and the two second gate oxide layers respectively. The depths of the three sub-regions are greater than the depth of the N+ doped region, and are not greater than the depth of the second gate oxide layer.

[0050] The back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer of the chip are stacked in order from bottom to top (from back to front). The first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region, the P+ contact region and the Pwell layer are all located in the epitaxial layer. The Pwell layer does not extend to the side boundary of the epitaxial layer. The SiO2 dielectric layer is located on the epitaxial layer and is divided into two sub-regions. One sub-region covers from one side boundary of the epitaxial layer to the N+ contact region on that side. The upper surface of the doped region is partially covered by the other sub-region from the other side boundary of the epitaxial layer to the upper surface of the N+ doped region on this side; the front metal layer is located on the SiO2 dielectric layer, does not extend to the side boundary of the epitaxial layer, and fills the gap between the two sub-regions of the SiO2 dielectric layer, so as to contact the upper surface of the P+ contact region and the upper surface of the N+ doped region; the PI glue passivation layer is located on the front metal layer, and fills the gap between the side boundary of the front metal layer and the side boundary of the SiO2 dielectric layer, so as to contact the upper surface of the SiO2 dielectric layer. The substrate on the back of the chip is connected to the drain metal. In the implementation method of the first embodiment of the present invention, in the middle connecting part of the two grooves, there is only a concave corner in the horizontal direction without a convex corner structure, thereby avoiding the electric field concentration effect at the convex corner position of the groove, and further improving the long-term reliability of the device during use.

[0051] The trench-gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure. The gate oxide thickness at the trench bottom and sidewalls can be controlled separately. The gate oxide layer at the trench bottom, where the electric field intensity is higher, is thickened, thereby improving the long-term reliability of the device during use. The gate oxide layer is retained thinner in the sidewall trench, helping to reduce the device's channel resistance and conduction losses. Furthermore, the composite trench gate structure can reduce the device's Miller capacitance, improve switching speed, and reduce overall losses.

[0052] The first embodiment of the present invention further provides a method for manufacturing a trench gate SiC MOSFET chip, which is used to manufacture the chip as in the first embodiment of the present invention. Figure 3 As shown, the specific production method includes:

[0053] S11: Setting a substrate, and growing a buffer layer and an epitaxial layer on the substrate in sequence;

[0054] S12: Pwell ions, Source ions and Pplus ions are sequentially implanted into the epitaxial layer to form corresponding Pwell layers, N+ doped regions and P+ contact regions respectively;

[0055] S13: depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a trench on the SiO2 etching hard mask layer, growing a sacrificial oxide layer on the inner surface of the trench, removing the sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the trench, growing polysilicon in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a first polysilicon gate;

[0056] S14: wet-etching the first gate oxide layer located on the inner surface of the upper portion of the trench, growing a second gate oxide layer on the inner surface of the upper portion of the trench, growing polysilicon deposits in the first gate oxide layer, and etching the entire surface of the polysilicon to obtain a second polysilicon gate;

[0057] S15: Photolithography defines the dummy gate contact hole area, etches away the upper polysilicon in the trench, and deposits and grows a SiO2 dielectric layer on the upper surface of the epitaxial layer. The SiO2 dielectric layer is densified, and the SiO2 dielectric layer is etched to form a source contact hole and a gate contact hole including a dummy gate and a true gate;

[0058] S16: sputtering metal nickel on a portion of the SiO2 dielectric layer and a portion of the epitaxial layer, performing thermal annealing to form an ohmic contact, wet-etching the unreacted metal nickel, continuously sputtering metal aluminum and wet-etching it for patterning to obtain a front metal layer, and covering a portion of the front metal layer and a portion of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer;

[0059] S17: Grind the lower surface of the substrate to remove silicon oxide, sputter metal nickel, perform thermal annealing to form an ohmic contact, and continue sputtering metal titanium, nickel or silver to obtain a back metal layer.

[0060] The manufacturing process of the trench gate SiC MOSFET chip provided in the first embodiment of the present invention includes ion implantation, high-temperature activation annealing of impurities, SiO2 wet etching, SiC trench dry etching, sacrificial oxide layer and gate oxide layer growth, polysilicon deposition and dry etching, wafer backside thinning, RTA metal alloying and other process steps. The specific manufacturing method can be as follows:

[0061] Use 4H-SiC single crystal substrate, the wafer size is 4-8 inches, the substrate thickness is 350-500um, the conductivity type is N-type, and the doping concentration is greater than 1E18cm-3;

[0062] The buffer layer and epitaxial layer (both mainly SiC) are grown on the SiC substrate using CVD epitaxy. The thickness of the buffer layer is 0.5-2um, and the thickness of the epitaxial layer is 10-30um. The doping concentration of the buffer layer is 5E16-1E18cm-3, and the doping concentration of the epitaxial layer is 1E14-1E17cm-3. During the epitaxial growth process, the process chamber temperature is 1400℃-1800℃. The surface of the wafer after epitaxial growth must be kept clean.

[0063] Implement Pwell ion implantation (Al+ ions) in the epitaxial layer to simultaneously form the Pwell layer (mainly P SiC) in the cell region and the terminal field limiting ring. The implantation dose is 1E13-1E14 and the implantation energy is 200-800keV.

[0064] Implement Source ion implantation (N ions) in the epitaxial layer to form a Source region (i.e., N+ doped region, mainly NSiC) with an implantation dose of 5E14-5E15 and an implantation energy of 40-300keV.

[0065] Implement Pplus ion implantation (Al+ ions) in the epitaxial layer to form a P+ contact region (mainly P SiC) with an implantation dose of 5E14-5E15 and an implantation energy of 50-500keV.

[0066] The impurities are activated by furnace tube annealing. The process temperature of the furnace tube is above 1600℃. It is necessary to ensure that the one-time activation rate of all impurities is above 80%.

[0067] A SiO2 etching hard mask layer is deposited on the upper surface of the epitaxial layer by PECVD with a thickness of 5000-10000A;

[0068] The upper surface of the epitaxial layer is trench-etched downwards to a depth of 0.5-3 μm;

[0069] A sacrificial oxide layer is grown in the trench with a thickness of 800-1200 Å and then removed;

[0070] 10) The first gate oxide layer (mainly SiO2) is grown in the trench. The process temperature of the furnace tube is above 1400℃, and the thickness of the gate oxide layer is 2000-5000A.

[0071] 11) Polysilicon deposition growth (Dpoly, LPCVD process) is achieved at the bottom of the trench with a thickness of 8000-10000A;

[0072] 12) Etch the entire surface of polysilicon to a depth of 1-2 μm to obtain the first polysilicon gate (mainly Poly Si);

[0073] 13) Wet-etch the oxide layer on the upper part of the trench with a thickness of 2000-10000A;

[0074] 14) A second gate oxide layer (mainly SiO2) is grown on the upper part of the trench. The process temperature of the furnace is above 1400°C, and the thickness of the gate oxide layer is 500-1500Å.

[0075] 15) Polysilicon deposition growth (Dpoly, LPCVD process) is achieved on the upper part of the trench, with a thickness of 8000-10000A;

[0076] 16) Etch the entire surface of polysilicon to a depth of 0.5-1 μm to obtain the second polysilicon gate (mainly Poly Si);

[0077] 17) Define the dummy gate contact hole area by photolithography and remove the upper polysilicon in the trench by etching;

[0078] 18) A SiO2 dielectric layer is deposited on the upper surface of the epitaxial layer using a PECVD process. The dielectric layer thickness is 9000-12000A.

[0079] 19) Use furnace tube annealing process to densify the dielectric layer, with the furnace tube temperature at 600-800℃;

[0080] 20) Etching the SiO2 dielectric layer to form contact holes for the true gate, dummy gate, and source;

[0081] 21) Front sputtering of metal Ni, thickness 500-1000A;

[0082] 22) RTA rapid thermal annealing treatment forms ohmic contact and wet etching of unreacted metal Ni;

[0083] 23) Sputter metal Al on the front with a thickness of 4-8 μm, and pattern it with wet etching to obtain the front metal layer;

[0084] 24) PI glue coating forms a passivation protective layer (i.e. PI glue passivation layer, mainly PI), and performs photolithography with a thickness of 8-12um;

[0085] 25) Wafer back grinding to remove silicon oxide and reduce thickness to 120-250um;

[0086] 26) Back-sputtering of metal Ni with a thickness of 500-1500A, and RTA rapid thermal annealing treatment to form ohmic contact;

[0087] 27) Sputter Ti / Ni / Ag metal on the back with a thickness of 1-2um to obtain a back metal layer.

[0088] See also Figure 4 , which shows a structural schematic diagram of a trench gate SiC MOSFET chip provided by Example 2 of the present invention, wherein the cell region includes a first trench, a second trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and the transition region includes a gate metal, a source metal and a plurality of contact holes; wherein, the first polysilicon gate is located in the first trench, the first gate oxide layer is located on the outer surface of the first polysilicon gate, the second polysilicon gate is located in the second trench, the second gate oxide layer is located on the outer surface of the second polysilicon gate, the number of the second trenches is two, and they are respectively located on both sides of the first trench, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the depth of the first trench is greater than the depth of the second trench, the first polysilicon gate is connected to the source metal through corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal through corresponding contact holes in the transition region.

[0089] A second embodiment of the present invention provides a high-reliability trench-gate SiC MOSFET chip, wherein a basic cell (cell region) includes a first trench, a second trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer, and a second gate oxide layer, and a transition region includes a gate metal, a source metal, and multiple contact holes. The first polysilicon gate and the first gate oxide layer are located in the first trench, the first gate oxide layer is between the first polysilicon gate and the inner surface of the first trench, and covers the outer surface of the first polysilicon gate. The second polysilicon gate and the second gate oxide layer are located in the second trench, the second gate oxide layer is between the second polysilicon gate and the inner surface of the second trench, and covers the outer surface of the second polysilicon gate. There are two second trenches, which are located on both sides of the first trench and respectively contact the adjacent side of the first trench. The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the depth of the first trench is greater than the depth of the second trench. The first polysilicon gate is connected to the source metal through corresponding contact holes in the chip transition region, and the second polysilicon gate is connected to the gate metal through corresponding contact holes in the chip transition region. Therefore, when the device is in the blocking state, the first gate oxide layer at the bottom of the first trench is subjected to a greater electric field strength. A larger first gate oxide layer thickness can improve the long-term reliability of the device during use. At the same time, the capacitance of this portion of the gate oxide layer is not included in the Miller capacitance, which can reduce the Miller capacitance of the device, improve switching speed, and reduce overall device losses. When the device is in the conducting state, the second gate oxide layer on the sidewall of the second trench has a thinner thickness, which can reduce the channel resistance and conduction loss of the device.

[0090] The trench-gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure. The gate oxide thickness at the trench bottom and sidewalls can be controlled separately. The gate oxide layer at the trench bottom, where the electric field intensity is greater, is thickened, thereby improving the long-term reliability of the device during use. The gate oxide layer is retained thinner in the sidewall trench, helping to reduce the device's channel resistance and conduction losses. This shows that the present invention can effectively reduce channel resistance and conduction losses while ensuring high device reliability.

[0091] In a trench gate SiC MOSFET chip provided in a second embodiment of the present invention, the cell region further includes an N+ doped region, a P+ contact region, and a substrate, and the transition region further includes a drain metal; wherein, the number of N+ doped regions and the number of P+ contact regions are both two, the two N+ doped regions are respectively located on the outside of the two second trenches relative to the first trench, the two P+ contact regions are respectively located on the outside of the two N+ doped regions relative to the second trench, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0092] The cell area also includes back metal, Buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer; among them, the back metal, substrate, Buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer are stacked in sequence from bottom to top, the first trench, the second trench, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0093] The cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

[0094] In the second embodiment of the present invention, the structure of the basic cell of the chip may include a substrate, a buffer layer, an epitaxial layer, a Pwell layer, an N+ doped region, a P+ contact region, a first polysilicon gate, a first gate oxide layer, a second polysilicon gate, a second gate oxide layer, a SiO2 dielectric layer, a front metal, a PI glue passivation layer, a trench, and a back metal, etc. The transition region includes a gate metal, a drain metal, a source metal, and a plurality of contact holes, etc. Figure 5 shown.

[0095] The number of N+ doped regions is 2, which are respectively located outside the two second trenches relative to the first trench and in contact with the adjacent second gate oxide layer. The depth of the N+ doped region is less than the depth of the second gate oxide layer, and the depths of the two N+ doped regions may be the same. The number of P+ contact regions is also 2, which are respectively located outside the two N+ doped regions relative to the second trenches and in contact with the adjacent N+ doped region. The depth of the P+ contact region may be the same as the depth of the N+ doped region. The N+ doped region and the P+ contact region are connected to the source metal in the transition region. The Pwell layer may include two sub-regions, the two sub-regions are respectively located outside the two P+ contact regions relative to the N+ doped region and in contact with the two P+ contact regions. The depths of the two sub-regions are greater than the depth of the N+ doped region and are not greater than the depth of the second gate oxide layer.

[0096] The back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer of the chip are stacked in order from bottom to top (from back to front). The first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region, the P+ contact region and the Pwell layer are all located in the epitaxial layer. The Pwell layer does not extend to the side boundary of the epitaxial layer. The SiO2 dielectric layer is located on the epitaxial layer and is divided into two sub-regions. One sub-region covers from one side boundary of the epitaxial layer to the N+ contact region on that side. The upper surface of the doped region is partially covered by the other sub-region from the other side boundary of the epitaxial layer to the upper surface of the N+ doped region on this side; the front metal layer is located on the SiO2 dielectric layer, does not extend to the side boundary of the epitaxial layer, and fills the gap between the two sub-regions of the SiO2 dielectric layer to contact the upper surface of the P+ contact region and the upper surface of the N+ doped region; the PI glue passivation layer is located on the front metal layer, and fills the gap between the side boundary of the front metal layer and the side boundary of the SiO2 dielectric layer to contact the upper surface of the SiO2 dielectric layer. The substrate on the back of the chip is connected to the drain metal. In the implementation method of the second embodiment of the present invention, in the middle connecting part of the two grooves, there is only a concave corner in the horizontal direction without a convex corner structure, thereby avoiding the electric field concentration effect at the convex corner position of the groove, further improving the long-term reliability of the device during use.

[0097] The trench-gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure. The gate oxide thickness at the trench bottom and sidewalls can be controlled separately. The gate oxide layer at the trench bottom, where the electric field intensity is higher, is thickened, thereby improving the long-term reliability of the device during use. The gate oxide layer is retained thinner in the sidewall trench, helping to reduce the device's channel resistance and conduction losses. Furthermore, the composite trench gate structure can reduce the device's Miller capacitance, improve switching speed, and reduce overall losses.

[0098] The first embodiment of the present invention further provides a method for manufacturing a trench gate SiC MOSFET chip, which is used to manufacture the chip as in the first embodiment of the present invention. Figure 6 As shown, the manufacturing method may specifically include:

[0099] S21: Setting a substrate, and growing a buffer layer and an epitaxial layer sequentially upward on the substrate;

[0100] S22: Pwell ions, Source ions and Pplus ions are sequentially implanted into the epitaxial layer to form corresponding Pwell layers, N+ doped regions and P+ contact regions, respectively;

[0101] S23: depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a first trench on the SiO2 etching hard mask layer, growing a first sacrificial oxide layer on the inner surface of the first trench, removing the first sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the first trench, growing polysilicon in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a first polysilicon gate;

[0102] S24: etching a second trench on the SiO2 etching hard mask layer, growing a second sacrificial oxide layer on the inner surface of the second trench, removing the second sacrificial oxide layer and growing a second gate oxide layer on the inner surface of the second trench, growing polysilicon deposit in the second gate oxide layer and etching the polysilicon on the entire surface to obtain a second polysilicon gate;

[0103] S25: depositing and growing a SiO2 dielectric layer on the upper surface of the epitaxial layer, densifying the SiO2 dielectric layer, and etching the SiO2 dielectric layer to form a source contact hole and a gate contact hole including a dummy gate and a real gate;

[0104] S26: sputtering metal nickel on a portion of the SiO2 dielectric layer and a portion of the epitaxial layer, performing thermal annealing to form an ohmic contact, wet-etching the unreacted metal nickel, continuously sputtering metal aluminum and wet-etching it for patterning to obtain a front metal layer, and covering a portion of the front metal layer and a portion of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer;

[0105] S27: Grind the lower surface of the substrate to remove silicon oxide, sputter metal nickel, perform thermal annealing to form an ohmic contact, and continue sputtering metal titanium, nickel or silver to obtain a back metal layer.

[0106] The manufacturing process of the trench gate SiC MOSFET chip provided in the second embodiment of the present invention includes ion implantation, high-temperature activation annealing of impurities, SiO2 wet etching, SiC trench dry etching, sacrificial oxide layer and gate oxide layer growth, polysilicon deposition and dry etching, wafer backside thinning, RTA metal alloying and other process steps. The specific manufacturing method is as follows:

[0107] Use 4H-SiC single crystal substrate, the wafer size is 4-8 inches, the substrate thickness is 350-500um, the conductivity type is N-type, and the doping concentration is greater than 1E18cm-3;

[0108] The buffer layer and epitaxial layer (both mainly SiC) are grown on the SiC substrate using CVD epitaxy. The thickness of the buffer layer is 0.5-2um, and the thickness of the epitaxial layer is 10-30um. The doping concentration of the buffer layer is 5E16-1E18cm-3, and the doping concentration of the epitaxial layer is 1E14-1E17cm-3. During the epitaxial growth process, the process chamber temperature is 1400℃-1800℃. The surface of the wafer after epitaxial growth must be kept clean.

[0109] Implement Pwell ion implantation (Al+ ions) in the epitaxial layer to simultaneously form the Pwell layer (mainly P SiC) in the cell region and the terminal field limiting ring. The implantation dose is 1E13-1E14 and the implantation energy is 200-800keV.

[0110] Implement Source ion implantation (N ions) in the epitaxial layer to form a Source region (i.e., N+ doped region, mainly NSiC) with an implantation dose of 5E14-5E15 and an implantation energy of 40-300keV.

[0111] Implement Pplus ion implantation (Al+ ions) in the epitaxial layer to form a P+ contact region (mainly P SiC) with an implantation dose of 5E14-5E15 and an implantation energy of 50-500keV.

[0112] The impurities are activated by furnace tube annealing. The process temperature of the furnace tube is above 1600℃. It is necessary to ensure that the one-time activation rate of all impurities is above 80%.

[0113] A SiO2 etching hard mask layer is deposited on the upper surface of the epitaxial layer by PECVD with a thickness of 5000-10000A;

[0114] Perform the first trench etching from the upper surface of the epitaxial layer downwards to a depth of 0.5-3 μm;

[0115] Growing a sacrificial oxide layer in the first trench with a thickness of 800-1200 Å, and removing the sacrificial oxide layer;

[0116] 10) The first gate oxide layer (mainly SiO2) is grown in the first trench. The process temperature of the furnace tube is above 1400℃, and the thickness of the gate oxide layer is 2000-5000A.

[0117] 11) Deposition and growth of polysilicon (Dpoly, LPCVD process) in the first trench with a thickness of 8000-10000A;

[0118] 12) Etch the entire surface of polysilicon to a depth of 8000-10000A to obtain the first polysilicon gate (mainly Poly Si);

[0119] 13) Etch the second trench area from the top surface of the epitaxial layer downward to a depth of 0.5-1.5 μm;

[0120] 14) Grow a sacrificial oxide layer in the second trench with a thickness of 800-1200 Å and remove the sacrificial oxide layer;

[0121] 15) A second gate oxide layer (mainly SiO2) is grown in the second trench. The process temperature of the furnace is above 1400°C, and the thickness of the gate oxide layer is 500-1500Å.

[0122] 16) Deposition and growth of polysilicon (Dpoly, LPCVD process) in the second trench with a thickness of 5000-10000A;

[0123] 17) Etch the entire surface of polysilicon to a depth of 5000-10000A to obtain the second polysilicon gate (mainly Poly Si);

[0124] 18) A SiO2 dielectric layer is deposited on the upper surface of the epitaxial layer using a PECVD process. The dielectric layer thickness is 9000-12000A.

[0125] 19) Use furnace tube annealing process to densify the dielectric layer, with the furnace tube temperature at 600-800℃;

[0126] 20) Etching the SiO2 dielectric layer to form contact holes for the true gate, dummy gate, and source;

[0127] 21) Front sputtering of metal Ni, thickness 500-1000A;

[0128] 22) RTA rapid thermal annealing treatment forms ohmic contact and wet etching of unreacted metal Ni;

[0129] 23) Sputter metal Al on the front with a thickness of 4-8 μm, and pattern it with wet etching to obtain the front metal layer;

[0130] 24) PI glue coating forms a passivation protective layer (i.e. PI glue passivation layer, mainly PI), and performs photolithography with a thickness of 8-12um;

[0131] 25) Wafer back grinding to remove silicon oxide and reduce thickness to 120-250um;

[0132] 26) Back-sputtering of metal Ni with a thickness of 500-1500A, and RTA rapid thermal annealing treatment to form ohmic contact;

[0133] 27) Back-sputtering metal Ti / Ni / Ag, thickness 1-2um.

[0134] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest manner consistent with the principles and novel features disclosed herein.

Claims

1. A trench gate SiC MOSFET chip, characterized in that: The cell region includes a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer, and a second gate oxide layer, and the transition region includes a gate metal, a source metal, and a plurality of contact holes; wherein the first polysilicon gate is located at the bottom of the trench, the first gate oxide layer is located on the outer surface of the first polysilicon gate, the second polysilicon gate is located at the upper portion of the trench, the second gate oxide layer is located on the outer surface of the second polysilicon gate, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; The grooves of the cell region are arranged in parallel in two or more lines in the transition region; In the transition region, by connecting two or more trenches in parallel, the first polysilicon gates in the two or more trenches are connected to the source metal through the corresponding contact holes; and by connecting two or more trenches in parallel, the second polysilicon gates in the two or more trenches are connected to the gate metal through the corresponding contact holes; when the transition region is provided with two trenches in parallel, there is only a concave corner in the horizontal direction in the middle connecting part of the two parallel trenches.

2. The trench gate SiC MOSFET chip according to claim 1, characterized in that: The cell region also includes an N+ doped region, a P+ contact region and a substrate, and the transition region also includes a drain metal; wherein, the number of the N+ doped region and the number of the trenches are both two, the two N+ doped regions are located between the two trenches, and are respectively in contact with the two first gate oxide layers, the P+ contact region is sandwiched between the two N+ doped regions and is respectively in contact with the two N+ doped regions, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

3. The trench gate SiC MOSFET chip according to claim 2, characterized in that: The cell area also includes a back metal, a Buffer layer, an epitaxial layer, a SiO2 dielectric layer, a front metal and a PI glue passivation layer; wherein the back metal, the substrate, the Buffer layer, the epitaxial layer, the SiO2 dielectric layer, the front metal and the PI glue passivation layer are stacked in sequence from bottom to top, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

4. The trench gate SiC MOSFET chip according to claim 3, characterized in that: The cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

5. A method for manufacturing a trench gate SiC MOSFET chip, characterized in that: For manufacturing the trench gate SiC MOSFET chip according to any one of claims 1 to 4, the manufacturing method comprises: Providing a substrate, and sequentially growing a buffer layer and an epitaxial layer upward on the substrate; In the epitaxial layer, Pwell ions, Source ions and Pplus ions are sequentially implanted to form corresponding Pwell layers, N+ doped regions and P+ contact regions, respectively; Depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a trench on the SiO2 etching hard mask layer, growing a sacrificial oxide layer on the inner surface of the trench, removing the sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the trench, growing polysilicon in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a first polysilicon gate; Wet etching a first gate oxide layer located on the inner surface of the upper portion of the trench, growing a second gate oxide layer on the inner surface of the upper portion of the trench, growing polysilicon deposits in the first gate oxide layer, and etching the entire surface of the polysilicon to obtain a second polysilicon gate; Photolithographically defining a dummy gate contact hole region, etching away an upper layer of polysilicon in the trench, and depositing and growing a SiO2 dielectric layer on the upper surface of the epitaxial layer, densifying the SiO2 dielectric layer, and etching the SiO2 dielectric layer to form a source contact hole and a gate contact hole including a dummy gate and a true gate; Sputtering metal nickel on a portion of the SiO2 dielectric layer and a portion of the epitaxial layer, performing thermal annealing to form an ohmic contact, wet-etching unreacted metal nickel, continuously sputtering metal aluminum and wet-etching it for patterning to obtain a front metal layer, and covering the portion of the front metal layer and the portion of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer; The lower surface of the substrate is ground to remove silicon oxide, and metal nickel is sputtered, and thermal annealing is performed to form an ohmic contact, and metal titanium, nickel or silver is continuously sputtered to obtain a back metal layer.

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