Monitoring circuit of radio frequency reference frequency source and frequency calibration method

Abstract

The invention discloses a monitoring circuit of a radio frequency reference frequency source and a frequency calibration method. The monitoring circuit comprises: a reset signal generation circuit, which is used for generating and outputting a reset signal; the first input end of the reset signal delay circuit is connected with the output end of the reset signal generation circuit, and the reset signal delay circuit is used for resetting a circuit module of the radio frequency reference frequency source; the first input end of the reset signal generation circuit is connected with the output end of the comparator, and the second input end of the reset signal generation circuit is connected with the output end of the radio frequency reference frequency source; and the output end of the reset signal delay circuit is connected with a reset port of at least one circuit module of the radio frequency reference frequency source. The monitoring circuit disclosed by the invention can automatically detect the radio frequency reference frequency source and automatically output the reset signal to reset each module of the radio frequency reference frequency source.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a monitoring circuit and a frequency calibration method for a radio frequency reference frequency source. Background Art

[0002] See also Figure 1 An oscillator comprises two comparators for outputting pulse signals; two charging and discharging circuits, wherein the output end of a first charging and discharging circuit C1 of the two charging and discharging circuits is connected to the negative input end of a first comparator CMP1 of the two comparators, and the output end of a second charging and discharging circuit C2 of the two charging and discharging circuits is connected to the negative input end of a second comparator CMP2 of the two comparators; two reference voltage generating circuits, wherein the reference voltage output end of a first reference voltage generating circuit REF1 of the two reference voltage generating circuits is connected to the positive input end of the first comparator CMP1, the comparator offset cancellation reference voltage output end of the first reference voltage generating circuit REF1 of the two reference voltage generating circuits is connected to the comparator offset cancellation reference voltage input end of the first comparator CMP1, the reference voltage output end of a second reference voltage generating circuit REF2 of the two reference voltage generating circuits is connected to the positive input end of the second comparator CMP2, and the comparator offset cancellation reference voltage output end of the second reference voltage generating circuit REF2 of the two reference voltage generating circuits is connected to the comparator offset cancellation reference voltage input end of the first comparator CMP2.

[0003] The above-mentioned oscillator needs to meet certain working timing to work normally, but in the event of emergencies such as sudden changes in power supply voltage, the oscillator may have timing disorders and fail to output the target clock signal normally. After the power supply voltage is restored, it cannot return to normal, and the output clock frequency of the oscillator will deviate from the target frequency. Summary of the invention

[0004] The present invention provides a monitoring circuit and a frequency calibration method for a radio frequency reference frequency source, which are used for automatically detecting the radio frequency reference frequency source and automatically outputting a reset signal to reset each module of the radio frequency reference frequency source.

[0005] In a first aspect, an embodiment of the present invention provides a monitoring circuit, comprising:

[0006] A reset signal generating circuit, wherein the reset signal generating circuit is used to generate and output a reset signal;

[0007] A reset signal delay circuit, wherein a first input end of the reset signal delay circuit is connected to an output end of the reset signal generating circuit, and the reset signal delay circuit is used to reset a circuit module of a radio frequency reference frequency source;

[0008] The monitoring circuit is configured in a reset module of the radio frequency reference frequency source;

[0009] The first input terminal of the reset signal generating circuit is connected to the output terminal of the comparator in the radio frequency reference frequency source, and the second input terminal is connected to the output terminal of the radio frequency reference frequency source;

[0010] The output end of the reset signal delay circuit is connected to a reset port of at least one circuit module of a radio frequency reference frequency source.

[0011] The monitoring circuit provided in the present application generates a reset signal by using the output signal of the comparator and the output signal of the RF reference frequency source, and can automatically detect the RF reference frequency source and automatically output a reset signal to reset each module of the RF reference frequency source.

[0012] In a second aspect, an embodiment of the present invention provides a radio frequency reference frequency source, comprising a monitoring circuit as in the first aspect.

[0013] In a third aspect, an embodiment of the present invention provides a frequency calibration method, which is applied to the radio frequency reference frequency source as described in the second aspect, and the method includes:

[0014] According to different ambient temperatures, the frequency of the radio frequency reference frequency source is adjusted respectively so that the temperature coefficient of the frequency of the radio frequency reference frequency source reaches a minimum value;

[0015] Based on the reset signal output by the monitoring circuit, the first control word and the second control word are adjusted simultaneously until the frequency of the RF reference frequency source reaches the target frequency; wherein the first control word is used to adjust the resistance value of the RF reference frequency source, and the second control word is used to adjust the temperature coefficient.

[0016] The control method provided in the present application is used to adjust the frequency of a radio frequency reference frequency source to a target frequency by simultaneously adjusting a first control word and a second control word. When adjusting the first control word, the second control word is also adjusted, thereby ensuring that the frequency adjustment workload can be effectively reduced while the frequency temperature coefficient is fixed.

[0017] In a fourth aspect, an embodiment of the present invention further provides an electronic device, comprising a processor and a memory, wherein the memory is used to store programs executable by the processor, and the processor is used to read the programs in the memory and execute the steps of any one of the methods described in the second aspect above.

[0018] In a fifth aspect, an embodiment of the present invention further provides a computer storage medium on which a computer program is stored, and when the program is executed by a processor, it is used to implement the steps of any one of the methods described in the second aspect above.

[0019] In a sixth aspect, the present application provides a computer program product, comprising: a computer program code, when the computer program code is run on a computer, the computer executes any one of the methods described in the second aspect.

[0020] These and other aspects of the present application will be more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 A schematic diagram of the circuit structure of an existing radio frequency reference frequency source provided by an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of a working waveform of a radio frequency reference frequency source in an abnormal state provided by an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of a monitoring circuit provided by an embodiment of the present invention;

[0025] Figure 4 A schematic diagram of a reset signal generating circuit provided by an embodiment of the present invention;

[0026] Figure 5 A schematic diagram of the structure of a monitoring circuit provided by an embodiment of the present invention;

[0027] Figure 6 A waveform diagram of a monitoring circuit under normal working conditions provided by an embodiment of the present invention;

[0028] Figure 7 A waveform diagram of an abnormal working state of a monitoring circuit provided by an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of the full-process working waveform of a monitoring circuit provided by an embodiment of the present invention;

[0030] Fig. 9 A circuit diagram of a radio frequency reference frequency source provided by an embodiment of the present invention;

[0031] Fig.10 A flow chart of a frequency calibration method implementation provided by an embodiment of the present invention;

[0032] Fig.11 A schematic diagram of a frequency adjustment circuit for a radio frequency reference frequency source provided by an embodiment of the present invention;

[0033] Fig.12 A flow chart of a frequency calibration method implementation provided by an embodiment of the present invention;

[0034] Fig.13 A waveform diagram of a monitoring circuit in an abnormal state provided by an embodiment of the present invention;

[0035] Fig.14 An implementation process of a dichotomy method for frequency adjustment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0038] The application scenarios described in the embodiments of the present invention are intended to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided by the embodiments of the present invention are also applicable to similar technical problems. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0039] Before introducing the monitoring circuit provided in the embodiment of the present application, in order to facilitate understanding, the technical background of the embodiment of the present application is first introduced in detail below.

[0040] See also Figure 1An oscillator comprises two comparators for outputting pulse signals; two charging and discharging circuits, wherein the output end of a first charging and discharging circuit C1 of the two charging and discharging circuits is connected to the negative input end of a first comparator CMP1 of the two comparators, and the output end of a second charging and discharging circuit C2 of the two charging and discharging circuits is connected to the negative input end of a second comparator CMP2 of the two comparators; two reference voltage generating circuits, wherein the reference voltage output end of a first reference voltage generating circuit REF1 of the two reference voltage generating circuits is connected to the positive input end of the first comparator CMP1, the comparator offset elimination reference voltage output end of the first reference voltage generating circuit REF1 of the two reference voltage generating circuits is connected to the comparator offset elimination reference voltage input end of the first comparator CMP1, the reference voltage output end of a second reference voltage generating circuit REF2 of the two reference voltage generating circuits is connected to the positive input end of the second comparator CMP2, and the comparator offset elimination reference voltage output end of the second reference voltage generating circuit REF2 of the two reference voltage generating circuits is connected to the positive input end of the second comparator CMP2. The voltage output terminal is connected to the comparator offset elimination reference voltage input terminal of the first comparator CMP2. Under the logic timing control of the two reference voltage generating circuits, each comparison cycle includes a precharging stage and a charging stage. In the first half of each comparison cycle, the first comparator CMP1 is in the precharging stage, and the input voltage of the first comparator CMP1 is charged to the first reference voltage. The second comparator CMP2 is in the charging stage, and the input voltage of the second comparator CMP2 is charged from the first reference voltage to the second reference voltage. In the second half of each comparison cycle, the first comparator CMP1 is in the charging stage, and the input voltage of the first comparator CMP1 is charged from the first reference voltage to the second reference voltage. The second comparator CMP2 is in the precharging stage, and the input voltage of the second comparator CMP2 is charged from the second reference voltage to the first reference voltage after being reset. The delays and voltage offsets in the two comparison processes of the comparator in the same comparison cycle cancel each other out, wherein the first reference voltage is less than the second reference voltage. The above oscillator is based on an existing relaxation oscillator. The oscillator may include an IREF circuit, a CMP circuit (such as a first comparator CMP1 and a second comparator CMP2), a delay generation (DELAY) circuit (such as DELAY1 and DELAY2), a logic control (LOGIC) circuit (such as LOGCI1 and LOGCI2), a charge and discharge circuit (such as C1 and C2), a chopping circuit (CHOP) circuit (such as CHOP1, etc. Specifically, the IREF circuit, CMP circuit, DELAY circuit, LOGCI circuit, charge and discharge circuit, and CHOP circuit included in the above oscillator may all adopt an existing circuit structure.

[0041] The above oscillators need to meet certain working timings to work properly. However, when there are sudden situations such as sudden changes in the power supply voltage, the oscillator may have timing disorder and cannot output the target clock signal normally. Figure 2 As shown, the waveforms from top to bottom in the figure are: power supply voltage, comparator input signal vc1, comparator output signal cmp1o, oscillator output signal CK, and oscillator output signal frequency. In the figure, the power supply voltage starts to drop at 2us and returns to normal at about 4.2us. The comparator input signal vc1 starts to become abnormal at about 2.3us and cannot return to normal after the power supply voltage is restored. The comparator output signal cmp1o also starts to become abnormal at about 2.3us and cannot return to normal after the power supply voltage is restored. The oscillator output clock CK also starts to become abnormal at about 2.3us and cannot return to normal after the power supply voltage is restored. It can be seen from the frequency of the oscillator output clock that the oscillator output clock frequency is about 18MHz after the power supply voltage is restored, which deviates from the target frequency by 8MHz.

[0042] In order to solve the above technical problems, the present application provides a monitoring circuit for generating a reset signal according to the output signal of the comparator of the RF reference frequency source and the output signal of the RF reference frequency source, automatically resetting each circuit module of the RF reference frequency source, and solving the problem that the RF reference frequency source may have timing disorder and cannot output the target clock signal normally when there is an emergency such as a sudden change in the power supply voltage. The RF reference frequency source can be an oscillator or other frequency domain source in the RF field.

[0043] like Figure 3 As shown, this embodiment provides a schematic diagram of a monitoring circuit, including:

[0044] A reset signal generating circuit 300, wherein a first input terminal of the reset signal generating circuit 300 is connected to an output terminal of the comparator, and a second input terminal of the reset signal generating circuit 300 is connected to an output terminal of a radio frequency reference frequency source, and the reset signal generating circuit 300 is used to generate and output a reset signal;

[0045] A reset signal delay circuit 301, wherein the first input end of the reset signal delay circuit 301 is connected to the output end of the reset signal generating circuit 300, and the output end of the reset signal delay circuit 301 is connected to the reset port of at least one circuit module of the RF reference frequency source, and the reset signal delay circuit 301 is used to reset the circuit module of the RF reference frequency source.

[0046] In some embodiments, the reset signal generating circuit 300 includes a first generating circuit 300a and a second generating circuit 300b; the first generating circuit 300a is used to perform a two-frequency division process on the output signal of the comparator to obtain a two-frequency division signal; the second generating circuit 300b is used to sample the two-frequency division signal according to the output signal of the RF reference frequency source, and generate and output a reset signal.

[0047] Optionally, the RF reference frequency source in this embodiment includes but is not limited to an oscillator, or a frequency source applied to the RF field, and this embodiment does not impose too many limitations on this.

[0048] In some embodiments, Figure 4 As shown, this embodiment provides a schematic diagram of a reset signal generating circuit, wherein:

[0049] The first input terminal of the first generating circuit 300a is connected to the output terminal of the comparator, and the output terminal of the first generating circuit is connected to the first input terminal of the second generating circuit 300b;

[0050] The second input terminal of the second generating circuit 300 b is connected to the output terminal of the radio frequency reference frequency source, and the output terminal of the second generating circuit 300 b is connected to the first input terminal of the reset signal delay circuit 301 .

[0051] In some embodiments, the reset signal delay circuit 301 further includes a second input terminal, and the second input terminal of the reset signal delay circuit 301 is used to connect to a reset port.

[0052] Optionally, the reset port is used to access a reset signal from the outside and reset only once after power-on.

[0053] In some embodiments, the reset signal delay circuit 301 includes a plurality of delay modules, and the delay modules are used to perform delay processing on the reset signal.

[0054] like Figure 5As shown, this embodiment provides a structural schematic diagram of a monitoring circuit, wherein the reset signal generating circuit includes two clock circuits (Clk) and a delay circuit; the reset signal delay circuit includes four delay circuits. The first input terminal of the reset signal generating circuit is connected to the output terminal cmp1o of the comparator CMP1, the second input terminal is connected to the output terminal CK of the RF reference frequency source, the output terminal AUTO_RSTN of the reset signal generating circuit is connected to the first input terminal of the reset signal delay circuit, and the second input terminal of the reset signal delay circuit is connected to the external reset signal RSTN, which is reset only once after power-on. Various reset signals RSTNN, RST, RSTN_DLYO, RSTN_DLY1, RSTN_DLY2, RSTN_DLY3, etc. in the reset signal delay circuit are connected to the inside of the RF reference frequency source to reset each circuit module of the RF reference frequency source.

[0055] The reset signal generating circuit includes a first generating circuit and a second generating circuit, wherein a first input terminal of the first generating circuit is connected to an output terminal cmp1o of the comparator CMP1, and an output terminal cmp1o_div2 of the first generating circuit is connected to a first input terminal of the second generating circuit;

[0056] The second input terminal of the second generating circuit is connected to the output terminal CK of the radio frequency reference frequency source, and the output terminal AUTO_RSTN of the second generating circuit is connected to the first input terminal of the reset signal delay circuit.

[0057] Optionally, this embodiment does not limit the number of delay modules Delay included in the reset signal delay circuit.

[0058] like Figure 6 As shown, the present embodiment provides a waveform diagram of a monitoring circuit in a normal working state, wherein the waveforms from top to bottom are waveforms 1 to 5. Waveform 1 represents the comparator precharge signal vc1, waveform 2 represents the comparator output signal cmp1o, waveform 3 represents the two-frequency division signal cmp1o_div2 of cmp1o, waveform 4 represents the signal CKB after the output signal CK of the RF reference frequency source passes through the inverter, that is, the reverse output signal CKB of the RF reference frequency source, and waveform 5 represents the output signal AUTO_RSTN of the reset signal generating circuit.

[0059] Since vc1 has a pre-charging stage, under normal circumstances, the cmp1o signal outputs two pulses in one clock cycle, and the output of the cmp1o two-division signal cmp1o_div2 will be as shown in waveform 3. The cmp1o_div2 is sampled by the CKB signal of waveform 4, and the AUTO_RSTN signal of waveform 5 will always maintain a high level.

[0060] like Figure 7 As shown, the present embodiment provides a waveform diagram of an abnormal working state of a monitoring circuit, wherein the waveforms from top to bottom are waveforms 1 to 5. Waveform 1 represents the comparator precharge signal vc1, waveform 2 represents the comparator output signal cmp1o, waveform 3 represents the two-frequency division signal cmp1o_div2 of cmp1o, waveform 4 represents the signal CKB after the output signal CK of the RF reference frequency source passes through the inverter, that is, the reverse output signal CKB of the RF reference frequency source, and waveform 5 represents the output signal AUTO_RSTN of the reset signal generating circuit.

[0061] Among them, in the abnormal working state, the waveform of vc1 is abnormal, and the cmp1o signal cannot output two pulses in one clock cycle, then the output of cmp1o_div2 will be as shown in waveform 3 in the figure, and the CKB signal of waveform 4 is used to sample cmp1o_div2, then the AUTO_RSTN signal of waveform 5 will appear low level, thereby triggering the reset of the entire RF reference frequency source to restore it to normal operation.

[0062] like Figure 8 As shown, the present embodiment provides a schematic diagram of the full-process working waveform of a monitoring circuit, wherein the waveforms from top to bottom are waveforms 0 to 5. Waveform 0 represents the signal VDDA of the power supply voltage of the RF reference frequency source, waveform 1 represents the comparator precharge signal vc1, waveform 2 represents the comparator output signal cmp1o, waveform 3 represents the two-frequency division signal cmp1o_div2 of cmp1o, waveform 4 represents the signal CKB after the output signal CK of the RF reference frequency source passes through the inverter, that is, the reverse output signal CKB of the RF reference frequency source, and waveform 5 represents the output signal AUTO_RSTN of the reset signal generating circuit.

[0063] Among them, under normal working conditions, the output signal AUTO_RSTN of the reset signal generating circuit maintains a high level. When the power supply voltage drops sharply and causes output abnormality, AUTO_RSTN will appear at a low level, thereby triggering the reset of the entire RF reference frequency source. After that, the RF reference frequency source is reset and returns to normal state, and AUTO_RSTN continues to maintain a high level.

[0064] Based on the same inventive concept, the present application also provides a radio frequency reference frequency source configured with a monitoring circuit, the radio frequency reference frequency source includes a monitoring circuit, the monitoring circuit includes a reset signal generating circuit and a reset signal delay circuit, wherein:

[0065] The reset signal generating circuit is used to generate and output a reset signal; the first input end of the reset signal delay circuit is connected to the output end of the reset signal generating circuit, and the reset signal delay circuit is used to reset the circuit module of the radio frequency reference frequency source;

[0066] The monitoring circuit is configured in a reset module of the radio frequency reference frequency source;

[0067] The first input end of the reset signal generating circuit is connected to the output end of the comparator in the RF reference frequency source, and the second input end is connected to the output end of the RF reference frequency source; the output end of the reset signal delay circuit is connected to the reset port of at least one circuit module of the RF reference frequency source.

[0068] like Fig. 9 As shown, this embodiment further provides a radio frequency reference frequency source, the radio frequency reference frequency source comprising:

[0069] A reset module, the reset module includes a monitoring circuit, which is used to reset the circuit module of the radio frequency reference frequency source; the first input end of the reset module is connected to the output end cmplo of the comparator in the radio frequency reference frequency source, the second input end is connected to the output end CK of the radio frequency reference frequency source, and also includes a third input end RSTN (i.e., the second input end of the reset signal delay circuit), which is used to connect to the reset port. The output includes multiple reset signal output ends, namely RESET, RSTN_DLY0, RSTN_DLY1, RSTN_DLY2, and RSTN_DLY3, which are used to connect different circuit modules in the radio frequency reference frequency source and reset the connected circuit modules;

[0070] Two comparators for outputting pulse signals;

[0071] Two charge and discharge circuits, wherein the output end of the first charge and discharge circuit C1 of the two charge and discharge circuits is connected to the negative input end of the first comparator CMP1 of the two comparators, and the output end of the second charge and discharge circuit C2 of the two charge and discharge circuits is connected to the negative input end of the second comparator CMP2 of the two comparators; two reference voltage generating circuits, wherein the reference voltage output end of the first reference voltage generating circuit REF1 of the two reference voltage generating circuits is connected to the positive input end of the first comparator CMP1, the comparator offset elimination reference voltage output end of the first reference voltage generating circuit REF1 of the two reference voltage generating circuits is connected to the comparator offset elimination reference voltage input end of the first comparator CMP1, the reference voltage output end of the second reference voltage generating circuit REF2 of the two reference voltage generating circuits is connected to the positive input end of the second comparator CMP2, and the comparator offset elimination reference voltage output end of the second reference voltage generating circuit REF2 of the two reference voltage generating circuits is connected to the first comparator The first comparator CMP1 is connected to the comparator offset elimination reference voltage input terminal of the comparator CMP2. Under the logic timing control of the two reference voltage generating circuits, each comparison cycle includes a precharging stage and a charging stage. In the first half of each comparison cycle, the first comparator CMP1 is in the precharging stage, and the input voltage of the first comparator CMP1 is charged to the first reference voltage. The second comparator CMP2 is in the charging stage, and the input voltage of the second comparator CMP2 is charged from the first reference voltage to the second reference voltage. In the second half of each comparison cycle, the first comparator CMP1 is in the charging stage, and the input voltage of the first comparator CMP1 is charged from the first reference voltage to the second reference voltage. The second comparator CMP2 is in the precharging stage, and the input voltage of the second comparator CMP2 is charged from the second reference voltage to the first reference voltage after being reset. The delays and voltage offsets in the two comparison processes of the comparator in the same comparison cycle cancel each other out, wherein the first reference voltage is less than the second reference voltage. The above-mentioned RF reference frequency source is based on an existing relaxation oscillator. The oscillator may include an IREF circuit, a CMP circuit (such as a first comparator CMP1 and a second comparator CMP2), a delay generation (DELAY) circuit (such as DELAY1 and DELAY2), a logic control (LOGIC) circuit (such as LOGCI1 and LOGCI2), a charge and discharge circuit (such as C1 and C2), a chopping circuit (CHOP) circuit (such as CHOP1, etc. Specifically, the IREF circuit, CMP circuit, DELAY circuit, LOGCI circuit, charge and discharge circuit, and CHOP circuit included in the above-mentioned RF reference frequency source may all adopt an existing circuit structure.

[0072] Based on the same inventive concept, the present application also provides a frequency calibration method, such as Fig.10As shown, the implementation process of this method is as follows:

[0073] Step 1000: adjusting the frequency of the RF reference frequency source according to different ambient temperatures, so that the temperature coefficient of the frequency of the RF reference frequency source reaches a minimum value;

[0074] In some embodiments, the capacitance value of the RF reference frequency source is adjusted by a third control word, and the frequency of the RF reference frequency source is roughly adjusted by adjusting the capacitance value; at a preset room temperature and a preset high temperature, the temperature coefficient of the frequency of the RF reference frequency source is adjusted to a minimum value by a second control word.

[0075] Step 1001: Based on a reset signal output by a monitoring circuit, the first control word and the second control word are adjusted simultaneously until the frequency of the radio frequency reference frequency source reaches a target frequency and the adjustment is stopped;

[0076] The first control word is used to adjust the resistance value of the radio frequency reference frequency source, and the second control word is used to adjust the temperature coefficient of the frequency of the radio frequency reference frequency source.

[0077] It should be noted that in a circuit, frequency adjustment usually involves adjusting the frequency of an RF reference frequency source (such as an oscillator) or a clock signal. A control word is a binary number or data structure used to configure or control a hardware device. It can contain multiple bits, each of which controls a specific parameter or function of the circuit. For frequency adjustment, the control word may contain bits for setting the frequency value, and possible other bits for controlling the range, step size, or other related parameters of the frequency adjustment. Specifically in the circuit, this control word may be sent to the RF reference frequency source or clock generator via a microprocessor, digital signal processor (DSP), or other digital controller.

[0078] In some embodiments, the temperature coefficient of frequency is adjusted simultaneously by:

[0079] The first control word is adjusted to a preset gear position, and the adjusted second control word is determined according to a linear function relationship between the first control word and the second control word.

[0080] In some embodiments, the linear functional relationship between the first control word and the second control word is as follows:

[0081] The second control word is determined according to the proportion of the resistance through which the temperature compensation current flows to the entire resistance when the temperature coefficient of the RF reference frequency source frequency reaches a minimum value, and the first control word.

[0082] In implementation, the linear function relationship between the first control word and the second control word is shown in the following formula:

[0083]

[0084] In formula (1), KT represents the second control word, WT represents the first control word, α represents the ratio of the resistance through which the temperature compensation current flows to the entire resistance, a, b, c are determined according to the value of the resistance R and the adjustment range of WT and KT, and a, b, c are constants.

[0085] Optionally, a = 456, b = 152, c = 4. The specific values ​​of a, b, and c in this embodiment are obtained through testing, and the above values ​​can reduce the number of frequency adjustment times.

[0086] During implementation, the capacitance value of the RF reference frequency source is first adjusted by the third control word, and the frequency of the RF reference frequency source is roughly adjusted by the change of the capacitance value, so that the current frequency of the RF reference frequency source is closest to the target frequency. After that, the temperature coefficient of the frequency of the RF reference frequency source is adjusted to a minimum value by the second control word. At this time, the proportion of the resistance through which the temperature compensation current flows to the entire resistance is calculated. In order to ensure that the proportion remains unchanged during the process of adjusting the resistance by the first controller and then fine-tuning the frequency of the RF reference frequency source, this embodiment simultaneously adjusts the first control word and the second control word to ensure that the temperature coefficient of the frequency is adjusted by the second control word while the resistance is adjusted by the first control word, so that the temperature coefficient of the frequency reaches the minimum value during the frequency adjustment process.

[0087] like Fig.11 As shown, this embodiment provides a schematic diagram of a frequency trimming circuit of a radio frequency reference frequency source, wherein: the frequency trimming includes two parts: the temperature coefficient trimming of the frequency and the absolute value trimming of the frequency. An example of frequency trimming is as follows:

[0088] The control word for adjusting the temperature coefficient of the frequency is the second control word KT<5:0>; the circuit characteristics of the temperature coefficient adjustment part are shown in the figure.

[0089] The first control word WT<7:0> and the third control word CT<1:0> for adjusting the absolute value of the frequency; wherein the third control word CT is used for coarse adjustment of the frequency, and the first control word WT is used for fine adjustment of the frequency;

[0090] The frequency of the RF reference frequency source is shown in the following formula:

[0091]

[0092] In formula (1), I p represents the current with a positive temperature coefficient, and α represents the temperature compensation current I pThe resistance through which the current flows accounts for the proportion of the entire resistance, R represents the resistance that affects the frequency of the RF reference frequency source, C represents the capacitance that affects the frequency of the RF reference frequency source, I represents the current that charges the capacitance, and f represents the frequency of the RF reference frequency source.

[0093] The value of α can be adjusted by the second control word KT, thereby achieving adjustment of the frequency temperature coefficient.

[0094] The value of the resistor R can be adjusted by the first control word WT, and the value of the capacitor C can be adjusted by the third control word CT, thereby achieving the effect of adjusting the absolute value of the frequency.

[0095] like Fig.12 As shown, this embodiment provides a frequency calibration method, and the specific implementation process of the method is as follows:

[0096] Step 1200, adjusting the third control word CT to adjust the frequency f of the radio frequency reference frequency source to be closest to the target frequency f0;

[0097] Step 1201, adjusting the second controller WT to the lowest gear;

[0098] Step 1202: At room temperature (25° C.) and high temperature (125° C.), respectively, the temperature coefficient of the frequency f of the radio frequency reference frequency source is minimized by adjusting the first control word KT;

[0099] Step 1203, calculating the ratio α of the resistance through which the temperature compensation current flows to the entire resistance;

[0100] Step 1204: Use the binary method to adjust the first controller WT at room temperature, and use the first controller WT and the ratio α to calculate and adjust the second controller KT to adjust the frequency f to be closest to the target frequency f0.

[0101] The KT value can be calculated according to the above formula (1), and the second controller KT is adjusted to the calculated KT value.

[0102] It should be noted that the present embodiment can solve the problem that the RF reference frequency source mentioned in the background technology may not work properly under the condition of exceeding the target frequency due to the low power consumption of the comparator used in the RF reference frequency source, thereby causing the RF reference frequency source to be unable to output the correct clock signal and unable to perform frequency measurement. The present embodiment automatically detects the abnormal working state of the RF reference frequency source through the monitoring circuit, and the reset signal AUTO_RSTN output by the reset signal generation circuit continuously outputs low-level pulses. Therefore, during the frequency test process, once it is found that AUTO_RSTN outputs a low-level pulse, it can be determined that the output frequency of the RF reference frequency source exceeds the target frequency at this time, and a lower first control word WT value should be selected.

[0103] like Fig.13 As shown, this embodiment provides a waveform diagram of a monitoring circuit under an abnormal state, which is a waveform output when the third control word CT=3, the second control word KT=16, and the first control word WT=255, wherein from top to bottom are waveforms 1 to 4, waveform 1 represents the output signal CK of the RF reference frequency source, waveform 2 represents the input signal vc1 of the comparator, waveform 3 represents the output signal cmp1o of the first generating circuit of the reset signal generating circuit; waveform 4 represents the reset signal AUTO_RSTN output by the reset signal generating circuit (i.e., the reset signal output by the second generating circuit of the reset signal generating circuit).

[0104] It can be seen from the figure that the output signal CK of the RF reference frequency source, the input signal vc1 of the comparator and the output signal cmp1o of the first generating circuit of the reset signal generating circuit are all abnormal, and the reset signal AUTO_RSTN output by the reset signal generating circuit is continuously output as a low level pulse.

[0105] In some embodiments, this embodiment simultaneously adjusts the first control word and the second control word based on the reset signal output by the monitoring circuit in the following manner until the frequency of the RF reference frequency source reaches the target frequency and stops adjusting:

[0106] 1) If it is determined that the current frequency of the RF reference frequency source exceeds the target frequency based on the reset signal output by the monitoring circuit, the largest first control word of the two first control words of the binary division is determined according to the binary division value; wherein the binary division value is obtained by averaging the sum of the two first control words of the binary division;

[0107] Among them, when it is determined that the current frequency of the RF reference frequency source exceeds the target frequency based on the reset signal output by the monitoring circuit, it is determined that the frequency corresponding to the binary value is closer to the target frequency than the frequency corresponding to the first control word, indicating that the output frequency of the RF reference frequency source exceeds the target frequency at this time, and a lower first control word WT value should be selected.

[0108] 2) using a binary search method to select a first control word corresponding to a frequency closest to the target frequency from the two first control words, and using the first control word and the second control word to adjust the current frequency of the radio frequency reference frequency source;

[0109] 3) If the current frequency does not reach the target frequency, the first control word is updated, and the first control word corresponding to the frequency closest to the target frequency is selected from the two updated first control words using a binary search method, and the first control word and the second control word corresponding to the first control word are used to continue adjusting the next frequency of the RF reference frequency source until the frequency of the RF reference frequency source reaches the target frequency and stops adjusting.

[0110] like Fig.14 As shown, this embodiment provides an implementation process of the dichotomy method of frequency adjustment. Assuming that the frequency f is a function of WT f=f(WT), the specific implementation process is as follows:

[0111] Step 1400, set WT1=0, WT2=255;

[0112] Step 1401, calculating WT according to WT1 and WT2;

[0113] The formula is as follows:

[0114]

[0115] In formula (3), WT1 and WT2 represent two first control words used in the binary division method, WT represents the first control word used in frequency adjustment, and int represents rounding.

[0116] Step 1402, determine whether [f(WT1)-f0]×[f(WT)-f0]<0; or whether [f(WT1)-f0]<0 and the reset signal generating circuit outputs a negative pulse. If so, execute step 1403, otherwise execute step 1404;

[0117] Step 1403, WT2=WT;

[0118] Step 1404, WT1=WT;

[0119] Step 1405, determine whether |WT1-WT2|=1 is true, if so, execute step 1406, otherwise execute step 1401;

[0120] Step 1406, determine whether [f(WT1)-f0]×[f(WT2)-f0]≥0 is true, if so, execute step 1407, otherwise execute step 1408;

[0121] Step 1407, WT2 is the final WT value;

[0122] Step 1408, WT1 is the final WT value.

[0123] Since the conventional method usually uses a free combination method to adjust the frequency of the RF reference frequency source, the total number of tests required for this RF reference frequency source = WT gear number × KT gear number × test temperature point number = 256 × 64 × 2 = 32768. This embodiment reduces the number of variables from WT and KT to WT through formula (1), and then uses the binary method. The actual total number of tests required = log2 WT挡位数+ KT gear number × test temperature points = 8 + 64 × 2 = 136. Therefore, the frequency calibration method provided in this embodiment can effectively reduce the number of adjustments and the workload of adjustments.

[0124] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device. Since the electronic device is the electronic device in the method in the embodiment of the present invention, and the principle of solving the problem by the electronic device is similar to that of the method, the implementation of the electronic device can refer to the implementation of the method, and the repeated parts are not repeated. The electronic device includes a processor and a memory, the memory is used to store a program executable by the processor, and the processor is used to read the program in the memory and execute the steps of any of the above-mentioned frequency calibration methods.

[0125] Based on the same inventive concept, an embodiment of the present disclosure provides a computer storage medium, the computer storage medium comprising: a computer program code, when the computer program code is executed on a computer, the computer executes any of the frequency calibration methods discussed above. Since the principle of solving the problem by the above-mentioned computer storage medium is similar to that of the frequency calibration method, the implementation of the above-mentioned computer storage medium can refer to the implementation of the method, and the repeated parts will not be repeated.

[0126] In the specific implementation process, the computer storage medium may include: Universal Serial Bus Flash Drive (USB), mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other storage media that can store program codes.

[0127] Based on the same inventive concept, the embodiment of the present disclosure further provides a computer program product, the computer program product comprising: computer program code, when the computer program code is run on a computer, the computer executes any of the frequency calibration methods discussed above. Since the principle of solving the problem by the above computer program product is similar to that of the frequency calibration method, the implementation of the above computer program product can refer to the implementation of the method, and the repeated parts will not be repeated.

[0128] The computer program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more conductors, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0129] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0130] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that has the functions specified in one or more boxes.

[0131] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0132] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0133] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A monitoring circuit for a radio frequency reference frequency source, characterized in that: include: A reset signal generating circuit, wherein the reset signal generating circuit is used to generate and output a reset signal; A reset signal delay circuit, wherein a first input end of the reset signal delay circuit is connected to an output end of the reset signal generating circuit, and the reset signal delay circuit is used to reset a circuit module of a radio frequency reference frequency source; The monitoring circuit is configured in a reset module of the radio frequency reference frequency source; The first input terminal of the reset signal generating circuit is connected to the output terminal of the comparator in the radio frequency reference frequency source, and the second input terminal is connected to the output terminal of the radio frequency reference frequency source; The output end of the reset signal delay circuit is connected to a reset port of at least one circuit module of a radio frequency reference frequency source.

2. The monitoring circuit according to claim 1, characterized in that: The reset signal generating circuit includes a first generating circuit and a second generating circuit; The first generating circuit is used to perform a two-frequency division process on the output signal of the comparator to obtain a two-frequency division signal; The second generating circuit is used to sample the two-frequency-divided signal according to the output signal of the radio frequency reference frequency source, and generate and output a reset signal.

3. The monitoring circuit according to claim 2, characterized in that: The first input terminal of the first generating circuit is connected to the output terminal of the comparator, and the output terminal of the first generating circuit is connected to the first input terminal of the second generating circuit; The second input end of the second generating circuit is connected to the output end of the radio frequency reference frequency source, and the output end of the second generating circuit is connected to the first input end of the reset signal delay circuit.

4. The monitoring circuit according to claim 1, characterized in that: The reset signal delay circuit also includes a second input end, and the second input end of the reset signal delay circuit is used to connect to the reset port.

5. The monitoring circuit according to claim 1, characterized in that: The reset signal delay circuit includes a plurality of delay modules, and the delay modules are used to perform delay processing on the reset signal.

6. A radio frequency reference frequency source, characterized in that: The monitoring circuit comprises the monitoring circuit as claimed in any one of claims 1 to 5.

7. A frequency calibration method, characterized in that: Applied to the radio frequency reference frequency source of claim 6, the method comprising: According to different ambient temperatures, the frequency of the radio frequency reference frequency source is adjusted respectively so that the temperature coefficient of the frequency of the radio frequency reference frequency source reaches a minimum value; Based on the reset signal output by the monitoring circuit, the first control word and the second control word are adjusted simultaneously until the frequency of the RF reference frequency source reaches the target frequency; wherein the first control word is used to adjust the resistance value of the RF reference frequency source, and the second control word is used to adjust the temperature coefficient.

8. The method according to claim 7, characterized in that The frequency adjustment of the radio frequency reference frequency source according to different ambient temperatures includes: Adjusting the capacitance value of the radio frequency reference frequency source by a third control word, and adjusting the frequency of the radio frequency reference frequency source by adjusting the capacitance value; At a preset room temperature and a preset high temperature, the temperature coefficient of the frequency of the radio frequency reference frequency source is adjusted to a minimum value through the second control word.

9. The method according to claim 7, characterized in that: The simultaneously adjusting the first control word and the second control word comprises: The first control word is adjusted to a preset gear position, and the adjusted second control word is determined according to a linear function relationship between the first control word and the second control word.

10. The method according to claim 9, characterized in that The linear function relationship is as follows: The second control word is determined according to the ratio of the resistance through which the temperature compensation current flows to the entire resistance when the temperature coefficient of the RF reference frequency source frequency reaches a minimum value, and the first control word.

11. The method according to claim 9, characterized in that The linear function relationship is as follows: Among them, WT represents the first control word, KT represents the second control word, α represents the proportion of the resistance through which the temperature compensation current flows to the entire resistance, a, b, c are determined according to the value of the resistance R and the adjustment range of WT and KT, and a, b, c are constants.

12. The method according to claim 11, characterized in that a=456, b=152, c=4.

13. The method according to claim 7, characterized in that The method of adjusting the first control word and the second control word simultaneously based on the reset signal output by the monitoring circuit until the frequency of the radio frequency reference frequency source reaches the target frequency includes: If it is determined that the current frequency of the RF reference frequency source exceeds the target frequency based on the reset signal output by the monitoring circuit, the largest first control word of the two first control words of the binary division is determined according to the binary value; wherein the binary value is obtained by averaging the sum of the two first control words of the binary division; Selecting a first control word corresponding to a frequency closest to a target frequency from two first control words by using a binary search method, and adjusting a current frequency of the radio frequency reference frequency source by using the first control word and the second control word; If the current frequency does not reach the target frequency, the first control word is updated, and the first control word corresponding to the frequency closest to the target frequency is selected from the two updated first control words by binary search, and the first control word and the second control word corresponding to the first control word are used to continue to adjust the next frequency of the RF reference frequency source until the frequency of the RF reference frequency source reaches the target frequency and stops adjusting.

14. The method according to claim 13, characterized in that Selecting the first control word corresponding to the frequency closest to the target frequency from the two first control words by using a binary search method includes: If the reset signal output by the monitoring circuit is a low level pulse, it is determined that the current frequency of the radio frequency reference frequency source exceeds the target frequency; A binary search method is used to select a smaller first control word from the two first control words.

15. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store a program executable by the processor, and the processor is used to read the program in the memory and execute the steps of any one of the methods of claims 7 to 14.

16. A computer storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 7 to 14 are implemented.

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