Mismatch calibration circuit based on voltage-to-time converter and control method thereof

Abstract

The present application provides a mismatch calibration circuit based on a voltage-to-time converter and a control method thereof, which relates to the technical field of analog-to-digital converters, and includes: using a first voltage-to-time converter and a second voltage-to-time converter to output a first time signal and a second time signal, using a phase detector to detect the phase difference between a third time signal and a fourth time signal, and outputting a first phase difference signal to a first trigger module, outputting a second phase difference signal to a second trigger module, and outputting a pulse signal to a successive approximation logic module. Using a successive approximation logic module to output a control signal according to the pulse signal so that the trigger module outputs a delay signal. The delay module delays the time signal according to the received delay signal to adjust the phase of the time signal. The above-mentioned mismatch calibration circuit can use a phase detector to detect the output time error of the voltage-to-time converter, and use a successive approximation logic module to modify the delay weight, thereby calibrating the mismatch of the voltage-to-time converter.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital converters, and in particular to a mismatch calibration circuit based on a voltage-to-time converter and a control method thereof. Background Art

[0002] A time-domain analog-to-digital converter is an electronic device that can convert continuous analog signals into digital signals. The time-domain analog-to-digital converter uses a voltage-to-time converter and a time-to-digital converter to achieve voltage-to-digital conversion. The voltage-to-time converter collects the input signal onto a capacitor and charges or discharges the capacitor. When the voltage on the capacitor exceeds or falls below a preset voltage threshold, the comparator is used to change the output level to achieve quantization from voltage to time. Since the two comparators in the voltage-to-time converter may mismatch, there is an error between the time pulse width of the output time signal and the true value, which reduces the performance of the time-domain analog-to-digital converter.

[0003] By adjusting the output time difference of the two comparators of the voltage-to-time converter off-chip, that is, changing the inverter current connected to the comparator, or changing the capacitance value on the comparator output path, the output delay of the two comparators can be changed, thereby correcting the mismatch of the comparators. However, since the above calibration method requires manual operation, each manufactured voltage-to-time converter must be calibrated individually, which cannot be automated and is difficult to be widely used. Summary of the invention

[0004] The present application provides a mismatch calibration circuit based on a voltage-to-time converter and a control method thereof, which can use a phase detector to detect the output time error of the voltage-to-time converter, and use a successive approximation logic module to modify the delay weight, thereby calibrating the voltage mismatch of the voltage-to-time converter.

[0005] In a first aspect, the present application provides a mismatch calibration circuit based on a voltage-to-time converter, comprising: a first voltage-to-time converter, configured to: output a first time signal to a first delay module according to a received first voltage;

[0006] A second voltage-to-time converter is configured to: output a second time signal to a second delay module according to a received second voltage;

[0007] A phase detector, configured to: detect a phase difference between a third time signal and a fourth time signal, and when the phase difference is greater than a preset phase threshold, output a first phase difference signal to a first trigger module, output a second phase difference signal to a second trigger module, and output a pulse signal to a successive approximation logic module, wherein the third time signal is an output signal of the first time signal adjusted according to a P-level delay signal, the fourth time signal is an output signal of the second time signal adjusted according to an N-level delay signal, and the pulse signal is generated according to the first phase difference signal and the second phase difference signal;

[0008] A successive approximation logic module, configured to: in response to receiving an enable signal, output a control signal to the first trigger module and the second trigger module according to the pulse signal, wherein the control signal is used to control the first trigger module to generate a delay weight for adjusting the phase of the first time signal, and to control the second trigger module to generate a delay weight for adjusting the phase of the second time signal;

[0009] A first trigger module is configured to: output the P-level delay signal to the first delay module according to the control signal, the enable signal and the first phase difference signal, wherein the P-level delay signal is used to characterize the delay weight of the first delay module;

[0010] A second trigger module is configured to: output the N-level delay signal to the second delay module according to the control signal, the enable signal and the second phase difference signal, wherein the N-level delay signal is used to characterize the delay weight of the second delay module;

[0011] A first delay module is configured to: delay the first time signal according to the received P-level delay signal to adjust the phase of the first time signal, and output the third time signal to the phase detector;

[0012] The second delay module is configured to: delay the second time signal according to the received N-level delay signal to adjust the phase of the second time signal, and output the fourth time signal to the phase detector.

[0013] Optionally, the successive approximation logic module includes: a first trigger, configured to: in response to a first rising edge of the pulse signal, output a first control signal to a second trigger, the first trigger module, and the second trigger module according to a voltage signal;

[0014] A second trigger is configured to: in response to a second rising edge of the pulse signal, output a second control signal to a third trigger, the first trigger module, and the second trigger module according to the first control signal;

[0015] a third trigger, configured to: in response to a third rising edge of the pulse signal, output a third control signal to a fourth trigger, the first trigger module, and the second trigger module according to the second control signal;

[0016] a fourth trigger, configured to: in response to a fourth rising edge of the pulse signal, output a fourth control signal to the fifth trigger, the first trigger module and the second trigger module according to the third control signal;

[0017] The fifth trigger is configured to: in response to the fifth rising edge of the pulse signal, output a fifth control signal to the first trigger module and the second trigger module according to the fourth control signal, and output a fifth inverted control signal to the phase detector, wherein the fifth inverted control signal is an inverted signal of the fifth control signal.

[0018] Optionally, the first trigger module includes: a sixth trigger, configured to: in response to obtaining the first control signal of a high level, output a first P-level delay signal to the first delay module according to the first phase difference signal;

[0019] a seventh trigger, configured to: in response to obtaining the second control signal of a high level, output a second P-level delay signal to the first delay module according to the first phase difference signal;

[0020] an eighth trigger, configured to: in response to obtaining the third control signal of a high level, output a third P-level delay signal to the first delay module according to the first phase difference signal;

[0021] a ninth trigger, configured to: in response to obtaining the fourth control signal of a high level, output a fourth P-level delay signal to the first delay module according to the first phase difference signal;

[0022] The tenth trigger is configured to: in response to obtaining the fifth control signal of a high level, output a fifth P-level delay signal to the first delay module according to the first phase difference signal.

[0023] Optionally, the second trigger module includes: an eleventh trigger, configured to: in response to obtaining the first control signal of a high level, output a first N-level delay signal to the second delay module according to the second phase difference signal;

[0024] A twelfth trigger is configured to: in response to obtaining the second control signal of a high level, output a second N-level delay signal to the second delay module according to the second phase difference signal;

[0025] A thirteenth trigger is configured to: in response to obtaining the third control signal of a high level, output a third N-level delay signal to the second delay module according to the second phase difference signal;

[0026] A fourteenth trigger is configured to: in response to obtaining the fourth control signal of a high level, output a fourth N-level delay signal to the second delay module according to the second phase difference signal;

[0027] The fifteenth trigger is configured to: in response to obtaining the fifth control signal of a high level, output a fifth N-level delay signal to the second delay module according to the second phase difference signal.

[0028] Optionally, the first delay module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor;

[0029] The first inverter, the second inverter, the third inverter and the fourth inverter are sequentially connected in series, a first node is provided between the first inverter and the second inverter, and a second node is provided between the third inverter and the fourth inverter;

[0030] One end of the first capacitor is connected to the first node, and the other end of the first capacitor is used to receive the first P-level delay signal;

[0031] One end of the second capacitor is connected to the first node, and the other end of the second capacitor is used to receive the second P-level delay signal;

[0032] One end of the third capacitor is connected to the second node, and the other end of the third capacitor is used to receive the third P-level delay signal;

[0033] One end of the fourth capacitor is connected to the second node, and the other end of the fourth capacitor is used to receive the fourth P-level delay signal;

[0034] One end of the fifth capacitor is connected to the second node, and the other end of the fifth capacitor is used to receive the fifth P-level delay signal.

[0035] Optionally, the second delay module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor;

[0036] The fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series, a third node is provided between the fifth inverter and the sixth inverter, and a fourth node is provided between the seventh inverter and the eighth inverter;

[0037] One end of the sixth capacitor is connected to the third node, and the other end of the sixth capacitor is used to receive the first N-level delay signal;

[0038] One end of the seventh capacitor is connected to the third node, and the other end of the seventh capacitor is used to receive the second N-level delay signal;

[0039] One end of the eighth capacitor is connected to the fourth node, and the other end of the eighth capacitor is used to receive the third N-level delay signal;

[0040] One end of the ninth capacitor is connected to the fourth node, and the other end of the ninth capacitor is used to receive the fourth N-level delay signal;

[0041] One end of the tenth capacitor is connected to the fourth node, and the other end of the tenth capacitor is used to receive the fifth N-stage delay signal.

[0042] Optionally, the mismatch calibration circuit based on the voltage-to-time converter also includes: an XOR gate, configured to: receive the first phase difference signal and the second phase difference signal, perform an XOR operation on the first phase difference signal and the second phase difference signal, and output the XOR gate result signal to the successive approximation logic module.

[0043] Optionally, the mismatch calibration circuit based on the voltage-to-time converter also includes: an AND gate, configured to: receive the XOR gate result signal and the fifth inverted control signal, perform an AND operation on the XOR gate result signal and the fifth inverted control signal, and output the AND gate result signal to the successive approximation logic module.

[0044] Optionally, the mismatch calibration circuit based on the voltage-to-time converter further includes: the successive approximation logic module is further configured to: reset the first trigger, the second trigger, the third trigger, the fourth trigger and the fifth trigger according to a received reset signal;

[0045] The first trigger module is further configured to: reset the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger according to the received reset signal;

[0046] The second trigger module is further configured to reset the eleventh trigger, the twelfth trigger, the thirteenth trigger, the fourteenth trigger and the fifteenth trigger according to a received reset signal.

[0047] In a second aspect, the present application further provides a method for controlling a mismatch calibration circuit based on a voltage-to-time converter, the method being applied to a mismatch calibration circuit based on a voltage-to-time converter as in the above-mentioned embodiment, wherein the method for controlling a mismatch calibration circuit based on a voltage-to-time converter comprises: outputting a first time signal to a first delay module according to a received first voltage;

[0048] Outputting a second time signal to a second delay module according to the received second voltage;

[0049] Detecting a phase difference between a third time signal and a fourth time signal, and when the phase difference is greater than a preset phase threshold, outputting a first phase difference signal to a first trigger module, outputting a second phase difference signal to a second trigger module, and outputting a pulse signal to a successive approximation logic module, wherein the third time signal is an output signal of the first time signal adjusted according to a P-level delay signal, the fourth time signal is an output signal of the second time signal adjusted according to an N-level delay signal, and the pulse signal is generated according to the first phase difference signal and the second phase difference signal;

[0050] In response to receiving the enable signal, outputting a control signal to the first trigger module and the second trigger module according to the pulse signal, wherein the control signal is used to control the first trigger module to generate a delay weight for adjusting the phase of the first time signal, and to control the second trigger module to generate a delay weight for adjusting the phase of the second time signal;

[0051] Outputting the P-level delay signal to the first delay module according to the control signal, the enable signal and the first phase difference signal, wherein the P-level delay signal is used to characterize the delay weight of the first delay module;

[0052] Outputting the N-level delay signal to the second delay module according to the control signal, the enable signal and the second phase difference signal, wherein the N-level delay signal is used to characterize the delay weight of the second delay module;

[0053] Delaying the first time signal according to the received P-level delay signal to adjust the phase of the first time signal, and outputting the third time signal to the phase detector;

[0054] The second time signal is delayed according to the received N-stage delay signal to adjust the phase of the second time signal, and the fourth time signal is output to the phase detector.

[0055] It can be seen from the above technical solutions that the present application provides a mismatch calibration circuit based on a voltage-time converter and a control method thereof, including: using a first voltage-time converter and a second voltage-time converter to output a first time signal and a second time signal, using a phase detector to detect the phase difference between a third time signal and a fourth time signal, and outputting a first phase difference signal to a first trigger module, outputting a second phase difference signal to a second trigger module, and outputting a pulse signal to a successive approximation logic module. Using a successive approximation logic module to output a control signal according to the pulse signal so that the trigger module outputs a delay signal. The delay module delays the time signal according to the received delay signal to adjust the phase of the time signal. The above-mentioned mismatch calibration circuit can use a phase detector to detect the output time error of the voltage-time converter, and use a successive approximation logic module to modify the delay weight, thereby calibrating the mismatch of the voltage-time converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0057] Figure 1 A schematic diagram of a mismatch calibration circuit based on a voltage-to-time converter according to an embodiment of the present application;

[0058] Figure 2 A circuit diagram of a phase detector according to an embodiment of the present application;

[0059] Figure 3 A circuit diagram of a successive approximation logic module according to an embodiment of the present application;

[0060] Figure 4 A circuit diagram of a first trigger module according to an embodiment of the present application;

[0061] Figure 5 This is a circuit diagram of a first delay module according to an embodiment of the present application;

[0062] Figure 6 A schematic diagram of the relationship between the input byte code and the delay duration of the delay module of an embodiment of the present application;

[0063] Figure 7 A histogram of simulation results of a non-calibration system according to an embodiment of the present application;

[0064] Figure 8 A histogram of simulation results of the start-up calibration system according to an embodiment of the present application;

[0065] Fig. 9 This is a flow chart of a control method of a mismatch calibration circuit based on a voltage-to-time converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0066] The embodiments will be described in detail below, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following embodiments do not represent all implementation methods consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application.

[0067] A time-domain analog-to-digital converter (TD-ADC) is an electronic device that can convert continuous analog signals into digital signals. The TD-ADC uses a voltage-to-time converter (VTC) and a time-to-digital converter to achieve voltage-to-digital conversion. The voltage-to-time converter collects the input signal onto a capacitor and charges or discharges the capacitor. When the voltage on the capacitor exceeds or falls below a preset voltage threshold, the comparator is used to change the output level to achieve quantization from voltage to time. During the use of the TD-ADC, changes in voltage and temperature will cause differences in the threshold voltage of the comparator between the two channels of the TD-ADC, which in turn causes an error between the output pulse time difference and the preset value, reducing the performance of the TD-ADC.

[0068] By adjusting the output time difference of the two comparators of the voltage-to-time converter off-chip, that is, changing the inverter current connected to the comparator, or changing the capacitance value on the comparator output path, the output delay of the two comparators can be changed, thereby correcting the mismatch of the comparators. However, since the above calibration method requires manual operation, each manufactured voltage-to-time converter must be calibrated individually, which cannot be automated and is difficult to be widely used.

[0069] In order to improve the calibration efficiency and calibration accuracy of the voltage-to-time converter, some embodiments of the present application provide a mismatch calibration circuit based on the voltage-to-time converter. Figure 1 This is a schematic diagram of a mismatch calibration circuit based on a voltage-to-time converter according to an embodiment of the present application. Figure 1 The mismatch calibration circuit based on the voltage-to-time converter of this embodiment is described in detail.

[0070] Some embodiments of the present application provide a mismatch calibration circuit based on a voltage-to-time converter, including: a first voltage-to-time converter VTCP, a second voltage-to-time converter VTCN, a phase detector PD, a successive approximation logic module SAR logic, a first trigger module DFF_P, a second trigger module DFF_N, a first delay module DCDL_P, and a second delay module DCDL_N. The first voltage-to-time converter VTCP is configured to output a first time signal to the first delay module DCDL_P according to a first voltage VP; the second voltage-to-time converter VTCN is configured to output a second time signal to the second delay module DCDL_N according to a received second voltage VN.

[0071] It should be noted that the voltage-to-time converter is a circuit that converts a voltage signal into a time signal, and is used to measure the change of the voltage signal and convert the voltage signal into time series data. In some embodiments, the same voltage is input to the first voltage-to-time converter VTCP and the second voltage-to-time converter VTCN. Since the signal may be affected by factors such as the transmission medium, temperature, and humidity during the process of transmitting from the input end to the output end, there is a difference in signal transmission, which in turn causes a phase difference between the output first time signal and the second time signal. By using a delay module to delay the first time signal and the second time signal, the phase difference of the output signal can be corrected to obtain a third time signal TP and a fourth time signal TN.

[0072] In some embodiments, the phase detector PD detects the phase difference between the third time signal TP and the fourth time signal TN, and when the phase difference is greater than a preset phase threshold, outputs a first phase difference signal OUTP to the first trigger module DFF_P, outputs a second phase difference signal OUTN to the second trigger module DFF_N, and outputs a pulse signal RDY to the successive approximation logic module SAR logic. The third time signal TP is the output signal of the first time signal adjusted according to the P-level delay signal, the fourth time signal TN is the output signal of the second time signal adjusted according to the N-level delay signal, and the pulse signal RDY is generated according to the first phase difference signal OUTP and the second phase difference signal OUTN.

[0073] Exemplarily, the phase detector PD detects the rising edge of the third time signal TP and the fourth time signal TN. If the third time signal TP has a rising edge before the fourth time signal TN, the first phase difference signal OUTP is set to a high level, and the second phase difference signal OUTN is set to a low level, and continues for a preset time. Within the preset time, if the fourth time signal TN has a rising edge, the levels of the first phase difference signal OUTP and the second phase difference signal OUTN are still not changed.

[0074] In some embodiments, Figure 2As shown, the phase detector PD includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9 and a tenth MOS tube M10. Among them, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are N-type MOS tubes. The fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9 and the tenth MOS tube M10 are P-type MOS tubes. The third MOS tube M3 and the fifth MOS tube M5 are the fifth nodes, and the fourth MOS tube M4 and the sixth MOS tube M6 are the sixth nodes.

[0075] When the phase detector PD starts to detect phase, the third time signal TP and the fourth time signal TN are both at low level, at this time, the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9 and the tenth MOS tube M10 are turned on, the fifth node and the sixth node are at high potential, so that the third MOS tube M3 and the fourth MOS tube M4 are turned on, the first phase difference signal OUTP and the second phase difference signal OUTN are both at low level. The first MOS tube M1, the second MOS tube M2, the fifth MOS tube M5 and the sixth MOS tube M6 are turned off.

[0076] When the third time signal TP appears a rising edge before the fourth time signal TN, the eighth MOS tube M8 and the ninth MOS tube M9 are turned off, and the power supply no longer injects charges into the fifth node and the sixth node. The first MOS tube M1 is turned on, and the potential of the fifth node becomes low. At the same time, the sixth MOS tube M6 is turned on, and the fourth MOS tube M4 is turned off, so that the sixth node maintains a high potential, the third MOS tube M3 remains turned on, and the fifth MOS tube M5 remains turned off. Then, the fifth node is at a low potential, the sixth node is at a high potential, the first phase difference signal OUTP is at a high level, and the second phase difference signal OUTN is at a low level, and finally the phase discrimination is completed.

[0077] After the third time signal TP and the fourth time signal TN are restored to the low level, the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9 and the tenth MOS tube M10 are turned on again, and the levels of the fifth node and the sixth node are restored to the high potential, waiting for the rising edge of the third time signal TP and the fourth time signal TN in the next cycle.

[0078] In some embodiments, the mismatch calibration circuit based on the voltage-to-time converter further includes an XOR gate, which is configured to: receive the first phase difference signal OUTP and the second phase difference signal OUTN, perform an XOR operation on the first phase difference signal OUTP and the second phase difference signal OUTN, and output an XOR gate result signal to the successive approximation logic module SAR logic. The XOR gate result signal can be used to generate a pulse that triggers the successive approximation logic module SAR logic. The XOR gate can avoid the influence of false triggering of the phase detector PD, thereby improving the accuracy of circuit calibration.

[0079] Exemplarily, the first phase difference signal OUTP is at a high level, the second phase difference signal OUTN is at a low level, and the XOR gate result signal output by the XOR gate is at a high level, thereby starting the successive approximation logic module SAR logic.

[0080] In some embodiments, the voltage-to-time converter-based mismatch calibration circuit further includes an AND gate AND configured to: receive the XOR gate result signal and the fifth inverted control signal STEP <5> , and the XOR gate result signal and the fifth inverting control signal STEP <5> Perform an AND operation and output an AND gate result signal to a successive approximation logic module SAR logic.

[0081] Exemplarily, the XOR gate result signal is at a high level, and the fifth inverting control signal STEP <5> is high level, the AND gate result signal output by the AND gate AND is high level, and the AND gate result signal is used as the pulse signal RDY to start the successive approximation logic module SAR logic.

[0082] In some embodiments, the successive approximation logic module SAR logic is configured to: in response to receiving an enable signal EN, output a control signal STEP to the first trigger module DFF_P and the second trigger module DFF_N according to the pulse signal RDY. The control signal STEP is used to control the first trigger module DFF_P to generate a delay weight for adjusting the phase of the first time signal, and to control the second trigger module DFF_N to generate a delay weight for adjusting the phase of the second time signal.

[0083] It should be noted that the successive approximation logic module SAR logic is a key timing control circuit module in the successive approximation register analog-to-digital converter (SAR ADC). The successive approximation logic module SAR logic is responsible for controlling the timing and logic of the entire conversion process to achieve successive approximation conversion of the input analog signal.

[0084] In the initial state, the enable signal EN is at a low level, the outputs of the trigger module and the successive approximation logic module SAR logic are both cleared, the first trigger module DFF_P and the second trigger module DFF_N are in the minimum delay state, the fifth inverting control signal is set to a high level, the AND gate AND and the phase detector PD are activated, and then EN is set to a high level, and the successive approximation logic module SAR logic enters an iterative process of comparison and approximation, and the delay weight of the delay module is changed by triggering the first trigger module DFF_P and the second trigger module DFF_N, thereby realizing the calibration process.

[0085] In some embodiments, Figure 3 As shown, the successive approximation logic module SAR logic includes five D flip-flops, namely: a first flip-flop D1, a second flip-flop D2, a third flip-flop D3, a fourth flip-flop D4 and a fifth flip-flop D5. When the rising edge of the pulse signal RDY arrives, the D flip-flop receives the input signal and flips from the current state to another stable state, for example, from 0 to 1.

[0086] The first trigger D1 is configured to: in response to the first rising edge of the pulse signal RDY, output the first control signal STEP to the second trigger D2, the first trigger module DFF_P and the second trigger module DFF_N according to the voltage signal <0> The second trigger D2 is configured to: respond to the second rising edge of the pulse signal RDY, according to the first control signal STEP <0> Output a second control signal STEP to the third trigger D3, the first trigger module DFF_P and the second trigger module DFF_N <1> The third trigger D3 is configured to: respond to the third rising edge of the pulse signal RDY, according to the second control signal STEP <1> Output a third control signal STEP to the fourth trigger D4, the first trigger module DFF_P and the second trigger module DFF_N <2> The fourth trigger D4 is configured to: respond to the fourth rising edge of the pulse signal RDY, according to the third control signal STEP <2> Output a fourth control signal STEP to the fifth trigger D5, the first trigger module DFF_P and the second trigger module DFF_N <3> The fifth flip-flop D5 is configured to: in response to the fifth rising edge of the pulse signal RDY, according to the fourth control signal STEP <3> Output a fifth control signal STEP to the first trigger module DFF_P and the second trigger module DFF_N <4> , and outputs the fifth inverting control signal STEP to the phase detector PD <5> , the fifth inverting control signal STEP <5> is the fifth control signal STEP <4> The inverted signal.

[0087] Exemplarily, the rising edge of the third time signal TP is earlier than that of the fourth time signal TN, the first phase difference signal OUTP is high, the second phase difference signal OUTN is low, and when the pulse signal RDY has a first rising edge, the successive approximation logic module SAR logic is triggered to shift once, and the first control signal STEP <0> When the pulse signal RDY has a second rising edge, the successive approximation logic module SAR logic is triggered to shift again, and the second control signal STEP <1> Converted from 0 to 1. The pulse signal RDY is continuously triggered for five cycles, so that the control signal is sequentially triggered to a high level, thereby using the successive approximation logic module SAR logic to trigger the first trigger module DFF_P and the second trigger module DFF_N to perform five rounds of successive approximation conversion.

[0088] In some embodiments, the first trigger module DFF_P is configured to output a P-level delay signal to the first delay module DCDL_P according to the control signal, the enable signal EN and the first phase difference signal OUTP. The second trigger module DFF_N is configured to output an N-level delay signal to the second delay module DCDL_N according to the control signal, the enable signal EN and the second phase difference signal OUTN. Among them, the P-level delay signal is used to characterize the delay weight of the first delay module, and the N-level delay signal is used to characterize the delay weight of the second delay module.

[0089] The first trigger module DFF_P includes five D triggers, namely a sixth trigger D6, a seventh trigger D7, an eighth trigger D8, a ninth trigger D9 and a tenth trigger D10. Figure 4 As shown in (a), the sixth trigger D6 is configured to: in response to obtaining the first control signal STEP of high level <0> , outputs the first P-level delay signal Code_P to the first delay module DCDL_P according to the first phase difference signal OUTP <0> .like Figure 4 As shown in (b), the seventh trigger D7 is configured to: in response to obtaining the high level second control signal STEP <1> , outputs the second P-level delay signal Code_P to the first delay module DCDL_P according to the first phase difference signal OUTP <1> .like Figure 4 As shown in (c), the eighth flip-flop D8 is configured to: in response to obtaining the third control signal STEP at a high level <2> , outputs a third P-level delay signal Code_P to the first delay module DCDL_P according to the first phase difference signal OUTP <2> .like Figure 4 As shown in (d), the ninth flip-flop D9 is configured to: in response to obtaining the high level fourth control signal STEP <3> , outputs the fourth P-level delay signal Code_P to the first delay module DCDL_P according to the first phase difference signal OUTP <3> .like Figure 4As shown in (e), the tenth flip-flop D10 is configured to: in response to obtaining the fifth control signal STEP at a high level <4> , outputs the fifth P-level delay signal Code_P to the first delay module DCDL_P according to the first phase difference signal OUTP <4> .

[0090] In some embodiments, the second trigger module DFF_N includes five D flip-flops, namely, an eleventh flip-flop D11, a twelfth flip-flop D12, a thirteenth flip-flop D13, a fourteenth flip-flop D14 and a fifteenth flip-flop D15. The eleventh flip-flop D11 is configured to: in response to obtaining a high-level first control signal STEP <0> , outputs the first N-level delay signal Code_N to the second delay module DCDL_N according to the second phase difference signal OUTN <0> The twelfth flip-flop D12 is configured to: in response to obtaining the second control signal STEP of high level <1> , outputs the second N-stage delay signal Code_N to the second delay module DCDL_N according to the second phase difference signal OUTN <1> The thirteenth flip-flop D13 is configured to: in response to obtaining the third control signal STEP of high level <2> , outputs a third N-level delay signal Code_N to the second delay module DCDL_N according to the second phase difference signal OUTN <2> The fourteenth flip-flop D14 is configured to: in response to obtaining the high level fourth control signal STEP <3> , outputs the fourth N-level delay signal Code_N to the second delay module DCDL_N according to the second phase difference signal OUTN <3> The fifteenth flip-flop D15 is configured to: in response to obtaining the fifth control signal STEP at a high level <4> , outputs the fifth N-level delay signal Code_N to the second delay module DCDL_N according to the second phase difference signal OUTN <4> .

[0091] Exemplarily, the rising edge of the third time signal TP precedes the rising edge of the fourth time signal TN. When the first rising edge of the pulse signal RDY occurs, the first control signal STEP <0> Changes from 0 to 1, and triggers the sixth trigger D6 to output the first P-level delay signal Code_P <0> Since the first phase difference signal OUTP input to the sixth flip-flop D6 is at a high level, the first P-level delay signal Code_P <0> = ... <0> It is set to a high level, and the delay of the second delay module DCDL_N does not change, that is, the delay of the second time signal remains unchanged.

[0092] When the second rising edge of the pulse signal RDY appears, if the rising edge of the delayed third time signal TP is still earlier than that of the fourth time signal TN, the second P-level delay signal Code_P <1> Set to low level, the second N-level delay signal Code_N <1> Set to a high level to increase the delay of the first time signal and keep the delay of the second time signal unchanged.

[0093] When the second rising edge of the pulse signal RDY appears, if the rising edge of the delayed third time signal TP lags behind the fourth time signal TN, the second P-level delay signal Code_P <1> Set to high level, the second N-level delay signal Code_N <1> Set to a low level to increase the delay of the second time signal and keep the delay of the first time signal unchanged.

[0094] After five successive approximation judgment processes, the phase difference between the first time signal and the second time signal after delay gradually decreases. <4> Set high to indicate that the mismatch calibration is complete. The phase detector PD and the AND gate AND are automatically turned off to save power.

[0095] In some implementations, the first delay module DCDL_P is configured to delay the first time signal according to the received P-level delay signal to adjust the phase of the first time signal, and output the third time signal TP to the phase detector PD. The second delay module DCDL_N is configured to delay the second time signal according to the received N-level delay signal to adjust the phase of the second time signal, and output the fourth time signal TN to the phase detector PD. The first delay module DCDL_P and the second delay module DCDL_N adjust the phase of the time signal according to the delay signal until the calibrated phase difference between the first time signal and the second time signal is less than or equal to the preset phase threshold.

[0096] In some embodiments, Figure 5 As shown, the first delay module DCDL_P includes a first inverter F1, a second inverter F2, a third inverter F3, a fourth inverter F4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5. The first inverter F1, the second inverter F2, the third inverter F3 and the fourth inverter F4 are sequentially connected in series, a first node P is provided between the first inverter F1 and the second inverter F2, and a second node N is provided between the third inverter F3 and the fourth inverter F4.

[0097] One end of the first capacitor C1 is connected to the first node P, and the other end of the first capacitor C1 is used to receive the first P-level delay signal Code_P <0> One end of the second capacitor C2 is connected to the first node P, and the other end of the second capacitor C2 is used to receive the second P-level delay signal Code_P <1> One end of the third capacitor C3 is connected to the second node N, and the other end of the third capacitor C3 is used to receive the third P-level delay signal Code_P <2> One end of the fourth capacitor C4 is connected to the second node N, and the other end of the fourth capacitor C4 is used to receive the fourth P-level delay signal Code_P <3> One end of the fifth capacitor C5 is connected to the second node N, and the other end of the fifth capacitor C5 is used to receive the fifth P-level delay signal Code_P <4> .

[0098] In some embodiments, the second delay module DCDL_N includes a fifth inverter F5, a sixth inverter F6, a seventh inverter F7, an eighth inverter F8, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C10.

[0099] One end of the sixth capacitor C6 is connected to the third node Q, and the other end of the sixth capacitor C6 is used to receive the first N-level delay signal Code_N <0> One end of the seventh capacitor C7 is connected to the third node Q, and the other end of the seventh capacitor C7 is used to receive the second N-level delay signal Code_N. <1> One end of the eighth capacitor C8 is connected to the fourth node M, and the other end of the eighth capacitor C8 is used to receive the third N-level delay signal Code_N. <2> One end of the ninth capacitor C9 is connected to the fourth node M, and the other end of the ninth capacitor C9 is used to receive the fourth N-level delay signal Code_N. <3> One end of the tenth capacitor C10 is connected to the fourth node M, and the other end of the tenth capacitor C10 is used to receive the fifth N-level delay signal Code_N. <4> .

[0100] Exemplarily, by adding capacitors at the output ends of the first inverter F1 and the third inverter F3, the time constant of charging and discharging can be increased, and by changing the voltage value of the voltage on the capacitor drain source, the size of the capacitance value is changed, thereby realizing the delay function of the first delay module DCDL_P. The structure of the first delay module DCDL_P can reduce the area of ​​the module.

[0101] Figure 6 Schematic diagram of the relationship between the input byte code and the delay duration of the delay module in an embodiment of the present application, Figure 6 The horizontal axis represents the digital control code, and the vertical axis represents the delay time, and the delay time is in picoseconds ps. In some embodiments, the five-bit control code corresponds to 32 digital control codes, the step is 950fs, and the total correction range is .like Figure 6As shown, the linearity of the delay module is good, and the step and total correction range meet the preset requirements.

[0102] In some embodiments, the delay range can be adjusted by adjusting the number of inverters in the delay module and the capacitance of the capacitor.

[0103] In some embodiments, the successive approximation logic module SAR logic is configured to reset the first trigger D1, the second trigger D2, the third trigger D3, the fourth trigger D4, and the fifth trigger D5 according to the received reset signal RST. The first trigger module DFF_P is also configured to reset the sixth trigger D6, the seventh trigger D7, the eighth trigger D8, the ninth trigger D9, and the tenth trigger D10 according to the received reset signal RST. The second trigger module DFF_N is also configured to reset the eleventh trigger D11, the twelfth trigger D12, the thirteenth trigger D13, the fourteenth trigger D14, and the fifteenth trigger D15 according to the received reset signal RST. For example, when the reset signal RST is 0, the control trigger is cleared.

[0104] In some embodiments, a Monte Carlo simulation experiment is performed on the mismatch calibration circuit based on the voltage-to-time converter in the present application, the number of simulations is 200, and a Figure 7 and Figure 8 The simulation image shown. Figure 7 is a histogram of simulation results of a non-calibration system according to an embodiment of the present application, Figure 8 This is a histogram of simulation results of the start-up calibration system of the embodiment of the present application. Figure 7 and Figure 8 In the figure, the horizontal axis represents the time error output by the first voltage-to-time converter VTCP and the second voltage-to-time converter VTCN when the same voltage is input, and the unit is picoseconds ps. The vertical axis represents the number of points in the histogram. Figure 7 and Figure 8 The curve in the figure is a distribution curve fitted by statistical methods. The curve can be expressed as a normal distribution curve. The parameters of the normal distribution curve include the number of simulations Number, the mean value of the simulation results Mean, and the standard deviation of the simulation results Std Dev (i.e. ).

[0105] like Figure 7 and Figure 8As shown, before calibration, the same voltage is input to the first voltage-to-time converter VTCP and the second voltage-to-time converter VTCN, and the standard deviation of the output time error is 6.63ps, and the maximum error is 19.79ps. After correction, the standard deviation of the time error is 0.70ps. Compared with before correction, the time error is reduced by more than nine times, and the maximum error time is less than 2.2ps, which is less than the preset time threshold. According to the mismatch calibration circuit based on the voltage-to-time converter described in the above embodiment, some embodiments of the present application also provide a control method for the mismatch calibration circuit based on the voltage-to-time converter, and the control method is applied to the mismatch calibration circuit based on the voltage-to-time converter as described in the above embodiment. Fig. 9 FIG. 1 is a schematic diagram of the steps of the mismatch calibration circuit control method based on the voltage-to-time converter according to an embodiment of the present application, referring to FIG. Fig. 9 The mismatch calibration circuit control method based on the voltage-to-time converter of the embodiment of the present application includes the following steps.

[0106] Step S901: output a first time signal to a first delay module according to a received first voltage.

[0107] Step S902: output a second time signal to a second delay module according to the received second voltage.

[0108] Step S903, detecting the phase difference between the third time signal and the fourth time signal, and when the phase difference is greater than a preset phase threshold, outputting a first phase difference signal to the first trigger module, outputting a second phase difference signal to the second trigger module, and outputting a pulse signal to the successive approximation logic module, wherein the third time signal is an output signal of the first time signal adjusted according to the P-level delay signal, the fourth time signal is an output signal of the second time signal adjusted according to the N-level delay signal, and the pulse signal is generated according to the first phase difference signal and the second phase difference signal;

[0109] Step S904: in response to receiving the enable signal, outputting a control signal to the first trigger module and the second trigger module according to the pulse signal, wherein the control signal is used to control the first trigger module to generate a delay weight for adjusting the phase of the first time signal, and is used to control the second trigger module to generate a delay weight for adjusting the phase of the second time signal;

[0110] Step S905: outputting the P-level delay signal to the first delay module according to the control signal, the enable signal and the first phase difference signal, wherein the P-level delay signal is used to characterize the delay weight of the first delay module;

[0111] Step S906: Output the N-level delay signal to the second delay module according to the control signal, the enable signal, and the second phase difference signal, where the N-level delay signal is used to characterize the delay weight of the second delay module;

[0112] Step S907: Delay the first time signal according to the received P-level delay signal to adjust the phase of the first time signal, and output the third time signal to the phase detector;

[0113] Step S908: Delay the second time signal according to the received N-level delay signal to adjust the phase of the second time signal, and output the fourth time signal to the phase detector.

[0114] As can be seen from the above technical solutions, the present application provides a mismatch calibration circuit based on a voltage-time converter and its control method, including: using a first voltage-time converter and a second voltage-time converter to output a first time signal and a second time signal, using a phase detector to detect the phase difference between the third time signal and the fourth time signal, and outputting a first phase difference signal to the first trigger module, outputting a second phase difference signal to the second trigger module, and outputting a pulse signal to the successive approximation logic module. Using the successive approximation logic module to output a control signal according to the pulse signal, so that the trigger module outputs a delay signal. The delay module delays the time signal according to the received delay signal to adjust the phase of the time signal. The above mismatch calibration circuit can use the phase detector to detect the output time error of the voltage-time converter, and use the successive approximation logic module to modify the delay weight, thereby realizing automatic calibration inside the chip and improving the accuracy and convenience of calibration.

[0115] For the similar parts between the embodiments provided in the present application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of the present application, and do not constitute a limitation on the protection scope of the present application. For those skilled in the art, any other implementation manners extended based on the solution of the present application without creative efforts belong to the protection scope of the present application.

Claims

1. A mismatch calibration circuit based on a voltage-to-time converter, characterized in that: include: A first voltage-to-time converter is configured to: output a first time signal to a first delay module according to a received first voltage; A second voltage-to-time converter is configured to: output a second time signal to a second delay module according to a received second voltage; A phase detector, configured to: detect a phase difference between a third time signal and a fourth time signal, and when the phase difference is greater than a preset phase threshold, output a first phase difference signal to a first trigger module, output a second phase difference signal to a second trigger module, and output a pulse signal to a successive approximation logic module, wherein the third time signal is an output signal of the first time signal adjusted according to a P-level delay signal, the fourth time signal is an output signal of the second time signal adjusted according to an N-level delay signal, and the pulse signal is generated according to the first phase difference signal and the second phase difference signal; A successive approximation logic module, configured to: in response to receiving an enable signal, output a control signal to the first trigger module and the second trigger module according to the pulse signal, wherein the control signal is used to control the first trigger module to generate a delay weight for adjusting the phase of the first time signal, and to control the second trigger module to generate a delay weight for adjusting the phase of the second time signal; A first trigger module is configured to: output the P-level delay signal to the first delay module according to the control signal, the enable signal and the first phase difference signal, wherein the P-level delay signal is used to characterize the delay weight of the first delay module; A second trigger module is configured to: output the N-level delay signal to the second delay module according to the control signal, the enable signal and the second phase difference signal, wherein the N-level delay signal is used to characterize the delay weight of the second delay module; A first delay module is configured to: delay the first time signal according to the received P-level delay signal to adjust the phase of the first time signal, and output the third time signal to the phase detector; The second delay module is configured to: delay the second time signal according to the received N-level delay signal to adjust the phase of the second time signal, and output the fourth time signal to the phase detector.

2. The mismatch calibration circuit based on voltage-to-time converter according to claim 1, characterized in that: The successive approximation logic module comprises: A first trigger, configured to: in response to a first rising edge of the pulse signal, output a first control signal to a second trigger, the first trigger module, and the second trigger module according to a voltage signal; A second trigger is configured to: in response to a second rising edge of the pulse signal, output a second control signal to a third trigger, the first trigger module, and the second trigger module according to the first control signal; a third trigger, configured to: in response to a third rising edge of the pulse signal, output a third control signal to a fourth trigger, the first trigger module, and the second trigger module according to the second control signal; a fourth trigger, configured to: in response to a fourth rising edge of the pulse signal, output a fourth control signal to the fifth trigger, the first trigger module and the second trigger module according to the third control signal; The fifth trigger is configured to: in response to the fifth rising edge of the pulse signal, output a fifth control signal to the first trigger module and the second trigger module according to the fourth control signal, and output a fifth inverted control signal to the phase detector, wherein the fifth inverted control signal is an inverted signal of the fifth control signal.

3. The mismatch calibration circuit based on voltage-to-time converter according to claim 2, characterized in that: The first trigger module includes: a sixth trigger, configured to: in response to obtaining the first control signal of a high level, output a first P-level delay signal to the first delay module according to the first phase difference signal; a seventh trigger, configured to: in response to obtaining the second control signal of a high level, output a second P-level delay signal to the first delay module according to the first phase difference signal; an eighth trigger, configured to: in response to obtaining the third control signal of a high level, output a third P-level delay signal to the first delay module according to the first phase difference signal; a ninth trigger, configured to: in response to obtaining the fourth control signal of a high level, output a fourth P-level delay signal to the first delay module according to the first phase difference signal; The tenth trigger is configured to: in response to obtaining the fifth control signal of a high level, output a fifth P-level delay signal to the first delay module according to the first phase difference signal.

4. The mismatch calibration circuit based on voltage-to-time converter according to claim 3, characterized in that: The second trigger module includes: an eleventh trigger, configured to: in response to obtaining the first control signal of a high level, output a first N-level delay signal to the second delay module according to a second phase difference signal; A twelfth trigger is configured to: in response to obtaining the second control signal of a high level, output a second N-level delay signal to the second delay module according to the second phase difference signal; A thirteenth trigger is configured to: in response to obtaining the third control signal of a high level, output a third N-level delay signal to the second delay module according to the second phase difference signal; A fourteenth trigger is configured to: in response to obtaining the fourth control signal of a high level, output a fourth N-level delay signal to the second delay module according to the second phase difference signal; The fifteenth trigger is configured to: in response to obtaining the fifth control signal of a high level, output a fifth N-level delay signal to the second delay module according to the second phase difference signal.

5. The mismatch calibration circuit based on voltage-to-time converter according to claim 4, characterized in that: The first delay module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor; The first inverter, the second inverter, the third inverter and the fourth inverter are sequentially connected in series, a first node is provided between the first inverter and the second inverter, and a second node is provided between the third inverter and the fourth inverter; One end of the first capacitor is connected to the first node, and the other end of the first capacitor is used to receive the first P-level delay signal; One end of the second capacitor is connected to the first node, and the other end of the second capacitor is used to receive the second P-level delay signal; One end of the third capacitor is connected to the second node, and the other end of the third capacitor is used to receive the third P-level delay signal; One end of the fourth capacitor is connected to the second node, and the other end of the fourth capacitor is used to receive the fourth P-level delay signal; One end of the fifth capacitor is connected to the second node, and the other end of the fifth capacitor is used to receive the fifth P-level delay signal.

6. The mismatch calibration circuit based on voltage-to-time converter according to claim 4, characterized in that: The second delay module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor; The fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series, a third node is provided between the fifth inverter and the sixth inverter, and a fourth node is provided between the seventh inverter and the eighth inverter; One end of the sixth capacitor is connected to the third node, and the other end of the sixth capacitor is used to receive the first N-level delay signal; One end of the seventh capacitor is connected to the third node, and the other end of the seventh capacitor is used to receive the second N-level delay signal; One end of the eighth capacitor is connected to the fourth node, and the other end of the eighth capacitor is used to receive the third N-level delay signal; One end of the ninth capacitor is connected to the fourth node, and the other end of the ninth capacitor is used to receive the fourth N-level delay signal; One end of the tenth capacitor is connected to the fourth node, and the other end of the tenth capacitor is used to receive the fifth N-stage delay signal.

7. The mismatch calibration circuit based on voltage-to-time converter according to claim 2, characterized in that: Also includes: The XOR gate is configured to: receive the first phase difference signal and the second phase difference signal, perform an XOR operation on the first phase difference signal and the second phase difference signal, and output an XOR gate result signal to the successive approximation logic module.

8. The mismatch calibration circuit based on voltage-to-time converter according to claim 7, characterized in that: Also includes: The AND gate is configured to: receive the XOR gate result signal and the fifth inverted control signal, perform an AND operation on the XOR gate result signal and the fifth inverted control signal, and output the AND gate result signal to the successive approximation logic module.

9. The mismatch calibration circuit based on voltage-to-time converter according to claim 4, characterized in that: Also includes: The successive approximation logic module is further configured to: reset the first trigger, the second trigger, the third trigger, the fourth trigger, and the fifth trigger according to a received reset signal; The first trigger module is further configured to: reset the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger according to the received reset signal; The second trigger module is further configured to reset the eleventh trigger, the twelfth trigger, the thirteenth trigger, the fourteenth trigger and the fifteenth trigger according to a received reset signal.

10. A method for controlling a mismatch calibration circuit based on a voltage-to-time converter, characterized in that: The method applied to the mismatch calibration circuit based on the voltage-to-time converter according to any one of claims 1 to 9 comprises: Outputting a first time signal to a first delay module according to the received first voltage; Outputting a second time signal to a second delay module according to the received second voltage; Detecting a phase difference between a third time signal and a fourth time signal, and when the phase difference is greater than a preset phase threshold, outputting a first phase difference signal to a first trigger module, outputting a second phase difference signal to a second trigger module, and outputting a pulse signal to a successive approximation logic module, wherein the third time signal is an output signal of the first time signal adjusted according to a P-level delay signal, the fourth time signal is an output signal of the second time signal adjusted according to an N-level delay signal, and the pulse signal is generated according to the first phase difference signal and the second phase difference signal; In response to receiving the enable signal, outputting a control signal to the first trigger module and the second trigger module according to the pulse signal, wherein the control signal is used to control the first trigger module to generate a delay weight for adjusting the phase of the first time signal, and to control the second trigger module to generate a delay weight for adjusting the phase of the second time signal; Outputting the P-level delay signal to the first delay module according to the control signal, the enable signal and the first phase difference signal, wherein the P-level delay signal is used to characterize the delay weight of the first delay module; Outputting the N-level delay signal to the second delay module according to the control signal, the enable signal and the second phase difference signal, wherein the N-level delay signal is used to characterize the delay weight of the second delay module; Delaying the first time signal according to the received P-level delay signal to adjust the phase of the first time signal, and outputting the third time signal to the phase detector; The second time signal is delayed according to the received N-stage delay signal to adjust the phase of the second time signal, and the fourth time signal is output to the phase detector.

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