OFDM (Orthogonal Frequency Division Multiplexing) video transmission system based on Zynq platform

Abstract

The invention discloses an OFDM (Orthogonal Frequency Division Multiplexing) video transmission system based on a Zynq platform, which relates to the technical field of video transmission, and comprises the following steps: firstly, starting to construct an OFDM channel from MATLAB (Matrix Laboratory) to verify whether an algorithm function and a receiving and transmitting test are correct or not, if not, entering the MATLAB to construct an OFDM channel system to reconstruct the system, and if yes, entering a driver AD9361, then carrying out communication system RTL design at a PL end, and then carrying out Modelsim simulation. And verifying whether the algorithm function and the receiving and transmitting test are correct for the second time, and if not, returning to the PL end to carry out RTL design of the communication system for redesign. According to the OFDM video transmission system based on the Zynq platform, the Linux host is configured for software encoding and decoding after data receiving and transmitting are correct, local video transmission and real-time video transmission are tested respectively, the real-time transmission rate and transmission delay are mainly tested, and RTL design still needs to be modified when the performance is poor so as to reduce unnecessary time sequence delay.

Description

Technical Field

[0001] The present invention relates to the technical field of video transmission, and in particular to an OFDM video transmission system based on a Zynq platform. Background Art

[0002] The OFDM video transmission system based on the Zynq platform is a complex system that combines the Zynq heterogeneous processor and OFDM (Orthogonal Frequency Division Multiplexing) technology. The system aims to achieve high-quality video data transmission by effectively utilizing the hardware acceleration capabilities of the Zynq platform and the efficient frequency band utilization of OFDM technology;

[0003] The Zynq platform is a highly integrated SoC (system-on-chip) launched by Xilinx, which integrates an ARM processor and an FPGA (field programmable gate array) on a single chip. This architecture combines the software programmability of the ARM processor with the hardware acceleration capability of the FPGA, making it very suitable for implementing complex communication protocols and video processing tasks.

[0004] Efficient bandwidth utilization: OFDM technology greatly improves bandwidth utilization by allocating high-speed data streams to multiple orthogonal subcarriers for parallel transmission;

[0005] Anti-multipath capability: OFDM technology has strong anti-multipath interference capability and can maintain stable signal transmission in complex environments;

[0006] The processor processes data in a pipeline manner. According to the processing flow at the video frame level, frame interval level delay of the video frame may be introduced in each link of the pipeline. Therefore, the end-to-end transmission delay of traditional video encoding and decoding systems is generally high. Summary of the invention

[0007] The present invention provides an OFDM video transmission system based on a Zynq platform to solve the problems raised in the above background technology.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] The OFDM video transmission system based on the Zynq platform first starts with building the OFDM channel in MATLAB to verify whether the algorithm function and the transceiver test are correct. If not, enter MATLAB to build the OFDM channel system and rebuild the system. If correct, enter the driver AD9361 and then go to the PL end to perform the RTL design of the communication system and then perform the Mode ls im simulation. Then verify the algorithm function and the transceiver test for the second time. If not, return to the PL end to redesign the RTL design of the communication system. If correct, enter the OFDM communication system board-level verification, and then enter the verification algorithm function and transceiver test again. If not, return to the PL end to redesign the RTL design of the communication system. If correct, enter the PS end to write the UDP protocol. After entering, enter the stage of testing whether the UDP transceiver is correct. If not, enter the PS end to write the UDP protocol for protocol writing. If correct, enter the Li nux host to configure the video codec, and then enter the test whether the video transmission meets the indicators. If not, return to the PL end to redesign the RTL design of the communication system. If correct, complete the transmission.

[0010] Preferably, the radio platform part is designed after the algorithm and transceiver functions are verified to be correct using MATLAB; first, the configuration and drive test of AD9361 is carried out. Once the AD9361 is driven successfully, only some parameters will be modified later; then the focus of this design is RTL design. When designing, the overall architecture must be determined first, and then the module implementation is carried out. Try to reduce resource occupancy while ensuring the correctness of the function as much as possible, reduce timing delays, and perform low-power design; an important means of saving FPGA resource occupancy is resource reuse, which is reflected in the design and implementation of the joint synchronization algorithm based on short training sequences and the Viterbi decoding module.

[0011] Preferably, for algorithm design, its implementation may involve some mathematical operations such as multiplication, division, and square root. These operations will consume a lot of resources when implemented in FPGA, especially DSP resources; so approximate operations can be used to complete them when the error is acceptable. Taking the joint synchronization algorithm based on short training sequences as an example, an approximate estimation algorithm is used in amplitude estimation, and in the joint phase estimation algorithm based on hardware optimization, four multiplications and one division operation are converted into shift operations to achieve implementation.

[0012] Preferably, after the RTL design of each module is completed, Mode ls im simulation is performed and compared with the results of MATLAB to verify, so as to avoid errors that are difficult to troubleshoot later. After all modules are verified to be correct, one frame and multiple consecutive frames of data sending and receiving experiments are performed; the data source at the receiving end can be generated by MATLAB, and noise and frequency deviation interference can be superimposed on the transmitted data in MATLAB. The data output by the module during Mode ls im simulation can also be imported into MATLAB for analysis.

[0013] Preferably, after the Mode ls im simulation verification is completed, Vi vado software is used to synthesize and implement, and the timing violation problem is solved. When the timing violation exists, it may cause errors in the system when the board is actually running; after the bit file is generated, it is verified on the board, and the packet capture test is performed using the ILA IP core. After the functional verification and the receiving and sending test are successful, the video transmission function is designed and implemented, otherwise the RTL design still needs to be checked, and importing the captured data into MATLAB for analysis is a simple and effective method to find the cause of the error.

[0014] Preferably, the PS side writes the Lightweight Internet Protocol (LwIP) protocol, and finally performs a UDP loopback test. After the test is successful, the baseband part is combined to perform a data transmission and reception test; after the data is correctly transmitted and received, the Linux host is configured to perform software encoding and decoding, and local video and real-time video transmission tests are performed respectively, mainly testing the real-time transmission rate and transmission delay. When the performance is poor, the RTL design still needs to be modified to reduce unnecessary timing delays.

[0015] Preferably, after the performance of the video transmission system meets the design requirements, the system integration is finally performed.

[0016] Due to the adoption of the above technical solution, the present invention has the following technical advances compared with the prior art:

[0017] 1. The present invention provides an OFDM video transmission system based on the Zynq platform. After the data is sent and received correctly, the Linux host is configured to perform software encoding and decoding, and local video and real-time video transmission tests are performed respectively. The real-time transmission rate and transmission delay are mainly tested. When the performance is poor, the RTL design still needs to be modified to reduce unnecessary timing delays.

[0018] 2. The present invention provides an OFDM video transmission system based on the Zynq platform, which uses the ILA IP core to perform packet capture testing. After the functional verification and the receiving and sending tests are successful, the video transmission function is designed and implemented. Otherwise, the RTL design still needs to be checked. Importing the captured data into MATLAB for analysis is a simple and effective method to find the cause of the error.

[0019] 3. The present invention provides an OFDM video transmission system based on the Zynq platform. When implemented in FPGA, these operations will consume a large amount of resources, especially valuable DSP resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the design process of the present invention;

[0021] Figure 2 A frame receiving data diagram of the present invention;

[0022] Figure 3 A power spectrum density diagram of a received signal of the present invention;

[0023] Figure 4 This is a constellation diagram of the present invention without synchronization;

[0024] Figure 5 It is a board-level verification diagram of the group detection function of the present invention;

[0025] Figure 6 This is a board-level verification diagram of the symbol synchronization function of the present invention;

[0026] Figure 7 It is a board-level verification diagram of the channel estimation and equalization function of the present invention;

[0027] Figure 8 is a channel estimation diagram of the present invention;

[0028] Fig. 9 This is a board-level verification diagram of the carrier frequency offset estimation and phase correction function of the present invention;

[0029] Fig.10 This is a diagram for joint verification of the carrier frequency offset estimation and phase correction functions of the present invention;

[0030] Fig.11 It is the constellation diagram before and after phase compensation of the present invention;

[0031] Fig.12 is a graph of estimated values ​​of RCFO and SFO of the present invention;

[0032] Fig.13 It is a board-level verification diagram of the CRC de-checking module of the present invention;

[0033] Fig.14 Sending data graph to JPerf of the present invention;

[0034] Fig.15 This is a maximum data transmission rate test diagram of the present invention. DETAILED DESCRIPTION

[0035] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0036] like Figure X As shown in Figure 1, the OFDM video transmission system based on the Zynq platform first starts to build the OFDM channel in MATLAB to verify whether the algorithm function and the transceiver test are correct. If not, enter MATLAB to build the OFDM channel system and rebuild the system. If correct, enter the driver AD9361 and then go to the PL end to perform the RTL design of the communication system and then perform the Mode l sim simulation. Then, verify the algorithm function and the transceiver test for the second time. If not, return to the PL end to redesign the RTL design of the communication system. If correct, enter the OFDM communication system board-level verification, and then enter the verification algorithm function and transceiver test again. If not, return to the PL end to redesign the RTL design of the communication system. If correct, enter the PS end to write the UDP protocol. After entering, enter the stage of testing whether the UDP transceiver is correct. If not, enter the PS end to write the UDP protocol for protocol writing. If correct, enter the Linux host to configure the video codec, and then enter the test whether the video transmission meets the indicators. If not, return to the PL end to redesign the RTL design of the communication system. If correct, complete the transmission.

[0037] After verifying the correctness of the algorithm and transceiver functions using MATLAB, the radio platform part is designed; the first step is to test the configuration and drive of AD9361. Once the AD9361 is driven successfully, only some parameters will be modified later; the focus of this design is RTL design. When designing, the overall architecture must be determined first, and then implemented in modules, trying to reduce resource usage while ensuring the correctness of the functions as much as possible, reduce timing delays, and perform low-power design; an important means of saving FPGA resource usage is resource reuse, which is reflected in the design and implementation of the joint synchronization algorithm based on short training sequences and the Viterbi decoding module.

[0038] Regarding algorithm design, its implementation may involve some mathematical operations such as multiplication, division, and square root. These operations will consume a lot of resources when implemented in FPGA, especially DSP resources. Therefore, approximate operations can be used to complete the operation when the error is acceptable. Taking the joint synchronization algorithm based on short training sequences as an example, an approximate estimation algorithm is used in amplitude estimation, and in the joint phase estimation algorithm based on hardware optimization, four multiplications and one division operation are converted into shift operations to achieve implementation.

[0039] After the RTL design of each module is completed, Mode ls im simulation is performed and compared with the results of MATLAB to avoid errors that are difficult to troubleshoot later. After all modules are verified to be correct, sending and receiving experiments of one frame and multiple frames of data are carried out; the data source at the receiving end can be generated by MATLAB, and noise and frequency deviation interference can be superimposed on the transmitted data in MATLAB. The data output by the module during Mode ls im simulation can also be imported into MATLAB for analysis.

[0040] After the Mode ls im simulation verification is completed, use Vivado software to synthesize, implement, and solve the timing violation problem. Timing violations may cause errors in the system when the board is actually running; after the bit file is generated, it is verified on the board, and the ILA IP core is used to perform packet capture test. After the functional verification and transceiver test are successful, the video transmission function is designed and implemented. Otherwise, the RTL design still needs to be checked. Importing the captured data into MATLAB for analysis is a simple and effective way to find the cause of the error.

[0041] The Lightweight Internet Protocol (LwIP) protocol is written on the PS side, and finally a UDP loopback test is performed. After the test is successful, a data transmission and reception test is performed in conjunction with the baseband part. After the data is transmitted and received correctly, the Linux host is configured for software encoding and decoding, and local video and real-time video transmission tests are performed respectively. The real-time transmission rate and transmission delay are mainly tested. When the performance is poor, the RTL design still needs to be modified to reduce unnecessary timing delays.

[0042] After the video transmission system performance meets the design requirements, the system is finally integrated.

[0043] Communication transceiver test:

[0044] The communication transceiver test does not involve video encoding and decoding and UDP data transmission. The original data of the transmitter is generated locally. When the system is running, ILA is used to capture and view the actual signal, which occupies the RAM resources of FPGA. Pay attention to setting the trigger conditions when capturing.

[0045] like Figure 2 As shown in the figure, a frame of data transmitted from AD9361 to the baseband receiving end, in order not to exceed the limited RAM resources of the board and to facilitate observation, when constructing a frame of PPDU at the transmitting end, the data field has only 150 bytes.

[0046] like Figure 3 As shown, the power spectrum density of a frame of data actually captured by the receiver, from which it can be observed that the effective bandwidth is about 16MHz, which is consistent with the theory.

[0047] like Figure 4 As shown in the figure, due to the use of AD9361, the local oscillator frequencies of the transmitter and receiver are basically the same; in order to test the performance of the designed synchronization algorithms, the local oscillator frequencies of the transmitter and receiver were adjusted to a certain extent during the test; the local oscillator frequency deviation between the transmitter and the receiver was set to 15kHz, and a frame of captured data that had not yet entered the synchronization process was imported into the constellation diagram drawn by MATLAB; subsequent tests were also carried out based on the 15kHz local oscillator frequency deviation.

[0048] like Figure 5 As shown in the board-level verification of the packet detection function, you can see that the short_preamble_detected signal in the red box generates a pulse, which means that a frame of data is successfully captured.

[0049] like Figure 6 As shown in the figure, the board-level verification of the symbol synchronization function. It can be seen from the red box in the figure that the signal cross_corr has two peaks. At the moment of the second peak, the signal It_detect_ok is pulled high, marking the successful identification of the starting position of the FFT window. At this time, the signal sampled e ay_out after the input data delay is intercepted and output, and the output signals are signal align_it1_fil e_i and signal align_it1_fil e_q.

[0050] like Figure 7 As shown, the board-level verification of the channel estimation and equalization module, the signals h_csi_out_i and h_csi_out_q are the obtained real and imaginary part values, and the signals channel_data_i and channel_data_q are the output signals after equalization.

[0051] like Figure 8 As shown, a captured frame of signal is imported into the channel estimation diagram drawn in MATLAB.

[0052] like Fig. 9As shown, in order to verify the correctness of the carrier frequency offset estimation and phase correction functions, the key signals of the coarse frequency offset correction module, the fine frequency offset correction module and the phase correction module are put into an ILA for capture, and a frame of key data is captured; among them, the angle_out_d i v16x2pi signal is the estimated value of the carrier frequency offset by the coarse frequency offset correction module, which is approximately -12.737kHz after calculation, and the angle_out_d iv64x2pi signal is the estimated value of the carrier frequency offset by the fine frequency offset correction module, which is approximately -2.124kHz after calculation. The two modules compensated for a total of about 14.86kHz of the carrier frequency offset. It can be seen that the two modules function correctly and have excellent performance. The remaining carrier frequency offset will be compensated by the phase correction module. The signals data_chn l_out_i and data_chn l_out_q are the data outputs after phase compensation.

[0053] like Fig.10 As shown in the figure, due to the limited RAM resources on the Zynq PL side, in order to capture a frame of key data, the estimated value of the carrier by the coarse frequency offset correction, the estimated value of the carrier by the fine frequency offset correction, the I-channel data in the phase correction module and the data after compensation by the phase correction module are integrated into a signal data_out_i for output, and the signal data_out_valid_i is used to indicate the validity of the data, and the captured key data is imported into MATLAB for analysis;

[0054] Taking one frame of data as an example, the coarse frequency offset is estimated to be approximately -11.424kHz, the fine frequency offset is estimated to be approximately -4.732kHz, the residual frequency offset is estimated to be approximately 1.412kHz, the total compensated carrier frequency offset is approximately -14.744kHz, and the sampling frequency offset is estimated to be approximately 2.7ppm.

[0055] like Fig.11 and 12 As shown, it is the constellation diagram before and after phase compensation. Figure (a) is the constellation diagram before phase compensation, and the EVM is about -19.01dB. Figure (b) is the constellation diagram after phase compensation, and the EVM is about -28.96dB. Fig.12 To capture the RCFO and SFO values ​​calculated in MATLB after the sum data of the phase correction module; due to the small carrier frequency deviation caused by the multipath effect, the local oscillator frequencies of the transmitter and receiver are set to a 15kHz deviation during the test, so the estimation and compensation of the carrier frequency deviation are correct. From the comparison of the constellation diagrams in Figure (a) and Figure (b), it can be seen that the phase correction module solves the phase rotation problem caused by the residual carrier frequency deviation and sampling frequency deviation.

[0056] Table 1: The key parameters of each synchronization link are imported into MATLAB for calculation results, and the coarse frequency offset estimation value, fine frequency offset estimation value, residual frequency offset estimation value, total compensation value of carrier frequency offset, sampling frequency offset estimation value, EVM before phase compensation and EVM after phase compensation are analyzed; It can be seen from the data in the table that the total compensation of carrier frequency offset of the 6 frames of data is close to 15kHz, and the EVM after phase compensation is improved compared with the EVM before phase compensation.

[0057] Table 1 Calculation of key parameters of each synchronization link

[0058]

[0059] like Fig.13 As shown in the figure, the board-level verification of the CRC de-checking module, the signal fcs_ok_strobe is pulled high to indicate that the FCS check of a frame of data is completed, and the signal fcs_ok is pulled high to indicate that the FCS check of a frame of data is successful. The signal fcs_ok_strobe_cnt and the signal fcs_ok_cnt are the counts of the check completion and the check success respectively. The count value of the fcs_ok_cnt signal can be divided by the count value of the fcs_ok_strobe_cnt signal to calculate the PER of the system during long-term communication; the figure shows the counts of the two after running for 1 hour, and it can be seen that the PER is 0, which also reflects the stability of the baseband communication of this design.

[0060] Table 2 shows the occupation of various types of FPGA internal resources by the transmitter and receiver. From the data in the table, it can be seen that the receiver uses more FPGA resources than the transmitter, which also confirms that the receiver design is much more complicated than the transmitter.

[0061] Table 2 Transmitter and receiver FPGA resource usage

[0062] Baseband transmitter Baseband Receiver Slice LUTs 11140 23331 Slice Registers 20676 34197 F7 Muxes 6 66 F8 Muxes 3 28 Slice 3628 7837 LUT as Logic 7722 21775 LUT as Memory 3418 1556 Block RAM 27 50.5 DSPs 55 53 BUFGCTRL 1 0

[0063] Video transmission test:

[0064] like Fig.14 and Fig.15As shown in the figure, i Perf is a cross-platform network performance testing tool, which supports platforms such as Wi n / L inux / Mac / Android / iOS. i Perf can test the quality of TCP and UDP bandwidth, and can configure multiple parameters for testing. At the same time, i Perf can also report bandwidth, delay jitter and packet loss. JPerf is its graphical interface program; JPerf is configured to send data with a transmission rate of 13Mbps to the receiver using the UDP protocol; the receiving activity of the receiver's Ethernet port is tested. The data transmission rate received by the receiving end is about 12.5Mbps, that is, the maximum real-time data transmission rate supported by the video transmission system of this design is about 12.5Mbps. If the sent data stream exceeds the transmission rate, packet loss will occur.

[0065] When the sender sends a video with a resolution of 1080p and a frame rate of 24fps and a total bit rate of 3.527Mbps, the video displayed on the receiver's screen is stable, but some frames may freeze. After testing and analysis, this is because the data rate of the sender exceeds 12.5Mbps at certain moments. When the data rate of the video is less than 12.5Mbps at all times, there will be no freeze.

[0066] When the transmitter sends the real-time image of the camera, the image displayed on the receiving end screen is stable, but there is a certain delay, which is inevitable. Most of the delay is caused by software encoding and decoding. The transmission delay has been tested and stabilized at about 2.5s.

[0067] Table 3 shows the power consumption range of each module under the same test conditions. The reason why the receiver consumes more power than the transmitting Linux host is that the receiver's display screen is larger;

[0068]

[0069] From the above series of tests, it can be seen that each module of the baseband communication system operates normally and has good performance, and the real-time transmission rate and transmission delay of the entire video transmission system meet the standards set at the beginning.

[0070] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. OFDM video transmission system based on Zynq platform, characterized by: First, start to build the OFDM channel in MATLAB to verify whether the algorithm function and the transceiver test are correct. If not, enter MATLAB to build the OFDM channel system and rebuild the system. If correct, enter the driver AD9361 and then go to the PL end to perform the RTL design of the communication system and then perform Modelsim simulation. Then verify the algorithm function and the transceiver test for the second time. If not, return to the PL end to redesign the RTL design of the communication system. If correct, enter the OFDM communication system board-level verification, and then enter the verification algorithm function and transceiver test again. If not, return to the PL end to redesign the RTL design of the communication system. If correct, enter the PS end to write the UDP protocol. After entering, enter the stage of testing whether the UDP transceiver is correct. If not, enter the PS end to write the UDP protocol for protocol writing. If correct, enter the Linux host to configure the video codec, and then enter to test whether the video transmission meets the indicators. If not, return to the PL end to redesign the RTL design of the communication system. If correct, complete the transmission.

2. The OFDM video transmission system based on the Zynq platform according to claim 1, characterized in that: After verifying the correctness of the algorithm and transceiver functions using MATLAB, the radio platform part is designed; the first step is to test the configuration and drive of AD9361. Once the AD9361 is driven successfully, only some parameters will be modified later; the focus of this design is RTL design. When designing, the overall architecture must be determined first, and then implemented in modules, trying to reduce resource usage while ensuring the correctness of the functions as much as possible, reduce timing delays, and perform low-power design; an important means of saving FPGA resource usage is resource reuse, which is reflected in the design and implementation of the joint synchronization algorithm based on short training sequences and the Viterbi decoding module.

3. The OFDM video transmission system based on the Zynq platform according to claim 2, characterized in that: Regarding algorithm design, its implementation may involve some mathematical operations such as multiplication, division, and square root. These operations will consume a lot of resources when implemented in FPGA, especially DSP resources. Therefore, approximate operations can be used to complete the operation when the error is acceptable. Taking the joint synchronization algorithm based on short training sequences as an example, an approximate estimation algorithm is used in amplitude estimation, and in the joint phase estimation algorithm based on hardware optimization, four multiplications and one division operation are converted into shift operations to achieve implementation.

4. The OFDM video transmission system based on the Zynq platform according to claim 1, characterized in that: After the RTL design of each module is completed, Modelsim simulation is performed and compared with the results of MATLAB to avoid errors that are difficult to troubleshoot later. After all modules are verified to be correct, one-frame and multiple-frame data sending and receiving experiments are carried out; the data source at the receiving end can be generated by MATLAB, and noise and frequency offset interference can be superimposed on the transmitted data in MATLAB. The data output by the module during Modelsim simulation can also be imported into MATLAB for analysis.

5. The OFDM video transmission system based on Zynq platform according to claim 1, characterized in that: After Modelsim simulation verification is completed, use Vivado software to synthesize, implement, and solve timing violations. Timing violations may cause errors in the system when the actual board is running; After the bit file is generated, it is verified on the board and the packet capture test is performed using the ILA IP core. After the functional verification and the transceiver test are successful, the video transmission function is designed and implemented. Otherwise, the RTL design still needs to be checked. Importing the captured data into MATLAB for analysis is a simple and effective way to find the cause of the error.

6. The OFDM video transmission system based on the Zynq platform according to claim 1, characterized in that: The PS side writes a lightweight network interconnection protocol and finally performs a UDP loopback test. After the test is successful, the baseband part is combined to perform data transmission and reception test; After the data is sent and received correctly, the Linux host is configured for software encoding and decoding, and local video and real-time video transmission are tested respectively. The real-time transmission rate and transmission delay are mainly tested. When the performance is poor, the RTL design still needs to be modified to reduce unnecessary timing delays.

7. The OFDM video transmission system based on Zynq platform according to claim 1, characterized in that: After the video transmission system performance meets the design requirements, the system is finally integrated.

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