Address allocation method, battery module management method and electronic equipment

Abstract

The invention discloses an address allocation method, a battery module management method and electronic equipment, and belongs to the technical field of communication. The method comprises the following steps: acquiring first equipment direct-current internal resistance of a first node and second equipment direct-current internal resistance of a plurality of second nodes which are in communication connection with the first node; according to a preset test rule, cable direct current resistance between the first node and each second node in the plurality of second nodes is determined in sequence; determining a cable resistance value of a transmission cable between the first node and each second node according to the first equipment direct-current internal resistance, the second equipment direct-current internal resistance and the cable direct-current resistance; and allocating network addresses to the second nodes according to the sequence of the cable resistance values from small to large. Therefore, through the cable resistance value of the transmission cable between the first node and the second node, the physical sequence of cable connection of the node equipment is determined, and the corresponding network address is allocated to each node, so that the complexity of a communication interface can be reduced, and the reliability of the system is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of industrial control technology, and in particular to an address allocation method, a battery module management method, and an electronic device. Background Art

[0002] With the development of technology and the improvement of living standards, electronic products such as industrial control, medical treatment, communication, and consumption are becoming increasingly intelligent. Embedded systems with microprocessors as the core have been widely used, and on-site networking and management of these intelligent devices have also become the focus of embedded applications.

[0003] In the field of industrial control, embedded devices use field buses such as RS485 and CAN to achieve LAN communication at the field device level. An embedded device (called a host) can monitor other embedded devices (called slaves). Due to the large number of slaves, the host mostly uses the device communication address to distinguish each slave. When a slave fails, the address is lost or the same causes a bus conflict, the communication address needs to be reallocated to ensure normal communication.

[0004] The existing address allocation methods generally include the following:

[0005] (1) DIP configuration. The slave to be configured has a DIP switch. Each DIP switch has multiple key positions. The key positions of the DIP switches of different slaves must be different.

[0006] (2) Binding. When using the binding method, you need to press the button one by one to trigger the slave to enter the binding mode, and press the button again to exit the mode after the binding is completed;

[0007] (3) Power on one by one. Power on the slaves whose addresses are to be configured one by one (other slaves are powered off or not working), and let the host complete the address setting of the connected slaves in sequence through the CAN network.

[0008] (4) Auxiliary information identification method. This is to add auxiliary identification information for each slot to the slave, such as assigning a different level value to each slot. The most common approach is to add an SVB bus with a precision resistor voltage divider in series to provide each slot with a different level value. The slave recognizes the level and can set a different communication address value by itself.

[0009] (5) Daisy chain or token ring method. That is, a daisy chain channel is added between each slave node, and the input end of each slave is connected to the output end of the previous slave; by passing information to the next slave node step by step, the sequential allocation of addresses is achieved.

[0010] The above-mentioned address allocation method through dial code configuration, code matching, and power-on one by one requires manual operation and is prone to coding errors; while the auxiliary information recognition method, daisy chain or token ring method can automatically allocate addresses, but the wiring system is no longer a standard single-pair twisted pair, there are compatibility issues, and new signal lines need to be added to the standard communication bus, making the interface more complicated. At the same time, the system also increases the possibility of external risks being introduced, and additional ESD electrostatic protection and surge protection need to be added to the newly added interface, reducing communication reliability. Summary of the invention

[0011] The embodiments of the present application provide an address allocation method, a battery module management method and an electronic device to solve the problems in the prior art that manual address allocation is prone to coding errors, automatic address allocation requires the addition of new signal lines, and has complex interfaces and poor communication reliability.

[0012] In order to solve the above technical problems, this application is implemented as follows:

[0013] In a first aspect, an embodiment of the present application provides an address allocation method, including:

[0014] Acquire a first device DC internal resistance of a first node and a second device DC internal resistance of a plurality of second nodes that are communicatively connected to the first node;

[0015] Determine the cable DC resistance between the first node and each of the plurality of second nodes in sequence according to a preset test rule;

[0016] Determine a cable resistance of a transmission cable between the first node and each second node according to the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable;

[0017] A network address is allocated to each second node in the ascending order of the cable resistance.

[0018] In a second aspect, an embodiment of the present application provides a battery module management method for controlling a battery energy storage system, wherein the battery energy storage system comprises a battery system controller, a battery cluster management unit and a battery module; the battery system controller is communicatively connected to a plurality of battery cluster management units via a field bus, and each battery cluster management unit is communicatively connected to a plurality of battery modules via a field bus, and the field bus communication address is allocated based on the method described in the first aspect above.

[0019] In a third aspect, an embodiment of the present application provides a cable DC resistance measurement circuit, including:

[0020] A first node, the first node comprises a first transceiver, a first branch and a second branch; wherein a first switch and a first matching resistor are sequentially connected in series to form the first branch; a first on-resistance, a second switch, a bridge measurement topology circuit, a third switch and a second on-resistance are sequentially connected in series to form the second branch; the first transceiver, the first branch and the second branch are connected in parallel to a field bus;

[0021] A plurality of second nodes, wherein each of the second nodes comprises: a second transceiver, a third branch, and a fourth branch; a fourth switch and a second matching resistor are sequentially connected in series to form the third branch; a fifth switch and a third on-resistor are sequentially connected in series to form the fourth branch; the second transceiver, the third branch, and the fourth branch are connected in parallel to the field bus;

[0022] A bridge measurement topology circuit is built at both ends of the first node, and is used to measure the DC resistance of the cable between the first node and the second node to be measured when the second switch, the third switch and the fifth switch in each branch of the first node and the second node to be measured among the plurality of second nodes are turned on.

[0023] In a fourth aspect, an embodiment of the present application provides an electronic device, characterized in that it includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect or the second aspect above are implemented.

[0024] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect or the second aspect are implemented.

[0025] An embodiment of the present application provides an address allocation method, which obtains the DC internal resistance of a first device of a first node and the DC internal resistance of a second device of a plurality of second nodes that are interconnected and communicated with the first node; determines the DC resistance of a cable between the first node and each of the plurality of second nodes in sequence according to a preset test rule; determines the cable resistance of a transmission cable between the first node and each of the second nodes according to the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable; and allocates a network address to each second node in order of the cable resistance from small to large.

[0026] In this way, by determining the physical order of the node device cable connections through the cable resistance of the transmission cable between the first node and the second node, and assigning a corresponding network address to each node, automatic configuration of the network address can be achieved. Compared with the existing auxiliary information identification method, daisy chain or token ring method, the method provided in the embodiment of the present application can reduce the complexity of the communication interface and reduce the possibility of introducing external risks, thereby helping to improve the reliability of the system.

[0027] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0029] Figure 1 A schematic diagram of a flow chart of an address allocation method provided in an embodiment of the present application is shown;

[0030] Figure 2 The overall architecture diagram of the battery energy storage system provided by the embodiment of the present application is shown;

[0031] Figure 3 A schematic diagram of CAN network daisy chain engineering wiring provided by an embodiment of the present application is shown;

[0032] Figure 4 The topological structure diagram of the standard dual-terminal CAN network bus provided in the embodiment of the present application is shown;

[0033] Figure 5 A CAN network cable DC resistance measurement circuit diagram provided in an embodiment of the present application is shown;

[0034] Figure 6 A schematic diagram of the operation of allocating sub-device addresses of a CAN network provided by an embodiment of the present application is shown;

[0035] Figure 7 A flowchart of sequentially allocating communication addresses of sub-devices provided in an embodiment of the present application is shown;

[0036] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] In the field of industrial control, embedded devices use field buses such as RS485 and CAN to achieve LAN communication at the field device level. An embedded device (called a host) can monitor other embedded devices (called slaves). Due to the large number of slaves, the host mostly uses the device communication address to distinguish each slave. Taking the energy storage system as an example, in a typical large-scale energy storage system, a large number of battery modules connected in series and parallel are usually interconnected by the CAN bus and accept unified management by the superior management unit (such as a battery cluster controller or a battery system controller) to complete charge and discharge control, balancing, current sharing, abnormal protection, etc., in order to achieve value services such as frequency modulation and peak regulation, multi-energy complementarity, smooth power generation, and peak shaving and valley filling.

[0039] When a field bus such as CAN is used to form a field LAN, each slave needs to be distinguished by device identification. The simplest way is to use the device communication address to distinguish. In the CAN network of the energy storage system, the battery cluster controller or battery system controller is usually the host, and the numerous battery modules are slaves; each slave has a unique communication address, so that there will be no bus conflict.

[0040] Existing address allocation methods include dial configuration, code pairing, and power-on one by one. These methods usually require manual operation and are prone to coding errors. In addition, there are auxiliary information recognition methods, daisy chain or token ring methods. Although addresses can be automatically allocated, the wiring system is no longer a standard single-pair twisted pair. There are compatibility issues in the evolution to future technologies such as SPE; and new signal lines need to be added to the standard communication bus, making the interface more complicated. At the same time, the system also increases the possibility of external risks being introduced, and additional ESD electrostatic protection and surge protection need to be added to the new interface, reducing communication reliability.

[0041] In addition, no matter which method is used, the problem of matching resistance cannot be solved automatically. The CAN bus topology generally has three structures: daisy chain, tree and star. Among them, the daisy chain structure is the most commonly used topology on the project site. Generally, a 120-ohm terminal resistor is connected at both ends of the bus (the starting device and the end device) to achieve impedance matching between the transmission line and the load, reduce signal reflection, and improve signal quality and anti-interference ability. At present, the resistor needs to be manually connected at the start, which is very complicated and requires a lot of labor costs.

[0042] The embodiment of the present application provides an address allocation method, which determines the physical order of the node device cable connection through the cable resistance of the transmission cable between the first node and the second node, and allocates a corresponding network address to each node, so as to reduce the complexity of the communication interface and improve the reliability of the system. Figure 1 As shown in , the address allocation method 100 may include the following steps:

[0043] S101: Acquire a first device DC internal resistance of a first node and a second device DC internal resistance of a plurality of second nodes that are communicatively connected to the first node;

[0044] S102: determining the cable DC resistance between the first node and each of the plurality of second nodes in sequence according to a preset test rule;

[0045] S103: determining a cable resistance of a transmission cable between the first node and each second node according to the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable;

[0046] S104: Allocating a network address to each second node in the ascending order of the cable resistance.

[0047] Let's explain this with a specific example. Take the energy storage system as an example. Figure 2 As shown in the figure, the energy storage system includes: a battery module management unit BMU, a battery cluster management unit BCMU, and a battery system controller BSMU; BMU, BCMU and BSMU constitute a standard three-level BMS technical architecture: BCMU manages multiple BMUs through the CAN bus, and BCMU and BMU cooperate with each other to achieve sequential identification and allocation of BMU network addresses by carefully measuring the cable resistance of the transmission cable between the BCMU master node and each BMU slave node. BSMU also completes the sequential identification and allocation of each BCMU network address.

[0048] Since the cable resistance of the transmission cable is usually small, it is necessary to consider the DC internal resistance of the equipment at each node. In order to accurately determine the cable resistance, the embodiment of the present application tests the cable DC resistance between the master node and the slave node, determines the cable resistance according to the cable DC resistance and the DC internal resistance of the equipment at each node, and then sorts the cable resistance from large to small, correspondingly identifies the physical connection order of each slave node device, and sequentially allocates network addresses to each slave node. Compared with the existing auxiliary information identification method, daisy chain or token ring method, this method does not need to add new signal lines, and the sequential allocation of network addresses can be achieved by measuring the cable DC resistance. In this way, the complexity of the communication interface can be reduced, and the possibility of introducing external risks can be reduced, which is conducive to improving the reliability of the system.

[0049] In a possible implementation, in the above step S101, obtaining a first device DC internal resistance of a first node and a second device DC internal resistance of a plurality of second nodes that are communicatively connected to the first node includes:

[0050] The first node and the plurality of second nodes are sequentially cascaded in a daisy chain manner to establish a communication network between the first node and the plurality of second nodes;

[0051] Sending a request message to a target node in the communication network, and receiving a request response message carrying configuration information returned by the target node, the target node including a first node and a second node;

[0052] According to the configuration information carried in the request response message, a first device DC internal resistance of the first node and second device DC internal resistances of multiple second nodes are determined.

[0053] In a specific implementation, since the network engineering wiring based on the field bus is usually a sequential structure in the form of a daisy chain, the first node and the plurality of second nodes are sequentially cascaded in a daisy chain manner. Figure 3 As shown in , a communication network is established between the first node and multiple second nodes. In addition, the first node and multiple second nodes are cascaded in a daisy chain manner, and the cable length between each second node and the first node is different. In this way, a network address is assigned to each second node in the order of cable resistance from small to large, which can effectively avoid the problem of network address conflict.

[0054] Then, a request message is periodically sent to a target node in the communication network, and the target node responds and sends a request response message carrying configuration information; based on the configuration information carried in the request response message, the DC internal resistance of the first device of the first node and the DC internal resistance of the second devices of multiple second nodes are determined.

[0055] The configuration information includes a device serial number; in the above step S102, determining the cable DC resistance between the first node and each of the plurality of second nodes in sequence according to a preset test rule includes:

[0056] Sorting the target nodes according to the device serial numbers, and determining the test serial numbers corresponding to the target nodes according to the sorting results;

[0057] Send test configuration information to the target node, and when it is determined that the target node enters a test state, measure the DC resistance of the cable between the first node and each of the plurality of second nodes, wherein the test configuration information includes a test sequence number.

[0058] In the specific implementation, the device serial number DSN is the unique identification of each target node, which is sorted according to the size of the DSN and assigned a test serial number; through the established communication network, all target nodes are broadcast to inform them to start the resistance network test procedure, and the test configuration information sent includes: the total number of tests, the duration of a single test (also known as a test cycle), and the test serial number of the specified DSN. Obviously, if the number of slave nodes is 16 and the duration of a single test is 2 seconds, the entire test duration is 32 seconds.

[0059] When it is determined that the target node enters the test state, the DC resistance of the cable between the first node and each of the plurality of second nodes is measured. When a response message from the target node is received, it is determined that the target node enters the test state. That is, all target nodes are informed to formally start the test process through the established communication network broadcast, and if each target node confirms the response, all enter the test state.

[0060] In a possible implementation manner, the DC resistance of the cable between the first node and each of the plurality of second nodes may be measured in the following manner:

[0061] Controlling the electrical connection between the first node and a second node to be tested among a plurality of second nodes and a field bus to be turned on, so as to form a closed loop between the first node and the second node to be tested;

[0062] The direct current resistance of the cable between the first node and the second node to be tested is measured by using a bridge topology circuit pre-built at both ends of the first node.

[0063] Among them, the standard dual-terminal CAN network bus topology is as follows Figure 4As shown in , the first node BCMU is connected to each second node BMU.1, ..., BMU.m through the CAN bus, and matching resistors are connected to both ends of the bus (the starting device and the end device) to achieve impedance matching between the transmission line and the load. The embodiment of the present application first connects the first node and the second node to be tested into a closed loop through the field bus; then, the DC resistance of the cable between the first node and the second node to be tested is measured by a bridge measurement topology circuit pre-built at both ends of the first node.

[0064] The present application also provides a measurement circuit for the DC resistance of a cable. Figure 5 As shown in , the measurement circuit includes a first node, a plurality of second nodes and a bridge measurement topology circuit; wherein the first node includes a first transceiver r T0 , the first branch and the second branch; the first switch 1 and the first matching resistor r M0 are connected in series to form a first branch; the first on-resistance r 0n2 , the second switch 2, the bridge measurement topology circuit, the third switch 3 and the second on-resistance r 0n3 The first transceiver, the first branch and the second branch are connected in parallel to form a second branch; the first transceiver, the first branch and the second branch are connected to the field bus;

[0065] Each second node comprises a second transceiver t1 or tm , the third branch, the fourth branch; the fourth switch 2 and the second matching resistor r M1 The fifth switch 1 and the third on-resistance r 0n1 The fourth branch is sequentially connected in series; the second transceiver, the third branch, and the fourth branch are connected in parallel to the field bus;

[0066] A bridge measurement topology circuit is built at both ends of a first node, and is used to measure the DC resistance of a cable between a first node and a second node to be measured when a second switch 2, a third switch 3 and a fifth switch 1 in each branch of the first node and a second node to be measured among multiple second nodes are turned on.

[0067] Combination Figure 5 For the circuit structure shown in , the process of measuring the cable DC resistance may include the following steps:

[0068] Step 1: The slave node with the smallest test sequence number enters the test state first;

[0069] Step 2: For the second node (slave node) to be tested, close switch 1 on the CAN interface, i.e., turn on the resistance switch, to realize the loop of the cable to be tested; at the same time, disconnect switch 2 on the CAN interface, i.e., the matching resistance switch, to eliminate the influence of the matching resistance;

[0070] Step 3: For other slave nodes that are not measured, keep switches 1 and 2 on the CAN interface normally open;

[0071] Step 4: For the first node (master node), disconnect the matching resistance switch 1 on the CAN interface, and close the bridge measurement topology switches 2 and 3;

[0072] Step 5: The master node measures the DC resistance Zt of the entire cable between the master node and the slave node to be tested through a bridge measurement topology circuit. To avoid the influence of clock deviation, it is best to measure the resistance Zt near the center of the test cycle. For example, if the test cycle is 2 seconds, it is best to test in the period of 0.9 to 1.1 seconds;

[0073] Step 6: The cable resistance can be determined in the following way: after subtracting the master node DDIR value from the entire cable DC resistance Zt and then subtracting the slave node DDIR value, the actual cable resistance TCR of the transmission twisted pair can be obtained;

[0074] Step 7: Wait for the test cycle to end;

[0075] Step 8: According to the rules, start the slave node test of the next test sequence number;

[0076] Step 9: Repeat steps 2 to 7 to complete the cable resistance TCR test of all slave nodes;

[0077] Step 10: Complete all tests.

[0078] The DC internal resistance of the device is the sum of the single board internal resistance of the network interface end of the target node and the on-resistance of the analog switch; the DC internal resistance of the device is determined in the following manner:

[0079] Use a multimeter to measure the DC internal resistance of the device at the network interface end of the target node; or,

[0080] The first node and the second node are directly connected one-to-one by cable, and a bridge topology circuit pre-built at both ends of the first node is used to measure the DC internal resistance of the device at the network interface end of the second node.

[0081] In the specific implementation, during the factory commissioning phase, the DC internal resistance DDIR of each node is tested, combined with Figure 5 For the circuit structure shown in the figure, the steps for testing DDIR before leaving the factory are as follows:

[0082] Step 1: After the first node (master node) is powered on, run the commissioning subroutine, open switch 1, and close switches 2 and 3. Use the multimeter to measure small resistances with high precision (such as the four-wire measurement method and the four-wire measurement plus constant current source method to reduce the feeder resistance error) to measure the resistance at both ends of the CAN interface, that is, the DDIR of the master node; you can also build a bridge topology tooling for small resistance measurement to achieve automated measurement;

[0083] Step 2: After the second node (slave node) is powered on, run the commissioning subroutine, close switch 1, and open switch 2; as with the master node, use a multimeter or a measuring bridge topology tool to measure the slave node DDIR. Of course, you can also use the measuring bridge topology inside the master node to build a tool. For example, the master node and the slave node are directly connected one by one, and the connecting cable is as short as possible; run the cable resistance test process, obtain the cable DC resistance Zt, and then subtract the master node DDIR to obtain the slave node DDIR value (assuming that the connecting cable is as short as possible and the cable resistance is 0).

[0084] In a possible implementation, in the above step S104, after allocating a network address to each second node in the ascending order of the cable resistance, the address allocation method 100 further includes:

[0085] The first node sends an address allocation message to each second node, where the address allocation message includes a device serial number and a network address of the second node.

[0086] In a specific implementation, a network address is allocated to each second node in the order of the cable resistance from small to large, and the specific steps are as follows:

[0087] Step 1: The master node and slave node end the test state and return to the initial state; all switches on the CAN interfaces of all nodes return to the normally open state. The CAN network resumes normal communication;

[0088] Step 2: The master node sorts the TCR values ​​of all slave nodes from small to large;

[0089] Step 3: The smaller the TCR value, the shorter the cable length, the closer to the master node, and the smallest network communication address DNA is allocated, starting from 1;

[0090] Step 4: The master node saves all DNA values ​​to the system configuration table; and broadcasts the specified DSN and the assigned network address DNA to each slave node through the CAN network; each slave node with the specified DSN confirms the response and saves the DNA locally;

[0091] Step 5: Complete the sequential allocation of network addresses for all slave nodes.

[0092] In a possible implementation, in the above step S104, after allocating a network address to each second node in the ascending order of the cable resistance, the address allocation method 100 further includes:

[0093] A first matching resistor is configured at both ends of the first node, and a second matching resistor is configured at both ends of a second node having a largest network address among the plurality of second nodes.

[0094] In the specific implementation, combined with Figure 5 The circuit structure shown in the figure configures the first matching resistor at both ends of the first node through the analog switch, and configures the second matching resistor at both ends of the second node with the largest network address among multiple second nodes. Specifically, the master node closes switch 1 on the CAN interface to configure the matching resistor at the beginning of the network; the largest slave node of DNA closes switch 2 on the CAN interface to configure the matching resistor at the end of the network; all other nodes and all switches remain in a normally open state; each node locally stores whether the matching resistor is configured.

[0095] In a possible implementation, after receiving the request response message carrying the configuration information returned by the target node, the method further includes:

[0096] Storing the configuration information of the target node in a system configuration table;

[0097] A configuration information change message sent by the target second node is obtained, and the configuration information corresponding to the target second node in the system configuration table is updated according to the configuration change information carried in the configuration information change message.

[0098] Among them, the system configuration table is shown in Table 1:

[0099] Table 1 System Configuration Table

[0100] Master node configuration Number of slave nodes = m 1# Slave node configuration 2# Slave node configuration ..... m# Slave node configuration

[0101] From the above system configuration table, the number of slave nodes and the configuration information of the master node and each slave node can be obtained. The configuration information of the node can be as shown in Table 2:

[0102] Table 2 Node configuration table

[0103] Device Serial Number DSN Device DC internal resistance DDIR Device Network Address DNA Transmission cable resistance TCR

[0104] Among them, the device serial number DSN can be used as an index of the configuration information of each target node, and the multiple DC internal resistance, the allocated device network address and the calculated transmission cable resistance are all stored in the system configuration table.

[0105] When the configuration information of the target second node changes, the target second node actively reports a configuration information change message, and updates the configuration information corresponding to the target second node in the system configuration table according to the configuration change information carried in the configuration information change message.

[0106] In the specific implementation, if the second node is replaced in situ, for example, a sub-node device is unplugged due to a failure, and then a new device is inserted to replace it. Since the new device has just been connected to the network, it will actively broadcast its own DSN and apply for address configuration from the system. After the master node recognizes this scenario (the original node exits and the new node joins), the corresponding processing steps are as follows:

[0107] The master node updates the sub-device configuration information table; the sub-device with a changed communication address replaces the original DSN with a new DSN; the master node informs the new sub-device through CAN communication to use the configuration information of the original node, including the assigned sequential network address and whether the matching resistor is configured.

[0108] After updating the configuration information corresponding to the target second node in the system configuration table, the method further includes:

[0109] According to the configuration information of each target node in the updated system configuration table, determine the cable update resistance value of the transmission cable between the first node and each second node; assign a temporary network address to each second node in the order of the cable update resistance value from small to large; and configure a second matching resistor at both ends of the second node with the largest temporary network address among the second nodes.

[0110] Optionally, after allocating a temporary network address to each second node in the ascending order of the cable update resistance value, the method further includes:

[0111] Updating the network address of each second node to the temporary network address;

[0112] The first node sends an address allocation message to each second node, where the address allocation message includes a device serial number and an updated network address of the second node.

[0113] During the operation and maintenance phase, complex scenarios such as equipment expansion or partial replacement may occur. It is more important to make the configuration address simple, fast, automatic identification, and automatic update. The core technology is to achieve this through the intelligent collaboration of various devices, which can be divided into the following scenarios:

[0114] The first possible scenario: the number of child nodes decreases. For example, a child node device fails and is removed from the slot for maintenance. For the CAN network, this is equivalent to a child node exiting. When the master node discovers that a network child node has exited, the corresponding processing steps are as follows:

[0115] If the exiting child node is the terminal device, that is, the child node with the largest DNA value, the master node will notify the child node with the second largest DNA value to configure the terminal matching resistor; other configuration information of the system remains unchanged;

[0116] If the exited child node is an intermediate child device, that is, a child node with a non-maximum DNA value, all system configuration information can remain unchanged. Of course, you can also re-execute the automatic configuration at the start of the game according to the maintenance requirements or conventions of some users to achieve re-sequential address allocation to avoid discontinuity of child node addresses.

[0117] The second possible scenario: the increase in sub-nodes is equivalent to the expansion of the system. The newly inserted sub-node will actively broadcast its own DSN and apply for address configuration from the system; therefore, it can be determined whether there is a new device added. After the master node recognizes this scenario, the corresponding processing steps are as follows:

[0118] Re-execute the automatic configuration at the start of the deployment to temporarily redistribute addresses; analyze and compare the original address allocation and the new address allocation results;

[0119] If the address of the newly added child node is ranked the largest, it means that the system expansion is sequential expansion (that is, the newly added child device is after the original child device). The system uses the latest allocation result and informs the new node with the largest address to configure the terminal resistance matching.

[0120] If the addresses allocated to the newly added sub-nodes are ranked in the middle, it means that the system expansion is an empty slot expansion (that is, the newly added sub-device is inserted into the empty slot in the middle of the original device); at this time, the system uses the latest allocation result and informs the operation and maintenance system of all sub-node information with changed network addresses (indexed by DSN).

[0121] Through the above method, the system can realize automatic identification and automatic update of address configuration during the operation and maintenance phase, regardless of the expansion, replacement or reduction of equipment. In particular, when the network's starting and ending devices are changed, the terminal matching resistance can be changed automatically and dynamically. The sub-node with the largest network address is detected in real time, and the node is notified to dynamically configure the matching resistance by closing the matching resistance switch.

[0122] By adopting the address allocation method provided in the embodiment of the present application, it is possible to realize the automatic configuration of matching resistors, avoid the most common phenomenon of manual omission of matching resistor changes in daily operation and maintenance, and eliminate the operational risks such as occasional communication anomalies and positioning difficulties caused by resistance mismatch in the subsequent operation of the CAN network.

[0123] The following is a detailed description of the above steps with specific examples:

[0124] Assume that a company provides a large-capacity communication battery energy storage product for the core and aggregation rooms of telecom operators to replace the original lead-acid battery system. The energy storage product is completed by up to 192 groups of 48V / 100Ah intelligent lithium battery modules in parallel; among them, every 32 groups of battery modules form a battery cabinet, which is managed by the controller BCMU on the battery cabinet through the CAN network; when up to 6 such battery cabinets are connected in parallel, the entire energy storage system is formed. The entire energy storage system has a centralized controller BSMU, which manages 6 BCMUs through the CAN network; this constitutes a standard three-level BMS architecture.

[0125] In the original design, the 32 battery modules in each CAN network were assigned communication addresses 1 to 32 through address competition. Obviously, the communication address is completely inconsistent with the actual physical address of the slot, which will be very inconvenient in daily operation and maintenance. Therefore, the solution provided in the application is adopted to transform the BMU, BCMU and BSMU in the battery module, which can well realize the sequential allocation of communication addresses of each battery module and BCMU in the CAN network.

[0126] like Figure 6 As shown in the figure, during the product design phase, the CAN interface of each node needs to be modified by hardware, that is, adding a low-resistance analog switch to the slave node and adding a bridge topology for small resistance measurement to the master node. At the same time, the twisted pair and CAN interface need to be analyzed:

[0127] 1) CAN communication cable is a standard twisted pair cable, which is also the most commonly used transmission medium in integrated wiring projects. Generally, it is required that the resistance of Category 3 links does not exceed 170Ω, and that of Category 3 and above links does not exceed 30Ω. The ISO / IEC 11801 standard stipulates that the DC resistance of twisted pair cables shall not exceed 19.2Ω, and the difference in DC resistance between each pair of twisted pairs shall be less than 0.1Ω. Therefore, the DC loop resistance of each slave node cable to be measured is on the order of 0.1Ω;

[0128] 2) The CAN interface of each node device is usually deployed near the external connector, and the resistance of the PCB single board resistance is also in the order of 0.1Ω. The input resistance of the common CAN transceiver in the industry is generally above 20KΩ. We chose NXP's high-speed CAN transceiver TJA1051T / E, which has a typical input impedance of 30KΩ and has the ideal passive performance of the CAN bus when the power is off (that is, the ability of the transceiver to disconnect from the bus), which is very suitable for measuring the DC loop resistance of the cable;

[0129] 3) Since the cable DC loop resistance is in the order of 0.1Ω, in the bridge circuit in the master node, R0 selects a 1.0Ω precision resistor, R1 and R2 select 10Ω precision resistors, and the ratio arm multiplier k = R1 / R2 = 1.0, the highest test sensitivity can be obtained;

[0130] 4) Similarly, since the cable DC loop resistance is in the order of 0.1Ω, the on-resistance of the selected analog switch cannot be too large, otherwise the measurement accuracy will be affected. Therefore, we chose TI's dual SPST analog switch TS5A23166, which has a typical low on-resistance of 0.9Ω and a maximum flatness of only 0.2Ω;

[0131] During factory commissioning, the DDIR of each node needs to be tested and configured and saved together with the DSN. Self-developed tooling equipment is used in the commissioning. The core of the tooling equipment is a Kelvin bridge (double-arm bridge method) that can complete precision testing of small resistance values, and send the measured values ​​to the node equipment through communication for configuration and storage, which improves the automation level of production commissioning.

[0132] When the system is started, the CAN bus daisy chain cascade method is used to complete the sequential connection between the master node BCMU and each slave node BMU in each cabinet; similarly, the CAN bus daisy chain cascade between the system control unit master node BSMU and each parallel cabinet BCMU slave node is completed. Figure 7 As shown, taking a battery cabinet as an example, the address sequence and matching resistor automatic configuration of each slave node BMU is completed. The specific steps are as follows:

[0133] 1) The BCMU in the cabinet and each slave node BMU are turned on and running. Since each slave node is newly connected to the network, it will actively apply for address configuration; the master node BCMU obtains and saves the DSN and DDIR of each slave node;

[0134] 2) The master node BCMU sorts the DSN sizes of each slave node and assigns a test sequence number;

[0135] 3) The master node broadcasts to inform that it is ready to start the resistance network test, and informs the test procedures: total number of tests, single test duration, and test sequence number of the specified DSN. Each slave node confirms the response. Obviously, the number of slave nodes is 32, the single test duration is 2 seconds, and the entire test duration is 64 seconds;

[0136] 4) The master and slave nodes cooperate with each other to complete the TCR test of the transmission cable resistance of all slave nodes in turn;

[0137] 5) The master node sorts all the tested TCR values ​​from small to large, and uses the DSN of the slave node as the index, and allocates addresses sequentially starting from 1; the node with the smallest TCR value is allocated the smallest address DNA;

[0138] 6) The master node broadcasts to inform each slave node of the network address DNA assigned by the specified DSN. Each designated slave node confirms the response; in this way, the network address sequence allocation of all slave nodes is completed;

[0139] 7) The master node and the slave node with the largest address complete the resistance matching at the beginning and end;

[0140] Other battery cabinets can be operated in parallel to complete the sequential configuration of all slave node BMU addresses. Similarly, the sequential configuration of all BCMU addresses can also be completed.

[0141] Since the DC loop resistance of the cable to be measured is small, an analog switch with low on-resistance is selected to improve the measurement accuracy. Since analog switches may have different suppliers and different batches, there are some differences in their on-resistance Ron, which has been solved by configuring the DC internal resistance value DDIR of the factory test equipment. In addition, there is also a flatness problem with the on-resistance Ron, that is, Ron will change with the power supply voltage and input voltage value, and the difference between its maximum and minimum values ​​is the flatness of Ron. From the device data of various manufacturers, when the power supply voltage is high (such as exceeding 3.3V) or the input voltage is high (such as exceeding 2.5V), the flatness is very good, that is, the Ron value is basically stable.

[0142] Therefore, on the one hand, when supplying power to the analog switch, try to choose a higher voltage level. For example, for TI's TS5A23166, the power supply voltage range is -0.5V to 6.5V. Therefore, after providing a standard 5.0V power supply, the flatness of Ron is better. On the other hand, when testing the DDIR of each node during the factory commissioning phase, multi-point tests with different input voltages can be performed, and the test results can be saved in the node configuration table; when the host measures the DC loop resistance of the cable, it can be fitted or compensated according to the actual input voltage value to obtain a more accurate loop resistance measurement.

[0143] Figure 8 A schematic diagram of the hardware structure of an electronic device that implements the embodiment of the present application is shown. Referring to the figure, at the hardware level, the electronic device includes a processor, and optionally, an internal bus, a network interface, and a memory. Among them, the memory may include a memory, such as a high-speed random access memory (Random-Access Memory, RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage, etc. Of course, the electronic device may also include hardware required for other services.

[0144] The processor, the network interface and the memory may be interconnected through an internal bus, which may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one bidirectional arrow is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0145] The memory stores the program. Specifically, the program may include a program code, and the program code includes a computer operation instruction. The memory may include a memory and a non-volatile memory, and provides instructions and data to the processor.

[0146] The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a device for locating the target user at the logical level. The processor executes the program stored in the memory and specifically performs: Figure 1 The method disclosed in the illustrated embodiment realizes the functions and beneficial effects of each method described in the foregoing method embodiments, which will not be described in detail here.

[0147] The above application Figure 1The method disclosed in the illustrated embodiment may be implemented in a processor or by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method may be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application may be directly embodied as being executed by a hardware decoding processor, or may be executed by a combination of hardware and software modules in a decoding processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0148] The electronic device can also execute the methods described in the foregoing method embodiments, and realize the functions and beneficial effects of the methods described in the foregoing method embodiments, which will not be repeated here.

[0149] Of course, in addition to software implementation methods, the electronic device of the present application does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0150] The embodiment of the present application also provides a computer-readable storage medium, wherein the computer-readable medium stores one or more programs, and when the one or more programs are executed by an electronic device including multiple application programs, the electronic device executes Figure 1 The method disclosed in the illustrated embodiment realizes the functions and beneficial effects of each method described in the foregoing method embodiments, which will not be described in detail here.

[0151] The computer-readable storage medium includes a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0152] Furthermore, an embodiment of the present application also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, and when the program instructions are executed by a computer, the following process is implemented: Figure 1 The method disclosed in the illustrated embodiment realizes the functions and beneficial effects of each method described in the foregoing method embodiments, which will not be described in detail here.

[0153] In short, the above is only a preferred embodiment of the present application and does not limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0154] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0155] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0156] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0157] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

Claims

1. An address allocation method, characterized in that: include: Acquire a first device DC internal resistance of a first node and a second device DC internal resistance of a plurality of second nodes that are communicatively connected to the first node; Determine the cable DC resistance between the first node and each of the plurality of second nodes in sequence according to a preset test rule; Determine a cable resistance of a transmission cable between the first node and each second node according to the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable; A network address is allocated to each second node in the ascending order of the cable resistance.

2. The method according to claim 1, characterized in that The step of obtaining a first device DC internal resistance of a first node and a second device DC internal resistance of a plurality of second nodes that are communicatively connected to the first node includes: The first node and the plurality of second nodes are sequentially cascaded in a daisy chain manner to establish a communication network between the first node and the plurality of second nodes; Sending a request message to a target node in the communication network, and receiving a request response message carrying configuration information returned by the target node, the target node including a first node and a second node; According to the configuration information carried in the request response message, a first device DC internal resistance of the first node and second device DC internal resistances of multiple second nodes are determined.

3. The method according to claim 2, characterized in that The configuration information includes a device serial number; and determining the cable DC resistance between the first node and each of the plurality of second nodes in sequence according to a preset test rule includes: Sorting the target nodes according to the device serial numbers, and determining the test serial numbers corresponding to the target nodes according to the sorting results; Send test configuration information to the target node, and when it is determined that the target node enters a test state, measure the DC resistance of the cable between the first node and each of the plurality of second nodes, wherein the test configuration information includes a test sequence number.

4. The method according to claim 3, characterized in that The step of determining that the target node enters a test state includes: In case of receiving the response message from the target node, it is determined that the target node enters a test state.

5. The method according to claim 3, characterized in that: The measuring the cable DC resistance between the first node and each second node of the plurality of second nodes comprises: Controlling the electrical connection between the first node and a second node to be tested among a plurality of second nodes and a field bus to be turned on, so as to form a closed loop between the first node and the second node to be tested; The direct current resistance of the cable between the first node and the second node to be tested is measured by using a bridge measurement topology circuit pre-built at both ends of the first node.

6. The method according to claim 2, characterized in that The determining, according to the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable, a cable resistance of the transmission cable between the first node and each second node includes: The total device DC internal resistance is determined according to the first device DC internal resistance and the second device DC internal resistance, and the difference between the cable resistance and the total device DC internal resistance is determined as the cable resistance.

7. The method according to claim 6, characterized in that The device DC internal resistance is the sum of the single board internal resistance of the network interface end of the target node and the analog switch on-resistance; The DC internal resistance of the device is determined in the following manner: Use a multimeter to measure the DC internal resistance of the device at the network interface end of the target node; or, The first node and the second node are directly connected one-to-one by cable, and a bridge topology circuit pre-built at both ends of the first node is used to measure the DC internal resistance of the device at the network interface end of the second node.

8. The method according to claim 1, characterized in that After allocating a network address to each second node in the ascending order of the cable resistance, the method further includes: The first node sends an address allocation message to each second node, where the address allocation message includes a device serial number and a network address of the second node.

9. The method according to claim 1, characterized in that: After allocating a network address to each second node in the ascending order of the cable resistance, the method further includes: A first matching resistor is configured at both ends of the first node, and a second matching resistor is configured at both ends of a second node having a largest network address among the plurality of second nodes.

10. The method according to claim 2, characterized in that After receiving the request response message carrying the configuration information returned by the target node, the method further includes: Storing the configuration information of the target node in a system configuration table; A configuration information change message sent by the target second node is obtained, and the configuration information corresponding to the target second node in the system configuration table is updated according to the configuration change information carried in the configuration information change message.

11. The method according to claim 10, characterized in that After updating the configuration information corresponding to the target second node in the system configuration table, the method further includes: Determine, according to the configuration information of each target node in the updated system configuration table, an updated cable resistance value of the transmission cable between the first node and each second node; Allocating a temporary network address to each second node in the ascending order of the cable update resistance value; Second matching resistors are configured at both ends of the second node having the largest temporary network address among the second nodes.

12. The method according to claim 11, characterized in that After allocating a temporary network address to each second node in the ascending order of the updated cable resistance value, the method further includes: Updating the network address of each second node to the temporary network address; The first node sends an address allocation message to each second node, where the address allocation message includes a device serial number and an updated network address of the second node.

13. A battery module management method for controlling a battery energy storage system, wherein the battery energy storage system comprises a battery system controller, a battery cluster management unit and a battery module; the battery system controller is connected to multiple battery cluster management units through a field bus, and each battery cluster management unit is connected to multiple battery modules through a field bus, characterized in that: The field bus communication address is allocated based on the method according to any one of claims 1 to 12.

14. A cable DC resistance measurement circuit, characterized in that: include: A first node, the first node comprises a first transceiver, a first branch and a second branch; wherein a first switch and a first matching resistor are sequentially connected in series to form the first branch; a first on-resistance, a second switch, a bridge measurement topology circuit, a third switch and a second on-resistance are sequentially connected in series to form the second branch; the first transceiver, the first branch and the second branch are connected in parallel to a field bus; A plurality of second nodes, wherein each of the second nodes comprises: a second transceiver, a third branch, and a fourth branch; a fourth switch and a second matching resistor are sequentially connected in series to form the third branch; a fifth switch and a third on-resistor are sequentially connected in series to form the fourth branch; the second transceiver, the third branch, and the fourth branch are connected in parallel to the field bus; A bridge measurement topology circuit is built at both ends of the first node, and is used to measure the DC resistance of the cable between the first node and the second node to be measured when the second switch, the third switch and the fifth switch in each branch of the first node and the second node to be measured among the plurality of second nodes are turned on.

15. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 13 are implemented.

16. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 13 are implemented.

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