Self-adaptive reset large dynamic range pixel structure, image sensor and electronic equipment

Abstract

The invention discloses an adaptive reset large dynamic range pixel structure, an image sensor and electronic equipment. A pixel unit of the large dynamic range pixel structure realizes self-adaptive control of resetting of pixels in different light intensity scenes through column feedback, realizes dynamic range expansion in a low-light environment, and comprises a photodiode, a transmission tube, a charge storage capacitor, a reset tube, a first switch, a first capacitor, a first source follower, a second switch and a row selection tube, the first source follower, the second source follower, the third switch, the latch, the first AND gate and the second AND gate. The readout selection circuit is used for controlling the pixels to read out the reset voltage and the signal voltage in sequence, and the feedback logic circuit is used for receiving a comparison result of a frame on the column readout circuit to control whether the pixels are reset or not. In the low-light environment, the pixel is not reset and then the exposure of the next frame is started, and low-light-intensity signal quantization is realized through frame-by-frame accumulation, so that the low-light detection capability of the pixel is expanded, and the dynamic range in the low-light environment is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a large dynamic range pixel structure, an image sensor and an electronic device suitable for adaptive reset in a dim light environment. Background Art

[0002] Dynamic Range (DR) is one of the key performance parameters of CIS. It represents the range of the maximum light intensity signal and the minimum light intensity signal that CIS can detect simultaneously in the same frame of image. The higher the dynamic range, the clearer the contrast details of the image. The low-light detection capability of CIS is closely related to the conversion gain of the pixel and the quantization accuracy of the ADC. The light signal is very small in a low-light environment, and a high conversion gain is required to convert the light signal into an electrical signal, and then quantize it through a high-precision ADC to obtain effective light information. The conversion gain of the pixel is determined by the capacitance of the charge-voltage conversion node, and it is difficult to further improve it due to parasitic effects. The quantization accuracy of the ADC is determined by the number of bits of the counter. Improving the accuracy of the ADC will lead to an increase in power consumption and area. Therefore, there are huge challenges in improving the low-light detection capability of pixels. Summary of the invention

[0003] The purpose of the present invention is to solve the problem that the traditional pixel has weak low-light detection capability and low dynamic range in low-light environment, and proposes a large dynamic range pixel structure with adaptive reset, an image sensor and an electronic device. After each frame of exposure is completed, the large dynamic range pixel structure with adaptive reset determines whether the pixel is reset through the comparison result of the column-level circuit. When the light intensity is low, it is not reset and continues to be exposed on the basis of the previous frame, thereby realizing the quantization of the low-light signal and expanding the dynamic range of the low-light environment.

[0004] A first aspect of the present invention provides a large dynamic range pixel structure with adaptive reset, wherein the pixel unit realizes adaptive control of pixel reset in different light intensity scenes through column feedback, thereby realizing dynamic range expansion in low light environment, including a photodiode, a transmission tube, a charge storage capacitor, a reset tube, a first switch, a first capacitor, a first source follower, a second switch, a row selection tube, a second source follower, a third switch, a latch, a first AND gate, and a second AND gate;

[0005] Among them, the positive electrode of the photodiode is connected to the source of the transmission tube, the negative electrode of the photodiode is grounded, the gate of the transmission tube is connected to the transmission control signal, the drain of the transmission tube is connected to one end of the charge storage capacitor, the source of the first switch, and the source of the reset tube at the same time, the other end of the charge storage capacitor is grounded, the drain of the first switch is connected to one end of the first capacitor and the gate of the first source follower at the same time, the gate of the first switch is connected to the output of the first AND gate, the other end of the first capacitor is grounded, the drain of the first source follower is connected to the power supply voltage, the source of the first source follower is connected to the source of the second switch, the drain of the second switch is connected to the source of the row selection tube, the gate of the second switch is connected to the second switch signal, and the row selection tube The gate of the second source follower is connected to the row selection signal, the drain of the row selection tube is connected to the column bus, the gate of the second source follower is connected to the source of the first switch, the drain of the second source follower is connected to the power supply voltage, the source of the second source follower is connected to the source of the third switch, the drain of the third switch is connected to the source of the row selection tube, the gate of the third switch is connected to the third switch signal, the input of the latch is the column feedback signal, the clock signal of the latch is the latch signal, the output of the latch is simultaneously connected to one end of the input of the first AND gate and the second AND gate, the other end of the input of the first AND gate is the first switch signal, the other end of the input of the second AND gate is the reset control signal, the output of the second AND gate is connected to the gate of the reset tube, and the drain of the reset tube is connected to the power supply voltage.

[0006] Among them, after each frame of exposure is completed, the pixel unit determines whether the pixel is reset through the comparison result of the column-level circuit. If it is not reset, it continues to expose based on the previous frame, thereby realizing quantization of the low-light signal and expanding the dynamic range of the low-light environment.

[0007] Among them, the comparison result of the column-level circuit is used to determine whether the pixel is reset, and the judgment is made by determining whether the difference between the read reset voltage and the signal voltage is less than the reference voltage; if the difference between the reset voltage and the signal voltage is less than the reference voltage, the column feedback signal is low and the pixel is not reset; if the difference between the reset voltage and the signal voltage is greater than the reference voltage, the column feedback signal is high and the pixel is reset.

[0008] The read reset voltage and signal voltage are subtracted by correlated double sampling, and the subtraction result is compared with the reference voltage to generate a column feedback signal.

[0009] Wherein, the column feedback signal is transmitted to the second AND gate under the control of the latch signal, and the output of the second AND gate controls whether the reset tube is reset.

[0010] The process of the pixel unit performing signal processing and outputting a reset voltage and a signal voltage includes:

[0011] The first capacitor stores the reset voltage of the pixel, and the sampling voltage is read out through the first source follower. The charge storage capacitor stores the signal voltage of the pixel, and the signal voltage is read out through the second source follower. When the row select tube is turned on, the second switch signal and the third switch signal control the reset voltage and the signal voltage to be read out to the column bus in sequence.

[0012] The output of the pixel unit is connected to a column readout unit, and the column readout unit includes a fourth switch, a fifth switch, a second capacitor, a third capacitor, a CDS circuit, a first comparator, a ramp generator, a second comparator, and a counter;

[0013] Among them, the column bus Vpix is ​​connected to one end of the fourth switch and the fifth switch, the other end of the fourth switch is simultaneously connected to one end of the second capacitor and the first input end of the CDS circuit, the other end of the fifth switch is simultaneously connected to one end of the third capacitor and the second input end of the CDS circuit, the fourth switch is controlled by the second switch signal, the fifth switch is controlled by the third switch signal S3, the other ends of the second capacitor and the third capacitor are both grounded, the output end of the CDS circuit is simultaneously connected to the positive input end of the first comparator and the positive input end of the second comparator, the negative input end of the first comparator is connected to the reference voltage Vref, the output of the first comparator is the column feedback signal FS, the negative input end of the second comparator is connected to the output Vramp of the ramp generator, and the output of the second comparator is connected to the counter.

[0014] The signal processing process of the pixel unit includes:

[0015] When the result of the difference between the reset voltage and the signal voltage output by the pixel in the previous frame after the CDS circuit is greater than the set threshold value Vref, the output column feedback signal FS of the first comparator is high level. During the high level period of the clock signal LATCH, the column feedback signal FS is latched in the latch and keeps the latched result until the next high level arrives; when the reset signal RST is pulled high, the second AND gate outputs a high level, the reset tube in the pixel is turned on, and the transmission tube is turned on at the same time to reset the photodiode and the charge storage capacitor. After the reset is completed, the transmission tube is turned off, the reset signal RST is pulled low, and then the exposure stage is entered; after the exposure is completed, the signal transfer stage is entered, firstly the reset signal RST and the first switch signal S1 are pulled high, the first AND gate and the second AND gate both output high level, control the reset tube and the first switch to turn on, and reset the charge storage capacitor and the first capacitor; after the reset, the reset signal RST and the first switch signal S1 are pulled low, The reset voltage is stored in the first capacitor; then the transmission signal TX is pulled high, the transmission tube is turned on, and the charge accumulated by the photodiode during the exposure period is transferred to the charge storage capacitor. After the transfer is completed, the transmission signal TX is pulled low, and the signal voltage is stored in the charge storage capacitor, and then the readout stage is entered; during the readout period, the row selection signal SEL is pulled high, the row selection tube is turned on, and the pixel is connected to the column bus Vpix. First, the second switch signal S2 is pulled high, the second switch and the fourth switch are turned on, and the reset voltage stored in the first capacitor is read out to the second capacitor; then the third switch signal S3 is pulled high, the third switch and the fifth switch are turned on, and the signal voltage stored in the charge storage capacitor is read out to the third capacitor; then the CDS circuit in the column readout unit makes a difference between the reset voltage stored in the second capacitor and the signal voltage stored in the third capacitor, and the result of the difference is compared with the set threshold value Vref, and the comparison result FS is fed back to the pixel to control the reset of the next frame. At the same time, the result of the difference is compared with the ramp signal Vramp generated by the ramp generator through the second comparator, and quantized by the counter;

[0016] When the result of the difference between the reset voltage and the signal voltage of the pixel output of the previous frame after the CDS circuit is less than the set threshold value Vref, the column feedback signal FS is low. During the high level of the clock signal LATCH, the column feedback signal FS is latched in the latch, and the latch output is low. When the reset signal RST is pulled high, the output of the second AND gate remains low, the charge storage capacitor is not reset, and the signal voltage of the previous frame is still stored, and the exposure continues. After the exposure is completed, the reset signal RST and the first switch signal S1 are pulled high. Since the output of the latch is low, the outputs of the first and second AND gates remain low, and the reset tube and the first The switch will not be turned on, and the reset voltage stored in the first capacitor will not be refreshed. Then the transmission signal TX is pulled high, and the charge accumulated by the photodiode during the exposure period continues to be transferred to the charge storage capacitor. After the transfer is completed, it enters the readout stage; the signal readout process: first read the reset voltage and then read the signal voltage. After being stored in the second capacitor and the third capacitor respectively, they are subtracted through the CDS circuit. The result after the subtraction is compared with the reference voltage Vref in the first comparator, and the comparison result FS is fed back to the pixel to control the reset of the next frame; at the same time, the result after the subtraction is compared with the ramp signal Vramp generated by the ramp generator through the second comparator and quantized by the counter.

[0017] A second aspect of the present invention provides an image sensor including the adaptive reset large dynamic range pixel structure.

[0018] According to a third aspect of the present invention, an electronic device is provided, comprising the above-mentioned image sensor.

[0019] The first capacitor in the pixel structure of the present invention stores the reset voltage of the pixel, the sampling voltage is read out through the first source follower, the charge storage capacitor stores the signal voltage of the pixel, the signal voltage is read out through the second source follower, and when the row selection tube is turned on, the second switch signal and the third switch signal control the reset voltage and the signal voltage to be read out to the column bus in sequence; the read reset voltage and signal voltage are subtracted by Correlated Double Sample (CDS), and the result after subtraction is compared with the reference voltage to generate a column feedback signal, and the column feedback signal is transmitted to the second AND gate under the control of the latch signal, and the output of the second AND gate controls whether the reset tube is reset; if the difference between the reset voltage and the signal voltage is less than the reference voltage, the column feedback signal is low level, and the pixel is not reset; if the difference between the reset voltage and the signal voltage is greater than the reference voltage, the column feedback signal is high level, and the pixel is reset; adaptive control of pixel reset in different light intensity scenes is realized through column feedback, and dynamic range expansion of low light environment is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1Schematic diagram of a circuit of a pixel unit in an embodiment of the present invention.

[0021] Figure 2 Schematic diagram of a circuit of a column readout unit in an embodiment of the present invention.

[0022] Figure 3 Schematic diagram of the timing of the pixel unit in the embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0024] The first aspect of the embodiment of the present invention provides a large dynamic range pixel junction with adaptive reset, including a traditional 4T pixel circuit, a readout selection circuit 201 and a feedback logic circuit 301. The readout selection circuit 201 controls the pixel to read out the reset voltage and the signal voltage in sequence, and the feedback logic circuit 301 receives the comparison result of the previous frame of the column readout circuit to control whether the pixel is reset. In a low-light environment, the pixel does not reset and then starts the exposure of the next frame. The low-light intensity signal is quantized by accumulating frame by frame, thereby expanding the low-light detection capability of the pixel and improving the dynamic range in a low-light environment.

[0025] The embodiment of the present invention provides a large dynamic range pixel structure with adaptive reset, referring to Figure 1 As shown, the pixel structure includes a photodiode 101, a transmission tube 102, a charge storage capacitor 103, a reset tube 104, a row selection tube 105, a readout selection circuit 201, and a feedback logic circuit 301. The readout selection circuit 201 includes a first switch 2011, a first capacitor 2012, a first source follower 2013, a second switch 2014, a second source follower 2015, and a third switch 2016. The feedback logic circuit 301 includes a latch 3011, a first AND gate 3012, and a second AND gate 3013.

[0026] Reference Figure 1As shown, the positive electrode of the photodiode (PD) 101 is connected to the source of the transmission tube 102, the negative electrode of the photodiode 101 is grounded, the gate of the transmission tube 102 is connected to the transmission control signal TX, the drain of the transmission tube 102 is simultaneously connected to one end of the charge storage capacitor (FD) 103, the source of the first switch 2011, and the source of the reset tube 104, the other end of the charge storage capacitor 103 is grounded, and the drain of the first switch 2011 is simultaneously connected to the first capacitor (C1) 2012 The gate of the first switch 2011 is connected to the output of the first AND gate 3012, the other end of the first capacitor 2012 is grounded, the drain of the first source follower 2013 is connected to the power supply voltage, the source of the first source follower 2013 is connected to the source of the second switch 2014, the drain of the second switch 2014 is connected to the source of the row selection tube 105, the gate of the second switch 2014 is connected to the second switch signal S2, and the row selection tube 105 is connected. The gate of the second source follower 2015 is connected to the row selection signal SEL, the drain of the row selection tube 105 is connected to the column bus Vpix, the gate of the second source follower 2015 is connected to the source of the first switch 2011, the drain of the second source follower 2015 is connected to the power supply voltage, the source of the second source follower 2015 is connected to the source of the third switch 2016, the drain of the third switch 2016 is connected to the source of the row selection tube 105, the gate of the third switch 2016 is connected to the third switch signal S3, the latch 3011 The input of the latch 3011 is the column feedback signal FS, the clock signal of the latch 3011 is the latch signal LATCH, the output of the latch 3011 is connected to the first AND gate 3012 and one end of the second AND gate 3013 at the same time, the other end of the first AND gate 3012 is input as the first switch signal S1, the other end of the second AND gate 3013 is input as the reset control signal RST, the output of the second AND gate 3013 is connected to the gate of the reset tube 104, and the drain of the reset tube 104 is connected to the power supply voltage.

[0027] Figure 2 FIG. 1 is a circuit diagram of a readout unit in an embodiment of the present invention. Figure 2 As shown, the column readout unit includes a fourth switch 401 , a fifth switch 402 , a second capacitor 403 , a third capacitor 404 , a CDS circuit 405 , a first comparator 406 , a ramp generator 407 , a second comparator 408 , and a counter 409 .

[0028] Reference Figure 2As shown, the column bus Vpix is ​​simultaneously connected to one end of the fourth switch 401 and the fifth switch 402, the other end of the fourth switch 401 is simultaneously connected to one end of the second capacitor 403 and the first input end of the CDS circuit 405, the other end of the fifth switch 402 is simultaneously connected to one end of the third capacitor 404 and the second input end of the CDS circuit 405, the fourth switch 401 is controlled by the second switch signal S2, the fifth switch 402 is controlled by the third switch signal S3, the other ends of the second capacitor 403 and the third capacitor 404 are both grounded, the output end of the CDS circuit 405 is simultaneously connected to the positive input end of the first comparator 406 and the positive input end of the second comparator 408, the negative input end of the first comparator 406 is connected to the reference voltage Vref, the output of the first comparator 406 is the column feedback signal FS, the negative input end of the second comparator 408 is connected to the output Vramp of the ramp generator 407, and the output of the second comparator 408 is connected to the counter 409.

[0029] The CDS circuit 405 , the first comparator 406 , the second comparator 408 , the ramp generator 407 , and the counter 409 are all well-known technologies in the art and will not be described in detail herein.

[0030] Figure 3 Schematic diagram of the timing of the pixel unit in the embodiment of the present invention.

[0031] See also Figure 3As shown, when the result of the difference between the reset voltage and the signal voltage output by the pixel in the previous frame after the CDS circuit 405 is greater than the set threshold value Vref, the output column feedback signal FS of the first comparator 406 is high level, and during the high level period of the clock signal LATCH, the column feedback signal FS is latched in the latch 3011, and the latched result is kept until the next high level comes; when the reset signal RST is pulled high, the second AND gate 3013 outputs a high level, the reset tube 104 in the pixel is turned on, and the transmission tube 102 is turned on, and the photodiode 1 is turned on. 01 and the charge storage capacitor 103 are reset. After the reset is completed, the transmission tube 102 is turned off, the reset signal RST is pulled low, and then the exposure stage is entered; after the exposure is completed, the signal transfer stage is entered, firstly, the reset signal RST and the first switch signal S1 are pulled high, the first AND gate 3012 and the second AND gate 3013 both output high level, control the reset tube 104 and the first switch 2011 to be turned on, and the charge storage capacitor 103 and the first capacitor 2012 are reset; after the reset, the reset signal RST and the first switch signal S1 are pulled low, and the reset voltage is stored in the first capacitor 2012. Then the transmission signal TX is pulled high, the transmission tube 102 is turned on, and the charge accumulated by the photodiode 101 during the exposure period is transferred to the charge storage capacitor 103. After the transfer is completed, the transmission signal TX is pulled low, and the signal voltage is stored in the charge storage capacitor 103, and then the readout stage is entered; during the readout period, the row selection signal SEL is pulled high, the row selection tube 105 is turned on, and the pixel remains connected to the column bus Vpix. First, the second switch signal S2 is pulled high, the second switch 2014 and the fourth switch 401 are turned on, and the reset voltage stored in the first capacitor 2012 is read out to the second capacitor 403; then the third switch signal S3 is pulled high, the third switch 2016 and the fifth switch 402 are turned on, and the signal voltage stored in the charge storage capacitor 103 is read out to the third capacitor 404. Then the CDS circuit 405 in the column readout unit makes a difference between the reset voltage stored in the second capacitor 403 and the signal voltage stored in the third capacitor 404, and the result after the difference is compared with the set threshold value Vref, and the comparison result FS is fed back to the pixel to control the reset of the next frame. At the same time, the result after the difference is compared with the ramp signal Vramp generated by the ramp generator 407 through the second comparator 408, and quantized by the counter 409.

[0032] When the result of the difference between the reset voltage and the signal voltage output by the pixel of the previous frame after the CDS circuit 405 is less than the set threshold value Vref, the column feedback signal FS is at a low level. During the high level period of the clock signal LATCH, the column feedback signal FS is latched in the latch 3011, and the output of the latch 3011 is at a low level. When the reset signal RST is pulled high, the output of the second AND gate 3013 still remains at a low level, the charge storage capacitor 103 is not reset, and the signal voltage of the previous frame is still stored, and the exposure continues. After the exposure is completed, the reset signal RST and the first switch signal S1 are pulled high, but since the output of the latch 3011 is at a low level, the first AND gate 3012 The output of the second AND gate 3013 remains low, the reset tube 104 and the first switch 2011 will not be turned on, the reset voltage stored in the first capacitor 2012 will not be refreshed, and then the transmission signal TX is pulled high, and the charge accumulated by the photodiode 101 during the exposure period continues to be transferred to the charge storage capacitor 103, and the readout stage is entered after the transfer is completed; the readout process is still: first read the reset voltage and then read the signal voltage, after being stored by the second capacitor 403 and the third capacitor 404 respectively, the difference is made through the CDS circuit 405, and the result after the difference is compared with the reference voltage Vref in the first comparator 406, and the comparison result FS is fed back to the pixel to control the reset of the next frame. At the same time, the result after the difference is compared with the ramp signal Vramp generated by the ramp generator 407 through the second comparator 408, and quantized by the counter 409.

[0033] The large dynamic range pixel structure with adaptive reset proposed in the embodiment of the present invention determines whether the pixel is reset through the comparison result of the column readout circuit after the exposure of each frame is completed. When the light intensity is low, no reset is performed and exposure is continued based on the previous frame, thereby realizing quantization of the low-light signal and effectively expanding the dynamic range of the low-light environment.

[0034] A second aspect of the embodiments of the present invention provides an image sensor, comprising the adaptive reset large dynamic range pixel structure of the first aspect of the embodiments of the present invention.

[0035] According to a third aspect of the embodiments of the present invention, there is provided an electronic device, comprising the image sensor according to the second aspect of the embodiments of the present invention.

[0036] The basic principles and main features of the present invention and the advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0037] Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the claims are included in the present invention.

[0038] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A large dynamic range pixel structure with adaptive reset, characterized in that: The pixel unit realizes adaptive control of pixel reset in different light intensity scenes through column feedback, and realizes dynamic range expansion in low light environment, including photodiode, transmission tube, charge storage capacitor, reset tube, first switch, first capacitor, first source follower, second switch, row selection tube, second source follower, third switch, latch, first AND gate, and second AND gate; Among them, the positive electrode of the photodiode is connected to the source of the transmission tube, the negative electrode of the photodiode is grounded, the gate of the transmission tube is connected to the transmission control signal, the drain of the transmission tube is connected to one end of the charge storage capacitor, the source of the first switch, and the source of the reset tube at the same time, the other end of the charge storage capacitor is grounded, the drain of the first switch is connected to one end of the first capacitor and the gate of the first source follower at the same time, the gate of the first switch is connected to the output of the first AND gate, the other end of the first capacitor is grounded, the drain of the first source follower is connected to the power supply voltage, the source of the first source follower is connected to the source of the second switch, the drain of the second switch is connected to the source of the row selection tube, the gate of the second switch is connected to the second switch signal, and the row selection tube The gate of the second source follower is connected to the row selection signal, the drain of the row selection tube is connected to the column bus, the gate of the second source follower is connected to the source of the first switch, the drain of the second source follower is connected to the power supply voltage, the source of the second source follower is connected to the source of the third switch, the drain of the third switch is connected to the source of the row selection tube, the gate of the third switch is connected to the third switch signal, the input of the latch is the column feedback signal, the clock signal of the latch is the latch signal, the output of the latch is simultaneously connected to one end of the input of the first AND gate and the second AND gate, the other end of the input of the first AND gate is the first switch signal, the other end of the input of the second AND gate is the reset control signal, the output of the second AND gate is connected to the gate of the reset tube, and the drain of the reset tube is connected to the power supply voltage.

2. The large dynamic range pixel structure with adaptive reset according to claim 1, characterized in that: After each frame of exposure is completed, the pixel unit determines whether the pixel is reset through the comparison result of the column-level circuit. If it is not reset, the exposure is continued based on the previous frame, thereby realizing quantization of the low-light signal and expanding the dynamic range of the low-light environment.

3. The large dynamic range pixel structure with adaptive reset according to claim 2, characterized in that: The comparison result of the column-level circuit is used to determine whether the pixel is reset, and the judgment is made by determining whether the difference between the read reset voltage and the signal voltage is less than the reference voltage; if the difference between the reset voltage and the signal voltage is less than the reference voltage, the column feedback signal is low and the pixel is not reset; if the difference between the reset voltage and the signal voltage is greater than the reference voltage, the column feedback signal is high and the pixel is reset.

4. The large dynamic range pixel structure with adaptive reset according to claim 3, characterized in that: The read reset voltage and signal voltage are subtracted by correlated double sampling, and the subtraction result is compared with the reference voltage to generate a column feedback signal.

5. The large dynamic range pixel structure with adaptive reset according to claim 4, characterized in that: The column feedback signal is transmitted to the second AND gate under the control of the latch signal, and the output of the second AND gate controls whether the reset tube is reset.

6. The large dynamic range pixel structure with adaptive reset according to claim 5, characterized in that: The process of the pixel unit performing signal processing and outputting a reset voltage and a signal voltage includes: The first capacitor stores the reset voltage of the pixel, and the sampling voltage is read out through the first source follower. The charge storage capacitor stores the signal voltage of the pixel, and the signal voltage is read out through the second source follower. When the row select tube is turned on, the second switch signal and the third switch signal control the reset voltage and the signal voltage to be read out to the column bus in sequence.

7. The large dynamic range pixel structure with adaptive reset according to claim 1, characterized in that: The output of the pixel unit is connected to a column readout unit, and the column readout unit includes a fourth switch, a fifth switch, a second capacitor, a third capacitor, a CDS circuit, a first comparator, a ramp generator, a second comparator, and a counter; Among them, the column bus Vpix is ​​connected to one end of the fourth switch and the fifth switch, the other end of the fourth switch is simultaneously connected to one end of the second capacitor and the first input end of the CDS circuit, the other end of the fifth switch is simultaneously connected to one end of the third capacitor and the second input end of the CDS circuit, the fourth switch is controlled by the second switch signal, the fifth switch is controlled by the third switch signal S3, the other ends of the second capacitor and the third capacitor are both grounded, the output end of the CDS circuit is simultaneously connected to the positive input end of the first comparator and the positive input end of the second comparator, the negative input end of the first comparator is connected to the reference voltage Vref, the output of the first comparator is the column feedback signal FS, the negative input end of the second comparator is connected to the output Vramp of the ramp generator, and the output of the second comparator is connected to the counter.

8. The large dynamic range pixel structure with adaptive reset according to claim 7, characterized in that: The signal processing process of the pixel unit includes: When the result of the difference between the reset voltage and the signal voltage output by the pixel in the previous frame after the CDS circuit is greater than the set threshold value Vref, the output column feedback signal FS of the first comparator is high level. During the high level period of the clock signal LATCH, the column feedback signal FS is latched in the latch and keeps the latched result until the next high level arrives; when the reset signal RST is pulled high, the second AND gate outputs a high level, the reset tube in the pixel is turned on, and the transmission tube is turned on at the same time to reset the photodiode and the charge storage capacitor. After the reset is completed, the transmission tube is turned off, the reset signal RST is pulled low, and then the exposure stage is entered; after the exposure is completed, the signal transfer stage is entered, firstly, the reset signal RST and the first switch signal S1 are pulled high, the first AND gate and the second AND gate both output high level, control the reset tube and the first switch to turn on, and reset the charge storage capacitor and the first capacitor; after the reset, the reset signal RST and the first switch signal S1 are pulled low, and the reset voltage is stored in the first capacitor; then the transmission signal TX is pulled high, and the transmission signal TX is turned on. The transmission tube is turned on, and the charge accumulated by the photodiode during the exposure period is transferred to the charge storage capacitor. After the transfer is completed, the transmission signal TX is pulled low, and the signal voltage is stored in the charge storage capacitor, and then the readout stage is entered; during the readout period, the row selection signal SEL is pulled high, the row selection tube is turned on, and the pixel is connected to the column bus Vpix. First, the second switch signal S2 is pulled high, the second switch and the fourth switch are turned on, and the reset voltage stored in the first capacitor is read out to the second capacitor; then the third switch signal S3 is pulled high, the third switch and the fifth switch are turned on, and the signal voltage stored in the charge storage capacitor is read out to the third capacitor; then the CDS circuit in the column readout unit makes a difference between the reset voltage stored in the second capacitor and the signal voltage stored in the third capacitor, and the result after the difference is compared with the set threshold value Vref, and the comparison result FS is fed back to the pixel to control the reset of the next frame; at the same time, the result after the difference is compared with the ramp signal Vramp generated by the ramp generator through the second comparator, and quantized by the counter; When the result of the difference between the reset voltage and the signal voltage output by the pixel of the previous frame after the CDS circuit is less than the set threshold value Vref, the column feedback signal FS is at a low level. During the high level period of the clock signal LATCH, the column feedback signal FS is latched in the latch, and the latch output is at a low level. When the reset signal RST is pulled high, the output of the second AND gate still remains at a low level, the charge storage capacitor is not reset, and the signal voltage of the previous frame is still stored, and exposure continues. After the exposure is completed, the reset signal RST and the first switch signal S1 are pulled high. Since the output of the latch is at a low level, the outputs of the first and second AND gates still remain at a low level, and the reset tube and the first switch signal S1 are pulled high. A switch will not be turned on, the reset voltage stored in the first capacitor will not be refreshed, and then the transmission signal TX will be pulled high, and the charge accumulated by the photodiode during the exposure period will continue to be transferred to the charge storage capacitor. After the transfer is completed, it enters the readout stage; signal readout: first read the reset voltage and then read the signal voltage. After being stored in the second capacitor and the third capacitor respectively, they are subtracted through the CDS circuit. The result after the subtraction is compared with the reference voltage Vref in the first comparator, and the comparison result FS is fed back to the pixel to control the reset of the next frame; at the same time, the result after the subtraction is compared with the ramp signal Vramp generated by the ramp generator through the second comparator and quantized by the counter.

9. An image sensor, characterized in that A large dynamic range pixel structure with adaptive reset comprising any one of claims 1-8.

10. An electronic device, characterized in that Comprising the image sensor as claimed in claim 9.

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