Semiconductor device and preparation method thereof, electronic chip, memory and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, an electronic chip, a memory and electronic equipment, which not only reduce the area of the semiconductor device and realize higher capacity density of the memory, but also improve the conduction performance of a transistor, thereby improving the read-write speed of the memory under the condition of smaller current. The semiconductor device may include a capacitor and a transistor. The capacitor may include a first electrode. The transistor may include a third electrode, a fourth electrode, and a channel layer. The capacitor and the transistor share the second electrode. The second electrode, the third electrode and the fourth electrode are stacked in the first direction, the first electrode and the second electrode are stacked in the first direction, the first electrode is located on the surface, away from the third electrode, of the second electrode, or the first electrode is located in the second electrode. The semiconductor device further comprises a first through hole, the first through hole penetrates through the first electrode, the second electrode, the third electrode and the fourth electrode, and the channel layer is arranged in the first through hole in the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same, an electronic chip, a memory, and an electronic device. Background Art

[0002] With the rapid development of electronic devices such as computers and mobile phones, memories such as dynamic random access memory (DRAM) used in electronic devices have been widely used. Since the increase in memory capacity is limited by its structure, in order to increase the capacity of the memory, the structure of the memory needs to be improved.

[0003] The memory provided by the related art may include an electronic chip, and the electronic chip may include a plurality of semiconductor devices. Each semiconductor device may be a 1T1C structure including a transistor and a capacitor. Among them, the capacitor may include a first electrode (which may be used as a negative electrode), a capacitor dielectric layer, and a second electrode (which may be used as a positive electrode) arranged in a stacked manner. The transistor may include a second electrode (which may be used as a source electrode), a third electrode (which may be used as a gate electrode), and a fourth electrode (which may be used as a drain electrode) arranged in a stacked manner. It can be considered that the capacitor and the transistor share the second electrode. The transistor may also include a channel layer in contact with the source and the drain electrode. In other words, the transistor and the capacitor may be stacked. The projections of the transistor and the capacitor on the same plane overlap, and the area of ​​the semiconductor device is not increased additionally, thereby achieving a higher capacity density of the memory. However, due to the small contact area between the channel layer of the transistor and the second electrode and the fourth electrode, the conduction performance of the transistor is poor, which in turn causes the memory to have a slow reading and writing speed when the current is small.

[0004] Therefore, there is an urgent need for a technical solution that can improve the reading and writing speed of the memory. Summary of the invention

[0005] The present application provides a semiconductor device and a method for preparing the same, an electronic chip, a memory and an electronic device, which not only reduces the area of ​​the semiconductor device and achieves a higher capacity density of the memory, but also improves the conduction performance of the transistor, thereby increasing the read and write speed of the memory under low current conditions.

[0006] In a first aspect, the present application provides a semiconductor device that may include a capacitor and a transistor.

[0007] Wherein, the capacitor may include a first electrode. The transistor may include a third electrode, a fourth electrode and a channel layer. The capacitor and the transistor share a second electrode. It can be understood that the capacitor includes a first electrode and a second electrode. The transistor may include a second electrode, a third electrode, a fourth electrode and a channel layer.

[0008] Optionally, the second electrode, the third electrode and the fourth electrode may be stacked along the first direction.

[0009] In one example, the first electrode and the second electrode can be stacked along the first direction, and the first electrode can be located on a surface of the second electrode away from the third electrode. That is, the first electrode, the second electrode, the third electrode and the fourth electrode can be stacked along the first direction, which can reduce the area of ​​the semiconductor device in a direction perpendicular to the first direction.

[0010] In another example, the first electrode may be located inside the second electrode. It can be understood that the second electrode, the third electrode and the fourth electrode are stacked along the first direction, and the first electrode may also be stacked with the third electrode and the fourth electrode along the first direction. It can be seen that the first electrode is located inside the second electrode, which can reduce the size of the semiconductor device in the first direction.

[0011] Further, the semiconductor device may further include a first through hole. The first through hole may penetrate the first electrode, the second electrode, the third electrode and the fourth electrode. That is, the axial direction of the first through hole may be the same as the first direction. The channel layer may be arranged inside the first through hole along the first direction. That is, the thickness direction of the channel layer may be perpendicular to the first direction.

[0012] In the semiconductor device provided by the present application, the transistor and the capacitor can be stacked, thereby reducing the area of ​​the semiconductor device. Moreover, since the second electrode, the third electrode and the fourth electrode are stacked along the first direction, the first through hole can penetrate the first electrode, the second electrode, the third electrode and the fourth electrode, and the channel layer can be arranged inside the first through hole along the first direction, thereby increasing the contact area between the second electrode and the fourth electrode and the channel layer, thereby improving the conduction performance of the transistor, and further improving the reliability of the semiconductor device.

[0013] Exemplarily, the first electrode can be used as the positive terminal of the capacitor, and the second electrode can be used as the negative terminal of the capacitor. Alternatively, the first electrode can be used as the negative terminal of the capacitor, and the second electrode can be used as the positive terminal of the capacitor. At the same time, the second electrode can also be used as the source or drain of the transistor. Thus, the third electrode can be used as the gate of the transistor, and the fourth electrode can be used as the drain or source of the transistor.

[0014] Optionally, the doping concentration of part or all of the channel layer may be greater than or equal to 10 19 / cm 3, which can increase the overlapping area between the second electrode and the plate line PL, thereby increasing the capacitance of the capacitor, and can also reduce the contact resistance between the second electrode and the fourth electrode.

[0015] In a possible implementation, the transistor may further include a first dielectric layer. The first dielectric layer may be located between the third electrode and the channel layer. It is conceivable that since the third electrode may be used as a gate of the transistor, the first dielectric layer may be called a gate dielectric layer. It can be seen that the first dielectric layer serves to isolate the third electrode from the channel layer.

[0016] In another possible implementation manner, the capacitor may further include a second dielectric layer.

[0017] In one example, the second dielectric layer may be located between the first electrode and the second electrode. It can be understood that the first electrode, the second dielectric layer and the second electrode are stacked along the first direction. It can be seen that the second dielectric layer plays a role in isolating the first electrode from the second electrode, and therefore, the second dielectric layer can be called a capacitor dielectric layer.

[0018] In another example, the first portion of the second dielectric layer may be located between the first electrode and the second electrode, and the second portion of the second dielectric layer may be located between the first electrode and the channel layer. It can be understood that the second dielectric layer may be L-shaped. The first portion may be located between the first electrode and the second electrode, and the second portion may be located between the first electrode and the channel layer. It can be seen that the second dielectric layer not only serves to isolate the first electrode from the second electrode, but also serves to isolate the first electrode from the channel layer. Therefore, the second dielectric layer may be called a capacitor dielectric layer.

[0019] In yet another possible implementation, the transistor may further include a first insulating layer and a second insulating layer.

[0020] The first insulating layer may be located between the second electrode and the third electrode to isolate the second electrode from the third electrode. The second insulating layer may be located between the third electrode and the fourth electrode to isolate the third electrode from the fourth electrode.

[0021] Optionally, the semiconductor device may further include a third insulating layer. The third insulating layer may be located inside the first through hole. The third insulating layer may be located on the first surface of the channel layer, and the first electrode, the second electrode, the third electrode and the fourth electrode may all be located on the second surface of the channel layer. The first surface and the second surface are arranged opposite to each other.

[0022] That is, the channel layer and the third insulating layer may be located inside the first through hole, and the channel layer may include a first surface and a second surface disposed opposite to each other. The channel layer may be located between the third insulating layer and the first electrode, the second electrode, the third electrode, and the fourth electrode.

[0023] Exemplarily, the first electrode may be electrically connected to a plate line (PL), the third electrode may be electrically connected to a word line (word line), and the fourth electrode may be electrically connected to a bit line (BL).

[0024] In an example, the word line WL may be perpendicular to the bit line BL, and the word line WL may be parallel to the first direction. The plate line PL may be parallel to the bit line BL.

[0025] For example, the word lines WL and the first direction may be vertical directions, and the bit lines BL and the plate lines PL may be horizontal directions.

[0026] In another example, the word line WL may be perpendicular to the bit line BL, and the bit line BL may be parallel to the first direction. The plate line PL may be parallel to the bit line BL, or may be perpendicular to the bit line BL.

[0027] For example, the word line WL may be in a horizontal direction, the bit line BL and the first direction may be in a vertical direction, and the plate line PL may be in a horizontal direction or a vertical direction.

[0028] Optionally, a first end of the plate line PL may be electrically connected to the first electrode, and a second end of the plate line PL may be electrically connected to a ground terminal GND (ground). Alternatively, a second end of the plate line PL may be used to receive a power supply voltage VSS.

[0029] Optionally, the semiconductor device may further include a first isolation layer. The position of the first isolation layer may satisfy any of the following conditions:

[0030] ① When the word line WL is parallel to the first direction and the bit line BL is perpendicular to the word line WL, the first isolation layer can be located between the word line WL and the fourth electrode. It can be seen that the first isolation layer plays a role in isolating the word line WL from the fourth electrode.

[0031] ② When the bit line BL is parallel to the first direction, the bit line BL is perpendicular to the word line WL, and the plate line PL is perpendicular to the first direction, the first isolation layer can be located on the surface of the fourth electrode away from the channel layer.

[0032] ③ When the bit line BL and the plate line PL are parallel to the first direction and the bit line BL is perpendicular to the word line WL, the first isolation layer can be located between the plate line PL and the fourth electrode. It can be seen that the first isolation layer plays a role in isolating the plate line PL from the fourth electrode.

[0033] Furthermore, the semiconductor device may further include a second isolation layer. The position of the second isolation layer may satisfy any of the following conditions:

[0034] ① When the word line WL is parallel to the first direction and the bit line BL is perpendicular to the word line WL, the second isolation layer can be located between the word line WL and the second electrode. It can be seen that the second isolation layer plays a role in isolating the word line WL from the second electrode.

[0035] ② When the bit line BL is parallel to the first direction, the bit line BL is perpendicular to the word line WL, and the plate line PL is perpendicular to the first direction, the second isolation layer can be located between the bit line BL and the second electrode. It can be seen that the second isolation layer plays a role in isolating the bit line BL from the second electrode.

[0036] ③ When the bit line BL and the plate line PL are parallel to the first direction and the bit line BL is perpendicular to the word line WL, the second isolation layer is located between the bit line BL and the second electrode. It can be seen that the second isolation layer plays a role in isolating the bit line BL from the second electrode.

[0037] Furthermore, the semiconductor device may further include a third isolation layer. The position of the third isolation layer may satisfy any of the following conditions:

[0038] ① When the word line WL is parallel to the first direction and the bit line BL is perpendicular to the word line WL, the third isolation layer may be located on a surface of the third electrode away from the channel layer.

[0039] ② When the bit line BL is parallel to the first direction, the bit line BL is perpendicular to the word line WL, and the plate line PL is perpendicular to the first direction, the third isolation layer can be located between the bit line BL and the third electrode. It can be seen that the third isolation layer plays a role in isolating the bit line BL from the third electrode.

[0040] ③ When the bit line BL and the plate line PL are parallel to the first direction and the bit line BL is perpendicular to the word line WL, the third isolation layer can be located between the bit line BL and the third electrode, and the third isolation layer can also be located between the plate line PL and the third electrode. It can be seen that the third isolation layer not only isolates the bit line BL from the third electrode, but also isolates the plate line PL from the third electrode.

[0041] It can be seen from the positions of the first isolation layer, the second isolation layer and the third isolation layer that the first isolation layer, the second isolation layer and the third isolation layer can be an asymmetric structure in the semiconductor device, so as to reduce the parasitic capacitance between the word line WL and the bit line BL, the parasitic capacitance between the word line WL and the plate line PL, and the parasitic capacitance between the bit line BL and the plate line PL, thereby improving the conduction performance of the transistor and further improving the reliability of the semiconductor device.

[0042] In a second aspect, the present application provides a method for preparing a semiconductor device, which may include: etching a stacked structure to form a first through hole, forming a first electrode, a second electrode, a third electrode and a fourth electrode based on the stacked structure, and forming a channel layer inside the first through hole.

[0043] Optionally, the second electrode, the third electrode and the fourth electrode may be stacked along the first direction.

[0044] In one example, the first electrode and the second electrode may be stacked along the first direction, and the first electrode may be located on a surface of the second electrode away from the third electrode. That is, the first electrode, the second electrode, the third electrode and the fourth electrode may be stacked along the first direction.

[0045] In another example, the first electrode may be located inside the second electrode. It can be understood that the second electrode, the third electrode and the fourth electrode are stacked along the first direction, and the first electrode may also be stacked with the third electrode and the fourth electrode along the first direction.

[0046] Exemplarily, the first through hole may penetrate the first electrode, the second electrode, the third electrode and the fourth electrode. That is, the axial direction of the first through hole may be the same as the first direction. The channel layer may be located inside the first through hole.

[0047] Then, the first electrode and the second electrode may form a capacitor, and the second electrode, the third electrode, the fourth electrode and the channel layer may form a transistor.

[0048] In the method for preparing a semiconductor device provided by the present application, a first electrode and a second electrode formed based on a stacked structure can constitute a capacitor, and a second electrode, a third electrode and a fourth electrode formed based on a stacked structure and a channel layer formed inside a first through hole can form a transistor. It can be seen that the transistor and the capacitor are stacked, which reduces the area of ​​the semiconductor device. Moreover, since the second electrode, the third electrode and the fourth electrode are stacked along the first direction, the first through hole can penetrate the first electrode, the second electrode, the third electrode and the fourth electrode, and the channel layer can be arranged inside the first through hole along the first direction, increasing the contact area between the second electrode and the fourth electrode and the channel layer, thereby improving the conduction performance of the transistor, and then improving the reliability of the semiconductor device.

[0049] In a possible implementation, etching the stacked structure to form the first through hole may include: forming the stacked structure. Etching the stacked structure along a first direction to obtain the first through hole. It can be seen that the axial direction of the first through hole is the same as the first direction.

[0050] The stacked structure may include a first sacrificial layer, a first insulating layer, a second sacrificial layer, a second insulating layer and a third sacrificial layer stacked along a first direction. That is, the first sacrificial layer, the first insulating layer, the second sacrificial layer, the second insulating layer and the third sacrificial layer are stacked along the first direction to form a stacked structure.

[0051] In some possible implementations, the stacked structure may further include a fourth sacrificial layer. The fourth sacrificial layer and the first sacrificial layer may be stacked along the first direction, and the first sacrificial layer may be located between the fourth sacrificial layer and the first insulating layer. That is, the fourth sacrificial layer, the first sacrificial layer, the first insulating layer, the second sacrificial layer, the second insulating layer, and the third sacrificial layer are stacked along the first direction.

[0052] Then, forming the first electrode, the second electrode, the third electrode, and the fourth electrode based on the stacked structure may include:

[0053] The first sacrificial layer is etched along the second direction to form a second electrode inside the obtained second through hole. The second direction may be perpendicular to the first direction. That is, the first sacrificial layer is etched to obtain a second through hole. Then, a second electrode may be formed inside the second through hole.

[0054] The second sacrificial layer is etched along the second direction to form a third electrode inside the obtained third through hole. In other words, the second sacrificial layer is etched to obtain a third through hole. Further, a third electrode can be formed inside the third through hole.

[0055] The third sacrificial layer is etched along the second direction to form a fourth electrode inside the obtained fourth through hole. In other words, the fourth through hole can be obtained by etching the third sacrificial layer, and then the fourth electrode can be formed inside the fourth through hole.

[0056] The fourth sacrificial layer is etched along the second direction to form a first electrode inside the obtained fifth through hole. In other words, the fifth through hole can be obtained by etching the fourth sacrificial layer. Further, the first electrode can be formed inside the fifth through hole.

[0057] In one example, the stacked structure may further include a fifth sacrificial layer. The fifth sacrificial layer may be stacked with the fourth sacrificial layer along the first direction, and the fifth sacrificial layer may be located between the first sacrificial layer and the fourth sacrificial layer. That is, the fourth sacrificial layer, the fifth sacrificial layer, the first sacrificial layer, the first insulating layer, the second sacrificial layer, the second insulating layer, and the third sacrificial layer are stacked along the first direction.

[0058] Therefore, forming the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure may further include: etching the fifth sacrificial layer along the second direction to obtain a sixth through hole, and forming a second dielectric layer inside the sixth through hole.

[0059] The second dielectric layer may be located between the second electrode and the first electrode. It can be seen that the second dielectric layer may play a role in isolating the first electrode from the second electrode.

[0060] In another example, forming the first electrode, the second electrode, the third electrode, and the fourth electrode based on the stacked structure may further include: forming a second dielectric layer inside the fifth through hole. That is, the second dielectric layer may be formed inside the fifth through hole obtained by etching the fourth sacrificial layer. Then, the first electrode is formed inside the fifth through hole. It can be seen that the second dielectric layer may be formed first, and then the first electrode may be formed.

[0061] The first part of the second dielectric layer may be located between the first electrode and the second electrode, and the second part of the second dielectric layer may be located between the first electrode and the channel layer. In other words, the second dielectric layer may be an L-shaped structure consisting of the first part and the second part. The first part may serve to isolate the first electrode from the second electrode, and the second part may serve to isolate the first electrode from the channel layer.

[0062] In some other possible implementations, forming the first electrode, the second electrode, the third electrode, and the fourth electrode based on the stacked structure may include: etching the first sacrificial layer along the second direction to form the second electrode inside the obtained second through hole. The second direction may be perpendicular to the first direction. Etching the second sacrificial layer along the second direction to form the third electrode inside the obtained third through hole. Forming the first electrode inside the second electrode. Etching the third sacrificial layer along the second direction to form the fourth electrode inside the obtained fourth through hole.

[0063] Further, the etching of the first sacrificial layer along the second direction to form the second electrode inside the obtained second through hole may include: etching a portion of the first sacrificial layer along the second direction to obtain the second through hole. The second electrode is formed inside the second through hole. The unetched portion of the first sacrificial layer may serve as a second isolation layer. It can be seen that the first sacrificial layer is not completely etched.

[0064] The etching of the second sacrificial layer along the second direction to form the third electrode in the obtained third through hole may include: etching a portion of the second sacrificial layer along the second direction to obtain three through holes. The third electrode is formed inside the third through hole. The unetched portion of the second sacrificial layer may serve as a third isolation layer. It can be seen that the second sacrificial layer is not completely etched.

[0065] The etching of the third sacrificial layer along the second direction to form the fourth electrode in the obtained fourth through hole may include: etching a portion of the third sacrificial layer along the second direction to form the fourth through hole. The fourth electrode may be formed inside the fourth through hole. The unetched portion of the third sacrificial layer may serve as the first isolation layer. It can be seen that the third sacrificial layer is not completely etched.

[0066] It can be seen from the above process that the first isolation layer, the second isolation layer and the third isolation layer can be an asymmetric structure in the semiconductor device, so as to reduce the parasitic capacitance between the word line WL and the bit line BL, the parasitic capacitance between the word line WL and the plate line PL, and the parasitic capacitance between the bit line BL and the plate line PL, thereby improving the conduction performance of the transistor and further improving the reliability of the semiconductor device.

[0067] Furthermore, forming the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure may further include: forming a second dielectric layer inside the second through hole.

[0068] The second dielectric layer may be located between the second electrode and the first electrode. That is, the second dielectric layer may be formed inside the second through hole formed by etching the first sacrificial layer. Then, the first electrode is formed inside the second through hole. That is, the second dielectric layer may be formed first, and then the first electrode may be formed. It can be seen that the second dielectric layer may play a role in isolating the first electrode from the second electrode.

[0069] Exemplarily, the preparation method provided in the present application may further include: filling the first through hole with an insulating material. It is understandable that the insulating material may be filled in the first through hole after the first through hole is formed.

[0070] Therefore, forming the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure may further include: forming a first dielectric layer inside the third through hole.

[0071] It is understandable that the third through hole can be formed first, then the first dielectric layer can be formed inside the third through hole, and finally the third electrode can be formed inside the third through hole. It can be seen that the first dielectric layer can be located between the third electrode and the insulating material.

[0072] In some possible implementations, the preparation method provided in the present application may further include: filling an insulating material inside the channel layer to form a third insulating layer. It can be seen that the channel layer may be located between the third insulating layer and the second electrode, the third electrode, and the fourth electrode.

[0073] In a third aspect, the present application provides an electronic chip, which may include a word line WL, a bit line BL, a plate line PL and a plurality of semiconductor devices provided by the first aspect and possible implementations thereof.

[0074] The word lines WL, the bit lines BL, and the plate lines PL are all electrically connected to each semiconductor device in the plurality of semiconductor devices.

[0075] In a fourth aspect, the present application provides a memory, which may include a circuit board and the electronic chip provided in the third aspect. The electronic chip may be arranged on the circuit board.

[0076] Exemplarily, the memory may be a dynamic random access memory (DRAM) or the like, which is not limited in the embodiments of the present application.

[0077] In a fifth aspect, the present application provides an electronic device, which may include a power supply and the memory provided in the fourth aspect. The power supply may be electrically connected to the memory to supply power to the memory.

[0078] Exemplarily, the electronic device may be a computer, a mobile phone, a smart speaker, etc., which is not limited in this application.

[0079] It should be understood that the second to fifth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0081] Figure 1 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0082] Figure 2 is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0083] Figure 3 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0084] Figure 4 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0085] Figure 5 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0086] Figure 6is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0087] Figure 7 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0088] Figure 8 is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0089] Fig. 9 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0090] Fig.10 is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0091] Fig.11 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0092] Fig.12 is a schematic flow chart of the preparation process 200 in an embodiment of the present application;

[0093] Fig.13a is a schematic structural diagram of a stacked structure H in an embodiment of the present application;

[0094] Fig.13b is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0095] Fig.14a is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0096] Fig.14b is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0097] Fig.14c is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0098] Fig.14d is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0099] Fig.15 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0100] Fig.16a is a schematic structural diagram of a stacked structure H in an embodiment of the present application;

[0101] Fig.16b is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0102] Fig.17a is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0103] Fig.17b is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0104] Fig.17c is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0105] Fig.17d is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0106] Fig.18 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0107] Fig.19a is a schematic structural diagram of a stacked structure H in an embodiment of the present application;

[0108] Fig.19b is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0109] Fig.20a is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0110] Fig.20b is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0111] Fig.20c is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0112] Fig.20d is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0113] Fig.21 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0114] Fig. 22 is a schematic structural diagram of an electronic chip 300 in an embodiment of the present application;

[0115] Fig.23 is another schematic structural diagram of the electronic chip 300 in the embodiment of the present application;

[0116] Fig.24 is another schematic structural diagram of the electronic chip 300 in the embodiment of the present application;

[0117] Fig.25 is another schematic structural diagram of the electronic chip 300 in the embodiment of the present application;

[0118] Fig.26 is another schematic structural diagram of the electronic chip 300 in the embodiment of the present application;

[0119] In the figure, 100-semiconductor device, 200-preparation process, 300-electronic chip, F1-first through hole, 1-first electrode, 2-second electrode, 3-third electrode, 4-fourth electrode, 5-channel layer, 6-first dielectric layer, 7-second dielectric layer, 8-first insulating layer, 9-second insulating layer, 10-third insulating layer, 11-first isolation layer, 12-second isolation layer, 13-third isolation layer, H11-first sacrificial layer, H12-second sacrificial layer, H13-third sacrificial layer, H14-fourth sacrificial layer, H15-fifth sacrificial layer. DETAILED DESCRIPTION

[0120] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0121] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0122] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0123] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0124] With the rapid development of electronic devices such as computers and mobile phones, memories such as dynamic random access memory (DRAM) used in electronic devices have been widely used. Since the increase in memory capacity is limited by its structure, in order to increase the capacity of the memory, the structure of the memory needs to be improved.

[0125] The memory provided by the related art may include an electronic chip, and the electronic chip may include a plurality of semiconductor devices. Each semiconductor device may be a 1T1C structure including a transistor and a capacitor. Among them, the capacitor may include a first electrode (which may be used as a negative electrode), a capacitor dielectric layer, and a second electrode (which may be used as a positive electrode) arranged in a stacked manner. The transistor may include a second electrode (which may be used as a source electrode), a third electrode (which may be used as a gate electrode), and a fourth electrode (which may be used as a drain electrode) arranged in a stacked manner. It can be considered that the capacitor and the transistor share the second electrode. The transistor may also include a channel layer in contact with the source and the drain electrode. In other words, the transistor and the capacitor may be stacked. The projections of the transistor and the capacitor on the same plane overlap, and the area of ​​the semiconductor device is not increased additionally, thereby achieving a higher capacity density of the memory. However, due to the small contact area between the channel layer of the transistor and the second electrode and the fourth electrode, the conduction performance of the transistor is poor, which in turn causes the memory to have a slow reading and writing speed when the current is small.

[0126] In order to overcome the above-mentioned shortcomings, the present application provides a semiconductor device, such as Figures 1 to 3 As shown. The semiconductor device 100 may include a capacitor C( Figures 1 to 3 Not shown) and transistor T( Figures 1 to 3The transistor T may be a vertical gate all around field effect transistor (GAA FET) or other vertical field effect transistors (VFET). The present application embodiment takes GAA FET as an example for introduction.

[0127] The capacitor C may include a first electrode 1. The transistor T may include a third electrode 3, a fourth electrode 4, and a channel layer 5. The capacitor C and the transistor T share a second electrode 2. It can be understood that the capacitor C includes a first electrode 1 and a second electrode 2. The transistor T may include a second electrode 2, a third electrode 3, a fourth electrode 4, and a channel layer 5.

[0128] Optionally, the second electrode 2, the third electrode 3 and the fourth electrode 4 may be stacked along the first direction. Figures 1 to 3 , the first direction may be a vertical direction. That is to say, the second electrode 2, the third electrode 3 and the fourth electrode 4 may be stacked in the vertical direction.

[0129] In one example, if Figure 1 and Figure 2 As shown, the first electrode 1 and the second electrode 2 can be stacked along the first direction, and the first electrode 1 can be located on the surface of the second electrode 2 away from the third electrode 3. Figure 1 and Figure 2 , it can be understood that the first electrode 1 can be located on the lower surface of the second electrode 2. It can be seen that the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 can be stacked in the vertical direction, which can reduce the area of ​​the semiconductor device 100 in the horizontal direction.

[0130] In another example, if Figure 3 As shown, the first electrode 1 can be located inside the second electrode 2. It can be understood that the second electrode 2, the third electrode 3 and the fourth electrode 4 can be stacked in the vertical direction, and the first electrode 1 can also be stacked with the third electrode 3 and the fourth electrode 4 in the vertical direction. It can be seen that the first electrode 1 is located inside the second electrode 2, which can reduce the size of the semiconductor device 100 in the vertical direction.

[0131] Furthermore, if Figures 4 to 6 As shown, the semiconductor device 100 may further include a first through hole F1. The first through hole F1 may penetrate the first electrode 1, the second electrode 2, the third electrode 3, and the fourth electrode 4. In other words, the axial direction of the first through hole F1 may be the same as the first direction, that is, the axial direction of the first through hole F1 may be a vertical direction. Of course, the axial direction of the first through hole F1 may also have a certain angle with the vertical direction, which is not limited in the embodiment of the present application.

[0132] Alternatively, if Figures 1 to 3 As shown, the channel layer 5 can be disposed in the first through hole F1 ( Figures 1 to 3 Not marked, please refer to Figures 4 to 7 ) internally. Specifically, refer to Figure 1 , the channel layer 5 can be disposed in the first through hole F1 ( Figure 1 Not marked, please refer to Figure 4 ) internal. Reference Figure 2 , the channel layer 5 can be disposed in the first through hole F1 ( Figure 2 Not marked, please refer to Figure 5 ) internal. Reference Figure 3 , the channel layer 5 can be disposed in the first through hole F1 ( Figure 3 Not marked, please refer to Figure 6 )internal.

[0133] from Figures 1 to 3 It can be seen that the thickness direction of the channel layer 5 may be perpendicular to the vertical direction. In other words, the thickness direction of the channel layer 5 may be a horizontal direction, and the channel layer 5 may contact the inner wall of the first through hole F1.

[0134] In the semiconductor device 100 provided in the embodiment of the present application, the transistor T and the capacitor C can be stacked, thereby reducing the area of ​​the semiconductor device 100. Moreover, since the second electrode 2, the third electrode 3 and the fourth electrode 4 are stacked along the first direction, the first through hole F1 can penetrate the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4, and the channel layer 5 can be arranged inside the first through hole F1 along the first direction, thereby increasing the contact area between the second electrode 2 and the fourth electrode 4 and the channel layer 5, thereby improving the conduction performance of the transistor T, and further improving the reliability of the semiconductor device 100. At the same time, since the first electrode 1 can be located inside the second electrode 2, the height of the semiconductor device 100 can be reduced, which is conducive to the miniaturization design of the semiconductor device 100.

[0135] Exemplarily, the first electrode 1 can be used as the positive terminal of the capacitor C, and the second electrode 2 can be used as the negative terminal of the capacitor C. Alternatively, the first electrode 1 can be used as the negative terminal of the capacitor C, and the second electrode 2 can be used as the positive terminal of the capacitor C. At the same time, the second electrode 2 can also be used as the source or drain of the transistor T. Therefore, the third electrode 3 can be used as the gate of the transistor T, and the fourth electrode 4 can be used as the drain or source of the transistor T.

[0136] Optionally, the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 can all be made of conductive materials such as tungsten W. Of course, the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 can also be made of other materials, which is not limited in the embodiment of the present application.

[0137] Further, a conductive layer may be provided on the outer surfaces of the first electrode 1, the second electrode 2, the third electrode 3, and the fourth electrode 4. The conductive layer may be made of a metal material, a conductive metal oxide material such as indium tin oxide InSnO, or a conductive metal nitride such as titanium nitride TiN. Of course, the conductive layer may also be other conductive materials, which is not limited in the embodiments of the present application.

[0138] In one example, the thickness of the channel layer 5 may be 0.1 nm to 10 nm. Of course, the channel layer 5 may also be of other thicknesses, which are not limited in the present embodiment.

[0139] In another example, the channel layer 5 may be a thin film structure, and may be made of oxide semiconductor materials such as zinc gallium indium oxide InGaZnO, zinc gallium aluminum oxide InAlZnO, indium tungsten oxide InWO, or silicon materials such as amorphous silicon and polycrystalline silicon. Of course, the channel layer 5 may also be made of other materials, which is not limited in the present embodiment.

[0140] In another example, the doping concentration of part or all of the channel layer 5 may be greater than or equal to 10 19 / cm 3 That is to say, the doping concentration of the channel layer 5 is relatively high, which can increase the overlapping area of ​​the second electrode 2 and the plate line PL, thereby increasing the capacity of the capacitor C, and can also reduce the contact resistance between the second electrode and the fourth electrode.

[0141] In some embodiments, Figures 1 to 6 As shown, the transistor T may further include a first dielectric layer 6. The first dielectric layer 6 may be located between the third electrode 3 and the channel layer 5. It is conceivable that, since the third electrode 3 may be used as the gate of the transistor T, the first dielectric layer 6 may be called a gate dielectric layer. It can be seen that the first dielectric layer 6 serves to isolate the third electrode 3 from the channel layer 5.

[0142] Of course, reference Figures 1 to 3 , the first dielectric layer 6 can also be located on the surface of the third electrode 3 away from the second electrode 2. That is, the first dielectric layer 6 can also be located on the upper surface of the third electrode 3. The first dielectric layer 6 can also be located on the surface of the third electrode 3 away from the fourth electrode 4. That is, the first dielectric layer 6 can also be located on the lower surface of the third electrode 3. Therefore, it can be understood that the first dielectric layer 6 can include a first part, a second part and a third part. The first part can be located between the third electrode 3 and the channel layer 5, the second part can be located on the upper surface of the third electrode 3 (it can also be said to be located between the third electrode 3 and the fourth electrode 4), and the third part can be located on the lower surface of the third electrode 3 (it can also be said to be located between the third electrode 3 and the second electrode 2).

[0143] Optionally, the first dielectric layer 6 may be made of any material such as aluminum oxide AlO, hafnium oxide HfO, silicon nitride SiN, etc. Of course, the first dielectric layer 6 may also be made of other single materials or mixed materials, which is not limited in the embodiment of the present application.

[0144] In other examples, such as Figures 1 to 3 As shown, the capacitor C may further include a second dielectric layer 7 .

[0145] In one example, if Figure 1 As shown, the second dielectric layer 7 can be located between the first electrode 1 and the second electrode 2. It can be understood that the first electrode 1, the second dielectric layer 7 and the second electrode 2 are stacked in a vertical direction. It can be seen that the second dielectric layer 7 plays a role in isolating the first electrode 1 and the second electrode 2.

[0146] In another example, if Figure 2 As shown, the second dielectric layer 7 may include a first portion and a second portion. The first portion may be located between the first electrode 1 and the second electrode 2, and the second portion may be located between the first electrode 1 and the channel layer 5. It can be understood that the second dielectric layer 7 may be L-shaped. It can be seen that the second dielectric layer 7 not only serves to isolate the first electrode 1 from the second electrode 2, but also serves to isolate the first electrode 1 from the channel layer 5.

[0147] In another example, Figure 3 As shown, the first dielectric layer 7 may include a first portion, a second portion and a third portion. The first portion may be located between the first electrode 1 and the second electrode 2, and the first portion is located on the surface of the first electrode 1 close to the third electrode 3. The second portion may be located between the first electrode 1 and the channel layer 5. The third portion may also be located between the first electrode 1 and the second electrode 2, and the third portion is located on the surface of the first electrode 1 away from the third electrode 3. It can be seen that the second dielectric layer 7 not only serves to isolate the first electrode 1 from the second electrode 2, but also serves to isolate the first electrode 1 from the channel layer 5.

[0148] In the above three embodiments, the second dielectric layer 7 plays the role of isolating the first electrode 1 from the second electrode 2 , and therefore, the second dielectric layer 7 can be called a capacitor dielectric layer.

[0149] Optionally, the second dielectric layer 7 may be made of materials such as aluminum oxide AlO or zirconium oxide ZrO2. Of course, the second dielectric layer 7 may also be made of other materials, which is not limited in the embodiment of the present application.

[0150] In one possible implementation, reference Figures 1 to 3 The transistor T may further include a first insulating layer 8 and a second insulating layer 9 .

[0151] The first insulating layer 8 may be located between the second electrode 2 and the third electrode 3 to isolate the second electrode 2 from the third electrode 3. The second insulating layer 9 may be located between the third electrode 3 and the fourth electrode 4 to isolate the third electrode 3 from the fourth electrode 4.

[0152] In another possible implementation, continue to refer to Figures 1 to 3 , the semiconductor device 100 may further include a third insulating layer 10. The third insulating layer 10 may be located inside the first through hole F1. The third insulating layer 10 may be located on the first surface of the channel layer 5. The first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 may all be located on the second surface of the channel layer 5. Among them, the first surface and the second surface are arranged oppositely. That is, the channel layer 5 and the third insulating layer 10 may be located inside the first through hole F1, and the channel layer 5 may include a first surface (i.e., a surface close to the third insulating layer 10) and a second surface (i.e., a surface close to the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4) arranged oppositely. The channel layer 5 may be located between the third insulating layer 10 and the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4.

[0153] Optionally, the first insulating layer 8, the second insulating layer 9 and the third insulating layer 10 can all be made of silicon oxide SiO, silicon nitride SiN, silicon oxygen carbon SiOC, silicon carbon nitride SiCN, etc. Of course, the first insulating layer 8, the second insulating layer 9 and the third insulating layer 10 can also be made of other materials, which is not limited in the embodiment of the present application.

[0154] In one example, if Figure 7 As shown, the word line (word line) can be perpendicular to the bit line (bit line, BL), and the word line WL can be parallel to the first direction. The plate line (plate line, PL) can be parallel to the bit line BL. That is, in the embodiment of the present application, the word line WL can be in a vertical direction, the plate line PL and the bit line BL can be in a horizontal direction, and the plate line PL can be parallel to the bit line BL. Of course, the plate line PL can also be parallel to the word line WL, which is not limited in the embodiment of the present application.

[0155] In another example, Figure 8 As shown, the word line WL may be perpendicular to the bit line BL, and the bit line BL may be parallel to the first direction. The plate line PL may be perpendicular to the bit line BL. That is, in the embodiment of the present application, the bit line BL may be in a vertical direction, and the plate line PL and the bit line WL may be in a horizontal direction. Of course, the plate line PL may also be parallel to the bit line BL, which is not limited in the embodiment of the present application.

[0156] Optionally, the first electrode 1 (ie, the lower electrode of the capacitor C, Figure 7 and Figure 8The third electrode 3 (i.e., the gate of the transistor T) can be electrically connected to the plate line PL. Figure 7 and Figure 8 The fourth electrode 4 (ie, the drain or source of the transistor T) may be electrically connected to the word line WL. Figure 7 and Figure 8 (not shown) may be electrically connected to the bit line BL. Figure 7 and Figure 8 The second electrode 2 (serving as the upper electrode of the capacitor C and the source or drain of the transistor T) is not marked.

[0157] It can be seen that Figure 7 The semiconductor device 100 shown may be a semiconductor device based on vertical word lines WL and horizontal bit lines BL. Figure 8 The semiconductor device 100 shown may be a semiconductor device based on vertical bit lines BL and horizontal word lines WL.

[0158] Optionally, Figure 7 and Figure 8 In the embodiment, the first end of the plate line PL may be electrically connected to the first electrode 1, and the second end of the plate line PL may be electrically connected to the ground terminal GND (ground). Alternatively, the second end of the plate line PL may be used to receive the power supply voltage VSS.

[0159] Below is a diagram of the Figure 3 Taking the semiconductor device 100 shown as an example, the first isolation layer, the second isolation layer and the third isolation layer in the semiconductor device 100 provided in the embodiment of the present application are introduced.

[0160] In one example, if Figures 9 to 11 As shown, the semiconductor device 100 may further include a first isolation layer 11. The position of the first isolation layer 11 may satisfy any of the following conditions:

[0161] ① When the word line WL is in a vertical direction and the bit line BL is in a horizontal direction (ie, the word line WL is parallel to the first direction and the bit line BL is perpendicular to the word line WL), the first isolation layer 11 may be located between the word line WL and the fourth electrode 4, such as Fig. 9 As shown, it can be seen that the first isolation layer 11 plays a role in isolating the word line WL from the fourth electrode 4 .

[0162] ② When the bit line BL is in a vertical direction and the plate line PL and the word line WL are in a horizontal direction (i.e., the bit line BL is parallel to the first direction, the bit line BL is perpendicular to the word line WL, and the plate line PL is perpendicular to the first direction), the first isolation layer 11 can be located on the surface of the fourth electrode 4 away from the channel layer 5, such as Fig.10 shown.

[0163] ③ When the bit line BL and the plate line PL are both in the vertical direction and the word line WL is in the horizontal direction (that is, the bit line BL and the plate line PL are parallel to the first direction and the bit line BL is perpendicular to the word line WL), the first isolation layer 11 can be located between the plate line PL and the fourth electrode 4, such as Fig.11 It can be seen that the first isolation layer 11 plays a role in isolating the plate line PL from the fourth electrode 4 .

[0164] Optionally, the first isolation layer 11 may be made of silicon oxide SiO, silicon nitride SiN, silicon oxycarbon SiOC, aluminum oxide AlO, etc. Of course, the first isolation layer 11 may also be made of other materials, which is not limited in the embodiment of the present application.

[0165] In another example, reference Figures 9 to 11 , the semiconductor device 100 may further include a second isolation layer 12. The position of the second isolation layer 12 may satisfy any of the following conditions:

[0166] ① When the word line WL is in a vertical direction and the bit line BL is in a horizontal direction, the second isolation layer 12 may be located between the word line WL and the second electrode 2, such as Fig. 9 As shown, it can be seen that the second isolation layer 12 plays a role in isolating the word line WL from the second electrode 2 .

[0167] ② When the bit line BL is in a vertical direction and the plate line PL and the word line WL are in a horizontal direction, the second isolation layer 12 can be located between the bit line BL and the second electrode 2, such as Fig.10 As shown, it can be seen that the second isolation layer 12 plays a role in isolating the bit line BL from the second electrode 2 .

[0168] ③ In the case where the bit line BL and the plate line PL are both in the vertical direction and the word line WL is in the horizontal direction, the second isolation layer 12 may also be located between the bit line BL and the second electrode 2, such as Fig.11 As shown, it can be seen that the second isolation layer 12 plays a role in isolating the bit line BL from the second electrode 2 .

[0169] In yet another example, reference Figures 9 to 11 , the semiconductor device 100 may further include a third isolation layer 13. The position of the third isolation layer 13 may satisfy any of the following conditions:

[0170] ① When the word line WL is in a vertical direction and the bit line BL is in a horizontal direction, the third isolation layer 13 can be located on the surface of the third electrode 3 away from the channel layer 5, such as Fig. 9 shown.

[0171] ② When the bit line BL is in a vertical direction and the plate line PL and the word line WL are in a horizontal direction, the third isolation layer 13 can be located between the bit line BL and the third electrode 3, such as Fig.10As shown, it can be seen that the third isolation layer 13 plays a role in isolating the bit line BL from the third electrode 3 .

[0172] ③ When the bit line BL and the plate line PL are both in the vertical direction and the word line WL is in the horizontal direction, the third isolation layer 13 can be located between the bit line BL and the third electrode 3, or between the plate line PL and the third electrode 3. Fig.11 It can be seen that the third isolation layer 13 not only plays a role in isolating the bit line BL from the third electrode 3 , but also plays a role in isolating the plate line PL from the third electrode 3 .

[0173] from Figures 9 to 11 From the positions of the first isolation layer 11, the second isolation layer 12 and the third isolation layer 13, it can be seen that the first isolation layer 11, the second isolation layer 12 and the third isolation layer 13 in the semiconductor device 100 can be an asymmetric structure, which can reduce the parasitic capacitance between the word line WL and the bit line BL, the parasitic capacitance between the word line WL and the plate line PL, and the parasitic capacitance between the bit line BL and the plate line PL, thereby improving the conduction performance of the transistor 100, and further improving the reliability of the semiconductor device 100.

[0174] The present application also provides a method for preparing a semiconductor device, which can be used to prepare Figures 1 to 3 The semiconductor device 100 is shown. Fig.12 As shown, the preparation process 200 may include the following steps:

[0175] Step S201: etching the stacked structure H to form the first through hole F1. That is, the stacked structure H may be formed, and then the stacked structure H may be etched to form the first through hole F1.

[0176] Step S202 : Based on the stacked structure H, a first electrode 1 , a second electrode 2 , a third electrode 3 and a fourth electrode 4 are formed.

[0177] The second electrode 2, the third electrode 3 and the fourth electrode 4 may be stacked along a first direction (which may be a vertical direction), such as Figures 1 to 3 shown.

[0178] In one example, the first electrode 1 and the second electrode 2 may be stacked in a vertical direction, and the first electrode 1 may be located on a surface of the second electrode 2 away from the third electrode 3. That is, the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 may be stacked in a vertical direction, such as Figure 1 and Figure 2 shown.

[0179] In another example, the first electrode 1 may be located inside the second electrode 2. It can be understood that the second electrode 2, the third electrode 3 and the fourth electrode 4 are stacked in the vertical direction, and the first electrode 1 may also be stacked with the third electrode 3 and the fourth electrode 4 in the vertical direction. Figure 3 shown.

[0180] For example, Figures 4 to 6 As shown, the first through hole F1 may penetrate the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4. That is, the axial direction of the first through hole F1 may be a vertical direction, that is, the same as the first direction.

[0181] Step S203: forming a channel layer 5 inside the first through hole F1, such as Figures 1 to 3 shown.

[0182] then, Figures 1 to 3 The first electrode 1 and the second electrode 2 in the transistor 1 may form a capacitor C, and the second electrode 2 , the third electrode 3 , the fourth electrode 4 and the channel layer 5 may form a transistor T.

[0183] In the method for preparing the semiconductor device 100 provided in the embodiment of the present application, the first electrode 1 and the second electrode 2 formed based on the stacked structure H can constitute a capacitor C, and the second electrode 2, the third electrode 3 and the fourth electrode 4 formed based on the stacked structure H and the channel layer 5 formed inside the first through hole F1 can form a transistor T. It can be seen that the transistor T and the capacitor C are stacked, which reduces the area of ​​the semiconductor device 100. Moreover, since the second electrode 2, the third electrode 3 and the fourth electrode 4 are stacked in the vertical direction, the first through hole F1 can penetrate the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4, and the channel layer 5 can be arranged inside the first through hole F1 in the vertical direction, which increases the contact area between the second electrode 2 and the fourth electrode 4 and the channel layer 5, thereby improving the conduction performance of the transistor T, and further improving the reliability of the semiconductor device 100.

[0184] Furthermore, the preparation process provided in the embodiment of the present application can also fill the channel layer 5 with insulating material to form a third insulating layer 10, such as Figures 1 to 3 shown.

[0185] In a possible implementation, in the above step S201, etching the stacked structure H to form the first through hole F1 may include:

[0186] Step S201a1: forming a stacked structure H, such as Fig.13a shown.

[0187] The stacked structure H may include a fourth sacrificial layer H14, a fifth sacrificial layer H15, a first sacrificial layer H11, a first insulating layer 8, a second sacrificial layer H12, a second insulating layer 9, and a third sacrificial layer H13 stacked in a vertical direction. That is, the fourth sacrificial layer H14, the fifth sacrificial layer H15, the first sacrificial layer H11, the first insulating layer 6, the second sacrificial layer H12, the second insulating layer 9, and the third sacrificial layer H13 may be stacked in a vertical direction to form a stacked structure H.

[0188] Optionally, the first sacrificial layer H11, the second sacrificial layer H12, the third sacrificial layer H13, the fourth sacrificial layer H14, and the fifth sacrificial layer H15 may be made of materials such as silicon nitride SiN, silicon oxygen carbon SiOC, carbon C, and zinc gallium indium oxide InGaZnO. Of course, the first sacrificial layer H11, the second sacrificial layer H12, the third sacrificial layer H13, the fourth sacrificial layer H14, and the fifth sacrificial layer H15 may also be made of other materials, which are not limited in the embodiments of the present application.

[0189] Step S201b1: Etching the stacked structure H along the vertical direction to obtain a first through hole F1, such as Fig.13b shown.

[0190] Further, in Fig.13b On the basis of, in the above step S202, forming the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 based on the stacked structure H may include:

[0191] Step S202a1: Fill the first through hole F1 with insulating material, and etch the first sacrificial layer H11 along the horizontal direction to form a second electrode 2 inside the obtained second through hole. Fig.14a shown.

[0192] Step S202b1: Etch the fifth sacrificial layer H15 along the horizontal direction to obtain a sixth through hole. A second dielectric layer 7 is formed inside the sixth through hole, such as Fig.14b shown.

[0193] Step S202c1: Etching the second sacrificial layer H12 along the horizontal direction to form a first dielectric layer 6 inside the obtained third through hole. Fig.14b Of course, the first dielectric layer 6 may not be limited to being formed inside the sixth through hole, but may also be formed inside the sixth through hole. Fig.14b A first dielectric layer 6 is formed at the edges of each sacrificial layer.

[0194] Step S202d1: forming a third electrode 3, such as Fig.14c It can be seen that the first dielectric layer 6 is located between the third electrode 3 and the insulating material in the first through hole F1.

[0195] Step S202e1: Etching the third sacrificial layer H13 along the horizontal direction to form a fourth electrode 4 inside the obtained fourth through hole. Fig.14d shown.

[0196] Step S203f1: Etching the fourth sacrificial layer H14 along the horizontal direction to form a first electrode 1 inside the obtained fifth through hole. Fig.14d shown.

[0197] It can be understood that in the above steps, different etching selectivities can be selected to etch the sacrificial layers in the stacked structure H to form the first electrode 1 , the second electrode 2 , the third electrode 3 and the fourth electrode 4 .

[0198] Furthermore, in Fig.14d Based on the above, in step S203, forming the channel layer 5 inside the first through hole F1 may include: etching the insulating material inside the first through hole F1 to form the channel layer 5 inside the first through hole F1, such as Fig.15 shown.

[0199] In the embodiment of the present application, after the above step S203, an insulating material may be filled inside the channel layer 5 to form a third insulating layer 10, such as Figure 1 shown.

[0200] In another possible implementation, in the above step S201, etching the stacked structure H to form the first through hole F1 may include:

[0201] Step S201a2: forming a stacked structure H, such as Fig.16a shown.

[0202] The stacked structure H may include a fourth sacrificial layer H14, a first sacrificial layer H11, a first insulating layer 8, a second sacrificial layer H12, a second insulating layer 9, and a third sacrificial layer H13 stacked in a vertical direction. That is, the fourth sacrificial layer H14, the first sacrificial layer H11, the first insulating layer 8, the second sacrificial layer H12, the second insulating layer 9, and the third sacrificial layer H13 may be stacked in a vertical direction to form a stacked structure H.

[0203] Step S201b2: Etching the stacked structure H along the vertical direction to obtain a first through hole F1, such as Fig.16b shown.

[0204] Further, in Fig.16b On the basis of, in the above step S202, forming the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 based on the stacked structure H may include:

[0205] Step S202a2: Fill the first through hole F1 with insulating material, and etch the first sacrificial layer H11 along the horizontal direction to form a second electrode 2 inside the obtained second through hole. Fig.17a shown.

[0206] Step S202b2: Etching the second sacrificial layer H12 along the horizontal direction to form a first dielectric layer 6 and a third electrode 3 inside the obtained third through hole. Fig.17b As shown in FIG. 1 , it can be seen that the first dielectric layer 6 is located between the third electrode 3 and the insulating material in the first through hole F1. Of course, the first dielectric layer 6 may be formed not only in the sixth through hole, but also in Fig.17b A first dielectric layer 6 is formed at the edges of each sacrificial layer.

[0207] Step S202c2: Etching the third sacrificial layer H13 along the horizontal direction to form a fourth electrode 4 inside the obtained fourth through hole. Fig.17c shown.

[0208] Step S202d2: Etching the fourth sacrificial layer H14 along the horizontal direction to form a second dielectric layer 7 and a first electrode 1 inside the obtained fifth through hole, such as Fig.17d shown.

[0209] Furthermore, in Fig.17d Based on the above, in step S203, forming the channel layer 5 inside the first through hole F1 may include: etching the insulating material inside the first through hole F1 to form the channel layer 5 inside the first through hole F1, such as Fig.18 shown.

[0210] In the embodiment of the present application, after the above step S203, an insulating material may be filled inside the channel layer 5 to form a third insulating layer 10, such as Figure 2 shown.

[0211] In another possible implementation, in the above step S201, etching the stacked structure H to form the first through hole F1 may include:

[0212] Step S201a3: forming a stacked structure H, such as Fig.19a shown.

[0213] The stacked structure H may include a first sacrificial layer H11, a first insulating layer 8, a second sacrificial layer H12, a second insulating layer 9, and a third sacrificial layer H13 stacked in a vertical direction. That is, the first sacrificial layer H11, the first insulating layer 8, the second sacrificial layer H12, the second insulating layer 9, and the third sacrificial layer H13 may be stacked in a vertical direction to form a stacked structure H.

[0214] Step S201b3: Etching the stacked structure H along the vertical direction to obtain a first through hole F1, such as Fig.19b shown.

[0215] Further, in Fig.19b On the basis of, in the above step S202, forming the first electrode 1, the second electrode 2, the third electrode 3 and the fourth electrode 4 based on the stacked structure H may include:

[0216] Step S202a3: Fill the first through hole F1 with insulating material, etch part of the first sacrificial layer H11 along the horizontal direction, form a second electrode 2 inside the obtained second through hole, and fill it with insulating material, such as Fig.20a It can be understood that the unetched portion of the first sacrificial layer H11 can be used as the second isolation layer 12 .

[0217] Step S202b3: etching a portion of the second sacrificial layer H12 along the horizontal direction to form a first dielectric layer 6 and a third electrode 3 inside the obtained third through hole, such as Fig.20b It can be understood that the unetched portion of the second sacrificial layer H12 can be used as the third isolation layer 13 .

[0218] Step S202c3: etching a portion of the second electrode 2 and the insulating material wrapped by the second electrode 2, and forming a second dielectric layer 7 and the first electrode 1 inside the second electrode 2, such as Fig.20c shown.

[0219] Step S202d3: etching a portion of the third sacrificial layer H13 along the horizontal direction to form a fourth electrode 4 inside the obtained fourth through hole, such as Fig.20d It can be understood that the unetched portion of the third sacrificial layer H13 can be used as the first isolation layer 11 .

[0220] Furthermore, in Fig.20d Based on the above, in step S203, forming the channel layer 5 inside the first through hole F1 may include: etching the insulating material inside the first through hole F1 to form the channel layer 5 inside the first through hole F1. Insulating material may also be filled inside the channel layer 5 to form a third insulating layer 10, such as Fig.21 shown.

[0221] Will Fig.21 and Figure 3 By comparing, we can find that Figure 3 During the manufacturing process of the semiconductor device 100 shown, the first sacrificial layer H11 , the second sacrificial layer H12 , and the third sacrificial layer H13 may be completely etched. Fig.21In the manufacturing process of the semiconductor device 100 shown, the first sacrificial layer H11, the second sacrificial layer H12 and the third sacrificial layer H13 are not completely etched to obtain the first isolation layer 11, the second isolation layer 12 and the third isolation layer 13. In other words, Fig.21 The semiconductor device 100 shown can be an asymmetric structure, which can reduce the parasitic capacitance between the word line WL and the bit line BL, the parasitic capacitance between the word line WL and the plate line PL, and the parasitic capacitance between the bit line BL and the plate line PL, thereby improving the conduction performance of the transistor 100 and further improving the reliability of the semiconductor device 100.

[0222] It should be understood that the serial numbers of the various steps of preparing the semiconductor device 100 described above in the present application do not mean the order of execution. The execution order of each process should be determined based on the ability to prepare the semiconductor device 100, and will not constitute any limitation on the implementation process of the embodiment of the present application.

[0223] The present application also provides an electronic chip, such as Figure 22 to Figure 24 The electronic chip 300 may include word lines WL, bit lines BL, plate lines PL, and a plurality of semiconductor devices 100 .

[0224] Optionally, the electronic chip 300 may include a plurality of sub-arrays arranged in parallel. Each sub-array may include a plurality of Figure 3 The semiconductor device 100 shown. In the embodiment of the present application, the electronic chip 300 includes a sub-array and the sub-array includes two semiconductor devices 100 as an example. Fig. 22 shown.

[0225] The two semiconductor devices 100 may include a semiconductor device 100a and a semiconductor device 100b that are stacked. An insulating material may be provided between the semiconductor device 100a and the semiconductor device 100b. The third electrodes 3 of the semiconductor devices 100a and 100b are electrically connected to the same word line WL, and the first electrodes 1 of the semiconductor devices 100a and 100b are electrically connected to the same plate line PL ( Fig. 22 The fourth electrode 4 of the semiconductor device 100a can be electrically connected to the second bit line BL2 ( Fig. 22 ), the fourth electrode 4 of the semiconductor device 100b may be electrically connected to the first bit line BL1 ( Fig. 22 ) electrical connections.

[0226] The electronic chip 300 is introduced below from the perspective of topological structure.

[0227] like Fig.23 and Fig.24As shown, the electronic chip 300 may include multiple word lines WL (word line WL1, word line WL2, ..., word line WLn), multiple bit lines BL (bit line BL1, bit line BL2, ..., bit line BLn), multiple plate lines PL (plate line PL1, plate line PL2, ..., plate line PLn) and multiple semiconductor devices 100 (such as semiconductor device 100a and semiconductor device 100b, etc.).

[0228] In one example, the word lines WL1, WL2, ..., and WLn may be in a vertical direction, and the bit lines BL1, BL2, ..., and BLn and the plate lines PL1, PL2, ..., and PLn may be in a horizontal direction. Fig.23 As shown. Thus, the semiconductor device 100a and the semiconductor device 100b may be different semiconductor devices located in the same column. The third electrode 3 in each of the semiconductor device 100a and the semiconductor device 100b may be electrically connected to the word line WLn, the fourth electrode 4 of the semiconductor device 100a may be electrically connected to the bit line BL1, and the fourth electrode 4 of the semiconductor device 100b may be electrically connected to the bit line BL2. The first electrode 1 of the semiconductor device 100a may be electrically connected to the plate line PL1, and the first electrode 1 of the semiconductor device 100b may be electrically connected to the plate line PL2. That is, the third electrode 3 in different semiconductor devices located in the same column may be electrically connected to the same word line WL, and the fourth electrode 4 in different semiconductor devices located in the same column may be electrically connected to different bit lines BL. Similarly, the first electrode 1 in different semiconductor devices located in the same column may be electrically connected to different plate lines PL.

[0229] In another example, the bit lines BL1, BL2, ..., BLn may be in a vertical direction, and the word lines WL1, WL2, ..., WLn and the plate lines PL1, PL2, ..., PLn may be in a horizontal direction. Fig.24As shown. Thus, the semiconductor device 100a and the semiconductor device 100b may be different semiconductor devices located in the same column. The fourth electrode 4 in each of the semiconductor device 100a and the semiconductor device 100b may be electrically connected to the bit line BL1, the third electrode 3 in the semiconductor device 100a may be electrically connected to the word line WL1, and the third electrode 3 in the semiconductor device 100b may be electrically connected to the word line WL2. The first electrode 1 of the semiconductor device 100a may be electrically connected to the plate line PL1, and the first electrode 1 of the semiconductor device 100b may be electrically connected to the plate line PL2. In other words, the fourth electrode 4 in different semiconductor devices located in the same column may be electrically connected to the same bit line BL. The third electrode 3 in different semiconductor devices located in the same column may be electrically connected to different word lines WL. The first electrode 1 in different semiconductor devices located in the same column may be electrically connected to different plate lines PL, or the first electrode 1 in the semiconductor device 100 located in the same column may be electrically connected to the same plate line PL.

[0230] Furthermore, a first end of the plate line PL (such as the plate line PL1 ) may be electrically connected to the first electrode 1 , and a second end of the plate line PL may be electrically connected to the ground terminal GND (ground) or used to receive the power supply voltage VSS.

[0231] It is conceivable that the bit line BL1, the bit line BL2, ..., the bit line BLn may also be in a vertical direction, which is not limited in the embodiment of the present application.

[0232] In some embodiments, Fig.23 In the electronic chip 300 shown, different bit lines BL can be combined, such as Fig.25 shown. Fig.25 In the embodiment, transistors T11, T12, and T13 are electrically connected to word lines WL11, WL12, and WL13 in a one-to-one correspondence. Similarly, transistors T21, T22, and T23 are electrically connected to word lines WL21, WL22, and WL23 in a one-to-one correspondence. Transistors T11, T12, T13, T21, T22, and T23 are all electrically connected to bit line BL1. In other words, multiple Fig.23 The electronic chip 300 shown may share a bit line BL (eg Fig.25 The bit lines BL1, BL2, . . . , BLn in the electronic chip 300 can save the spacing between two bit lines BL and reduce the width of one bit line BL, thereby increasing the horizontal density of the electronic chip 300.

[0233] In other embodiments, Fig.24 In the electronic chip 300 shown in FIG. 1 , different bit lines BL may also be combined, such as Fig.26 shown. Fig.26In the embodiment, transistors T11, T12, and T13 are electrically connected to word line WL1. Similarly, transistors T21, T22, and T23 are electrically connected to word line WL2. Transistors T11 and T21 are both electrically connected to bit line BL1, transistors T12 and T22 are both electrically connected to bit line BL2, and transistors T13 and T31 are both electrically connected to bit line BL3. In other words, multiple Fig.24 The electronic chip 300 shown may share a bit line BL (eg Fig.25 The bit lines BL1, BL2 and BL3 in the electronic chip 300 can save the spacing between two bit lines BL, reduce the width of one bit line BL, and increase the horizontal density of the electronic chip 300.

[0234] The embodiment of the present application further provides a memory, which may include a circuit board and an electronic chip 300. The electronic chip 300 may be disposed on the circuit board.

[0235] Exemplarily, the memory may be a dynamic random access memory (DRAM) or the like, which is not limited in the embodiments of the present application.

[0236] Since the electronic chip 300 may include a plurality of semiconductor devices 100 , the semiconductor device 100 provided in the embodiment of the present application has good conduction performance, and can improve the read and write speed of the memory under a low current condition.

[0237] The embodiment of the present application further provides an electronic device, which may include a power supply and the above-mentioned memory. The power supply may be electrically connected to the memory to supply power to the memory.

[0238] Exemplarily, the electronic device may be a computer, a mobile phone, a smart speaker, etc., which is not limited in the embodiments of the present application.

[0239] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: comprising a capacitor and a transistor; the capacitor comprising a first electrode, the transistor comprising a third electrode, a fourth electrode and a channel layer, and the capacitor and the transistor share a second electrode; The second electrode, the third electrode and the fourth electrode are stacked along a first direction; the first electrode and the second electrode are stacked along the first direction, and the first electrode is located on a surface of the second electrode away from the third electrode; or the first electrode is located inside the second electrode; The semiconductor device further includes a first through hole, the first through hole penetrates the first electrode, the second electrode, the third electrode and the fourth electrode, and the channel layer is arranged inside the first through hole along the first direction.

2. The semiconductor device according to claim 1, wherein: The transistor further includes a first dielectric layer, wherein the first dielectric layer is located between the third electrode and the channel layer.

3. The semiconductor device according to claim 1 or 2, characterized in that: The capacitor also includes a second dielectric layer; The second dielectric layer is located between the first electrode and the second electrode; or, a first portion of the second dielectric layer is located between the first electrode and the second electrode, and a second portion of the second dielectric layer is located between the first electrode and the channel layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The transistor further includes a first insulating layer and a second insulating layer; The first insulating layer is located between the second electrode and the third electrode, and the second insulating layer is located between the third electrode and the fourth electrode.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The semiconductor device further comprises a third insulating layer; The third insulating layer is located inside the first through hole, the third insulating layer is located on the first surface of the channel layer, the first electrode, the second electrode, the third electrode and the fourth electrode are all located on the second surface of the channel layer; wherein the first surface and the second surface are arranged opposite to each other.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The first electrode is electrically connected to a plate line, the third electrode is electrically connected to a word line, and the fourth electrode is electrically connected to a bit line.

7. The semiconductor device according to claim 6, characterized in that The word line is perpendicular to the bit line, and the word line or the bit line is parallel to the first direction.

8. The semiconductor device according to claim 7, characterized in that The semiconductor device further includes a first isolation layer, and a position of the first isolation layer satisfies any of the following conditions: The first isolation layer is located between the word line and the fourth electrode; The first isolation layer is located on a surface of the fourth electrode away from the channel layer; The first isolation layer is located between the plate line and the fourth electrode.

9. The semiconductor device according to claim 7 or 8, characterized in that: The semiconductor device further includes a second isolation layer; The second isolation layer is located between the word line and the second electrode, or the second isolation layer is located between the bit line and the second electrode.

10. The semiconductor device according to any one of claims 7 to 9, characterized in that: The semiconductor device further includes a third isolation layer, and a position of the third isolation layer satisfies any of the following conditions: The third isolation layer is located on a surface of the third electrode away from the channel layer; The third isolation layer is located between the bit line and the third electrode; The third isolation layer is located between the bit line and the third electrode, and between the plate line and the third electrode.

11. A method for preparing a semiconductor device, characterized in that: include: Etching the stacked structure to form a first through hole; forming a first electrode, a second electrode, a third electrode and a fourth electrode based on the stacked structure; forming a channel layer inside the first through hole; Among them, the second electrode, the third electrode and the fourth electrode are stacked along the first direction; the first electrode and the second electrode are stacked along the first direction, and the first electrode is located on the surface of the second electrode away from the third electrode; or, the first electrode is located inside the second electrode; the first through hole passes through the first electrode, the second electrode, the third electrode and the fourth electrode, and the channel layer is arranged inside the first through hole along the first direction; the first electrode and the second electrode form a capacitor, and the second electrode, the third electrode, the fourth electrode and the channel layer form a transistor.

12. The preparation method according to claim 11, characterized in that: The step of etching the stacked structure to form a first through hole comprises: forming the stacked structure; the stacked structure comprises a first sacrificial layer, a first insulating layer, a second sacrificial layer, a second insulating layer and a third sacrificial layer stacked along the first direction; The stacked structure is etched along the first direction to obtain the first through hole.

13. The preparation method according to claim 12, characterized in that: The forming of the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure comprises: Etching the first sacrificial layer along a second direction to form the second electrode inside the obtained second through hole; Etching the second sacrificial layer along the second direction to form the third electrode in the obtained third through hole; forming the first electrode inside the second electrode; Etching the third sacrificial layer along the second direction to form the fourth electrode in the obtained fourth through hole; The second direction is perpendicular to the first direction.

14. The preparation method according to claim 13, characterized in that: The etching of the first sacrificial layer along the second direction to form the second electrode inside the obtained second through hole includes: Etching a portion of the first sacrificial layer along the second direction to obtain the second through hole; wherein the unetched portion of the first sacrificial layer serves as a second isolation layer; The second electrode is formed inside the second through hole.

15. The preparation method according to claim 13 or 14, characterized in that: The etching the second sacrificial layer along the second direction to form the third electrode in the obtained third through hole comprises: Etching a portion of the second sacrificial layer along the second direction to obtain the three through holes; wherein the unetched portion of the second sacrificial layer serves as a third isolation layer; The third electrode is formed inside the third through hole.

16. The preparation method according to any one of claims 13 to 15, characterized in that: The etching the third sacrificial layer along the second direction to form the fourth electrode in the obtained fourth through hole comprises: Etching a portion of the third sacrificial layer along the second direction to form the fourth through hole; wherein the portion of the third sacrificial layer that is not etched serves as a first isolation layer; The fourth electrode is formed inside the fourth through hole.

17. The preparation method according to any one of claims 13 to 16, characterized in that: The forming of the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure further includes: A second dielectric layer is formed inside the second through hole; wherein the second dielectric layer is located between the second electrode and the first electrode.

18. The preparation method according to claim 12, characterized in that: The stacked structure further includes a fourth sacrificial layer; the fourth sacrificial layer and the first sacrificial layer are stacked along the first direction, and the first sacrificial layer is located between the fourth sacrificial layer and the first insulating layer; The forming of the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure comprises: Etching the first sacrificial layer along a second direction to form the second electrode inside the obtained second through hole; Etching the second sacrificial layer along the second direction to form the third electrode inside the obtained third through hole; Etching the third sacrificial layer along the second direction to form the fourth electrode inside the obtained fourth through hole; Etching the fourth sacrificial layer along the second direction to form the first electrode inside the obtained fifth through hole; The second direction is perpendicular to the first direction.

19. The preparation method according to claim 18, characterized in that: The stacked structure further includes a fifth sacrificial layer, the fifth sacrificial layer and the fourth sacrificial layer are stacked along the first direction, and the fifth sacrificial layer is located between the first sacrificial layer and the fourth sacrificial layer; The forming of the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure further includes: Etching the fifth sacrificial layer along the second direction to obtain a sixth through hole; A second dielectric layer is formed inside the sixth through hole; wherein the second dielectric layer is located between the first electrode and the second electrode.

20. The preparation method according to claim 18, characterized in that: The forming of the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure further includes: A second dielectric layer is formed inside the fifth through hole; wherein a first portion of the second dielectric layer is located between the first electrode and the second electrode, and a second portion of the second dielectric layer is located between the first electrode and the channel layer.

21. The preparation method according to any one of claims 13 to 20, characterized in that: The preparation method further comprises: An insulating material is filled in the first through hole.

22. The preparation method according to claim 21, characterized in that: The forming of the first electrode, the second electrode, the third electrode and the fourth electrode based on the stacked structure further includes: A first dielectric layer is formed inside the third through hole; wherein the first dielectric layer is located between the third electrode and the insulating material.

23. The preparation method according to any one of claims 11 to 22, characterized in that: The preparation method further comprises: The insulating material is filled inside the channel layer to form a third insulating layer.

24. An electronic chip, characterized in that: comprising word lines, bit lines, plate lines and a plurality of semiconductor devices as claimed in claims 1 to 10; The word line, the bit line, and the plate line are each electrically connected to each semiconductor device of the plurality of semiconductor devices.

25. A memory, characterized in that: It comprises a circuit board and the electronic chip as claimed in claim 24, wherein the electronic chip is arranged on the circuit board.

26. An electronic device, characterized in that: The device comprises a power source and the memory as claimed in claim 25, wherein the power source is electrically connected to the memory.

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