Semiconductor device including magnetic tunnel junction structure

Abstract

In one embodiment, a semiconductor device includes a spin-orbit torque (SOT) line extending in a first direction; an electrode layer spaced apart from the SOT line in a third direction; and a magnetic tunnel junction structure interposed between the SOT line and the electrode layer, and including a free layer adjacent to the SOT line in the third direction, a pinned layer adjacent to the electrode layer in the third direction, and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the magnetic tunnel junction structure includes a first portion overlapping the SOT line in the second direction and a second portion not overlapping the SOT line, the electrode layer overlaps at least a portion of the second portion, and a thickness of the free layer in the first portion is greater than a thickness of the free layer in the second portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0084132, filed on Jun. 29, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The technology disclosed in this patent document relates to semiconductor technology, and more particularly to a semiconductor device including a magnetic tunnel junction structure. Background Art

[0004] Recently, the trend of the electrical and electronic industries toward miniaturization, low power consumption, high performance, and multifunctionality has forced semiconductor manufacturers to focus on high-performance, high-capacity semiconductor devices. Examples of such high-performance, high-capacity semiconductor devices include memory devices that can store data by switching between different resistance states according to applied voltage or current, such as RRAM (resistance random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), and electronic fuses (fuses). Summary of the invention

[0005] In one embodiment, a semiconductor device may include: one or more first conductive lines extending in a first direction to carry current flowing through the first conductive lines; one or more electrode layers, each electrode layer being spaced apart from a corresponding first conductive line in a third direction intersecting the first direction; and one or more magnetic tunnel junction structures, each magnetic tunnel junction structure being interposed between a corresponding first conductive line and a corresponding electrode layer, each of the one or more magnetic tunnel junction structures including a free layer, a pinned layer, and a tunnel barrier layer stacked in the third direction, the free layer being arranged to be adjacent to the arranged first conductive line, the pinned layer being arranged to be adjacent to the electrode layer, and the tunnel barrier layer being interposed between the free layer and the pinned layer, wherein each of the magnetic tunnel junction structures includes a first portion overlapping with the first conductive line, and a second portion not overlapping with the first conductive line, the magnetic tunnel junction structure extending in a second direction intersecting the first direction and the third direction, the electrode layer at least partially overlapping with the second portion, and a thickness of the free layer in the first portion being greater than a thickness of the free layer in the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and Figure 1B are views showing semiconductor devices based on some embodiments of the disclosed technology;

[0007] FIG. 2A to FIG. 2Cis a cross-sectional view showing a state of a semiconductor device based on some embodiments of the disclosed technology;

[0008] Figure 3A and Figure 3B is a voltage-time diagram illustrating an example of the operation of a semiconductor device based on some embodiments of the disclosed technology;

[0009] Figure 4 is a cross-sectional view showing a semiconductor device according to some embodiments of the disclosed technology;

[0010] Figure 5 is a cross-sectional view showing a semiconductor device according to some embodiments of the disclosed technology;

[0011] FIG. 6A to FIG. 6C are views showing semiconductor devices based on some embodiments of the disclosed technology;

[0012] FIG. 7A to FIG. 7C are views showing semiconductor devices based on some embodiments of the disclosed technology;

[0013] Figure 8 is a cross-sectional view showing a semiconductor device according to some embodiments of the disclosed technology;

[0014] Fig. 9 are views showing semiconductor devices based on some embodiments of the disclosed technology; and

[0015] Fig.10 is a cross-sectional view showing a semiconductor device based on some embodiments of the disclosed technology. DETAILED DESCRIPTION

[0016] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0017] The drawings are not necessarily drawn to scale. In some cases, in order to clearly illustrate certain features of the described embodiments, the proportions of at least some structures in the drawings may be exaggerated. When a specific example is presented in a drawing or description having two or more layers in a multilayer structure, the relative positioning relationship of these layers as shown or the order of the arrangement layers reflects the specific implementation of the described or illustrated example, and different relative positioning relationships or the order of the arrangement layers may be possible. In addition, the description or illustrated example of a multilayer structure may not reflect all layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two layers shown). As a specific example, when the first layer in the multilayer structure described or illustrated is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0018] Figure 1A and Figure 1B are views showing semiconductor devices based on some embodiments of the disclosed technology. Figure 1A A perspective view is shown, and Figure 1B Shown along Figure 1A A cross-sectional view taken along line AA'.

[0019] refer to Figure 1A and Figure 1B, a semiconductor device of an embodiment may include a spin-orbit torque (SOT) line (or first conductive line) 110 and an electrode layer 130 spaced apart from each other in a vertical direction, and a magnetic tunnel junction (MTJ) structure 120 interposed between the SOT line 110 and the electrode layer 130 and including a free layer 122, a tunnel barrier layer 124, and a pinned layer (also referred to as a "fixed layer") 126. The free layer 122 may be disposed relatively adjacent to the SOT line 110, and the pinned layer 126 may be disposed relatively adjacent to the electrode layer 130, with the tunnel barrier layer 126 therebetween. In some implementations, the term "SOT line" may be used to indicate a conductive material layer used to perform a spin-orbit torque (SOT) method as described below to change the magnetization direction of the free layer 122 within the MTJ structure 120. As an example, as shown in the figure, the SOT line 110, the free layer 122, the tunnel barrier layer 124, the pinned layer 126 and the electrode layer 130 can be stacked or arranged sequentially in one direction (e.g., the vertical direction). Here, the vertical direction can correspond to the stacking direction of the free layer 122, the tunnel barrier layer 124 and the pinned layer 126. In some implementations, the horizontal direction can be a direction substantially perpendicular to the vertical direction and / or the stacking direction while being substantially parallel to the lower surface of the free layer 122 or the upper surface of the pinned layer 126. The SOT line 110 can extend in a first direction parallel to the horizontal direction. The second direction can be a direction substantially perpendicular to the first direction and parallel to the horizontal direction.

[0020] In the magnetic tunnel junction structure 120, the free layer 122 may be a layer that stores different data by having a variable magnetization direction, and may also be referred to as a storage layer. The pinned layer 126 may be a layer having a fixed magnetization direction different from the magnetization direction of the free layer 122. In some implementations, the pinned layer 126 may be referred to as a reference layer. Each of the free layer 122 and the pinned layer 126 may have a magnetization direction substantially parallel to the vertical direction, or may have a magnetization direction substantially parallel to the horizontal direction. The tunnel barrier layer 124 may physically separate the pinned layer 126 and the free layer 122 from each other, and may enable electrons to tunnel between the pinned layer 126 and the free layer 122.

[0021] The magnetic tunnel junction structure 120 can store different data bits by switching between different resistance states according to an applied voltage or current. In some implementations, when the magnetization direction of the free layer 122 changes according to a voltage or current applied to the magnetic tunnel junction structure 120 and becomes parallel to the magnetization direction of the pinned layer 126, the magnetic tunnel junction structure 120 can have a low resistance state and, for example, can store a data bit "1". On the other hand, when the magnetization direction of the free layer 122 changes according to a voltage or current applied to the magnetic tunnel junction structure 120 and becomes antiparallel to the magnetization direction of the pinned layer 126, the magnetic tunnel junction structure 120 can have a high resistance state and, for example, can store a data bit "0". In one embodiment, the magnetization direction of the free layer 122 of the magnetic tunnel junction structure 120 can be changed by a voltage or current applied via the SOT line 110 and the electrode layer 130, as described below.

[0022] In the magnetic tunnel junction structure 120, each of the free layer 122 and the pinned layer 126 may include a single layer structure or a multilayer structure including a ferromagnetic material. As an example, any one or each of the free layer 122 and the pinned layer 126 may include an alloy containing Fe, Ni or Co as a main component, for example, at least one of an Fe-Pt alloy, an Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, an Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy or a Co-Fe-B alloy; or, a laminated structure such as Co / Pt or Co / Pd may be included. The tunnel barrier layer 124 may have a single layer or a multilayer structure including an insulating material. As an example, the tunnel barrier layer 124 may include an insulating oxide such as MgO, CaO, SrO, TiO, VO or NbO. The magnetic tunnel junction structure 120 may have a columnar shape. In addition, the magnetic tunnel junction structure 120 may have a columnar shape, wherein its length in the first direction is less than its length in the second direction. In one embodiment, the magnetic tunnel junction structure 120 may have a rectangular shape in a plan view, but the disclosed technology is not limited thereto, and the planar shape of the magnetic tunnel junction structure 120 may be modified in various ways.

[0023] The SOT line 110 may be adjacent to the free layer 122 of the magnetic tunnel junction structure 120 in a vertical direction and may be used to change the magnetization direction of the free layer 122 by the SOT method. In other words, the magnetization direction of the free layer 122 may be changed by a current flowing through the SOT line 110 (see Figure 1AThe dotted arrow ① in the figure changes under the influence of the spin current generated by the strong spin-orbit coupling force generated by the pinned layer 126. Materials with spin-orbit coupling force can have a high conversion efficiency of charge current to spin current, that is, a high spin Hall effect. The SOT line 110 can have a single-layer structure or a multi-layer structure including one or more different conductive materials. As an example, the SOT line 110 may include a heavy metal (such as α-W, β-W, Mo, Ru, β-Ta or a combination thereof), or an antiferromagnetic material (such as IrMn) to produce a strong spin-orbit interaction with the variable magnetization of the free layer 122 while the magnetization direction of the pinned layer 126 is fixed and does not change.

[0024] The SOT line 110 may have a linear shape extending in the first direction, and may overlap and connect with a portion of the magnetic tunnel junction structure 120 below the magnetic tunnel junction structure 120. The SOT line 110 may be in direct contact with a portion of the lower surface of the free layer 122. Because the SOT line 110 overlaps with a portion of the magnetic tunnel junction structure 120, the remaining portion of the magnetic tunnel junction structure 120 may protrude from the SOT line 110 in the second direction. The portion of the magnetic tunnel junction structure 120 overlapping with the SOT line 110 may be referred to as a first portion 120P1, and the portion of the SOT line 110 other than the first portion 120P1 may be referred to as a second portion 120P2.

[0025] The electrode layer 130 may be located on the opposite side of the SOT line 110 in the vertical direction, with the magnetic tunnel junction structure 120 interposed therebetween, and therefore, the electrode layer 130 may be adjacent to the pinned layer 126 in the vertical direction. The electrode layer 130 may be used to change the magnetization direction of the free layer 122 using a spin transfer torque (STT) method. In other words, the free layer 122 is magnetized by the electrode layer 130 in the vertical direction (see Figure 1A The dotted arrow ② in the figure) The spin polarized charge carriers generated by the current flowing through the magnetic tunnel junction structure 120 can be injected into the free layer 122, and thus, the magnetization of the free layer 122 can be changed. The electrode layer 130 can have a single layer structure or a multilayer structure including at least one of various conductive materials. As an example, the electrode layer 130 can include a metal (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), or tantalum (Ta)), a metal nitride (such as titanium nitride (TiN) or tantalum nitride (TaN)), or a combination thereof.

[0026] The electrode layer 130 may have a columnar shape and may overlap and connect with at least a portion of the second portion 120P2 of the magnetic tunnel junction structure 120 above the magnetic tunnel junction structure 120. Therefore, the electrode layer 130 may be disposed to deviate from the SOT line 110 in the second direction. In one embodiment, the electrode layer 130 is in direct contact with a portion of the upper surface of the pinned layer 126, but the disclosed technology is not limited thereto. In another embodiment, a conductive layer (not shown) may be interposed between the electrode layer 130 and the pinned layer 126, and in this case, the electrode layer 130 and the pinned layer 126 may be electrically connected to each other through the conductive layer. In one embodiment, a case is shown in which the electrode layer 130 has a circular shape in a plan view, but the disclosed technology is not limited thereto, and the planar shape of the electrode layer 130 may be modified in various ways. In addition, in one embodiment, the electrode layer 130 has a width smaller than the width of the second portion 120P2 in each of the first direction and the second direction, so that the plane area of ​​the electrode layer 130 is smaller than the plane area of ​​the second portion 120P2, but the disclosed technology is not limited thereto, and the plane area of ​​the electrode layer 130 may be modified in various ways on the premise that the plane area of ​​the electrode layer 130 is smaller than or equal to the plane area of ​​the second portion 120P2. For example, in another embodiment, the shape and area of ​​the electrode layer 130 in a plan view may be substantially the same as the shape and area of ​​the second portion 120P2.

[0027] In such a semiconductor device, each of the thickness of the free layer 122 and the thickness of the pinned layer 126 may not be constant and may vary depending on the position. More specifically, the thickness t3 of the free layer 122 in the first portion 120P1 overlapping the SOT line 110 may be greater than the thickness t7 of the free layer 122 in the second portion 120P2 overlapping the electrode layer 130, and the thickness t1 of the pinned layer 126 in the first portion 120P1 may be less than the thickness t5 of the pinned layer 126 in the second portion 120P2. In addition, the thickness t3 may be greater than the thickness t1, and the thickness t7 may be less than the thickness t5. In addition, the thickness t1 and the thickness t7 may be substantially the same as each other, and the thickness t3 and the thickness t5 may be substantially the same as each other. Here, when the deviation between two different values ​​such as a thickness value is within 10% of the value, it can be said that the two different values ​​are substantially the same. For example, the thickness t1 may have a value of 90% to 110% of the thickness t7, and the thickness t3 may have a value of 90% to 110% of the thickness t5. Due to the difference in thickness, when the lower surface of the free layer 122 is located at substantially the same height in the vertical direction, the height of the upper surface of the free layer 122 may vary in its position. That is, the height of the upper surface of the free layer 122 in the first portion 120P1 may be greater than the height of the upper surface of the free layer 122 in the second portion 120P2. The upper surface of the free layer 122 in each of the first portion 120P1 and the second portion 120P2 may be substantially parallel to the horizontal direction, and the upper surface of the free layer 122 at the boundary between the first portion 120P1 and the second portion 120P2 may be substantially parallel to the vertical direction while connecting the upper surface of the free layer 122 in the first portion 120P1 and the upper surface of the free layer 122 in the second portion 120P2 to each other. In addition, due to the difference in thickness, when the upper surface of the pinned layer 126 is located at substantially the same height in the vertical direction, the height of the lower surface of the pinned layer 126 may vary according to its position. That is, the height of the lower surface of the pinned layer 126 in the first portion 120P1 may be greater than the height of the lower surface of the pinned layer 126 in the second portion 120P2. The lower surface of the pinned layer 126 in each of the first portion 120P1 and the second portion 120P2 may be substantially parallel to the horizontal direction, and the lower surface of the pinned layer 126 at the boundary between the first portion 120P1 and the second portion 120P2 may be substantially parallel to the vertical direction while connecting the lower surface of the pinned layer 126 in the first portion 120P1 and the lower surface of the pinned layer 126 in the second portion 120P2 to each other. In some implementations, the thickness of the tunnel barrier layer 124 may be substantially constant regardless of its position.That is, the thickness t2 of the tunnel barrier layer 124 in the first portion 120P1, the thickness t6 of the tunnel barrier layer 124 in the second portion 120P2, and the thickness t4 of the tunnel barrier layer 124 at the boundary between the first portion 120P1 and the second portion 120P2 may be substantially the same as each other. For example, any one or each of the thickness t4 and the thickness t6 may have a value of 90% to 110% of the thickness t2. The sum of the thickness t1 of the pinned layer 126 in the first portion 120P1, the thickness t2 of the tunnel barrier layer 124, and the thickness t3 of the free layer 122 may be substantially equal to the sum of the thickness t5 of the pinned layer 126 in the second portion 120P2, the thickness t6 of the tunnel barrier layer 124, and the thickness t7 of the free layer 122.

[0028] Generally, when the free layer in the magnetic tunnel junction structure has a perpendicular magnetization direction, the perpendicular magnetic anisotropy of the free layer may be inversely proportional to the thickness of the free layer. That is, as the thickness of the free layer increases, the perpendicular magnetic anisotropy may decrease, and as the thickness of the free layer decreases, the perpendicular magnetic anisotropy may increase. When the thickness of the free layer decreases and the perpendicular magnetic anisotropy increases accordingly, it becomes difficult to switch the magnetization direction of the free layer, resulting in problems of reduced operating speed and high power consumption. On the other hand, when the thickness of the free layer increases and the perpendicular magnetic anisotropy decreases accordingly, thermal stability may deteriorate. To solve this problem, in one embodiment, the thickness t3 of the free layer 122 in the first portion 120P1 overlapping the SOT line 110 may be relatively large, and therefore, the switching of the magnetization direction of the free layer 122 by the SOT method may be facilitated. In addition, thermal stability may be ensured by reducing the thickness t7 of the free layer 122 in the second portion 120P2 that does not overlap the SOT line 110.

[0029] However, since the thickness t7 of the free layer 122 in the second portion 120P2 is thinner than other regions of the free layer 122, the spin current generated by the SOT line 110 alone may not be sufficient to switch the magnetization direction of the free layer 122. The disclosed technology may be implemented in some embodiments to solve this problem by facilitating the switching of the magnetization direction of the free layer 122. In some embodiments, the STT method may be used to facilitate the switching of the magnetization direction of the free layer 122 by setting the electrode layer 130 to overlap with the second portion 120P2.

[0030] Therefore, switching of the magnetization direction of the free layer 122 may occur using the SOT method using the horizontal current and the STT method using the vertical current simultaneously, so that the semiconductor device may perform high-speed and low-power operations and ensure thermal stability.

[0031] Will refer to FIG. 2A to FIG. 2C as well as Figure 3A and Figure 3BThe operation of the above-mentioned semiconductor device is described.

[0032] FIG. 2A to FIG. 2C is a cross-sectional view showing a state of a semiconductor device based on some embodiments of the disclosed technology, and Figure 3A and Figure 3B is a voltage-time diagram illustrating an example of the operation of a semiconductor device based on some embodiments of the disclosed technology. Figure 2A , Figure 2B and Figure 2C They are shown respectively Figure 3A and Figure 3B The states at time T0, time T1 and time T2 in . Figure 3A Shows the application of Figure 1A The voltage between the first node N1 and the second node N2 of the SOT line 110, and Figure 3B Shows the application to Figure 1A The voltage of the third node N3 of the electrode layer 130 is obtained.

[0033] refer to Figure 3A and Figure 3B In the initial state, that is, at time T0, the magnetic tunnel junction structure 120 may have Figure 2A The status shown or Figure 2C Status. Figure 2A , the magnetization direction of the free layer 122 and the magnetization direction of the pinned layer 126 may be parallel to each other, and therefore, the magnetic tunnel junction structure 120 may have a low resistance state. Figure 2C , the magnetization direction of the free layer 122 and the magnetization direction of the pinned layer 126 may be antiparallel to each other, and therefore, the magnetic tunnel junction structure 120 may have a high resistance state. In one embodiment, the free layer 122 and the pinned layer 126 may have a Figure 2A , Figure 2B and Figure 2C The arrows shown indicate perpendicular magnetization directions. As an example, the pinned layer 126 may have a magnetization direction from top to bottom, and the free layer 122 may have a magnetization direction from top to bottom or from bottom to top.

[0034] Subsequently, in the time period between time T0 and time T1, a first voltage V1 may be applied through the first node N1 and the second node N2 to change the resistance state of the magnetic tunnel junction structure 120. The first voltage V1 may be used for SOT type magnetization direction switching. In addition, in this time period, a second voltage V2 may be applied through the third node N3. The second voltage V2 may be used for STT type magnetization direction switching. The second voltage V2 may be applied optionally in this time period. That is, in one embodiment, a second voltage V2 of a predetermined magnitude is applied in this time period, but the disclosed technology is not limited thereto. In another embodiment, the second voltage V2 may not be applied in this time period, or the magnitude of the second voltage V2 may be 0.

[0035] After the first voltage V1 is applied, at time T1, the magnetic tunnel junction structure 120 may have Figure 2B status. Figure 2B , the magnetization direction of the free layer 122 is indicated by a horizontal arrow. This may indicate that the magnetization direction of the free layer 122 is not parallel or antiparallel to the magnetization direction of the pinned layer 126 having a perpendicular magnetization direction, and therefore, the magnetization direction of the free layer 122 is not sufficiently switched.

[0036] In order to compensate for the switching of the magnetization direction of the free layer 122, the magnitude of the second voltage V2 applied through the third node N3 in the time period between time T1 and time T2 may be increased. The magnitude of the second voltage V2 applied in the time period between time T0 and time T1 may be 0 or more, and may be less than the magnitude of the second voltage V2 applied in the time period between time T1 and time T2.

[0037] After the second voltage V2 is applied, at time T2, the magnetic tunnel junction structure 120 may have Figure 2C status or Figure 2A If the magnetic tunnel junction structure 120 has a Figure 2A state, the magnetic tunnel junction structure 120 may have a Figure 2C On the contrary, if the magnetic tunnel junction structure 120 has a Figure 2C state, the magnetic tunnel junction structure 120 may have a Figure 2A status.

[0038] In this manner, resistance state switching of the magnetic tunnel junction structure 120 may be performed.

[0039] In some embodiments, as long as the magnetic tunnel junction structure 120 includes a free layer 122, a pinned layer 126, and a tunnel barrier layer 124 therebetween, the layer structure of the magnetic tunnel junction structure 120 may be modified in various ways. As an example, the vertical positions of the pinned layer 126 and the free layer 122 may be reversed with each other. However, in this case, the SOT line 110 may need to be closer to the free layer 122 than the pinned layer 126 for SOT switching. Therefore, the vertical positions of the SOT line 110 and the electrode layer 130 may also be reversed with each other. This will refer to Figure 4 Alternatively, as an example, the magnetic tunnel junction structure 120 may further include one or more layers to improve its characteristics. For example, the magnetic tunnel junction structure 120 may include another pinned layer that is antiferromagnetically coupled to the pinned layer 126 to form a synthetic antiferromagnetic (SAF) structure to strengthen the fixation of the magnetization direction of the pinned layer 126. This will refer to Figure 5 Alternatively, for example, the magnetic tunnel junction structure 120 may further include one or more conductive layers interposed between the pinned layer 126 and the electrode layer 130. The conductive layer may be referred to as an electrode layer, a hard mask layer, a capping layer, etc. according to its function.

[0040] Figure 4 is a cross-sectional view showing a semiconductor device based on some embodiments of the disclosed technology. The description will focus on Figure 1A and Figure 1B The differences between semiconductor devices.

[0041] refer to Figure 4 , the semiconductor device of the embodiment may include an electrode layer 230 arranged from bottom to top, a magnetic tunnel junction structure 220 including a pinned layer 226 , a tunnel barrier layer 224 , and a free layer 222 , and a SOT line 210 .

[0042] The thickness t3 of the free layer 222 in the first portion 220P1 overlapping the SOT line 210 may be greater than the thickness t7 of the free layer 222 in the second portion 220P2 overlapping the electrode layer 230. In addition, the thickness t1 of the pinned layer 226 in the first portion 220P1 may be less than the thickness t5 of the pinned layer 226 in the second portion 220P2. The thicknesses t2, t4, and t6 of the tunnel barrier layer 224 may be substantially constant.

[0043] In some implementations, the magnetic tunnel junction structure 220 in the embodiment may include a pinned layer 226 disposed below the tunnel barrier layer 224 and a free layer 222 disposed above the tunnel barrier layer 224. The electrode layer 230 may be disposed below the magnetic tunnel junction structure 220, and the SOT line 210 may be disposed above the magnetic tunnel junction structure 220.

[0044] As described below, the SOT line and the free layer are relatively located below the pinned layer and the electrode layer, while the pinned layer and the electrode layer are relatively located above the SOT line and the free layer, similar to Figure 1A and Figure 1B However, the disclosed technology is not limited thereto, and in the semiconductor devices in some embodiments described below, the vertical positions of the SOT line and the free layer, and the vertical positions of the pinned layer and the electrode layer may be modified, similar to Figure 4 .

[0045] Figure 5 is a cross-sectional view showing a semiconductor device based on some embodiments of the disclosed technology. The description will focus on Figure 1A and Figure 1B The differences between semiconductor devices.

[0046] refer to Figure 5 , the semiconductor device of the embodiment may include a SOT line 310, a magnetic tunnel junction structure 320 including a free layer 322, a tunnel barrier layer 324 and a pinned layer 326, and an electrode layer 330. In addition, the magnetic tunnel junction structure 320 may further include an additional pinned layer 328 interposed between the pinned layer 326 and the electrode layer 330.

[0047] The additional pinned layer 328 may be antiferromagnetically coupled to the pinned layer 326 to form a SAF structure, thereby strengthening the magnetization direction of the pinned layer 324. A SAF coupling pattern 327 including a non-magnetic material may be interposed between the additional pinned layer 328 and the pinned layer 326. In one embodiment, only one additional pinned layer 328 is added, but the disclosed technology is not limited thereto. Two or more additional pinned layers may be interposed between the pinned layer 326 and the electrode layer 330, and a SAF coupling pattern may be interposed between adjacent additional pinned layers.

[0048] The additional pinned layer 328 and the SAF coupling pattern 327 may be part of the magnetic tunnel junction structure 320 and may be patterned together with the free layer 322, the tunnel barrier layer 324, and the pinned layer 326. Therefore, the sidewalls of the additional pinned layer 328 and the SAF coupling pattern 327 may be aligned with the sidewalls of the free layer 322, the tunnel barrier layer 324, and the pinned layer 326.

[0049] In some implementations, Figure 1A and Figure 1BIn the semiconductor device, a case has been described in which one SOT line 110 is connected to one magnetic tunnel junction structure 120 and one electrode layer 330, but the disclosed technology is not limited thereto. In another embodiment, one SOT line may be connected to multiple magnetic tunnel junction structures and multiple electrode layers corresponding to the multiple magnetic tunnel junction structures, respectively. In addition, multiple SOT lines may be arranged, and each of the multiple SOT lines may be connected to one or more magnetic tunnel junction structures and one or more electrode layers corresponding to the one or more magnetic tunnel junction structures, respectively. This will refer to FIG. 6A to FIG. 6C To describe by way of example.

[0050] FIG. 6A to FIG. 6C are views showing semiconductor devices based on some embodiments of the disclosed technology. Fig. 6A It is a floor plan. Figure 6B It is along Fig. 6A A cross-sectional view taken along line BB' of Figure 6C It is along Fig. 6A The description will focus on the cross-sectional view taken along the line CC'. Figure 1A and Figure 1B The differences between semiconductor devices.

[0051] refer to FIG. 6A to FIG. 6C , a semiconductor device of an embodiment may include a substrate 400 , a plurality of SOT lines 410 disposed on the substrate 400 , a plurality of magnetic tunnel junction structures 420 disposed on the plurality of SOT lines 410 , and a plurality of electrode layers 430 disposed on the plurality of magnetic tunnel junction structures 420 .

[0052] The substrate 400 may include a semiconductor material such as silicon. In addition, the substrate 400 may include a required base (not shown). As an example, the substrate 400 may include a driving circuit connected to the SOT line 410 and / or the electrode layer 430 for driving them.

[0053] A plurality of SOT lines 410 may extend in a first direction over the substrate 400 and may be arranged to be spaced apart from each other in a second direction. Spaces between the plurality of SOT lines 410 may be filled with a first interlayer insulating layer 405. The first interlayer insulating layer 405 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0054] The SOT line 410 and the first interlayer insulating layer 405 may be formed in the following manner. As an example, the SOT line 410 and the first interlayer insulating layer 405 may be formed in the following manner: depositing a conductive material for forming the SOT line 410 over the substrate 400, selectively etching the conductive material to form the SOT line 410, depositing an insulating material thick enough to cover the SOT line while filling the space between the SOT lines 410, and performing a planarization process such as chemical mechanical polishing (CMP) to expose the upper surface of the SOT line 410. As another example, the SOT line 410 and the first interlayer insulating layer 405 may be formed in the following manner: depositing an insulating material for forming the first interlayer insulating layer 405 over the substrate 400, selectively etching the insulating material to form the first interlayer insulating layer 405 providing a space for the SOT line 410 to be formed, depositing a conductive material thick enough to cover the first interlayer insulating layer 405 while filling the space, and performing a planarization process to expose the upper surface of the first interlayer insulating layer 405.

[0055] A plurality of magnetic tunnel junction structures 420 arranged in the first direction may overlap with each SOT line 410. Since a plurality of SOT lines 410 are arranged in the second direction, a plurality of magnetic tunnel junction structures 420 may be arranged in a matrix form along the first direction and the second direction. Each of the plurality of magnetic tunnel junction structures 420 may have a columnar shape and may be spaced apart from each other in the first direction and the second direction. Each of the plurality of magnetic tunnel junction structures 420 may have a portion overlapping with the corresponding SOT line 410 and a remaining portion that does not overlap with the corresponding SOT line 410 and protrudes from the corresponding SOT line 410 to one side in the second direction (e.g., to the right).

[0056] Each of the plurality of magnetic tunnel junction structures 420 may include a free layer 422, a tunnel barrier layer 424, and a pinned layer 426. Here, a thickness of a portion of the free layer 422 overlapping with the corresponding SOT line 410 may be greater than a thickness of a remaining portion of the free layer 422 protruding from the corresponding SOT line 410. In addition, a thickness of a portion of the pinned layer 426 overlapping with the corresponding SOT line 410 may be less than a thickness of a remaining portion of the pinned layer 426 protruding from the corresponding SOT line 410.

[0057] The magnetic tunnel junction structure 420 can be formed in the following manner. First, a first magnetic material for forming a free layer 422 can be deposited on the SOT line 410 and the first interlayer insulating layer 405, and then the first magnetic material in the area not overlapping with the SOT line 410 can be selectively etched to a predetermined thickness. Here, the mask for selectively etching the first magnetic material can have a shape covering the area overlapping with the SOT line 410 and exposing the remaining area. Subsequently, an insulating material for forming a tunnel barrier layer 424 can be conformally deposited along the lower profile on the etched first magnetic material. Subsequently, a second magnetic material for forming a pinned layer 426 can be formed on the insulating material, and then a flattening process can be performed on the second magnetic material. Subsequently, the stacked structure of the first magnetic material, the insulating material and the second magnetic material can be selectively etched so that it has a columnar shape. As a result, a magnetic tunnel junction structure 420 as shown in the figure can be formed.

[0058] The spaces between the plurality of magnetic tunnel junction structures 420 may be filled with a second interlayer insulating layer 425. The second interlayer insulating layer 425 may be formed by depositing an insulating material thick enough to cover the magnetic tunnel junction structures 420 while filling the spaces between the magnetic tunnel junction structures 420, and performing a planarization process to expose the upper surfaces of the magnetic tunnel junction structures 420.

[0059] The plurality of electrode layers 430 may be arranged to overlap the plurality of magnetic tunnel junction structures 420, respectively. In particular, each electrode layer 430 may overlap at least a portion of the remaining portion of each magnetic tunnel junction structure 420. The remaining portion may include a portion that does not overlap the SOT line 410. Thus, the plurality of electrode layers 430 may be arranged in a matrix along the first direction and the second direction.

[0060] The electrode layer 430 may be formed in the following manner. As an example, the electrode layer 430 may be formed in the following manner: depositing a conductive material over the magnetic tunnel junction structure 420 and the second interlayer insulating layer 425, and selectively etching the conductive material. As another example, the electrode layer 430 may be formed in the following manner: depositing an insulating material (not shown) over the magnetic tunnel junction structure 420 and the second interlayer insulating layer 425, selectively etching the insulating material to form a hole exposing the remaining portion of the magnetic tunnel junction structure 420, and filling the hole with a conductive material.

[0061] One magnetic tunnel junction structure 420, one SOT line 410 connected thereto, and one electrode layer 430 connected thereto may form one memory cell. Therefore, a semiconductor device implemented based on one embodiment may include a plurality of memory cells arranged in a matrix along the first direction and the second direction.

[0062] In one embodiment, the magnetic tunnel junction structure 420 has a columnar shape, and a plurality of magnetic tunnel junction structures 420 arranged in the second direction may be spaced apart from each other. However, the disclosed technology is not limited thereto. In another embodiment, the magnetic tunnel junction structure excluding the free layer may have a linear shape extending in the second direction. When the free layers are separated from each other in the second direction, a plurality of memory cells may be formed, as will be described below with reference to FIG. 7A to FIG. 7C discussed.

[0063] FIG. 7A to FIG. 7C are views showing semiconductor devices based on some embodiments of the disclosed technology. Fig. 7A It is a floor plan. Figure 7B It is along Fig. 7A A cross-sectional view taken along line BB' of Figure 7C It is along Fig. 7A The description will focus on the cross-sectional view taken along the line CC'. FIG. 6A to FIG. 6C The differences between semiconductor devices.

[0064] refer to FIG. 7A to FIG. 7C A semiconductor device implemented based on an embodiment may include a substrate 500, a plurality of SOT lines 510 disposed on the substrate 500, a plurality of magnetic tunnel junction structures 520 disposed on the plurality of SOT lines 510, and a plurality of electrode layers 530 disposed on the plurality of magnetic tunnel junction structures 520.

[0065] The plurality of SOT lines 510 may extend in the first direction over the substrate 500 , and may be arranged to be spaced apart from each other in the second direction. Spaces between the plurality of SOT lines 510 may be filled with the first interlayer insulating layer 505 .

[0066] The magnetic tunnel junction structure 520 may include a free layer 522, a tunnel barrier layer 524, and a pinned layer 526. In a plan view, the free layer 522 may have a FIG. 6A to FIG. 6CThe free layer 422 of the magnetic tunnel junction structure 520 has substantially the same shape and is arranged in the same manner. That is, each free layer 522 may have a columnar shape, and a plurality of free layers 522 may be arranged in a matrix along the first direction and the second direction. On the other hand, in addition to the free layer 522 of the magnetic tunnel junction structure 520, the tunnel barrier layer 524 and the pinned layer 526 of the magnetic tunnel junction structure 520 may have a linear shape extending in the second direction to intersect with a plurality of SOT lines 510 arranged in the second direction. The free layer 522 may include a portion overlapping with the SOT line 510 and a remaining portion not overlapping with the SOT line 510. In addition, each of the pinned layer 524 and the tunnel barrier layer 526 may include a portion overlapping with the SOT line 510 and a remaining portion not overlapping with the SOT line 510. Here, the thickness of the portion of the free layer 522 overlapping with the SOT line 510 may be greater than the thickness of the remaining portion of the free layer 522 not overlapping with the SOT line 510. Furthermore, the thickness of a portion of the pinned layer 526 overlapping the SOT line 510 may be smaller than the thickness of a remaining portion of the pinned layer 526 not overlapping the SOT line 510 .

[0067] The magnetic tunnel junction structure 520 may be formed in the following manner. First, a first magnetic material for forming a free layer 522 may be deposited over the SOT line 510 and the first interlayer insulating layer 505, the first magnetic material may be patterned into a columnar shape to form a first magnetic pattern, and a portion of the first magnetic pattern in an area not overlapping the SOT line 510 may be selectively etched to a predetermined thickness to form the free layer 522. Here, the mask for selectively etching the first magnetic pattern may have a shape that covers the area overlapping the SOT line 510 and exposes the remaining area. Subsequently, the space between the free layers 522 may be filled with an insulating material, and an insulating material for forming a tunnel barrier layer 524 may be conformally deposited along the lower profile over the free layer 522 and the insulating material. Subsequently, a second magnetic material for forming a pinned layer 526 may be deposited over the insulating material for forming the tunnel barrier layer 524, and a planarization process may be performed on the second magnetic material. Subsequently, the stacked structure of the insulating material and the second magnetic material for forming the tunnel barrier layer 524 may be selectively etched to have a linear shape. Therefore, a stacked structure of a tunnel barrier layer 524 and a pinned layer 526 having a linear shape can be formed, and accordingly, a magnetic tunnel junction structure 520 as shown in the figure can be formed. The space between the stacked structure of the tunnel barrier layer 524 and the pinned layer 526 can be filled with an insulating material. The insulating material filling the space between the free layer 522 and the insulating material filling the space between the stacked structure of the tunnel barrier layer 524 and the pinned layer 526 will be referred to as a second interlayer insulating layer 525.

[0068] The plurality of electrode layers 530 may be arranged to respectively overlap the remaining portions of the plurality of magnetic tunnel junction structures 520 that do not overlap the SOT line 510. Thus, the plurality of electrode layers 530 may be arranged in a matrix form along the first direction and the second direction.

[0069] One SOT line 510, one electrode layer 530, and a portion of the magnetic tunnel junction structure 520 therebetween may form one memory cell MC. Therefore, a semiconductor device implemented based on one embodiment may include a plurality of memory cells MC arranged in a matrix along the first direction and the second direction.

[0070] As described above, the thickness of the pinned layer may vary. However, in another embodiment, the thickness of the pinned layer may have a substantially constant value under the premise that the thickness of the free layer is variable. For example, the deviation of the thickness of the pinned layer may be within 10%. For example, the maximum thickness of the pinned layer may be 110% or less of the minimum thickness of the pinned layer, while being greater than the minimum thickness of the pinned layer. This will refer to Figure 8 To describe by way of example.

[0071] Figure 8 is a cross-sectional view showing a semiconductor device based on some embodiments of the disclosed technology. The description will focus on Figure 1A and Figure 1B The differences between semiconductor devices.

[0072] refer to Figure 8 The semiconductor device of the embodiment may include a SOT line 610 , a magnetic tunnel junction structure 520 including a free layer 622 , a tunnel barrier layer 624 , and a pinned layer 626 , a magnetic loss layer 640 , and an electrode layer 630 .

[0073] Here, the thickness of the free layer 622 may not be constant and may vary according to its position. More specifically, the thickness t3' of the portion of the free layer 622 overlapping the SOT line 610 may be greater than the thickness t7' of the remaining portion of the free layer 622 not overlapping the SOT line 610. Figure 1A and Figure 1B Unlike the example shown, the upper surface of the free layer 622 may be located at substantially the same height in the vertical direction, and in this case, the height of the lower surface of the free layer 622 may vary. That is, the height of the lower surface of the remaining portion of the free layer 622 may be greater than the height of the lower surface of the portion of the free layer 622.

[0074] The magnetic loss layer 640 may be disposed below the remaining portion of the free layer 622 to compensate for the height difference between the lower surfaces of the free layer 622. In other words, the thickness t3' of the portion of the free layer 622 overlapping the SOT line 610 may be substantially equal to the sum of the thickness t7' of the remaining portion of the free layer 622 that does not overlap the SOT line 610 and the thickness t9' of the magnetic loss layer 640. As will be described later, the magnetic loss layer 640 may be formed by doping a portion of the magnetic material forming the free layer 622 with a dopant that causes magnetic loss, or by oxidizing a portion of the magnetic material. Therefore, the magnetic loss layer 640 may be formed of a material containing the constituent elements of the free layer 622 and an element used as a dopant, or may be formed of a material containing the constituent elements of the free layer 622 and oxygen. As an example, the dopant may be an inert element such as Ar.

[0075] Each of the thickness t2' of the tunnel barrier layer 624 and the thickness t1' of the pinned layer 626 may be substantially constant. Since the upper surface of the free layer 622 has a flat surface substantially parallel to the horizontal direction, each of the upper and lower surfaces of the tunnel barrier layer 624 may be substantially parallel to the horizontal direction while being located at substantially the same height, and each of the upper and lower surfaces of the pinned layer 626 may be substantially parallel to the horizontal direction while being located at substantially the same height.

[0076] As described above, a SOT line 610 can be connected to a magnetic tunnel junction structure 620 and an electrode layer 630, but the disclosed technology is not limited thereto. FIG. 6A to FIG. 6C and FIG. 7A to FIG. 7C In the embodiment described in the above, one SOT line can be connected to a plurality of magnetic tunnel junction structures and a plurality of electrode layers respectively corresponding to the plurality of magnetic tunnel junction structures, as will be described below with reference to Fig. 9 discussed.

[0077] Fig. 9 are views showing semiconductor devices based on some embodiments of the disclosed technology. Fig. 9 The cross section in can correspond to the cross section along Fig. 7A The cross section is taken along the line BB'.

[0078] refer to Fig. 9 , a semiconductor device of an embodiment may include a substrate 600 , a plurality of SOT lines 610 disposed on the substrate 600 , a plurality of magnetic tunnel junction structures 620 disposed on the plurality of SOT lines 610 and having a linear shape, and a plurality of electrode layers 630 disposed on the magnetic tunnel junction structures 620 .

[0079] The plurality of SOT lines 610 may extend in the first direction over the substrate 600 , and may be arranged to be spaced apart from each other in the second direction. Spaces between the plurality of SOT lines 610 may be filled with the first interlayer insulating layer 605 .

[0080] The magnetic tunnel junction structure 620 may include a free layer 622, a tunnel barrier layer 624, and a pinned layer 626. In a plan view, each free layer 622 has a columnar shape, and a plurality of free layers 622 may be arranged in a matrix along a first direction and a second direction. On the other hand, in addition to the free layer 622 of the magnetic tunnel junction structure 620, the tunnel barrier layer 624 and the pinned layer 626 may have a linear shape extending in the second direction to intersect with a plurality of SOT lines 610 arranged in the second direction.

[0081] Here, in the region overlapping with the SOT line 610, the free layer 622 may include a stacked structure of a first free layer 622A and a second free layer 622B. On the other hand, in the region not overlapping with the SOT line 610, the free layer 622 may include a second free layer 622B without including the first free layer 622A. Therefore, the thickness of the free layer 622 in the region overlapping with the SOT line 610 may be greater than the thickness of the free layer 622 in the region not overlapping with the SOT line 610. In the region not overlapping with the SOT line 610, the magnetic loss layer 640 may be disposed under the second free layer 622B. The first free layer 622A and the second free layer 622B may include the same magnetic material and thus may form a block. In the second direction, adjacent first free layers 622A may be separated from each other by the magnetic loss layer 640. In addition, in the second direction, adjacent second free layers 622B may be separated from each other by the second interlayer insulating layer 625.

[0082] The magnetic tunnel junction structure 620 can be formed in the following manner. First, a first magnetic material for forming a first free layer 622A can be deposited on the SOT line 610 and the first interlayer insulating layer 605, and the first magnetic material can be patterned into a columnar shape to form a first magnetic pattern. Subsequently, after forming a mask pattern that exposes an area that does not overlap the SOT line 610, the portion of the first magnetic pattern exposed by the mask pattern can be doped with a dopant, which loses magnetism by ion implantation, or the portion of the first magnetic pattern exposed by the mask pattern can be oxidized to form a first magnetic free layer 622A and a magnetic loss layer 530. Subsequently, a second magnetic material for forming a second free layer 622B can be deposited, and the second magnetic material can be patterned into a columnar shape to form a second magnetic pattern. The space between the second magnetic patterns can be filled with an insulating material. Subsequently, an insulating material for forming a tunnel barrier layer 624 can be deposited on the second magnetic pattern and the insulating material. Subsequently, a third magnetic material for forming a pinned layer 626 can be deposited on the insulating material for forming the tunnel barrier layer 624. Subsequently, the stacked structure of the insulating material and the third magnetic material used to form the tunnel barrier layer 624 can be selectively etched to have a linear shape. As a result, a magnetic tunnel junction structure 620 as shown in the figure can be formed. For reference, in another embodiment, the entire magnetic tunnel junction structure 620 can have a columnar shape instead of a linear shape. In this case, the stacked structure of the insulating material and the third magnetic material used to form the tunnel barrier layer 624 can be selectively etched so that it has a columnar shape instead of a linear shape.

[0083] The plurality of electrode layers 630 may be arranged to respectively overlap the remaining portions of the magnetic tunnel junction structure 620 that do not overlap the SOT line 610 .

[0084] Fig.10 is a cross-sectional view showing a semiconductor device based on some embodiments of the disclosed technology. The description will focus on Figure 1A and Figure 1B The differences between semiconductor devices.

[0085] refer to Fig.10 , the semiconductor device of the embodiment may include a SOT line 110, a magnetic tunnel junction structure 120 including a free layer 122, a tunnel barrier layer 124 and a pinned layer 126, an electrode layer 130, and a selector layer 150. That is, Figure 1A and Figure 1B Compared with the semiconductor device of the embodiment, the semiconductor device of the embodiment may further include a selector layer 150 .

[0086] The selector layer 150 may have a columnar shape interposed between the electrode layer 130 and the magnetic tunnel junction structure 120 and overlapped with the electrode layer 130. In one embodiment, the selector layer 150 may be patterned together with the electrode layer 130 to have the same planar shape as the electrode layer 130. That is, the sidewall of the selector layer 150 may be aligned with the sidewall of the electrode layer 130. However, the disclosed technology is not limited thereto, and the selector layer 150 may have a different planar shape and / or planar area from the electrode layer 130, provided that the selector layer 150 overlaps with the electrode layer 130.

[0087] The selector layer 150 can control access to the magnetic tunnel junction structure 120, and can be used to prevent and / or reduce current leakage between the magnetic tunnel junction structures 120 that share the SOT line 110 or another wire (not shown). To this end, the selector layer 150 can have the following threshold switching characteristics: when the magnitude of the voltage supplied to the top and bottom thereof is less than a predetermined threshold voltage, the current is blocked or the current is almost not allowed to flow, and above the threshold voltage, the current is allowed to flow quickly. That is, the selector layer 150 can be turned on at a threshold voltage or higher, and cut off below the threshold voltage.

[0088] The selector layer 150 may include a diode, an o-threshold switching (OTS) material such as a chalcogenide-based material, a mixed ion electron conduction (MIEC) material such as a metal chalcogenide-based material, a metal insulator transition (MIT) material such as NbO2 and VO2, or a tunnel insulating material with a relatively wide bandgap such as SiO2 and Al2O3.

[0089] Alternatively, the selector layer 150 may include an insulating material layer doped with a dopant. Here, the insulating material layer may include a silicon-containing insulating material (such as silicon oxide, silicon nitride, and silicon oxynitride), an insulating metal oxide, an insulating metal nitride, or a combination thereof. A deep well may exist in the insulating material layer, and the deep well has an energy level closer to the energy level of the valence band of the insulating material layer than the energy level of the conduction band of the insulating material layer. The dopant may be used to create a shallow well that provides a path for the movement of conductive carriers (such as electrons or holes) in the insulating material layer. The shallow well may have an energy level closer to the energy level of the conduction band of the insulating material layer than the energy level of the valence band of the insulating material layer. As an example, when the insulating material layer contains silicon, the dopant may be a metal having a different valence from silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof. Alternatively, when the insulating material layer includes a metal, the dopant may include another metal having a different valence from the metal, or silicon. As an example, the selector layer 150 may include arsenic (As)-doped silicon oxide, such as silicon dioxide (SiO2). When a voltage higher than the threshold voltage is applied to the selector layer 150, carriers trapped in the deep well may jump to the shallow well by thermal emission or tunneling, and the carriers may be transferred through the shallow well, thereby achieving an on-state in which current flows through the selector layer 150. On the other hand, when no voltage is applied to the selector layer 150 or a voltage less than the threshold voltage is applied, the phenomenon of carriers jumping into the shallow well can be reduced or prevented, resulting in an off-state in which no current flows through the selector layer 150.

[0090] As described above, in some embodiments of the disclosed technology, a semiconductor device can perform high-speed low-power operation and ensure thermal stability.

[0091] Although various embodiments have been described for purposes of illustration, it should be understood that modifications to the disclosed embodiments and other embodiments may be made based upon what is described and / or illustrated in this patent document.

Claims

1. A semiconductor device, comprising: One or more first conductors extending in a first direction to carry current passing through the first conductors; one or more electrode layers, each electrode layer being spaced apart from the corresponding first conductive line in a third direction, the third direction intersecting the first direction; as well as one or more magnetic tunnel junction structures, each magnetic tunnel junction structure is inserted between a corresponding first wire and a corresponding electrode layer, each of the one or more magnetic tunnel junction structures comprises a free layer, a pinned layer and a tunnel barrier layer stacked in the third direction, the free layer is arranged to be adjacent to the arranged first wire, the pinned layer is arranged to be adjacent to the electrode layer, and the tunnel barrier layer is inserted between the free layer and the pinned layer, Each of the magnetic tunnel junction structures includes a first portion overlapping the first conductive line and a second portion not overlapping the first conductive line, and the magnetic tunnel junction structure extends in a second direction, the second direction intersecting the first direction and the third direction. The electrode layer at least partially overlaps the second portion, and A thickness of the free layer in the first portion is greater than a thickness of the free layer in the second portion.

2. A semiconductor device according to claim 1, wherein the resistance state of the magnetic tunnel junction structure is switched by: a spin-orbit torque (SOT) method of switching the resistance state of the magnetic tunnel junction structure using a current flowing through the first conductive wire; and a spin transfer torque (STT) method of switching the resistance state of the magnetic tunnel junction structure using a current flowing from the electrode layer through the magnetic tunnel junction structure. 3 . The semiconductor device according to claim 1 , wherein each of the magnetic tunnel junction structure and the electrode layer has a pillar shape. 4 . The semiconductor device according to claim 3 , wherein a length of the magnetic tunnel junction structure in the first direction is smaller than a length in the second direction.

5. The semiconductor device according to claim 1 , wherein the pinned layer of the magnetic tunnel junction structure has a linear shape extending in the second direction, and Each of the free layer and the electrode layer of the magnetic tunnel junction structure has a pillar shape.

6. The semiconductor device according to claim 1 , wherein the one or more first conductive lines include a plurality of first conductive lines arranged in the second direction, and The magnetic tunnel junction structure and the electrode layer are connected to each of the plurality of first conductive lines.

7. The semiconductor device according to claim 1 , wherein the one or more first conductive lines include a plurality of first conductive lines arranged in the second direction, The one or more magnetic tunnel junction structures include a plurality of magnetic tunnel junction structures arranged to be spaced apart from each other in the first direction and respectively connected to the plurality of first conductive lines, and The one or more electrode layers include a plurality of electrode layers respectively connected to the plurality of magnetic tunnel junction structures.

8. The semiconductor device according to claim 1, wherein the magnetic tunnel junction structure further comprises: an additional pinned layer interposed between the pinned layer and the electrode layer and antiferromagnetically coupled to the pinned layer; and a non-magnetic material layer interposed between the additional pinned layer and the pinned layer.

9. The semiconductor device according to claim 1, further comprising: A magnetic loss layer contacts the free layer in the second portion of each magnetic tunnel junction structure in the third direction. 10 . The semiconductor device according to claim 9 , wherein the magnetic loss layer includes at least one of: a constituent element of the free layer; an element causing loss of magnetic characteristics of the free layer, or oxygen. 11 . The semiconductor device according to claim 9 , wherein a thickness of the free layer in the first portion of each magnetic tunnel junction structure is equal to a sum of a thickness of the free layer and a thickness of the magnetic loss layer in the second portion of each magnetic tunnel junction structure.

12. The semiconductor device according to claim 1, further comprising: One or more selector layers, each selector layer is interposed between a corresponding pinned layer and a corresponding electrode layer. 13 . The semiconductor device according to claim 1 , wherein a sum of thicknesses of the pinned layer in the first portion of each magnetic tunnel junction structure is smaller than a thickness of the pinned layer in the second portion of each magnetic tunnel junction structure.

14. A semiconductor device according to claim 13, wherein the sum of the thickness of the free layer, the thickness of the tunnel barrier layer, and the thickness of the pinned layer in the first part of each magnetic tunnel junction structure is equal to the sum of the thickness of the free layer, the thickness of the tunnel barrier layer, and the thickness of the pinned layer in the second part of each magnetic tunnel junction structure. 15 . The semiconductor device of claim 1 , wherein a thickness of the pinned layer in the first portion of each magnetic tunnel junction structure is equal to a thickness of the pinned layer in the second portion of each magnetic tunnel junction structure. 16 . The semiconductor device according to claim 1 , wherein each of the free layer and the pinned layer has a magnetization direction parallel to the third direction.

17. The semiconductor device according to claim 1, wherein the free layer includes a first surface facing the pinned layer, and The pinned layer includes a second surface facing the free layer, wherein the first surface and the second surface in each of the first portion and the second portion of each magnetic tunnel junction structure are parallel to a plane formed by an axis corresponding to the first direction and another axis corresponding to the second direction, and At a boundary between the first portion and the second portion of each magnetic tunnel junction structure, the first surface and the second surface are parallel to the third direction.

18. The semiconductor device according to claim 17, wherein the tunnel barrier layer includes a third surface facing the first surface or the second surface, wherein the third surface in each of the first portion and the second portion is parallel to the plane, and At the boundary between the first portion and the second portion of each magnetic tunnel junction structure, the third surface is parallel to the third direction.

19. The semiconductor device according to claim 1, wherein the free layer includes a first surface located opposite to a surface facing the pinned layer, and The pinned layer has a second surface facing the free layer, wherein the first surface in each of the first portion and the second portion of each magnetic tunnel junction structure is parallel to a plane formed by an axis corresponding to the first direction and another axis corresponding to the second direction, and the first surface at a boundary between the first portion and the second portion is parallel to the third direction, and The second surface is parallel to the plane.

20. The semiconductor device according to claim 19, wherein the tunnel barrier layer has a third surface facing the second surface, and The third surface is parallel to the plane.

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