Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a pattern disposed over the substrate; a hard mask pattern that is conductive and disposed over the pattern, the hard mask pattern including a lower hard mask pattern and an upper hard mask pattern over the lower hard mask pattern; a conductive pattern disposed over the hard mask pattern and electrically connected to the pattern through the hard mask pattern; and an insulating layer covering sidewalls of the pattern and sidewalls of the lower hard mask pattern, wherein the upper hard mask pattern is disposed to protrude from the insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to Korean Patent Application No. 10-2023-008346, filed on June 29, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present patent document relates to semiconductor technology, and in particular to a semiconductor device including a conductive hard mask and a method for manufacturing the same. Background Art

[0004] Recently, as electronic appliances have developed toward miniaturization, low power consumption, high performance, multi-functions, etc., semiconductor devices capable of storing information in various electronic appliances such as computers, portable communication devices, etc. have been needed in the art, and research has been conducted on semiconductor devices. Such semiconductor devices include semiconductor devices that can store data using a characteristic of switching between different resistance states according to an applied voltage or current, such as RRAM (resistance random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), one-time programmable memory, etc. Summary of the invention

[0005] In one embodiment, a semiconductor device may include: a substrate; a pattern disposed on the substrate; a hard mask pattern that is conductive and disposed on the pattern, the hard mask pattern including a lower hard mask pattern and an upper hard mask pattern on the lower hard mask pattern; a conductive pattern disposed on the hard mask pattern and electrically connected to the pattern through the hard mask pattern; and an insulating layer covering the sidewalls of the pattern and the sidewalls of the lower hard mask pattern, wherein the upper hard mask pattern is configured to protrude from the insulating layer.

[0006] In another embodiment, a method for manufacturing a semiconductor device may include: forming an etching target layer over a substrate; forming an initial hard mask pattern over the etching target layer, the initial hard mask pattern including a conductive material; forming a pattern by etching the etching target layer using the initial hard mask pattern as an etching barrier; forming an insulating layer, the insulating layer filling a space between the pattern and another pattern and exposing the initial hard mask pattern, the other pattern being adjacent to the pattern; exposing the initial hard mask pattern to a first element to form a hard mask pattern, the hard mask pattern having a volume larger than that of the initial hard mask pattern; and forming a conductive pattern over the hard mask pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 6Bis an exemplary diagram illustrating a semiconductor device according to an embodiment of the present disclosure and an exemplary method for manufacturing the semiconductor device.

[0008] Figure 7 is a cross-sectional view showing an example of a memory layer.

[0009] Figure 8 is a cross-sectional view showing a semiconductor device of a comparative example.

[0010] Fig. 9 is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure.

[0011] Fig.10 is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to still another embodiment of the present disclosure.

[0012] Fig.11 and Fig.12 is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0014] The drawings are not necessarily drawn to scale. In some cases, in order to clearly illustrate certain features of the described embodiments, the proportions of at least some structures in the drawings may have been exaggerated. When presenting a specific example in a drawing or description having two or more layers in a multilayer structure, the relative positioning relationship of such layers as shown or the order in which these layers are arranged reflect the specific implementation of the described or shown example, and different relative positioning relationships or different orders in which these layers are arranged may be possible. In addition, the described or shown examples of multilayer structures may not reflect all layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two layers shown). As a specific example, when the first layer in the described or shown multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or between the substrates.

[0015] Figures 1A to 6B is a view illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure. Figure 1A , Figure 2A , Figure 5A and Fig. 6A is a plan view, and Figure 1B , Figure 2B, Figure 3 , Figure 4 , Figure 5B and Figure 6B It is a cross-sectional view. Figure 1B , Figure 2B and Figure 5B Along the Figure 1A , Figure 2A and Figure 5A A cross-sectional view taken along line A-A', and Figure 6B It is along Fig. 6A Cross-sectional views taken along lines AA' and BB'.

[0016] First, the manufacturing method will be explained.

[0017] refer to Figure 1A and Figure 1B , a substrate 100 may be provided. The substrate 100 may include a semiconductor material such as silicon. In addition, a lower structure (not shown) may be formed within the substrate 100. For example, an integrated circuit may be formed in the substrate 100 to drive the first conductive line 110 and / or the second conductive line (see Fig. 6A and Figure 6B 160 in ), which will be described later.

[0018] Subsequently, a first wire 110 extending in a first direction may be formed on the substrate 100. A plurality of first wires 110 may be arranged to be spaced apart from each other in a second direction intersecting the first direction. Here, the first direction and the second direction may refer to directions substantially parallel to the upper surface of the substrate 100, i.e., horizontal directions. A direction substantially perpendicular to the upper surface of the substrate 100 will be referred to as a vertical direction hereinafter. The space between the first wires 110 may be filled with a first insulating layer 115. As an example, the first wire 110 and the first insulating layer 115 may be formed by depositing a conductive material for forming the first wire 110 on the substrate 100, selectively etching the conductive material to form the first wire 110, depositing a sufficiently thick insulating material to cover the first wire 110, while filling the space between the first wires 110, and performing a planarization process, such as CMP (chemical mechanical polishing), so that the upper surface of the first wire 110 is exposed. In another example, the first conductive line 110 and the first insulating layer 115 may be formed by depositing an insulating material for forming the first insulating layer 115 on the substrate 100, selectively etching the insulating material to form the first insulating layer 115, the first insulating layer 115 providing a space in which the first conductive line 110 will be filled, depositing a conductive material having a thickness covering the first insulating layer 115 while filling the space, and performing a planarization process so that the upper surface of the first insulating layer 115 is exposed. The first conductive line 110 may include at least one conductive material of various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. The first insulating layer 115 may include at least one insulating material of various insulating materials, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0019] Subsequently, a memory layer 120 may be formed over the first conductive line 110 and the first insulating layer 115. The memory layer 120 may be a layer for storing data in various ways, and may have a single-layer structure or a multi-layer structure. As an example, the memory layer 120 may include a variable resistance layer for storing different data by switching between different resistance states. The variable resistance layer may have a single-layer structure or a multi-layer structure including at least one of various materials used in RRAM, PRAM, FRAM, MRAM, etc., for example, a metal oxide such as a transition metal oxide or a perovskite material, a phase change material such as a chalcogenide material, a ferroelectric material, a ferromagnetic material, etc. In addition, as an example, the memory layer 120 may include a magnetic tunnel junction structure, which will be referred to as Figure 7 Describe in more detail.

[0020] Figure 7is a cross-sectional view showing an example of the memory layer 120 .

[0021] refer to Figure 7 , the memory layer 120 may include a magnetic tunnel junction structure including a stacked structure of a pinned layer 120A, a tunnel barrier layer 120B, and a free layer 120C. The pinned layer 120A may be a layer having a constant magnetization direction compared to the magnetization direction of the free layer 120C, and may also be referred to as a reference layer. The free layer 120C may be a layer that stores different data by having a variable magnetization direction, and may also be referred to as a memory layer. Each of the pinned layer 120A and the free layer 120C may have a magnetization direction substantially parallel to the surface of the layer, that is, a horizontal magnetization direction, or may have a magnetization direction substantially perpendicular to the surface of the layer, that is, a perpendicular magnetization direction. The tunnel barrier layer 120B may physically separate the pinned layer 120A and the free layer 120C, and may enable electrons to tunnel between the pinned layer 120A and the free layer 120C. Each of the pinned layer 120A and the free layer 120C may independently have a single-layer structure or a multi-layer structure including a ferromagnetic material. In one example, each of the fixed layer 120A and the free layer 120C may independently include an alloy containing Fe, Ni or Co as a main component, for example, a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy or a Co-Fe-B alloy, or a stacked structure of Co / Pt or Co / Pd. The tunnel barrier layer 120B may have a single-layer structure or a multi-layer structure including an insulating material. In one example, the tunnel barrier layer 120B may include an insulating oxide such as MgO, CaO, SrO, TiO, VO or NbO. The magnetization direction of the free layer 120C may vary according to the voltage or current applied to the memory layer 120. When the magnetization direction of the free layer 120C is parallel to the magnetization direction of the fixed layer 120A, the memory layer 120 may have a low resistance state, and, for example, data "1" may be stored. On the other hand, when the magnetization direction of the free layer 120C is antiparallel to the magnetization direction of the fixed layer 120A, the memory layer 120 may have a high resistance state and, for example, may store data "0". In another implementation, when the magnetization direction of the free layer 120C is antiparallel to the magnetization direction of the fixed layer 120A, data "0" may be stored, and when the magnetization direction of the free layer 120C is parallel to the magnetization direction of the fixed layer 120A, data "1" may be stored.

[0022] As long as the memory layer 120 includes a fixed layer 120A, a free layer 120C, and a tunnel barrier layer 120B between the fixed layer 120A and the free layer 120C, the layer structure of the memory layer 120 may be modified in various ways. In an example, the positions of the fixed layer 120A and the free layer 120C may be reversed with each other. Alternatively, in an example, although not shown, the memory layer 120 may further include one or more layers to improve the characteristics of the magnetic tunnel junction structure.

[0023] Reference again Figure 1A and Figure 1B , a preliminary hard mask pattern 130 for patterning the memory layer 120 may be formed on the memory layer 120. In an example, the preliminary hard mask pattern 130 may have an island shape so as to pattern the memory layer 120 into a columnar shape. A plurality of preliminary hard mask patterns 130 may be arranged in a matrix form along the first direction and the second direction. A plurality of preliminary hard mask patterns 130 arranged in the first direction may overlap with the corresponding first conductive lines 110.

[0024] In an implementation, the initial hard mask pattern 130 may include a conductive material whose volume increases when reacting with a specific element. For example, the initial hard mask pattern 130 may include a metal or alloy that can expand when reacting with hydrogen. For example, the metal or alloy may include V, Pd, LaNi5, TiMn2, TiFe, or a combination thereof. It is well known that when each of V, Pd, LaNi5, TiMn2, and TiFe is exposed to H2 gas, it reacts with hydrogen and causes volume expansion, so a detailed description thereof will be omitted.

[0025] refer to Figure 2A and Figure 2B , the memory layer 120 may be etched using the initial hard mask pattern 130 as an etching barrier to form the memory pattern 122. In this process, a portion of the initial hard mask pattern 130 may be lost, and the thickness of the initial hard mask pattern 130 may be reduced. The initial hard mask pattern with a reduced thickness is represented by reference numeral 132. However, in some implementations, the loss of the initial hard mask pattern 130 may rarely occur. In this case, the initial hard mask pattern 130 is hardly lost, and therefore, most of the initial hard mask pattern 130 may be maintained.

[0026] In an implementation, the memory pattern 122 may have a columnar shape, and a plurality of memory patterns 122 may be arranged in a matrix along the first direction and the second direction. The plurality of memory patterns 122 arranged in the first direction may overlap with the first conductive line 110 and may be electrically connected to the first conductive line 110. The initial hard mask pattern 132 may be on and overlap with each memory pattern 122.

[0027] The etching process for forming the memory pattern 122 may be performed in various ways, such as ion beam etching (IBE) or reactive ion etching (RIE).

[0028] refer to Figure 3 2. Thus, the protective layer 140 may be formed to cover the sidewalls and upper surface of the initial hard mask pattern 132, the sidewalls of the memory pattern 122, and the upper surface of the first conductive line 110 not covered by the memory pattern 122.

[0029] The protective layer 140 may be used to prevent the hard mask pattern (see Figure 5A and Figure 5B ) is infiltrated into the memory pattern 122 and degrades the characteristics of the memory pattern 122. For example, if the memory pattern 122 includes a magnetic tunnel junction structure, it may be degraded due to exposure to hydrogen. By having a protective layer 140 over the memory pattern 122, the memory pattern 122 can be prevented from being exposed to hydrogen. Therefore, the protective layer 140 can prevent such degradation of the memory pattern 122. The protective layer 140 may include silicon nitride. However, the present disclosure is not limited thereto, and various insulating materials that can prevent elements such as hydrogen from penetrating into the memory pattern 122 may be used as the protective layer 140.

[0030] Subsequently, a second insulating layer 150 may be formed over the protective layer 140, the second insulating layer 150 having a thickness sufficient to cover the protective layer 140. The second insulating layer 150 may include an insulating material different from the protective layer 140, and may include an insulating material having a better gap-filling property than the protective layer 140. As an example, the second insulating layer 150 may include silicon oxide.

[0031] Subsequently, an upper portion of the second insulating layer 150 may be removed to form a second insulating pattern 152. After removing the upper portion of the second insulating layer 150, some portions of the protective layer 140 may be exposed. The removed upper portion of the second insulating layer 150 is indicated by a dotted line. An upper surface of the second insulating pattern 152 may be located at a height equal to or lower than a height of an uppermost surface of the protective layer 140. For reference, the uppermost surface of the protective layer 140 may refer to a surface that is located on an upper surface of the initial hard mask pattern 132 and has a maximum height from an upper surface of the substrate 100. In some implementations, an upper surface of the second insulating pattern 152 may be located at a height equal to or higher than a height of an upper surface of the memory pattern 122. If the height of the upper surface of the second insulating pattern 152 is lower than the height of the upper surface of the memory pattern 122, the uppermost surface of the protective pattern may also be lowered during a subsequent formation process of the protective pattern (see Figure 4 ), thereby exposing a portion of the sidewall of the memory pattern 122.

[0032] The removal of the upper portion of the second insulating layer 150 may be performed using a planarization process such as CMP, and may be performed by aiming to expose the upper surface of the protective layer 140 .

[0033] refer to Figure 4 , the portion of the protective layer 140 exposed by the second insulating pattern 152 may be removed to form a protective pattern 142 exposing the initial hard mask pattern 132. The uppermost surface of the protective pattern 142 may be located at a height equal to or lower than the height of the upper surface of the initial hard mask pattern 132. In some implementations, the uppermost surface of the protective pattern 142 may be located at a height higher than or equal to the height of the upper surface of the memory pattern 122. This is because, if the height of the upper surface of the protective pattern 142 is lower than the height of the upper surface of the memory pattern 122, a portion of the sidewall of the memory pattern 122 is exposed and cannot be protected by the protective pattern 142. In this embodiment, the upper surface of the second insulating pattern 152, the uppermost surface of the protective pattern 142, and the upper surface of the initial hard mask pattern 132 are located at substantially the same height to form a flat surface. However, the present disclosure is not limited thereto, and the heights of these upper surfaces may be slightly different from each other.

[0034] The partial removal of the protective layer 140 may be performed by a process such as etch-back and may be performed with the goal of exposing the upper surface of the preliminary hard mask pattern 132. Although not shown, after the partial removal of the protective layer 140, a cleaning process may be further performed to expose the upper surface of the preliminary hard mask pattern 132.

[0035] In the present embodiment, the partial removal of the second insulating layer 150 and the partial removal of the protective layer 140 are performed in separate processes. However, the present disclosure is not limited thereto, and the partial removal of the second insulating layer 150 and the partial removal of the protective layer 140 may be performed in a single process. Figure 3 After the second insulating layer 150 is formed, a planarization process may be performed on the second insulating layer 150 and the protective layer 140 to expose the upper surface of the initial hard mask pattern 132, and thus, the hard mask pattern 132 may be obtained. Figure 4 The process results are shown.

[0036] refer to Figure 5A and Figure 5B , Figure 4 The process result may be exposed to an element. The element has a property of expanding the volume of the initial hard mask pattern 132 by reacting with the initial hard mask pattern 132. Hereinafter, the element will be referred to as the first element. Assuming that the initial hard mask pattern 132 includes a metal or an alloy such as V, Pd, LaNi5, TiMn2, TiFe, or a combination thereof, the volume of the metal or alloy may expand when reacting with hydrogen. Figure 4 The process result may be exposed to a hydrogen-containing gas, such as H2 gas. By reacting with hydrogen, the volume of the initial hard mask pattern 132 may expand.

[0037] As a result of this process, a hard mask pattern 134 is formed that is larger than the initial hard mask pattern 132. The volume of the hard mask pattern 134 is larger than the volume of the initial hard mask pattern 132. Therefore, the hard mask pattern 134 has an increased volume compared to the initial hard mask pattern 132.

[0038] The hard mask pattern 134 may include the constituent elements of the initial hard mask pattern 132 and the first element. For example, the hard mask pattern 134 may include a material including a metal or alloy forming the initial hard mask pattern 132 and hydrogen. For example, the hard mask pattern 134 may include a hydride of the metal or alloy. The hard mask pattern 134 may still be conductive. In one example, the hydride of the metal or alloy forming the hard mask pattern 134 may be conductive.

[0039] The expansion of the initial hard mask pattern 132 may initially occur in the vertical direction, and therefore, the thickness may expand. This is because the sidewalls of the initial hard mask pattern 132 are surrounded by the protection pattern 142. When the initial hard mask pattern 132 expands to form a portion protruding upward, by using the protruding portion that has been formed by the initial expansion in the vertical direction, the expansion proceeds in the horizontal direction as well as in the vertical direction. Therefore, expansion of the thickness and width may occur. As a result, a portion such as Figure 6B1. The hard mask pattern 134 is shown. The hard mask pattern 134 may include a lower hard mask pattern 134A whose sidewall is surrounded by the protection pattern 142 and an upper hard mask pattern 134B located above the lower hard mask pattern 134A and having a width greater than that of the lower hard mask pattern 134A. The sidewall of the lower hard mask pattern 134A may be aligned with the sidewall of the memory pattern 122. The thickness of the hard mask pattern 134 may be greater than that of the initial hard mask pattern 132, and the width of the upper hard mask pattern 134B may be greater than that of the initial hard mask pattern 132. The width of the lower hard mask pattern 134A may be substantially the same as that of the initial hard mask pattern 132.

[0040] The upper hard mask pattern 134B may be positioned above the protection pattern 142 and the second insulating pattern 152 in the vertical direction. Since the width of the upper hard mask pattern 134B is greater than the width of the lower hard mask pattern 134A, the upper hard mask pattern 134B may cover at least a portion of the uppermost surface of the protection pattern 142. In this embodiment, the upper hard mask pattern 134B is shown as covering the entire uppermost surface of the protection pattern 142 and having a sidewall aligned with the outer sidewall of the protection pattern 142, but the present disclosure is not limited thereto. As long as the upper hard mask pattern 134B covers at least a portion of the uppermost surface of the protection pattern 142, the width of the upper hard mask pattern 134B may be adjusted in various ways. For example, in another embodiment, the upper hard mask pattern 134B may have a width smaller than the width shown to cover a portion of the uppermost surface of the protection pattern 142, or may have a width larger than the width shown to cover the entire uppermost surface of the protection pattern 142 and a portion of the upper surface of the second insulating pattern 152. Even in this case, the width of the upper hard mask pattern 134B may be limited not to be connected to and / or not to contact another upper hard mask pattern 134B adjacent thereto in the first direction or the second direction.

[0041] refer to Fig. 6A and Figure 6B , you can Figure 5A and Figure 5B A second conductive line 160 extending in the second direction is formed on the result of the process of forming the second conductive line 160. A plurality of second conductive lines 160 may be arranged to be spaced apart from each other in the first direction. The second conductive line 160 may overlap and be electrically connected to a plurality of memory patterns 122 arranged in the second direction. The second conductive line 160 may not directly contact the memory pattern 122, but may be electrically connected to the memory pattern 122 through the hard mask pattern 134.

[0042] The space between the second conductive lines 160 may be provided for forming the third insulating layer 165. Therefore, the space between the second conductive lines 160 may be filled with the third insulating layer 165. In one example, the second conductive lines 160 and the third insulating layer 165 may be formed by: Figure 5A and Figure 5B A conductive material for forming the second conductive line 160 is deposited on the process result of the present invention, the conductive material is selectively etched to form the second conductive line 160, a sufficiently thick insulating material is deposited to cover the second conductive line 160 while filling the space between the second conductive lines 160, and a planarization process such as CMP is performed to expose the upper surface of the second conductive line 160. Alternatively, as another example, the second conductive line 160 and the third insulating layer 165 may be formed by: Figure 5A and Figure 5B An insulating material for forming a third insulating layer 165 is deposited on the process result of the present invention, the insulating material is selectively etched to form the third insulating layer 165, the third insulating layer 165 provides a space in which the second conductive line 160 will be filled, a conductive material thick enough to cover the third insulating layer 165 is deposited while filling the space, and a planarization process is performed to expose the upper surface of the third insulating layer 165. The second conductive line 160 may include at least one conductive material of various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. The third insulating layer 165 may include at least one insulating material of various insulating materials, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0043] Since the second conductive line 160 is formed on the second insulating pattern 152 and the hard mask pattern 134 protruding above the second insulating pattern 152, the height of the lower surface of the portion of the second conductive line 160 in the area overlapping with the hard mask pattern 134 can be higher than the height of the lower surface of the remaining portion of the second conductive line 160.

[0044] By the above manufacturing method, it is possible to manufacture Fig. 6A and Figure 6B The semiconductor device shown.

[0045] Reference again Fig. 6A and Figure 6BThe semiconductor device of this embodiment may include a substrate 100, a plurality of first conductive lines 110 disposed on the substrate 100 and extending in a first direction, a plurality of second conductive lines 160 disposed on the plurality of first conductive lines 110 and extending in a second direction, a plurality of memory patterns 122 respectively overlapping intersection areas between the plurality of first conductive lines 110 and the plurality of second conductive lines 160, a hard mask pattern 134 of a stacked structure that overlaps with each of the memory patterns 122 and includes a lower hard mask pattern 134A and an upper hard mask pattern 134B, and a protection pattern 142 covering a sidewall of the lower hard mask pattern 134A and a sidewall of the memory pattern 122.

[0046] Here, the upper hard mask pattern 134B may protrude above the protection pattern 142, and the width of the upper hard mask pattern 134B may be greater than the width of the lower hard mask pattern 134A. The upper hard mask pattern 134B may cover at least a portion of the uppermost surface of the protection pattern 142. In addition, the upper hard mask pattern 134B may also cover a portion of the upper surface of the second insulating pattern 152 filling the space defined by the protection pattern 142. In addition, the hard mask pattern 134 may include a conductive material and a specific element that increases the volume of the conductive material. For example, the hard mask pattern 134 may include a metal or alloy such as V, Pd, LaNi5, TiMn2, TiFe, or a combination thereof, and hydrogen for increasing the volume of the metal or alloy.

[0047] Since the components of the semiconductor device of the present embodiment have been described in detail in the process of explaining the above-mentioned manufacturing method, further detailed description will be omitted.

[0048] According to the implementation of the semiconductor device and the method for manufacturing the same, the following advantages can be obtained.

[0049] Even if the thickness of the initial hard mask pattern 132 remaining after etching the memory layer 120 is thin, the volume of the initial hard mask pattern 132 may expand, and then the second conductive line 160 may be formed. Therefore, alignment between the hard mask pattern 134 and the second conductive line 160 may be facilitated. In addition, even if misalignment occurs between the hard mask pattern 134 and the second conductive line 160, defects due to the misalignment may be reduced and / or prevented. This will be examined in more detail with reference to a comparative example described below.

[0050] Figure 8 is a cross-sectional view showing a semiconductor device of a comparative example.

[0051] refer to Figure 8The semiconductor device of the comparative example may include a substrate 10, a first conductive line 11, a memory pattern 12, a hard mask pattern 13, a protection pattern 14, an insulating pattern 15, and a second conductive line 16. The difference from the present embodiment is that the second conductive line 16 is formed in the process of performing the Figure 4 The hard mask pattern 12 is formed immediately after the process substantially the same as the process of the hard mask pattern 13 without any expansion of the hard mask pattern 13. In this case, the width of the hard mask pattern 13 is small, and thus the possibility of misalignment with the second conductive line 16 increases. In addition, as shown in the figure, when misalignment occurs between the hard mask pattern 13 and the second conductive line 16, a portion of the hard mask pattern 13 exposed by the second conductive line 16 may be lost in the etching process of the conductive material for forming the second conductive line 16. In this case, since the thickness of the hard mask pattern 13 is small, the loss of the memory pattern 12 may occur due to the loss of the hard mask pattern 13. As a result, the characteristics of the memory pattern 12 may be adversely affected.

[0052] In the present embodiment, since the second conductive line 160 is formed above the hard mask pattern 134, the thickness and width of the hard mask pattern 134 are expanded by the expansion of the initial hard mask pattern 132, and thus the alignment between the upper hard mask pattern 134B and the second conductive line 160B can be easier than in the comparative example. In addition, even if misalignment occurs between the second conductive line 160 and the hard mask pattern 134 so that the hard mask pattern 134 is lost, the thickness of the hard mask pattern 134 is greater than that of the comparative example, and therefore, the possibility of exposure and loss of the memory pattern 120 can be reduced.

[0053] In addition, in the present embodiment, since the expansion process of the initial hard mask pattern 132 occurs, the initial hard mask pattern 132 having a certain thickness can be designed more flexibly without greatly increasing the thickness of the initial hard mask pattern 130. As long as the initial hard mask pattern 132 remains on the memory pattern 122 with a thin thickness after the memory layer 120 is etched, the thickness of the initial hard mask pattern 132 can be sufficient. If the thickness of the initial hard mask pattern 130 is too large, there is an undesirable problem due to the shadow effect occurring in the IBE process, which not only blocks the etched area but also blocks the adjacent area, making it difficult to perform the etching process. However, in the present embodiment, since the thickness of the initial hard mask pattern 130 does not need to be increased, the undesirable problem caused by the shadow effect in the IBE process can be avoided and prevented.

[0054] Therefore, according to the implementation of the semiconductor device and the manufacturing method thereof according to the present embodiment, the characteristics of the semiconductor device can be ensured, and process defects can be prevented and / or reduced.

[0055] Fig. 9is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. Figures 1A to 6B The differences between the embodiments.

[0056] refer to Fig. 9 , can be executed with the above Figures 1A to 5B The process is basically the same as the process of the process to obtain a structure including the substrate 200, the first conductive line 210, the first insulating layer 215, the memory pattern 222, the hard mask pattern 234 including the lower hard mask pattern 234A and the upper hard mask pattern 234B, the protection pattern 242 and the second insulating pattern 252.

[0057] Subsequently, after depositing an insulating material covering the second insulating pattern 252 and the hard mask pattern 234, a planarization process may be performed to expose the upper surface of the hard mask pattern 234. As a result, a fourth insulating layer 268 may be formed to fill the space between the upper hard mask patterns 234B. The upper surface of the fourth insulating layer 268 and the upper surface of the hard mask pattern 234 may form a planar surface located at substantially the same height.

[0058] Subsequently, a process for forming the second conductive line 260 and the third insulating layer 265 may be performed. Since a flat surface is located below the second conductive line 260 and the third insulating layer 265, a deposition process, an etching process, etc. for forming the second conductive line 260 and the third insulating layer 265 may be performed more easily.

[0059] In this embodiment, a fourth insulating layer 268 filling the space between the upper hard mask patterns 234B and having an upper surface forming a flat surface with the upper surface of the hard mask pattern 234 can also be inserted between the second conductive wire 260 and the second insulating pattern 252, and therefore, the height of the lower surface of the second conductive wire 260 can be basically constant.

[0060] Fig.10 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. Figures 1A to 6B The differences between the embodiments.

[0061] refer to Fig.10 , can be executed with the above Figures 1A to 5B A process substantially the same as the process of the process to obtain a structure including a substrate 300, a first conductive line 310, a first insulating layer 315, a memory pattern 322, a hard mask pattern 334 including a lower hard mask pattern 334A and an upper hard mask pattern 334B, a protection pattern 342 and a second insulating pattern 352.

[0062] Subsequently, after depositing an insulating material covering the second insulating pattern 352 and the hard mask pattern 334, the insulating material may be selectively etched to form a fourth insulating layer 370 having a hole H1 exposing the hard mask pattern 334. Even when the hole H1 is formed, the width of the upper hard mask pattern 334B may be increased, and thus, alignment between the hole H1 and the upper hard mask pattern 334B may be facilitated. Even if misalignment occurs between the upper hard mask pattern 334B and the hole H1 and the hard mask pattern 334 is lost, the thickness of the hard mask pattern 334 has been increased, and thus the possibility of exposure and loss of the memory pattern 322 may be reduced.

[0063] Subsequently, after forming a conductive material thick enough to fill the hole H1, a planarization process may be performed to expose the upper surface of the fourth insulating layer 370. As a result, a contact plug 380 may be formed. The contact plug 380 may fill the hole H1 and may have an upper surface that forms a flat surface with the upper surface of the fourth insulating layer 370. The contact plug 380 may have a columnar shape overlapping the hard mask pattern 334.

[0064] Subsequently, a process for forming the second conductive line 360 ​​and the third insulating layer 365 may be performed. Since a flat surface is located below the second conductive line 360 ​​and the third insulating layer 365, a deposition process, an etching process, etc. for forming the second conductive line 360 ​​and the third insulating layer 365 may be performed more easily.

[0065] In an implementation of the semiconductor device, the contact plug 380 may be interposed between the second conductive line 360 ​​and the hard mask pattern 334, and the second conductive line 360 ​​and the hard mask pattern 334 may be electrically connected through the contact plug 380. Since the fourth insulating layer 370 filling the space between the contact plugs 380 has an upper surface forming a flat surface with the upper surface of the contact plug 380, the height of the lower surface of the second conductive line 360 ​​located on the flat surface may be substantially constant.

[0066] Although not shown, another contact plug may be further interposed between the first conductive line 310 and the memory pattern 322 to electrically connect them. The space between the contact plugs may be filled with an insulating material.

[0067] In some implementations, the protection pattern may be omitted. In various cases, the protection pattern may be skipped, for example, when the memory layer does not contain magnetic material and the first element, such as hydrogen, does not significantly affect the memory layer, or when the memory layer contains magnetic material but the first element does not affect the magnetic material. This will refer to Fig.11 and Fig.12 The description is given by way of example.

[0068] Fig.11 and Fig.12 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. Figures 1A to 6B The differences between the embodiments.

[0069] refer to Fig.11 , can be executed with the above Figures 1A to 2B The process is substantially the same as the process of the present invention to obtain a structure including the substrate 400, the first conductive line 410, the memory pattern 422 and the preliminary hard mask pattern 432.

[0070] Subsequently, a second insulating layer 450 having a thickness sufficiently covering the above structure may be formed.

[0071] Subsequently, the upper portion of the second insulating layer 450 may be removed to form a second insulating pattern 452 exposing the initial hard mask pattern 432. The removed upper portion of the second insulating layer 450 is indicated by a dotted line. The removal of the upper portion of the second insulating layer 450 may be performed by a planarization process so that the upper surface of the second insulating pattern 452 is positioned at substantially the same height as the upper surface of the initial hard mask pattern 432.

[0072] refer to Fig.12 , Fig.11 The process result may be exposed to the first element that may expand the initial hard mask pattern 432. As a result of the process, a hard mask pattern 434 that is expanded more than the initial hard mask pattern 432 may be formed. The hard mask pattern 434 may include a lower hard mask pattern 434A whose sidewall is surrounded by the second insulating pattern 452 and an upper hard mask pattern 434B that is located above the lower hard mask pattern 434A and has a width greater than that of the lower hard mask pattern 434A. The upper hard mask pattern 434B may protrude above the second insulating pattern 452 and cover a portion of an upper surface of the second insulating pattern 452.

[0073] Subsequently, a process for forming the second conductive line 460 and the third insulating layer 465 may be performed.

[0074] The semiconductor device of this embodiment is different from the above-mentioned embodiments in that the protection pattern is omitted.

[0075] In the above-mentioned embodiments, a semiconductor device having a cross-point structure has been described, in which a columnar memory pattern is inserted between two conductive lines that are spaced apart from each other in the vertical direction and intersect each other in the horizontal direction. However, the present disclosure is not limited thereto. The present disclosure can be applied to any structure formed by providing an etching target layer, etching the etching target layer using a conductive hard mask pattern as an etching barrier to form a pattern having a specific shape, and forming another conductive pattern on the conductive hard mask pattern to be electrically connected to the pattern through the conductive hard mask pattern. That is, the device of the present embodiment may include: a substrate; a pattern disposed on the substrate; a conductive hard mask pattern disposed on the pattern and including a lower hard mask pattern and an upper hard mask pattern on the lower hard mask pattern; a conductive pattern disposed on the hard mask pattern and electrically connected to the pattern through the hard mask pattern; and an insulating layer covering the sidewalls of the pattern and the sidewalls of the lower hard mask pattern, wherein the upper hard mask pattern protrudes above the insulating layer. In addition, the manufacturing method of the semiconductor device of the present embodiment may include: forming an etching target layer to be etched on a substrate; forming a conductive initial hard mask pattern above the etching target layer; forming a pattern by etching the etching target layer using the initial hard mask pattern as an etching barrier; forming an insulating layer that fills a space between the pattern and another pattern and exposes the initial hard mask pattern, the other pattern being adjacent to the pattern; exposing the initial hard mask pattern to a first element to form a hard mask pattern, the hard mask pattern having a volume larger than that of the initial hard mask pattern; and forming a conductive pattern above the hard mask pattern. In the above Figures 1A to 6B and Figures 9 to 12 In the embodiment of the present invention, the memory layer 110 may correspond to the etching target layer, the memory patterns 122, 222, 322 and 422 may correspond to the patterns, the hard mask patterns 134, 234, 334 and 434 may correspond to the conductive hard mask patterns, and the second conductive lines 160, 260, 360 and 460 may correspond to the conductive patterns. However, the type or shape of the etching target layer and the pattern may be modified in various ways. For example, the pattern may have a columnar shape, a linear shape, etc. When the pattern has a linear shape, the conductive hard mask pattern also has a linear shape overlapping the pattern, and the width of the upper portion of the conductive hard mask pattern in the direction intersecting the line may be greater than the width of the lower portion of the conductive hard mask pattern. In addition, the type or shape of the conductive pattern may be modified in various ways. For example, the conductive pattern may have a columnar shape, a linear shape, etc.

[0076] According to the above-described embodiments of the present disclosure, characteristics of a semiconductor device may be ensured and process defects may be prevented and / or reduced.

[0077] Although various embodiments are described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made to the disclosed examples or embodiments and / or other embodiments based on what is described and / or illustrated in this patent document.

Claims

1. A semiconductor device comprising: substrate; A pattern is disposed on the substrate; a hard mask pattern that is conductive and disposed over the pattern, the hard mask pattern comprising a lower hard mask pattern and an upper hard mask pattern over the lower hard mask pattern; a conductive pattern disposed over the hard mask pattern and electrically connected to the pattern through the hard mask pattern; as well as an insulating layer covering the sidewalls of the pattern and the sidewalls of the lower hard mask pattern, wherein the upper hard mask pattern is disposed to protrude from the insulating layer. 2 . The semiconductor device of claim 1 , wherein a width of the upper hard mask pattern is greater than a width of the lower hard mask pattern. 3 . The semiconductor device of claim 1 , wherein the sidewall of the lower hard mask pattern and the sidewall of the pattern are aligned with each other.

4. The semiconductor device according to claim 1, wherein: The hard mask pattern includes a conductive material and a first element, and The first element has a property of increasing the volume of the conductive material when the first element reacts with the conductive material.

5. The semiconductor device according to claim 4, wherein: The conductive material includes V, Pd, LaNi5, TiMn2, TiFe or a combination thereof, and The first element includes hydrogen. 6 . The semiconductor device of claim 1 , wherein the insulating layer comprises a protection pattern formed along a sidewall of the pattern and a sidewall of the lower hard mask pattern, and an insulating pattern filling a space defined by the protection pattern. 7 . The semiconductor device according to claim 6 , wherein the upper hard mask pattern covers at least a portion of an upper surface of the protection pattern. 8 . The semiconductor device according to claim 1 , wherein the upper hard mask pattern covers a portion of an upper surface of the insulating layer.

9. The semiconductor device according to claim 1, wherein: The pattern comprises a memory pattern, The substrate includes a first conductive line extending in a first direction and electrically connected to the pattern, and The conductive pattern includes a second conductive line extending in a second direction intersecting the first direction. 10 . The semiconductor device of claim 9 , wherein the second conductive line is disposed along an upper surface of the insulating layer and a surface of the upper hard mask pattern.

11. The semiconductor device according to claim 9, further comprising: an additional insulating layer disposed over the insulating layer and having an upper surface forming a flat surface with an upper surface of the upper hard mask pattern, The second conductive line is disposed on the flat surface.

12. The semiconductor device according to claim 9, further comprising: an additional insulating layer covering the insulating layer and the upper hard mask pattern; as well as a contact plug penetrating the additional insulating layer and contacting the upper hard mask pattern, The second conductive line is disposed over the additional insulating layer and the contact plug, and is connected to the upper hard mask pattern through the contact plug.

13. The semiconductor device according to claim 1, wherein the pattern comprises a magnetic tunnel junction structure.

14. A method for manufacturing a semiconductor device, comprising: forming an etching target layer over a substrate; forming an initial hard mask pattern over the etch target layer, the initial hard mask pattern comprising a conductive material; forming a pattern by etching the etch target layer using the initial hard mask pattern as an etch barrier; forming an insulating layer filling a space between the pattern and another pattern adjacent to the pattern and exposing the initial hard mask pattern; exposing the initial hard mask pattern to a first element to form a hard mask pattern having a volume greater than a volume of the initial hard mask pattern; as well as A conductive pattern is formed over the hard mask pattern. 15 . The method of claim 14 , wherein the conductive material of the preliminary hard mask pattern has a property that a volume of the conductive material increases when the conductive material reacts with the first element.

16. The method of claim 15, wherein: The conductive material includes V, Pd, LaNi5, TiMn2, TiFe or a combination thereof, and The first element includes hydrogen. 17 . The method of claim 14 , wherein the hard mask pattern has a thickness greater than a thickness of the initial hard mask pattern.

18. The method of claim 14, wherein the hard mask pattern comprises a lower hard mask pattern having a sidewall surrounded by the insulating layer and an upper hard mask pattern located above the lower hard mask pattern and protruding from the insulating layer. 19 . The method of claim 18 , wherein a width of the upper hard mask pattern is greater than a width of the lower hard mask pattern.

20. The method of claim 14, wherein: The pattern comprises a memory pattern, The substrate includes a first conductive line extending in a first direction and electrically connected to the pattern, and The conductive pattern includes a second conductive line extending in a second direction intersecting the first direction.

Images