Resistive random access memory structure and manufacturing method thereof

Abstract

The invention provides a resistive random access memory (RRAM) structure and a manufacturing method thereof. The resistive random access memory structure comprises a lower electrode located on a substrate, a resistance conversion layer located on the lower electrode, and an upper electrode located on the resistance conversion layer, and the resistive random access memory structure is provided with a flat top surface and two inclined side walls from a cross-sectional view, the maximum width of the resistance conversion layer is larger than the maximum width of the upper electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a side view pattern structure of a resistive random access memory (RRAM) unit and a manufacturing method thereof. Background Art

[0002] Resistive random access memory (RRAM) has the advantages of simple structure, low operating voltage, high operating speed, good durability and compatibility with CMOS process. RRAM is the most promising alternative to traditional flash memory to achieve the purpose of reducing the size of components. RRAM is being widely used in various components such as optical disks and non-volatile memory arrays.

[0003] RRAM cells store data in a material layer that can be induced to undergo phase change. The physical mechanism of RRAM that has attracted more attention at present is the Filament Theory. In all or part of the layers, the material can induce a phase change and switch between a high resistance state and a low resistance state. After different resistance states are detected, they can be represented as "0" or "1". In a typical RRAM cell, the data storage layer includes an amorphous metal oxide. After applying sufficient voltage, the voltage can form a metal bridge across the data storage layer, thus forming a low resistance state. Then, by applying a high current density pulse or otherwise, all or part of the metal structure can be decomposed or melted, the metal bridge can be broken, and the high resistance state can be restored. Then, when the data storage layer is rapidly cooled, it will change from a high resistance state to a low resistance state again. Summary of the invention

[0004] The present invention provides a resistance random access memory (RRAM) structure, comprising a lower electrode located on a substrate, a resistance conversion layer located on the lower electrode, and an upper electrode located on the resistance conversion layer, wherein from a cross-sectional view, the resistance random access memory structure has a flat top surface and two inclined side walls, and a maximum width of the resistance conversion layer is greater than a maximum width of the upper electrode.

[0005] The present invention also provides a method for manufacturing a resistive random access memory (RRAM) structure, comprising forming a lower electrode located on a substrate, forming a resistive conversion layer located on the lower electrode, and forming an upper electrode located on the resistive conversion layer, wherein from a cross-sectional view, the resistive random access memory structure has a flat top surface and two inclined side walls, and a maximum width of the resistive conversion layer is greater than a maximum width of the upper electrode.

[0006] The present invention provides a resistive random access memory (RRAM) cell structure and a manufacturing method thereof, characterized in that the structure of the RRAM cell is designed to be narrower on the top surface and wider on the bottom, and the cross section of the lower electrode is triangular, and the width of the lower electrode is smaller than the width of the upper electrode. When the RRAM cell of this structure is in operation, the electric field generated on the top surface will be more concentrated, so the reading and writing rates of the RRAM cell in operation can be accelerated, and the quality of the component can be improved. In addition, during the manufacturing process, the lower electrode can be completely covered by other materials to obtain better protection, thereby improving the reliability of the component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 10 A cross-sectional structure diagram of a resistive random access memory (RRAM) cell of the present invention is shown.

[0008]

Main component symbol description

[0009] 100: Resistive Random Access Memory (RRAM) Cell

[0010] 102: Contact structure

[0011] 102A: cushion layer

[0012] 102B: Conductive layer

[0013] 103: Dielectric layer

[0014] 104: Dielectric layer

[0015] 106: Intermetallic dielectric layer

[0016] 110: Lower electrode material layer

[0017] 110A: Lower electrode

[0018] 111: resistance conversion layer

[0019] 112: First material layer

[0020] 112A: Patterning the first material layer

[0021] 114: Second material layer

[0022] 114A: Patterning the second material layer

[0023] 116: Third material layer

[0024] 116A: cushion layer

[0025] 118: Fourth material layer

[0026] 118A: Upper electrode

[0027] 120: side wall sub-material layer

[0028] 120A: Side wall

[0029] 122: Dielectric layer

[0030] 124: Dielectric layer

[0031] 126: cushion layer

[0032] 128: Conductive layer

[0033] E1: First Etching Step

[0034] E2: Second Etching Step

[0035] E3: The third etching step

[0036] E4: Fourth Etching Step

[0037] M1: First metal layer

[0038] M2: Contact structure (second metal layer)

[0039] P: Raised part

[0040] T1: Top surface

[0041] S1: Sloped sidewall

[0042] S2: Sloped sidewall

[0043] S3: Sidewall

[0044] S4: Sidewall

[0045] W1: Width

[0046] W2: Width

[0047] W3: Width DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0049] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative components in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can all be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.

[0050] The present invention provides a resistive random access memory (RRAM) unit, each RRAM unit is located on a contact structure. The contact structure may be located in an intermetal dielectric (IMD). As shown in the following schematic diagram:

[0051] Please refer to Figure 1 , Figure 1 A schematic cross-sectional structure diagram of a resistive random access memory (RRAM) cell located on a contact structure is shown. Figure 1 As shown, a contact structure 102 is first provided. The contact structure 102 may be located in a single-layer or multi-layer dielectric layer, and may be electrically connected to another contact structure or wire below. Taking this embodiment as an example, the contact structure 102 is located in a dielectric layer 103 and a dielectric layer 104. The dielectric layer 103 is, for example, a nitrogen doped carbide dielectric layer (NDC), and the dielectric layer 104 is, for example, an insulating layer such as silicon monoxide, silicon nitride, or silicon oxynitride. The contact structure 102 includes a liner layer 102A located at the bottom and a conductive layer 102B located at the top, wherein the liner layer 102A is, for example, titanium nitride (TiN) or tantalum nitride (TaN). The liner layer 102A is first formed, and the conductive layer 102B formed subsequently can be preferably formed on the liner layer 102A. The material of the conductive layer 102B can include metals such as tungsten, cobalt, copper, aluminum, or other conductive materials, but the present invention is not limited thereto.

[0052] Please continue to refer to Figure 1 , under the contact structure 102, there may also be another first metal layer M1 located in an intermetallic dielectric layer 106, and the contact structure 102 is electrically connected to the first metal layer M1. The first metal layer M1 and the contact structure 102 are, for example, wires or conductive vias located in the IMD. The first metal layer M1 may be one of the multiple metal layers in the semiconductor stack structure, and there may be electronic components such as transistors connected thereto. For the sake of simplicity in the drawings, other material layers or electronic components under the first metal layer M1 are not shown, but those skilled in the art should understand that Figure 1 The semiconductor structure shown may include other electronic components or material layers underneath.

[0053] Then, an RRAM cell is formed above the contact structure 102. The dielectric layer 104 and the contact structure 102 are first planarized by, for example, chemical mechanical polishing (CMP), and then a lower electrode material layer 110 is formed, wherein the material of the lower electrode material layer 110 may be metal, metal oxide or polysilicon, for example, it may be selected from a combination of aluminum, titanium, tantalum, gold, platinum, tungsten, nickel, iridium, copper or copper-aluminum alloy. In other embodiments, for example, it is titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN). In other embodiments, for example, it is P+ doped polysilicon or N+ doped polysilicon. In this embodiment, the lower electrode material layer 110 takes titanium nitride (TiN) as an example, but the present invention is not limited to this.

[0054] Then as Figure 2 As shown, a first etching step E1 is performed to partially remove the lower electrode material layer 110 and form a lower electrode 110A. In this embodiment, the lower electrode 110A has a triangular or trapezoidal cross-sectional pattern after being etched. Figure 2 The trapezoid is taken as an example, but the triangular shape 110A also falls within the scope of the present invention. Specifically, a patterned photoresist (not shown) can be formed on the lower electrode material layer 110, and the lower electrode material layer 110 can be divided into a plurality of independent blocks that do not contact each other, and then etched in an isotropic manner. At this time, the portion covered by the patterned photoresist will be etched more slowly, while the portion not covered by the patterned photoresist will be etched more quickly. Therefore, after the etching is completed, the following can be formed: Figure 2 The bottom electrode 110A shown has a triangular or trapezoidal cross section. It should be noted that the above method of forming the bottom electrode 110A by isotropic etching is only one example of the present invention. If the bottom electrode with a similar structure is formed by other methods, it also falls within the scope of the present invention.

[0055] like Figure 3 As shown, a first material layer 112, a second material layer 114, a third material layer 116 and a fourth material layer 118 are sequentially stacked from bottom to top. The first material layer 112 and the second material layer 114 are used to form a resistance conversion layer in a subsequent step, and the material thereof includes, for example, titanium oxide (TiO), nickel oxide (NiO), tungsten oxide (WO3), zirconium oxide (ZrO), copper oxide (CuO), hafnium oxide (HfO), tantalum oxide (TaO), zinc oxide (ZnO), aluminum oxide (Al2O3), molybdenum oxide (MoO), etc., but is not limited thereto. In this embodiment, the first material layer 112 is hafnium oxide and the second material layer 114 is aluminum oxide, but the present invention is not limited thereto.

[0056] The third material layer 116 can be used to form a liner layer of the upper electrode in a subsequent step, and the fourth material layer 118 can be used to form the upper electrode in a subsequent step. The third material layer 116 and the fourth material layer 118 can be made of the same material as the lower electrode, for example, aluminum, titanium, tantalum, gold, platinum, tungsten, nickel, iridium, copper or a combination of copper and aluminum alloys. In other embodiments, for example, titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN). In other embodiments, for example, P+ doped polysilicon or N+ doped polysilicon. In this embodiment, the third material layer 116 is made of titanium, and the fourth material layer 118 is made of titanium nitride (TiN), but the present invention is not limited thereto.

[0057] like Figure 4 As shown, a second etching step E2 is performed to remove a portion of the fourth material layer 118 and the third material layer 116 to form the upper electrode 118A and the liner layer 116A, and to expose a portion of the surface of the second material layer 114. It is worth noting that, since the lower electrode 110A has a triangular or trapezoidal profile, the first material layer 112, the second material layer 114, the third material layer 116 and the fourth material layer 118 are conformally stacked on the lower electrode 110A, so that the first material layer 112 and the second material layer 114 form a protruding portion P, and the liner layer 116A and the upper electrode 118A are located on the protruding portion P.

[0058] In addition, in the present embodiment, the upper electrode 118A has a flat top surface T1 and two inclined side walls S1 and S2, wherein the upper portion of the inclined side wall S1 or S2 is closer to the vertical center line of the RRAM cell, and the lower portion of the inclined side wall S1 or S2 is farther from the vertical center line of the RRAM cell. In other words, from the cross-sectional view, the upper electrode 118A has a profile similar to the "A" shape (but the top is preferably a flat surface rather than a sharp corner). This structure is beneficial for making the electric field of the subsequently formed RRAM cell more concentrated on the top surface during operation, which can improve the operating speed of the overall RRAM element.

[0059] like Figure 5 As shown, a side wall sub-material layer 120 is then formed to cover the top surface T1 and the inclined side walls S1 and S2 of the upper electrode 118A. In this embodiment, the material selected for the side wall sub-material layer 120 is, for example, aluminum oxide, which can be the same as the second material layer 114, but the present invention is not limited thereto. Since a portion of the second material layer 114 is exposed after the aforementioned second etching step E2, the side wall sub-material layer 120 formed here will directly contact a portion of the second material layer 114.

[0060] like Figure 6As shown, a dielectric layer 122 is formed to cover the sidewall sub-material layer 120, wherein the thickness of the dielectric layer 122 is higher than the top surface of the sidewall sub-material layer 120, and then as shown in FIG. Figure 7 As shown, a third etching step E3 is performed to etch back the dielectric layer 122. It is worth noting that at this time, part of the dielectric layer 122 is still left in the gap between adjacent RRAM units. The dielectric layer 122 here can be made of tetraethoxysilane (TEOS), wherein TEOS has a better gap filling ability, so the dielectric layer 122 can penetrate into the gap between two RRAM units.

[0061] like Figure 8 As shown, a fourth etching step E4 is performed to remove part of the sidewall sub-material layer 120 and expose the top surface of the upper electrode 118A, so that the sidewall sub-material layer 120 is segmented into two sidewall sub-layers 120A, which are respectively located on the two inclined sidewalls S1 and S2 of the upper electrode 118A. In addition, during the etching step E4, the first material layer 112 and the second material layer 114 can be patterned together, that is, the first material layer 112 and the second material layer 114 are partially removed to form a patterned first material layer 112A and a patterned second material layer 114A, both of which can be regarded as the resistance conversion layer 111. In this step, the RRAM unit is disconnected from other adjacent components (other components originally connected to the first material layer 112 and the second material layer 114) to define the position of the RRAM unit. In addition, the area of ​​the patterned first material layer 112A and the patterned second material layer 114A are equal, and the sidewalls (such as Figure 8 The side wall S3 and the side wall S4 are flush with each other.

[0062] like Fig. 9 As shown, a dielectric layer 124 is formed to cover the dielectric layer 122 and the RRAM unit, wherein the dielectric layer 124 is, for example, an ultra low-k (ULK) dielectric material, and its dielectric constant is preferably lower than 2.9, but not limited thereto. Commonly used ULK materials may include Black Diamond (a carbon-doped silicon oxide low dielectric constant material introduced by Applied Materials), MSQ (methylsilsesquioxane), porous SiLK (a low dielectric constant material developed by Dow Chemical), etc., but not limited thereto.

[0063] In addition, in other embodiments of the present invention, the dielectric layer 122 and the dielectric layer 124 may also be formed of insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, and a single-layer dielectric layer may be used to replace the dielectric layer 122 and the dielectric layer 124 here. This structure also falls within the scope of the present invention.

[0064] like Fig.10 As shown, a contact structure (second metal layer) M2 is then formed on the top surface of the upper electrode 118A, wherein the contact structure M2 may include a pad layer 126 and a conductive layer 128, wherein the pad layer 126 is, for example, titanium nitride (TiN) or tantalum nitride (TaN), etc., and the conductive layer 128 can be preferably formed on the pad layer 126. The material of the conductive layer 128 may include metals such as tungsten, cobalt, copper, aluminum, or other conductive materials, but the present invention is not limited thereto.

[0065] like Fig.10 As shown, the RRAM cell 100 includes a lower electrode 118A, a resistance switching layer 111, a liner 116A, an upper electrode 118A and a sidewall 120A. The width W1 of the top surface of the RRAM cell is smaller than its maximum width W2 (i.e., the width of the resistance switching layer 111), but it is worth noting that the width W3 of the lower electrode 110A is also smaller than the width W2 of the resistance switching layer 111.

[0066] Since the RRAM cell of the present invention is designed to have a structure with a narrower top surface and a wider bottom surface, the electric field can be concentrated on the top when the RRAM is operating. In this way, the contact structure M2 touching the top surface of the RRAM cell can speed up the signal transmission speed and improve the operating efficiency of the device.

[0067] In summary, the present invention provides a resistive random access memory (RRAM) structure, including a lower electrode 110A located on a substrate (e.g., a dielectric layer 104), a resistive switching layer 111 located on the lower electrode 110A, and an upper electrode 118A located on the resistive switching layer 111. From a cross-sectional view, the resistive random access memory structure has a flat top surface T1 and two inclined sidewalls S1 and S2, and a maximum width W2 of the resistive switching layer 111 is greater than a maximum width W1 of the upper electrode 118A.

[0068] In some embodiments of the present invention, the bottom electrode 110A has a triangular or trapezoidal cross-sectional structure.

[0069] In some embodiments of the present invention, the resistance conversion layer 111 includes a multi-layer structure, and the multi-layer structure includes a first material layer 112A and a second material layer 114A stacked from bottom to top.

[0070] In some embodiments of the present invention, the first material layer 112A includes chromium oxide, and the second material layer 114A includes aluminum oxide.

[0071] In some embodiments of the present invention, the first material layer 112A directly contacts the substrate (dielectric layer 104 ) and the bottom electrode 110A.

[0072] In some embodiments of the present invention, a maximum width of the first material layer 112A is equal to a maximum width of the second material layer 114A (eg, Figure 8 As shown, side wall S3 is flush with side wall S4).

[0073] In some embodiments of the present invention, two side walls 120A are further included to cover the upper electrode 118A, wherein the material of the side walls 120A is the same as that of the second material layer 114A.

[0074] In some embodiments of the present invention, the sidewall portion 120A directly contacts a portion of the second material layer 114A.

[0075] In some embodiments of the present invention, from a cross-sectional view, the resistance switching layer 111 includes a protruding portion P, and the upper electrode 118A has a flat top surface T1 and two inclined sidewalls S1 and S2 , and covers the protruding portion P of the resistance switching layer 111 .

[0076] In some embodiments of the present invention, a maximum width W3 of the bottom electrode 110A is smaller than a maximum width of the resistance switching layer 111 .

[0077] The present invention also provides a method for manufacturing a resistive random access memory (RRAM) structure, comprising forming a lower electrode 110A located on a substrate (e.g., a dielectric layer 104), forming a resistive conversion layer 111 located on the lower electrode 110A, and forming an upper electrode 118A located on the resistive conversion layer, wherein from a cross-sectional view, the resistive random access memory structure has a flat top surface T1 and two inclined side walls S1 and S2, and a maximum width W2 of the resistive conversion layer 111 is greater than a maximum width W1 of the upper electrode 118A.

[0078] The present invention provides a resistive random access memory (RRAM) cell structure and a manufacturing method thereof, characterized in that the structure of the RRAM cell is designed to be narrower on the top surface and wider on the bottom, and the cross-section of the lower electrode is triangular or trapezoidal, and the width of the lower electrode is smaller than the width of the upper electrode. When the RRAM cell of this structure is in operation, the electric field generated on the top surface will be more concentrated, so the reading and writing rates of the RRAM cell in operation can be accelerated, and the quality of the component can be improved. In addition, during the manufacturing process, the lower electrode can be completely covered by other materials to obtain better protection, thereby improving the reliability of the component.

[0079] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A resistive random access memory structure, comprising: a lower electrode, located on the substrate; a resistance switching layer, located on the lower electrode; and The upper electrode is located on the resistance conversion layer, wherein from the cross-sectional view, the resistance random access memory structure has a flat top surface and two inclined side walls, and the maximum width of the resistance conversion layer is greater than the maximum width of the upper electrode. 2 . The resistance random access memory structure as claimed in claim 1 , wherein the bottom electrode has a triangular or trapezoidal cross-section structure. 3 . The resistance random access memory structure as claimed in claim 1 , wherein the resistance conversion layer comprises a multi-layer structure, and the multi-layer structure comprises a first material layer and a second material layer stacked from bottom to top. 4 . The resistance random access memory structure as claimed in claim 3 , wherein the first material layer comprises chromium oxide, and the second material layer comprises aluminum oxide. 5 . The resistance random access memory structure as claimed in claim 3 , wherein the first material layer directly contacts the substrate and the bottom electrode. 6 . The RRAM structure as claimed in claim 3 , wherein a maximum width of the first material layer is equal to a maximum width of the second material layer. 7 . The resistance random access memory structure as claimed in claim 3 , further comprising two side walls covering the upper electrode, wherein the material of the side walls is the same as that of the second material layer. 8 . The resistance random access memory structure as claimed in claim 7 , wherein the sidewall directly contacts a portion of the second material layer.

9. The resistance random access memory structure as claimed in claim 1, wherein from a cross-sectional view, the resistance switching layer includes a protruding portion, and the upper electrode has a flat top surface and two inclined sidewalls, and covers the protruding portion of the resistance switching layer. 10 . The resistance random access memory structure as claimed in claim 1 , wherein a maximum width of the bottom electrode is smaller than a maximum width of the resistance switching layer.

11. A method for manufacturing a resistive random access memory (RRAM) structure, comprising: forming a lower electrode located on the substrate; forming a resistance switching layer on the lower electrode; and An upper electrode is formed on the resistance conversion layer, wherein from the cross-sectional view, the resistance random access memory structure has a flat top surface and two inclined side walls, and the maximum width of the resistance conversion layer is greater than the maximum width of the upper electrode. 12 . The method for manufacturing a resistance random access memory structure as claimed in claim 11 , wherein the bottom electrode has a triangular or trapezoidal cross-section structure. 13 . The method for manufacturing a resistance random access memory structure as claimed in claim 11 , wherein the resistance conversion layer comprises a multi-layer structure, and the multi-layer structure comprises a first material layer and a second material layer stacked from bottom to top. 14 . The method for manufacturing a resistance random access memory structure as claimed in claim 13 , wherein the first material layer comprises chromium oxide, and the second material layer comprises aluminum oxide. 15 . The method for manufacturing a resistance random access memory structure as claimed in claim 13 , wherein the first material layer directly contacts the substrate and the bottom electrode. 16 . The method for manufacturing a resistance random access memory structure as claimed in claim 13 , wherein a maximum width of the first material layer is equal to a maximum width of the second material layer. 17 . The method for manufacturing a resistance random access memory structure as claimed in claim 13 , further comprising two side walls covering the upper electrode, wherein the material of the side walls is the same as that of the second material layer. 18 . The method for manufacturing a resistance random access memory structure as claimed in claim 17 , wherein the sidewall directly contacts a portion of the second material layer.

19. The method for manufacturing a resistance random access memory structure as claimed in claim 11, wherein from a cross-sectional view, the resistance switching layer includes a protruding portion, and the upper electrode has a flat top surface and two inclined sidewalls, and covers the protruding portion of the resistance switching layer. 20 . The method for manufacturing a resistance random access memory structure as claimed in claim 11 , wherein a maximum width of the bottom electrode is smaller than a maximum width of the resistance switching layer.

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