Thin film resistor (TFR) device structures for high performance radio frequency (RF) filter designs

Abstract

An integrated circuit (IC, 450) includes a substrate (402) and a thin film resistor (TFR, 460) device structure. The TFR device structure includes a first portion (462) of a first metallization layer (M1) on the substrate and a second portion (470) of the first metallization layer. The TFR device structure also includes a first portion (464) of the dielectric layer on the first portion (462) of the first metallization layer and a second portion (472) of the dielectric layer on the second portion (470) of the first metallization layer. The TFR device structure also includes a first portion (466) of a second metallization layer (M2) on the first portion (464) of the dielectric layer and a second portion (474) of the second metallization layer on the second portion (472) of the dielectric layer. The TFR device structure also includes a first portion (469) of a third metallization layer (M3) coupling the first portion (466) of the second metallization layer to the second portion (474) of the second metallization layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 830,196, filed on June 1, 2022, and entitled “THIN FILM RESISTOR (TFR) DEVICE STRUCTURE FOR HIGHPERFORMANCE RADIO FREQUENCY (RF) FILTER DESIGN,” the disclosure of which is expressly incorporated by reference in its entirety. Technical Field

[0003] Aspects of the present disclosure relate to semiconductor devices and integrated passive devices, and more particularly, to thin film resistor (TFR) device structures for high performance radio frequency (RF) filter designs. Background Art

[0004] Wireless communication devices incorporate radio frequency (RF) modules that facilitate communication and enable features that users expect. As wireless systems become more ubiquitous and include more capabilities, the production of chips has become more complex. Fifth generation (5G) / sixth generation (6G) new radio (NR) wireless communication devices incorporate the latest generation of electronic dies that pack many features and devices into smaller modules with increasingly smaller interconnects. As the density of these modules increases, resistors are very important for combining and / or distributing RF power.

[0005] The design challenges of mobile radio frequency (RF) chips, such as mobile RF transceivers, include analog / RF performance considerations, including mismatch, noise and other performance considerations. The design of these mobile RF transceivers includes the use of passive devices, such as resistors, for example, to perform filtering and coupling. These resistors are integrated into high-power system-on-chip devices, such as application processors and graphics processors.

[0006] In practice, the passive components of mobile RF transceivers may involve high performance resistor components. For example, analog integrated circuits use various types of passive components, such as resistors. The use of resistors can realize high performance power combiner / divider filters that use resistor components to combine / divide RF power. Unfortunately, due to parasitic capacitive coupling between electrodes of the resistor component, conventional resistor components cannot achieve the desired isolation. It is expected that a thin film resistor (TFR) device structure for providing the desired isolation to achieve 5G / 6G front-end applications. Summary of the invention

[0007] An integrated circuit (IC) includes a substrate and a thin film resistor (TFR) device structure. The TFR device structure includes a first portion of a first metallization layer on the substrate and a second portion of the first metallization layer. The TFR device structure also includes a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer. The TFR device structure includes a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer. The TFR device structure also includes a first portion of a third metallization layer coupling the first portion of the second metallization layer to the second portion of the second metallization layer.

[0008] A method for manufacturing a thin film resistor (TFR) device structure is described. The method includes forming a first portion of a first metallization layer and a second portion of the first metallization layer on a substrate. The method also includes forming a first portion of a dielectric layer on the first portion of the first metallization layer and forming the second portion of the dielectric layer on the second portion of the first metallization layer. The method also includes forming a first portion of a second metallization layer on the first portion of the dielectric layer and forming the second portion of the second metallization layer on the second portion of the dielectric layer. The method also includes forming a first portion of a third metallization layer to couple the first portion of the second metallization layer to the second portion of the second metallization layer.

[0009] This has broadly outlined the features and technical advantages of the present disclosure so that the following specific embodiments may be better understood. Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure may be easily used as a basis for modifying or designing other structures for implementing the same purposes as the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features considered to be characteristic of the present disclosure, both in terms of its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the accompanying drawings is provided for illustration and description purposes only and is not intended as a definition of limitations on the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a schematic diagram of a radio frequency front end (RFFE) module using an integrated passive device (IPD) filter.

[0012] Figure 2is a schematic diagram of a RF front end (RFFE) module for a chipset using an integrated passive device (IPD) filter.

[0013] Figure 3 is a block diagram illustrating a cross-sectional view of a radio frequency front end (RFFE) module including a semiconductor die and an integrated passive device (IPD) filter die according to aspects of the present disclosure.

[0014] Figure 4A and Figure 4B is a diagram illustrating a radio frequency integrated circuit (RFIC) chip including a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) device for a radio frequency (RF) filter according to aspects of the present disclosure.

[0015] FIG. 5A to FIG. 5D is a schematic diagram of a power combiner / divider filter having a thin film resistor (TFR) device structure according to aspects of the present disclosure.

[0016] FIG. 6A to FIG. 6J is a diagram illustrating a process of manufacturing a radio frequency integrated circuit (RFIC) chip including a metal-insulator-metal (MIM) capacitor, a thin film resistor (TFR) device structure, and an inductor according to aspects of the present disclosure.

[0017] Figure 7 is a process flow diagram illustrating a method for fabricating a thin film resistor (TFR) device structure according to aspects of the present disclosure.

[0018] Figure 8 is a block diagram illustrating an exemplary wireless communication system in which configurations of the present disclosure may be advantageously employed.

[0019] Fig. 9 is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration. DETAILED DESCRIPTION

[0020] The specific embodiments described below in conjunction with the accompanying drawings are intended to be descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, in order to avoid blurring such concepts, known structures and components are shown in block diagram form.

[0021] As described herein, the use of the term "and / or" is intended to mean "inclusive or", and the use of the term "or" is intended to mean "exclusive or". As described herein, the term "exemplary" used throughout the specification means "used as an example, instance, or illustration", and is not necessarily to be construed as being preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" used throughout the specification means "directly or indirectly connected through an intervening connection (e.g., a switch), electrically, mechanically, or otherwise", and is not necessarily limited to physical connections. In addition, a connection may be made so that an object is permanently connected or releasably connected. The connection may be made through a switch. As described herein, the term "close to" used throughout the specification means "adjacent, very close, immediately adjacent, or close". As described herein, the term "on..." used throughout the specification means "directly on..." in some configurations, and "indirectly on..." in other configurations.

[0022] Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to deep submicron process nodes for cost and power consumption considerations. Additional circuit functions to support communication enhancements such as fifth generation (5G) new radio (NR) / sixth generation (6G) communication systems complicate the design of mobile RF transceivers. Further design challenges for mobile RF transceivers include the use of passive components that directly impact analog RF performance considerations, including mismatch, noise, and other performance considerations.

[0023] Passive devices in mobile radio frequency (RF) transceivers may include high performance resistors, capacitors and inductor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors, integrated inductors and resistor components. Integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, pn junction capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-polysilicon capacitors, metal-oxide-metal (MOM) capacitors and other similar capacitor structures. Inductors are examples of electrical devices for temporarily storing energy in a magnetic field within a wire coil according to an inductance value. Resistors are passive two-terminal electrical components that implement resistance as circuit elements, which can be used to reduce current flow, adjust signal levels, divide voltages, bias active components and terminate transmission lines. For example, the design of mobile RF transceivers includes using RF filters with resistors, inductors and capacitors to meet bandwidth specifications.

[0024] 5G / 6G RF front-end (RFFE) modules may include combiner / divider filters and / or directional couplers having resistor components, MIM capacitors and inductors. These 5G / 6G RF front-end applications specify resistor components to combine / divide RF power to achieve high performance power of combiner / divider filters. Unfortunately, thin film resistors (TFRs) available using current integrated passive device (IPD) casting processes cannot achieve the desired isolation due to parasitic capacitive coupling of the electrodes of the TFR. Without the option of modifying the casting IPD process flow, it is impossible to implement and realize TFR devices for power combiner / divider filters. Therefore, it is desirable to have a TFR device structure with design techniques / optimizations to address these problems.

[0025] Various aspects of the present disclosure provide a TFR device structure for an RF filter. The process flow for manufacturing a TFR device structure for an RF filter may include a front-end-of-line (FEOL) process, a middle-of-line (MOL) process, and a back-end-of-line (BEOL) process. It should be understood that the term "layer" includes a film and is not to be interpreted as indicating a vertical or horizontal thickness unless otherwise specified. As described, the term "substrate" may refer to a substrate of a cut wafer or may refer to a substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably.

[0026] As described, a back-end-of-line (BEOL) interconnect layer may refer to a conductive interconnect layer (e.g., a first interconnect layer (M1) or metal one M1, metal two (M2), metal three (M3), metal four (M4), etc.) for electrically coupling to a front-end-of-line (FEOL) active device of an integrated circuit. Various BEOL interconnect layers are formed at corresponding BEOL interconnect layers, wherein lower BEOL interconnect layers use thinner metal layers relative to upper BEOL interconnect levels. The BEOL interconnect layer may be electrically coupled to a middle-of-line (MOL) interconnect layer, for example, to connect M1 to an oxide diffusion (OD) layer of an integrated circuit. The MOL interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of an integrated circuit. A BEOL first via (V2) may connect M2 to M3 or other layers in the BEOL interconnect layer.

[0027] Various aspects of the present disclosure relate to a thin film resistor (TFR) device structure that implements an RF filter (such as a power combiner / divider filter or a directional coupler). In some aspects of the present disclosure, the TFR device structure includes a split first metallization layer (e.g., M1). The TFR device structure also includes a dielectric layer portion on the split portion of the M1 metallization layer. In some aspects of the present disclosure, the TFR device structure includes a split M2 metallization layer on a corresponding portion of the dielectric layer. In some aspects of the present disclosure, the M1 and M2 metallization layers are split to provide the desired isolation specified by the TFR device structure. This configuration of the TFR device structure can match the desired radio frequency (RF) response and also meet the power combiner / divider filter design target specifications.

[0028] Figure 1 1 is a schematic diagram of a radio frequency front end (RFFE) module 100 using a filter 104 (e.g., an RF filter implemented using a TFR device structure). The RFFE module 100 includes a power amplifier 102, a filter 104, and a radio frequency (RF) switch module 106. The power amplifier 102 amplifies the signal to a certain power level for transmission. The filter 104 filters the input / output signal according to various parameters, including frequency, insertion loss, rejection, or other similar parameters. In addition, the RF switch module 106 can select certain portions of the input signal to pass to the rest of the RFFE module 100.

[0029] The radio frequency front end (RFFE) module 100 also includes a tuner circuit 112 (e.g., a first tuner circuit 112A and a second tuner circuit 112B), a second duplexer 190, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. The tuner circuit 112 (e.g., the first tuner circuit 112A and the second tuner circuit 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). The tuner circuit 112 may perform impedance tuning (e.g., voltage standing wave ratio (VSWR) optimization) on the antenna 114. The RFFE module 100 also includes a passive combiner 108 coupled to the wireless transceiver (WTR) 120. The passive combiner 108 combines the power detected from the first tuner circuit 112A and the second tuner circuit 112B. The wireless transceiver 120 processes the information from the passive combiner 108 and provides this information to a modem 130 (eg, a mobile station modem (MSM)). The modem 130 provides the digital signal to the application processor (AP) 110.

[0030] like Figure 1As shown, the second duplexer 190 is between the tuner components of the tuner circuit 112 and the capacitor 116, the inductor 118 and the antenna 114. The second duplexer 190 can be placed between the antenna 114 and the tuner circuit 112 to provide high system performance from the radio frequency front end (RFFE) module 100 to the chipset including the wireless transceiver 120, the modem 130 and the application processor 110. The second duplexer 190 also performs frequency domain multiplexing on both the high-band frequency and the low-band frequency. After the second duplexer 190 performs its frequency multiplexing function on the input signal, the output of the second duplexer 190 is fed to an optional inductor / capacitor (LC) network including capacitors 116 and inductors 118. When necessary, the LC network can provide additional impedance matching components for the antenna 114. Then, a signal with a specific frequency is sent or received by the antenna 114. Although a single capacitor and inductor are shown, multiple components can also be envisioned.

[0031] Figure 2 2 is a schematic diagram of a radio frequency integrated circuit (RFIC) chip 200 having a wireless local area network (WLAN) (e.g., Wi-Fi) module 150 and a radio frequency front end (RFFE) module 170 for a chipset 210. The Wi-Fi module 150 includes a first duplexer 162 that communicatively couples an antenna 164 to the WLAN module 152. A first RF switch 160 communicatively couples the first duplexer 162 to the WLAN module 152. The RFFE module 170 includes a second duplexer 190 that communicatively couples an antenna 192 to a wireless transceiver (WTR) 120 through a filter 172 (e.g., an RF filter implemented using a TFR device structure). A second RF switch 180 communicatively couples the second duplexer 190 to the filter 172.

[0032] The WTR 120 and the WLAN module 152 of the Wi-Fi module 150 are coupled to a modem (mobile station modem (MSM), such as a baseband modem) 130 powered by a power source 202 through a power management integrated circuit (PMIC) 140. The chipset 210 also includes capacitors 144 and 148 and an inductor 146 to provide signal integrity. The PMIC 140, modem 130, WTR 120, and WLAN module 152 each include capacitors (e.g., 142, 132, 122, and 154) and operate according to a clock 204. In addition, the inductor 146 couples the modem 130 to the PMIC 140. The geometry and arrangement of the various inductor and capacitor components in the RFIC) chip 200 can reduce electromagnetic coupling between components. According to aspects of the present disclosure, the design of the RFFE module 170 includes a filter 172, which can be a filter that utilizes, for example, Figure 3The TFR device structure shown is used to implement the RF filter.

[0033] Figure 3 3 is a block diagram illustrating a cross-sectional view of a radio frequency front end (RFFE) module 300 including a semiconductor die and an integrated passive device (IPD) filter die according to aspects of the present disclosure. In this example, the RFFE module 300 includes a semiconductor die 350 and an IPD filter die 320 supported by a substrate 310. The semiconductor die 350 can be an active die having a semiconductor substrate 360 ​​(e.g., an active silicon substrate) coupled to a package ball 302 through a back end of line (BEOL) layer 370. The BEOL layer 370 includes a plurality of BEOL metallization layers (M1, M2, M3, ..., Mn) on the semiconductor substrate 360 ​​(e.g., a diced silicon wafer). A redistribution layer 312 is coupled to the package ball 302.

[0034] The IPD filter die 320 includes a substrate 330 (e.g., a passive substrate) coupled to the package balls 302 through a back end of line (BEOL) layer 340. The redistribution layer 312 is coupled to the IPD filter die 320 through the package balls 302. In some aspects of the present disclosure, the substrate 330 is composed of glass and the IPD filter die 320 is a glass substrate integrated passive device (GIPD) filter die. The IPD filter die 320 can implement a fifth generation (5G) new radio (NR) / sixth generation (6G) power combiner / divider filter or a directional coupler.

[0035] The RFFE module 300 may include a power combiner / divider filter having a resistor component, a MIM capacitor, and an inductor. The RFFE module 300 may specify a resistor component to combine / divide RF power to achieve a high performance power combiner / divider filter. Unfortunately, thin film resistors (TFRs) produced by current IPD casting processes cannot achieve the desired isolation due to parasitic capacitive coupling between electrodes of the TFR device. Without the option of modifying the casting IPD process flow, it is not possible to implement and realize a TFR device that meets the specifications of the power combiner / divider filter. In some aspects of the present disclosure, the IPD filter die 320 includes a TFR device structure for an RF filter, such as Figure 4A and Figure 4B Further illustrated in .

[0036] Figure 4A and Figure 4B is a block diagram illustrating a radio frequency integrated circuit (RFIC) chip including metal-insulator-metal (MIM) capacitors and thin film resistor (TFR) devices for a radio frequency (RF) filter according to aspects of the present disclosure. Figure 4AThe RFIC chip 400 is illustrated and includes a substrate 402 having an oxide layer 404 (e.g., tetraethyl orthosilicate (TEOS) oxide) on its surface. In some aspects of the present disclosure, the RFIC chip 400 includes a metal-insulator-metal (MIM) capacitor 410 and a thin film resistor (TFR) device structure 420 on the oxide layer 404.

[0037] In some aspects of the present disclosure, the TFR device structure 420 includes a split first metallization layer (e.g., M1) including a first portion 422 of the M1 metallization layer and a second portion 424 of the M1 metallization layer on the surface of the oxide layer 404. The TFR device structure 420 also includes a dielectric layer 426 on the first portion 422 and the second portion 424 of the M1 metallization layer. The TFR device structure 420 also includes an M2 metallization layer 428 on the dielectric layer 426. The M2 metallization layer 428 may be composed of a TFR layer, such as titanium nitride (TiN), tantalum nitride (TaN), nickel chromium (NiCr), or other similar conductive materials used for resistors. In addition, a first portion 430 and a second portion 432 of a third metallization layer (e.g., M3 metallization layer) are coupled to the M2 metallization layer 428 through vias V2 to complete the formation of the TFR device structure 420.

[0038] In this example, the MIM capacitor 410 includes a first plate 412 composed of an M1 metallization layer on a surface of the oxide layer 404. The MIM capacitor 410 also includes a MIM insulator layer 414 on the first plate 412 of the MIM capacitor 410. In addition, a second plate 416 of the MIM capacitor 410 is composed of an M2 metallization layer on the MIM insulator layer 414. In addition, a first portion 418 and a second portion 419 of the M3 metallization layer are coupled to the second plate 416 and the first plate 412 through vias V2 in the first interlayer dielectric (ILD) layer 408 to complete the formation of the MIM capacitor 410. The passivation layer 406 is disposed on portions (e.g., 418, 419, 430, and 432) of the M3 metallization layer and the first ILD layer 408,

[0039] Figure 4BAn RFIC chip 450 is illustrated, which includes a substrate 402 having an oxide layer 404 (e.g., tetraethyl orthosilicate (TEOS) oxide) on a surface thereof. In some aspects of the present disclosure, the RFIC chip 450 includes a MIM capacitor 410 and a TFR device structure 460 on the oxide layer 404. In some aspects of the present disclosure, the TFR device structure 460 also includes a split M1 metallization layer, which includes a first portion 462 of the M1 metallization layer and a second portion 470 of the M1 metallization layer on the surface of the oxide layer 404. The TFR device structure 460 includes a first portion 464 of the dielectric layer on the first portion 462 of the M1 metallization layer and a second portion 472 of the dielectric layer on the second portion 470 of the M1 metallization layer.

[0040] In some aspects of the present disclosure, the TFR device structure 460 includes a split M2 metallization layer. In these aspects of the present disclosure, the TFR device structure 460 includes a first portion 464 of a dielectric layer on a first portion 462 of the M1 metallization layer and a second portion 472 of the dielectric layer on a second portion 470 of the M1 metallization layer. The TFR device structure 460 also includes a first portion 466 of an M2 metallization layer on the first portion 464 of the dielectric layer and a second portion 474 of an M2 metallization layer on the second portion 472 of the dielectric layer. The M2 metallization layer may be composed of a TFR layer, such as titanium nitride (TiN), tantalum nitride (TaN), nickel chromium (NiCr), or other similar conductive materials used for resistors. In these aspects of the present disclosure, a second portion 469 of the M3 metallization layer couples the first portion 466 of the M2 metallization layer to the second portion 474 of the M2 metallization layer. In addition, the first portion 468 and the third portion 476 of the M3 metallization layer are coupled to the first portion 466 and the second portion 474 of the M2 metallization layer through vias V2. A passivation layer 406 is also disposed on portions of the M3 metallization layer (e.g., 418, 419, 468, 469, and 476) and the first ILD layer 408 to complete the formation of the TFR device structure 460.

[0041] FIG. 5A to FIG. 5D is a schematic diagram of a power combiner / divider filter having a thin film resistor (TFR) device structure according to aspects of the present disclosure. Figure 5A A schematic diagram of a power combiner / divider filter 500 having a metal-insulator-metal (MIM) capacitor 510 , a thin film resistor (TFR) device structure 550 , and an inductor 580 is illustrated. Figure 5BA perspective view and an exploded view 570 of a first TFR device structure 560 according to aspects of the present disclosure are illustrated. As shown in the exploded view 570, the first TFR device structure 560 includes an M3 metallization layer joining a first portion and a second portion of an M1 metallization layer, including a dielectric layer (e.g., silicon nitride (SiN)), an M2 metallization layer, and a via V2.

[0042] Figure 5C A cross-sectional view 590 of a first TFR device structure 560 including a first port (eg, Port 1) and a second port (eg, Port 2) is illustrated. The cross-sectional view 590 of the first TFR device structure 560 further illustrates a split bottom electrode (M1) floating below a split top electrode (M2). Figure 5D A top view of a first TFR device structure 560 is illustrated. In this configuration, an aspect ratio (AR) between the length and width of a unit cell (e.g., a portion of the M1 metallization layer) of the first TFR device structure 560 is approximately 1.5. In addition, the spacing between portions of the M1 metallization layer is approximately one fifteenth (1 / 15) of the length. This configuration can be achieved through a low-cost advanced integrated passive device (IPD) process to achieve a high-performance power combiner (PC) with desired isolation that conventional TFR designs fail to achieve. The first TFR device structure 560 can match a desired radio frequency (RF) response and also meet the power combiner filter design target specifications. The formation of the TFR device structure in FIG. 6A to FIG. 6J Example in.

[0043] FIG. 6A to FIG. 6J is a diagram illustrating a process 600 of fabricating a radio frequency integrated circuit (RFIC) chip including metal-insulator-metal (MIM) capacitors, thin film resistor (TFR) device structures, and inductors according to aspects of the present disclosure. FIG. 6A to FIG. 6J Can be used with Figure 4B The RFIC chip 450 is shown with similar reference numerals. Fig. 6A Step 1 of the exemplary process 600 is where a high resistivity silicon (HRS) substrate 402 is prepared for fabrication. The substrate 402 may be composed of silicon (Si), HRS, glass, gallium arsenide (GaAs), aluminum oxide, silicon carbide (SiC), or other similar substrate materials.

[0044] Figure 6B is a diagram illustrating step 2 of process 600, in which an oxide layer 404 is deposited on the surface of substrate 402. Oxide layer 404 may be composed of tetraethyl orthosilicate (TEOS) oxide material or other similar oxide materials. M1 metallization material may be composed of aluminum oxide (Al), lightly copper-doped aluminum (AlCu), or other similar conductive materials.

[0045] Figure 6Cis a diagram illustrating step 3 of process 600, in which an M1 metallization layer 602 is deposited on an oxide layer 404 on a surface of a substrate 402. The M1 metallization layer 602 may be deposited on the oxide layer 404 using a physical vapor deposition (PVD) process.

[0046] Fig.6D is a diagram illustrating step 4 of process 600, in which a dielectric layer 604 is deposited on the surface of the M1 metallization layer 602. In this example, the dielectric layer 604 is composed of silicon nitride (SiN) and is deposited on the surface of the M1 metallization layer 602 using a plasma enhanced chemical vapor deposition (PECVD) process.

[0047] Fig. 6E is a diagram illustrating step 5 of process 600, in which an M2 metallization layer 606 is deposited on the surface of dielectric layer 604. In this example, a physical vapor deposition (PVD) process is used to perform the deposition of the M2 metallization layer 606 on the surface of dielectric layer 604. In some aspects of the present disclosure, the M2 metallization layer 606 provides the second plate of the MIM capacitor 410 and the TFR layer of the TFR device structure 460, e.g., as Figure 4B shown.

[0048] Fig. 6F 6 is a diagram illustrating step 6 of process 600, in which dielectric layer 604 and M2 metallization layer 606 are subjected to a patterning and etching process to expose portions of M1 metallization layer 602. Applying the patterning and etching process to dielectric layer 604 and M2 metallization layer 606 forms MIM insulator layer 414 and second plate 416 of MIM capacitor 410. Additionally, applying the patterning and etching process to dielectric layer 604 and M2 metallization layer 606 forms first portion 466 of M2 metallization layer 606 on first portion 464 of dielectric layer 604, and forms second portion 474 of M2 metallization layer 606 on second portion 472 of dielectric layer 604. In some aspects of the present disclosure, first portion 464 and second portion 474 of M2 metallization layer 606 are separated to provide a device structure 460 (e.g., as shown in FIG. 4 ) formed by TFR device structure 460 (e.g., as shown in FIG. 4 ). Figure 4B The desired isolation is specified as shown).

[0049] Figure 6Gis a diagram illustrating step 7 of process 600, in which the M1 metallization layer 602 is subjected to a patterning and etching process to expose portions of the oxide layer 404. Applying the patterning and etching process to the M1 metallization layer 602 forms the first plate 412 of the MIM capacitor 410. In addition, applying the patterning and etching process to the M1 metallization layer 602 forms the first portion 462 and the second portion 470 of the M1 metallization layer 602. Applying the patterning and etching process to the M1 metallization layer 602 forms the third portion 482 of the M1 metallization layer 602 to enable the formation of the inductor 480. In some aspects of the present disclosure, the first portion 462 and the second portion 470 of the M1 metallization layer 602 are separated to provide a device structure 460 (e.g., such as a TFR device structure 460) (e.g., Figure 4B The desired isolation is specified as shown).

[0050] Figure 6H 6 is a diagram illustrating step 8 of process 600, in which a first interlayer dielectric (ILD) layer 408 is deposited. The deposition of the first ILD layer 408 may be performed by using tetraethyl orthosilicate (TEOS) deposition of silicon oxide to form the first ILD layer 408. Alternatively, the first ILD layer 408 is formed by fabricating the first ILD layer 408 using polyimide (PI) and then performing a via opening process to expose a portion of the second plate 416 and the first plate 412 of the MIM capacitor 410. In addition, a via opening process is performed to expose a portion of the first portion 466 and the second portion 474 of the M2 metallization layer 606 and a portion of the third portion 482 of the M1 metallization layer 602 through the via opening 610.

[0051] Fig.6I is a diagram illustrating step 9 of a process 600 according to aspects of the present disclosure, wherein a physical vapor deposition (PVD) sputtering and patterning process is performed to form portions of an M3 metallization layer and vias V2. The sputtering and patterning process forms a first portion 418 and a second portion 419 of the M3 metallization layer, which are coupled to the second plate 416 and the first plate 412 through vias V2 in the first ILD layer 408 to complete the formation of the MIM capacitor 410. In addition, the sputtering and patterning process forms a second portion 469 of the M3 metallization layer, which couples the first portion 466 of the M2 metallization layer to the second portion 474. The first portion 468 and the third portion 476 of the M3 metallization layer are formed and coupled to the first portion 466 and the second portion 474 of the M2 metallization layer through vias V2 to complete the formation of the TFR device structure 460. Additionally, various portions (eg, 484, 486, 488, and 492) of the M3 metallization layer are formed for inductor 480 and pad 490. The M1 metallization material may be composed of aluminum oxide (Al), lightly copper doped aluminum (AlCu), or other similar conductive materials.

[0052] Figure 6J 1 is a diagram illustrating step 10 of a process 600 according to aspects of the present disclosure, wherein a plasma enhanced chemical vapor deposition (PECVD) of a passivation layer 406 and a via opening process are performed on the M3 metallization layer. Portions of the passivation layer 406 (e.g., silicon nitride (SiNx), silicon oxide (SiOx), etc.) are etched to expose certain portions of the M3 metallization layer (e.g., 418, 419, 468, 476, 484, 486, 488, and 492). The process for manufacturing an RFIC chip including MIM capacitors, TFR device structures, and inductors is described in, e.g. Figure 7 Shown in.

[0053] Figure 7 7 is a process flow diagram illustrating a method for manufacturing a thin film resistor (TFR) device structure according to aspects of the present disclosure. The method 700 begins at block 702, where a first portion of a first metallization layer and a second portion of the first metallization layer are formed on a substrate. For example, Figure 6G The M1 metallization layer 602 is illustrated as being subjected to a patterning and etching process to expose portions of the oxide layer 404. Applying the patterning and etching process to the M1 metallization layer 602 forms a first portion 462 and a second portion 470 of the M1 metallization layer 602.

[0054] At block 704, a first portion of a dielectric layer is formed on a first portion of a first metallization layer on a substrate, and a second portion of the dielectric layer is formed on a second portion of the first metallization layer. Fig. 6F As shown, dielectric layer 604 is subjected to a patterning and etching process to expose portions of M1 metallization layer 602. Applying the patterning and etching process to dielectric layer 604 forms first portion 464 of dielectric layer 604 and second portion 472 of dielectric layer 604 to second portion 470 of M1 metallization layer 602.

[0055] Refer again Figure 7 At block 706, a first portion of a second metallization layer is formed on the first portion of the dielectric layer, and a second portion of the second metallization layer is formed on the second portion of the dielectric layer. Fig. 6F As shown, the M2 metallization layer 606 is subjected to a patterning and etching process to expose a portion of the M1 metallization layer 602. Applying the patterning and etching process to the M2 metallization layer 606 forms a first portion 466 of the M2 metallization layer 606 on the first portion 464 of the dielectric layer 604, and forms a second portion 474 of the M2 metallization layer 606 on the second portion 472 of the dielectric layer 604. In some aspects of the present disclosure, the first portion 466 and the second portion 474 of the M2 metallization layer are separated to provide a TFR device structure 460 (e.g., as shown in FIG. 4 ). Figure 4B The desired isolation is specified as shown).

[0056] At block 708, a first portion of a third metallization layer is formed to couple the first portion of the second metallization layer to the second portion of the second metallization layer. Fig.6I As shown, according to various aspects of the present disclosure, the PVD sputtering and patterning process forms a portion of the M3 metallization layer and the via V2. The sputtering and patterning process forms a second portion 469 of the M3 metallization layer, which couples the first portion 466 of the M2 metallization layer 606 to the second portion 474. In addition, the first portion 468 and the third portion 476 of the M3 metallization layer are formed and coupled to the first portion 466 and the second portion 474 of the M2 metallization layer through the via V2 to complete the Figure 4B The formation of a TFR device structure 460 is shown.

[0057] Various aspects of the present disclosure relate to thin film resistor (TFR) device structures that implement RF filters (such as power combiner / divider filters and directional couplers). In some aspects of the present disclosure, the TFR device structure includes a split first metallization layer (e.g., M1). The TFR device structure also includes a dielectric layer portion on the split portion of the M1 metallization layer. In some aspects of the present disclosure, the TFR device structure includes a split M2 metallization layer on a corresponding portion of the dielectric layer. In some aspects of the present disclosure, the M1 and M2 metallization layers are split to provide the desired isolation specified by the TFR device structure. This configuration of the TFR device structure can match the desired radio frequency (RF) response and also meet the power combiner / divider filter design target specifications.

[0058] According to yet another aspect of the present disclosure, an integrated circuit (IC) includes a thin film resistor (TFR) device structure. In one configuration, the IC has a component for coupling a first portion and a second portion of a second metallization layer floating above a first portion and a second portion of a first metallization layer. In one configuration, the coupling component may be a second portion 469 of an M3 metallization layer that couples a first portion 466 of an M2 metallization layer to a second portion 474 of an M2 metallization layer, such as Figure 4B On the other hand, the aforementioned components may be any structure or any material configured to perform the functions recited by the aforementioned components.

[0059] Figure 8 8 is a block diagram illustrating an exemplary wireless communication system 800 in which aspects of the present disclosure may be advantageously employed. For purposes of illustration, Figure 8Three remote units 820, 830, and 850 and two base stations 840 are shown. It will be appreciated that the wireless communication system may have more remote units and base stations. The remote units 820, 830, and 850 include integrated circuit (IC) devices 825A, 825C, and 825B that include the disclosed TFR device structure. It will be appreciated that other devices may also include the disclosed TFR device structure, such as base stations, switchgear, and network equipment. Figure 8 Forward link signals 880 from base station 840 to remote units 820, 830, and 850, and reverse link signals 890 from remote units 820, 830, and 850 to base station 840 are shown.

[0060] exist Figure 8 , remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal data assistant), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit (such as a meter reading equipment), or other devices that store or retrieve data or computer instructions, or a combination thereof. Although Figure 8 Remote units according to aspects of the present disclosure are illustrated, but the present disclosure is not limited to these exemplary illustrated units.Aspects of the present disclosure may be suitable for use in many devices including the disclosed TFR device structures.

[0061] Fig. 9 9 is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components (such as the TFR device structure disclosed above). The design workstation 900 includes a hard disk 901, which contains operating system software, support files, and design software (such as Cadence or OrCAD). The design workstation 900 also includes a display 902 to facilitate the design of a circuit 910 or a radio frequency (RF) component 912 (such as a cross capacitor). A storage medium 904 is provided for tangibly storing the design of the circuit 910 or the RF component 912 (e.g., a TFR device structure). The design of the circuit 910 or the RF component 912 can be stored on the storage medium 904 in a file format such as GDSII or GERBER. The storage medium 904 can be a compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a hard disk, a flash memory, or other suitable device. In addition, the design workstation 900 includes a drive 903 for receiving input from the storage medium 904 or writing output to the storage medium.

[0062] The data recorded on the storage medium 904 may specify a logic circuit configuration, pattern data for a lithography mask, or mask pattern data for a serial write tool such as electron beam lithography. The data may also include logic verification data such as timing diagrams or network circuits associated with logic simulations. Providing the data on the storage medium 904 facilitates the design of the circuit 910 or radio frequency (RF) component 912 by reducing the number of processes used to design a semiconductor wafer.

[0063] Specific implementation examples are described in the following numbered clauses:

[0064] 1. An integrated circuit (IC), comprising:

[0065] substrate; and

[0066] A thin film resistor (TFR) device structure, the thin film resistor (TFR) device structure comprising:

[0067] a first portion of a first metallization layer on the substrate and a second portion of the first metallization layer;

[0068] a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer;

[0069] a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer; and

[0070] A first portion of a third metallization layer is coupled to the first portion of the second metallization layer to the second portion of the second metallization layer.

[0071] 2. The IC of clause 1, further comprising:

[0072] a first interlayer dielectric (ILD) layer on a surface of the substrate and the first portion and the second portion of the second metallization layer;

[0073] a first plurality of vias extending through the first ILD layer to the first portion of the second metallization layer;

[0074] a second plurality of vias extending through the first ILD layer to the second portion of the second metallization layer;

[0075] a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the first portion of the second metallization layer through the first plurality of vias; and

[0076] A third portion of the third metallization layer is on the first ILD layer and coupled to the second portion of the second metallization layer through the second plurality of vias.

[0077] 3. An IC according to any one of clauses 1 or 2, further comprising:

[0078] A metal-insulator-metal (MIM) capacitor, the metal-insulator-metal (MIM) capacitor comprising:

[0079] a first plate consisting of the first metallization layer on a surface of the substrate;

[0080] A MIM insulator layer on the first plate; and

[0081] A second plate is on the MIM insulator layer.

[0082] 4. The IC of clause 3, further comprising:

[0083] a first interlayer dielectric (ILD) layer on the surface of the substrate and the first plate and the second plate of the MIM capacitor;

[0084] a first plurality of vias extending through the first ILD layer to the second plate of the MIM capacitor;

[0085] a second plurality of vias extending through the first ILD layer to the first plate of the MIM capacitor;

[0086] a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the second plate of the MIM capacitor through the first plurality of vias; and

[0087] A third portion of the third metallization layer is on the first ILD layer and coupled to the first plate of the MIM capacitor through the second plurality of vias.

[0088] 5. An IC according to any one of clauses 1 to 4, further comprising an inductor, the inductor comprising:

[0089] a third portion of the first metallization layer on the surface of the substrate;

[0090] a first interlayer dielectric (ILD) layer on the surface of the substrate and the third portion of the first metallization layer;

[0091] a plurality of vias extending through the first ILD layer to the third portion of the first metallization layer; and

[0092] A second portion of the third metallization layer is on the first ILD layer and coupled to the third portion of the first metallization layer through the plurality of vias.

[0093] 6. The IC of any of clauses 1 to 5, further comprising an oxide layer directly on a surface of the substrate.

[0094] 7. An IC as described in any of clauses 1 to 6, wherein the substrate comprises a high-resistivity silicon (HRS) substrate.

[0095] 8. An IC according to any of clauses 1 to 7, wherein the IC is integrated in an integrated passive device (IPD).

[0096] 9. The IC of clause 8, wherein the IPD is integrated into a radio frequency (RF) filter.

[0097] 10. The IC of clause 9, wherein the RF filter is integrated into a radio frequency front end (RFFE) module.

[0098] 11. A method for manufacturing a thin film resistor (TFR) device structure, the method comprising:

[0099] forming a first portion of a first metallization layer and a second portion of the first metallization layer on a substrate;

[0100] forming a first portion of a dielectric layer on the first portion of the first metallization layer, and forming a second portion of the dielectric layer on the second portion of the first metallization layer;

[0101] forming a first portion of a second metallization layer on the first portion of the dielectric layer, and forming a second portion of the second metallization layer on the second portion of the dielectric layer; and

[0102] A first portion of a third metallization layer is formed to couple the first portion of the second metallization layer to the second portion of the second metallization layer.

[0103] 12. The method according to clause 11, further comprising:

[0104] depositing a first interlayer dielectric (ILD) layer on a surface of the substrate and the first portion and the second portion of the second metallization layer;

[0105] forming a first plurality of vias extending through the first ILD layer to the first portion of the second metallization layer;

[0106] forming a second plurality of vias extending through the first ILD layer to the second portion of the second metallization layer;

[0107] forming a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the first portion of the second metallization layer through the first plurality of vias; and

[0108] A third portion of the third metallization layer is formed, the third portion of the third metallization layer being on the first ILD layer and coupled to the second portion of the second metallization layer through the second plurality of vias.

[0109] 13. The method according to any one of clauses 11 or 12, further comprising:

[0110] forming a first plate consisting of the first metallization layer on a surface of the substrate;

[0111] forming a metal-insulator-metal (MIM) insulator layer on the first plate; and

[0112] A second plate is formed on the MIM insulator layer.

[0113] 14. The method according to clause 13, further comprising:

[0114] depositing a first interlayer dielectric (ILD) layer on the surface of the substrate and the first plate and the second plate;

[0115] forming a first plurality of vias extending through the first ILD layer to the second board;

[0116] forming a second plurality of vias extending through the first ILD layer to the first board;

[0117] forming a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the second plate through the first plurality of vias; and

[0118] A third portion of the third metallization layer is formed on the first ILD layer and coupled to the first plate through the second plurality of vias.

[0119] 15. The method according to any one of clauses 11 to 14, further comprising:

[0120] forming a third portion of the first metallization layer on a surface of the substrate;

[0121] depositing a first interlayer dielectric (ILD) layer on the surface of the substrate and the third portion of the first metallization layer;

[0122] forming a plurality of vias extending through the first ILD layer to the third portion of the first metallization layer; and

[0123] A second portion of the third metallization layer is formed, the second portion of the third metallization layer being on the first ILD layer and coupled to the third portion of the first metallization layer through the plurality of vias.

[0124] 16. The method according to any of clauses 11 to 15, further comprising depositing an oxide layer directly on the surface of the substrate.

[0125] 17. A method according to any one of clauses 11 to 16, wherein the substrate comprises a high resistivity silicon (HRS) substrate.

[0126] 18. The method of any of clauses 11 to 17, further comprising integrating the thin film resistor (TFR) device structure in an integrated passive device (IPD).

[0127] 19. The method of clause 18, further comprising integrating the IPD in a radio frequency (RF) filter.

[0128] 20. The method of clause 19, further comprising integrating the RF filter into a radio frequency front end (RFFE) module.

[0129] For firmware and / or software implementations, these methodologies can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described herein. A machine-readable medium that tangibly embodies instructions can be used to implement the methodologies described herein. For example, software code can be stored in a memory and executed by a processor unit. The memory can be implemented within the processor unit or outside the processor unit. As used herein, the term "memory" refers to various types of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a specific type of memory or number of memories, or the type of medium on which the memory is stored.

[0130] If implemented in firmware and / or software, the functions may be stored as one or more instructions or codes on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. Storage media can be available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disks and optical discs include: compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Optical disks, where magnetic disks typically reproduce data magnetically, while optical disks reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0131] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals on a transmission medium included in a communication device. For example, the communication device may include a transceiver with signals indicating instructions and data. These instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0132] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the technology of the present disclosure as defined in the appended claims. For example, relational terms such as "above" and "below" are used with respect to substrates or electronic devices. Of course, if the substrate or electronic device is inverted, the top becomes the bottom, and vice versa. In addition, if it is side-oriented, the top and the bottom may refer to the side of the substrate or electronic device. In addition, the scope of the present application is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, parts, methods and steps described in the specification. As will be easily understood by those of ordinary skill in the art from the present disclosure, processes, machines, manufactures, material compositions, parts, methods or steps that currently exist or will be developed later to perform functions substantially the same as the corresponding configurations described herein or to achieve results substantially the same as the corresponding configurations described herein can be utilized according to the present disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, parts, methods or steps within their scope.

[0133] The technician will further understand that the various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various exemplary components, frames, modules, circuits and steps have been generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints proposed to the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0134] The various illustrative logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Although a general purpose processor may be a microprocessor, in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0135] The steps or algorithms of the method described in conjunction with the present disclosure can be directly embodied in hardware, a software module executed by a processor, or a combination of the two. The software module can reside in a random access memory (RAM), a flash memory, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium can be integrated with the processor. The processor and the storage medium can reside in an application specific integrated circuit (ASIC). The ASIC can reside in a user terminal. In an alternative, the processor and the storage medium can reside in a user terminal as discrete components.

[0136] In one or more exemplary designs, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on a computer-readable medium or sent by a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any medium that facilitates the transfer of computer programs from one place to another. Storage media can be any available medium that a general or special-purpose computer can access. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage or other magnetic storage devices, or can be used to carry or store instructions or data structure forms of designated program code components and can be accessed by general or special-purpose computers, or general or special processors Any other medium. In addition, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio and microwave are included in the definition of medium. As used herein, disk and disc include: compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Optical disks, where magnetic disks typically reproduce data magnetically, while optical disks reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0137] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to be consistent with the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC), comprising: substrate; and A thin film resistor (TFR) device structure, the thin film resistor (TFR) device structure comprising: a first portion of a first metallization layer on the substrate and a second portion of the first metallization layer; a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer; a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer; and A first portion of a third metallization layer is coupled to the first portion of the second metallization layer to the second portion of the second metallization layer.

2. The IC of claim 1, further comprising: a first interlayer dielectric (ILD) layer on a surface of the substrate and the first portion and the second portion of the second metallization layer; a first plurality of vias extending through the first ILD layer to the first portion of the second metallization layer; a second plurality of vias extending through the first ILD layer to the second portion of the second metallization layer; a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the first portion of the second metallization layer through the first plurality of vias; and A third portion of the third metallization layer is on the first ILD layer and coupled to the second portion of the second metallization layer through the second plurality of vias.

3. The IC of claim 1 , further comprising: A metal-insulator-metal (MIM) capacitor, the metal-insulator-metal (MIM) capacitor comprising: a first plate consisting of the first metallization layer on a surface of the substrate; A MIM insulator layer on the first plate; and A second plate is on the MIM insulator layer.

4. The IC of claim 3, further comprising: a first interlayer dielectric (ILD) layer on the surface of the substrate and the first plate and the second plate of the MIM capacitor; a first plurality of vias extending through the first ILD layer to the second plate of the MIM capacitor; a second plurality of vias extending through the first ILD layer to the first plate of the MIM capacitor; a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the second plate of the MIM capacitor through the first plurality of vias; and A third portion of the third metallization layer is on the first ILD layer and coupled to the first plate of the MIM capacitor through the second plurality of vias.

5. The IC of claim 1 , further comprising an inductor, the inductor comprising: a third portion of the first metallization layer on the surface of the substrate; a first interlayer dielectric (ILD) layer on the surface of the substrate and the third portion of the first metallization layer; a plurality of vias extending through the first ILD layer to the third portion of the first metallization layer; and A second portion of the third metallization layer is on the first ILD layer and coupled to the third portion of the first metallization layer through the plurality of vias.

6. The IC of claim 1 further comprising an oxide layer directly on a surface of the substrate.

7. The IC of claim 1, wherein the substrate comprises a high resistivity silicon (HRS) substrate.

8. The IC of claim 1, wherein the IC is integrated in an integrated passive device (IPD).

9. The IC of claim 8, wherein the IPD is integrated into a radio frequency (RF) filter.

10. The IC of claim 9, wherein the RF filter is integrated into a radio frequency front end (RFFE) module.

11. A method for manufacturing a thin film resistor (TFR) device structure, the method comprising: forming a first portion of a first metallization layer and a second portion of the first metallization layer on a substrate; forming a first portion of a dielectric layer on the first portion of the first metallization layer, and forming a second portion of the dielectric layer on the second portion of the first metallization layer; forming a first portion of a second metallization layer on the first portion of the dielectric layer, and forming a second portion of the second metallization layer on the second portion of the dielectric layer; as well as A first portion of a third metallization layer is formed to couple the first portion of the second metallization layer to the second portion of the second metallization layer.

12. The method according to claim 11, further comprising: depositing a first interlayer dielectric (ILD) layer on a surface of the substrate and the first portion and the second portion of the second metallization layer; forming a first plurality of vias extending through the first ILD layer to the first portion of the second metallization layer; forming a second plurality of vias extending through the first ILD layer to the second portion of the second metallization layer; forming a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the first portion of the second metallization layer through the first plurality of vias; as well as A third portion of the third metallization layer is formed, the third portion of the third metallization layer being on the first ILD layer and coupled to the second portion of the second metallization layer through the second plurality of vias.

13. The method according to claim 11, further comprising: forming a first plate consisting of the first metallization layer on a surface of the substrate; forming a metal-insulator-metal (MIM) insulator layer on the first plate; as well as A second plate is formed on the MIM insulator layer.

14. The method according to claim 13, further comprising: depositing a first interlayer dielectric (ILD) layer on the surface of the substrate and the first plate and the second plate; forming a first plurality of vias extending through the first ILD layer to the second board; forming a second plurality of vias extending through the first ILD layer to the first board; forming a second portion of the third metallization layer, the second portion of the third metallization layer being on the first ILD layer and coupled to the second plate through the first plurality of vias; as well as A third portion of the third metallization layer is formed on the first ILD layer and coupled to the first plate through the second plurality of vias.

15. The method according to claim 11, further comprising: forming a third portion of the first metallization layer on a surface of the substrate; depositing a first interlayer dielectric (ILD) layer on the surface of the substrate and the third portion of the first metallization layer; forming a plurality of vias extending through the first ILD layer to the third portion of the first metallization layer; as well as A second portion of the third metallization layer is formed, the second portion of the third metallization layer being on the first ILD layer and coupled to the third portion of the first metallization layer through the plurality of vias.

16. The method of claim 11, further comprising depositing an oxide layer directly on a surface of the substrate.

17. The method of claim 11, wherein the substrate comprises a high resistivity silicon (HRS) substrate.

18. The method of claim 11, further comprising integrating the TFR device structure in an integrated passive device (IPD).

19. The method of claim 18, further comprising integrating the IPD in a radio frequency (RF) filter.

20. The method of claim 19, further comprising integrating the RF filter into a radio frequency front end (RFFE) module.

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