Metal thin film resistor and method of manufacturing the same

Abstract

The application provides a metal thin film resistor and a preparation method thereof. The original HiR mask pattern in a silicon-based high resistance resistor process is subjected to a Boolean operation NOT to remove the original SAB mask pattern, which is used as a contact area of a subsequent CT contact hole. Then, the original SAB mask pattern in the silicon-based high resistance resistor process is subjected to a Boolean operation to define a metal thin film resistor mask pattern. Subsequently, the metal thin film resistor is formed on the patterned low resistance metal layer. In the process of port migration from the silicon-based high resistance resistor process to the metal thin film resistor process, the mask pattern in the silicon-based high resistance resistor process does not need to be changed, and the consistency of the resistance length definition mode between the two ports can be realized only by subjecting the mask pattern in the silicon-based high resistance resistor process to the required Boolean operation. The layout of the back-end CT process is not changed, the design resistance lengths of the two ports have a consistent definition, and the risk of complex operation and poor CT and MET1 contact caused by the change of the layout of the back-end CT process is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a metal thin-film resistor and its preparation method. Background Technology

[0002] In current advanced logic chip manufacturing processes, high-resistance (Hi-R) layers are a key element in circuit design used to reduce voltage and current. High resistance can be divided into active resistors and passive resistors. Active resistors typically utilize the resistive characteristics exhibited by transistors in specific operating regions. Passive resistors are high-resistance thin-film conductive layers fabricated in specific areas of the device. Because passive resistors are unaffected by current and voltage and have stable performance, they are used in most integrated circuit designs.

[0003] Currently, there are two main technologies for passive resistors. One is... Figure 6 Metal thin-film resistors, used to achieve high-resistivity layers, are also called high-resistivity metal layer (Hi-R metal layer); another type is... Figure 5 Polycrystalline silicon resistors are formed by doping polycrystalline silicon materials.

[0004] For example Figure 5 Polycrystalline silicon resistors are generally prepared using the following methods: Figure 1 As shown, a doped polysilicon layer 101 is formed on the substrate 100; as Figure 2 As shown, the polysilicon layer 101 is then patterned using a HiR mask to form a patterned polysilicon layer 102 in a predetermined region (the region where a resistor needs to be formed); as Figure 3 As shown, an SAB thin film 104 is then formed, and the SAB thin film 104 is patterned based on the SAB mask 103 to obtain the following... Figure 4 The patterned SAB film 104 shown; as Figure 5 As shown, a metal silicide layer 105 is then formed in the remaining area of ​​the patterned polysilicon layer 102 using a Salicide process as the ohmic contact layer for subsequent contact holes (CTs); as Figure 5 As shown, a CT contact hole 106 is finally formed on the metal silicide layer 105. Therefore, for polysilicon resistors, as... Figure 5 As shown, its designed resistor length is defined by the boundary of the patterned SAB thin film 104, as... Figure 5 L1 in the middle. And for such as Figure 6The preparation method is generally as follows: forming the metal thin film resistor 107 on a preset area (an area where the resistor is to be formed) of the substrate 100; and then directly forming the CT contact hole 106 at two ends of the metal thin film resistor 107. Therefore, for the metal thin film resistor 107, the design resistor length is defined by the boundary of the two-end CT contact hole 106, that is, L2. Figure 6 When it is required to switch between the two resistors, due to the different resistor length definition manners, the resistor length will be offset during the migration, at which time the layout of the back-end CT contact hole process needs to be changed, as shown in FIG. 3, the CT contact hole 106 in FIG. 2 is migrated from the outer side to the inner side along the arrow direction through operation, so that the design resistor length (L2) of the metal thin film and the design resistor length (L1) of the polysilicon resistor are consistent, both of which are the boundary of the patterned SAB thin film 104, which needs to consume very complex operation, and there is a risk of poor connection with MET1 (the first metal layer) when the CT contact hole is moved, affecting the reliability of the circuit. Figure 7 Figure 6 SUMMARY

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a metal thin film resistor and a preparation method thereof, which are used to solve the problem that, in the migration process of the port of the metal thin film resistor to the port of the polysilicon resistor, due to the different boundary definition manners of the design resistor length of the two, the resistor length will be offset during the migration, the layout of the back-end CT process needs to be changed to make the design resistor length of the two consistent, thereby causing complex operation and the problem of poor contact between the subsequent CT and MET1.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a metal thin film resistor, which comprises the following steps:

[0007] providing a substrate, and sequentially forming a low-resistance metal layer and a first hard mask layer on the substrate;

[0008] performing etching patterning on the first hard mask layer based on a modified HiR mask to obtain a patterned first hard mask layer, and the area where the patterned first hard mask layer is located defines a subsequent CT contact hole forming area; wherein the modified HiR mask pattern is obtained by performing Boolean operation of the original HiR mask pattern NOT the original SAB mask pattern;

[0009] etching the low-resistance metal layer based on the patterned first hard mask layer to form a patterned low-resistance metal layer and remove the patterned first hard mask layer;

[0010] ​​forming a high-resistance metal layer and a second hard mask layer on the substrate and the patterned low-resistance metal layer in sequence;

[0011] etching and patterning the second hard mask layer based on the modified SAB mask to obtain a patterned second hard mask layer, wherein the area where the patterned second hard mask layer is located defines a subsequent metal thin film resistor forming area; wherein the modified SAB mask pattern is obtained by performing a Boolean operation on the original SAB mask pattern to obtain a metal thin film resistor mask pattern;

[0012] etching the high-resistance metal layer based on the patterned second hard mask layer to form the metal thin film resistor;

[0013] forming the CT contact hole through the metal thin film resistor and the patterned second hard mask layer on the patterned low-resistance metal layer.

[0014] Optionally, the substrate is a silicon-based substrate.

[0015] Optionally, a shallow trench isolation structure is formed in the substrate; and the metal thin film resistor is formed above the shallow trench isolation structure.

[0016] Further, a metal gate structure is formed on the shallow trench isolation structure, and the metal gate structure and the metal thin film resistor are isolated by an insulating layer.

[0017] Optionally, the material of the low-resistance metal layer is titanium nitride material, and the material of the high-resistance metal layer is titanium nitride material.

[0018] Further, the thickness of the low-resistance metal layer is more than ten times the thickness of the high-resistance metal layer.

[0019] Optionally, the first hard mask layer is a silicon nitride layer and / or a silicon oxide layer, and the second hard mask layer is a silicon nitride layer and / or a silicon oxide layer.

[0020] Optionally, the method for forming the CT contact hole comprises:

[0021] forming a surface-flat dielectric layer on the substrate and the patterned second hard mask layer;

[0022] etching the dielectric layer, the patterned second hard mask layer and the metal thin film resistor in sequence to form a CT hole;

[0023] filling the CT hole with a metal conductive material to obtain the CT contact hole.

[0024] Optionally, the method for obtaining the patterned first hard mask layer comprises:

[0025] forming a first photoresist layer on the first hard mask layer;

[0026] performing patterning on the first photoresist layer by using the modified HiR mask to obtain a patterned first photoresist layer;

[0027] etching the first hard mask layer based on the patterned first photoresist layer to obtain the patterned first hard mask layer;

[0028] removing the patterned first photoresist layer;

[0029] the method for obtaining the patterned second hard mask layer comprises:

[0030] forming a second photoresist layer on the second hard mask layer;

[0031] performing patterning on the second photoresist layer by using the modified SAB mask to obtain a patterned second photoresist layer;

[0032] etching the second hard mask layer based on the patterned second photoresist layer to obtain the patterned second hard mask layer;

[0033] removing the patterned second photoresist layer.

[0034] The application further provides a metal thin film resistor prepared by using the preparation method of the metal thin film resistor according to any one of the above.

[0035] As described above, the metal thin film resistor and its fabrication method of the present invention involve obtaining a modified HiR mask pattern by performing a Boolean operation NOT on the original HiR mask pattern in the silicon-based high-resistivity resistor process. This modified HiR mask pattern serves as the region for ohmic contact of the subsequent CT contact hole, i.e., the patterned low-resistivity metal layer region. Then, the original SAB mask pattern in the silicon-based high-resistivity resistor process is modified by performing a Boolean operation to obtain a modified SAB mask pattern, thereby defining the metal thin film resistor mask pattern. Subsequently, a metal thin film resistor is formed based on the metal thin film resistor mask pattern, covering the patterned low-resistivity metal layer. Finally, a CT contact hole connected to the patterned low-resistivity metal layer is formed. Since the regions between the patterned low-resistivity metal layers are actually the original SAB mask pattern, and the metal thin-film resistor is formed on the patterned low-resistivity metal layer, the design resistance length of the final metal thin-film resistor can be defined by the boundary of the original SAB mask pattern. This boundary of the original SAB mask pattern is also the method for defining the resistance length of silicon-based high-resistivity resistors in the silicon-based high-resistivity resistor process. Therefore, during the port migration from the silicon-based high-resistivity resistor process to the metal thin-film resistor process, there is no need to change the mask pattern in the silicon-based high-resistivity resistor process. The consistency of the resistance length definition between the two ports can be achieved simply by performing the required Boolean operations on the mask pattern in the silicon-based high-resistivity resistor process. This avoids the need to change the layout of the back-end CT process to ensure a consistent definition of the design resistance length between the two ports, thus avoiding the complex calculations and the risk of poor contact between the CT and MET1 caused by changing the layout of the back-end CT process. Attached Figure Description

[0036] Figures 1 to 5 The diagram shows the cross-sectional structure of each step in the fabrication process of polycrystalline silicon resistors in the prior art.

[0037] Figure 6 The diagram shows a cross-sectional structure of a metal thin-film resistor 107 in the prior art.

[0038] Figure 7 This is a top view diagram showing the structure where the CT contact hole needs to be moved when the design length of the metal thin film resistor needs to be consistent with the design length of the polycrystalline silicon resistor.

[0039] Figures 8 to 26 The diagram shows the steps in the preparation method of the metal thin film resistor of the present invention.

[0040] Component designation explanation

[0041] 100 substrate

[0042] 101 polycrystalline silicon layer

[0043] 102 Patterned polysilicon layers

[0044] 103 SAB mask layer

[0045] 104 SAB mask

[0046] 105 metal silicide layer

[0047] 106 CT contact hole

[0048] 107 metal thin film resistor

[0049] 200 substrate

[0050] 201 shallow trench isolation structure

[0051] 202 metal gate structure

[0052] 203 gate metal layer

[0053] 204 work function layer

[0054] 205 high-K gate dielectric layer

[0055] 206 insulating layer

[0056] 207 low-resistance metal layer

[0057] 208 first hard mask layer

[0058] 209 first photoresist layer

[0059] 210 patterned first photoresist layer

[0060] 211 patterned first hard mask layer

[0061] 212 patterned low-resistance metal layer

[0062] 213 high-resistance metal layer

[0063] 214 second hard mask layer

[0064] 215 second photoresist layer

[0065] 216 patterned second photoresist layer

[0066] 217 patterned second hard mask layer

[0067] 218 metal thin film resistor

[0068] 219 dielectric layer

[0069] 220 CT hole

[0070] 221 CT contact hole

[0071] 222 original HiR mask pattern

[0072] 223 original SAB mask pattern

[0073] 223a original SAB pattern

[0074] 224 modified HiR mask pattern

[0075] 224a modified HiR pattern

[0076] 225 modified SAB mask pattern DETAILED DESCRIPTION

[0077] The present application is herein described, by way of example only, with the assistance of specific details to facilitate a thorough understanding of the application. The description is intended only by way of description of the preferred embodiments of the application, and could be implemented or applied in a multitude of different ways. Other embodiments could be utilized or modifications could be made without departing from the spirit of the application.

[0078] Please refer to FIGS. 8 to Figure 24 It is to be understood that the figures provided in the embodiments are only schematic and are intended to provide the basic understanding of the application. In the description of the embodiments, only the components related to the application are shown and described, and the number, shape and size of the components are not drawn according to the actual implementation, and the actual implementation of each component can be changed arbitrarily, and the layout of the components can be more complex.

[0079] The embodiment provides a preparation method of a metal thin film resistor, and the preparation method comprises the following steps:

[0080] S1, providing a substrate, and sequentially forming a low-resistance metal layer and a first hard mask layer on the substrate;

[0081] S2, performing etching patterning on the first hard mask layer based on a modified HiR mask to obtain a patterned first hard mask layer, and a region where the patterned first hard mask layer is located defines a subsequent CT contact hole forming region; wherein the modified HiR mask pattern is obtained by Boolean operation of NOT original SAB mask pattern on original HiR mask pattern;

[0082] S3, etching the low-resistance metal layer based on the patterned first hard mask layer to form a patterned low-resistance metal layer and remove the patterned first hard mask layer;

[0083] S4, sequentially forming a high-resistance metal layer and a second hard mask layer on the substrate and the patterned low-resistance metal layer;

[0084] S5, the second hard mask layer is etched and patterned based on the modified SAB mask to obtain a patterned second hard mask layer. The region where the patterned second hard mask layer is located defines the subsequent metal thin film resistor formation region. The modified SAB mask pattern is obtained by performing Boolean operations on the original SAB mask pattern to obtain the metal thin film resistor mask pattern.

[0085] S6, based on the patterned second hard mask layer, the high-resistivity metal layer is etched to form the metal thin film resistor;

[0086] S7, forming the CT contact hole on the patterned low-resistivity metal layer, which penetrates the metal thin film resistor and the patterned second hard mask layer.

[0087] The method for fabricating the metal thin-film resistor in this embodiment involves using a Boolean operation to NOT the original HiR mask pattern in the silicon-based high-resistivity resistor process, resulting in a modified HiR mask pattern that serves as the area for ohmic contact of the subsequent CT contact hole, i.e., the patterned low-resistivity metal layer area. Then, the original SAB mask pattern in the silicon-based high-resistivity resistor process is modified using a Boolean operation to obtain a modified SAB mask pattern, which defines the metal thin-film resistor mask pattern. Next, a metal thin-film resistor is formed based on this metal thin-film resistor mask pattern, covering the patterned low-resistivity metal layer. Finally, a CT contact hole connected to the patterned low-resistivity metal layer is formed. Since the regions between the patterned low-resistivity metal layers are actually the original SAB mask pattern, and the metal thin-film resistor is formed on the patterned low-resistivity metal layer, the design resistance length of the final metal thin-film resistor can be defined by the boundary of the original SAB mask pattern. This boundary of the original SAB mask pattern is also the method for defining the resistance length of silicon-based high-resistivity resistors in the silicon-based high-resistivity resistor process. Therefore, during the port migration from the silicon-based high-resistivity resistor process to the metal thin-film resistor process, there is no need to change the mask pattern in the silicon-based high-resistivity resistor process. The consistency of the resistance length definition between the two ports can be achieved simply by performing the required Boolean operations on the mask pattern in the silicon-based high-resistivity resistor process. This avoids the need to change the layout of the back-end CT process to ensure a consistent definition of the design resistance length between the two ports, thus avoiding the complex calculations and the risk of poor contact between the CT and MET1 caused by changing the layout of the back-end CT process.

[0088] The method for preparing the metal thin-film resistor of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0089] like Figure 8 As shown, step S1 is performed first, a substrate 200 is provided, and a low-resistivity metal layer 207 and a first hard mask layer 208 are sequentially formed on the substrate 200.

[0090] It should be noted that, for the convenience of understanding, only a part of the substrate 200 related to the preparation of the metal thin film resistor is shown in the embodiment, and the substrate 200 actually further includes other areas required for the preparation of the device.

[0091] As an example, the substrate 200 can include a semiconductor compound, an insulating material, a conductor material, or any combination thereof, and can be a single-layer structure or include a multi-layer structure. Therefore, the substrate 200 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors; and can also include a layered substrate such as, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium on insulator. In the embodiment, the substrate 200 is selected to be a silicon-based substrate.

[0092] The metal thin film resistor is generally formed in a specific area of the device, for example, is generally formed on the shallow trench isolation structure 201 of the device. As shown in Figure 8 , in the embodiment, the shallow trench isolation structure 201 is formed in the substrate 200, and the subsequently formed metal thin film resistor is formed above the shallow trench isolation structure 201. In addition, for the convenience of understanding, only a part of the shallow trench isolation structure 201 is shown in the drawing, and other parts not related to the preparation of the metal thin film resistor in the embodiment are not shown.

[0093] Further, the metal gate structure 202 is further formed on the shallow trench isolation structure 201, and the surface flush insulating layer 206 is formed on the metal gate structure 202 and the shallow trench isolation structure 201, and the subsequently formed metal thin film resistor is prepared by stacking on the insulating layer 206 as a base layer. As shown in Figure 8 , as an example, the metal gate structure 202 includes, from inside to outside, the gate metal layer 203, the work function layer 204, and the high-K gate dielectric layer 205. Generally, aluminum material is selected as the gate metal layer 203, titanium nitride material and / or tantalum nitride material is selected as the work function layer 204, and silicon oxynitride material is selected as the high-K dielectric layer 205, but it is not limited thereto, and other suitable materials can also be used as the metal gate structure 202, which is only an example. It should be noted that the metal gate structure 202 is prepared synchronously with the metal gate structure of the active area of the device, and this structure does not affect the subsequently prepared metal thin film resistor, so the insulating layer 206 is required for electrical isolation.

[0094] As an example, the material of the low-resistance metal layer 207 can be selected from any suitable low-resistance metal material, such as aluminum, copper, titanium nitride, tantalum nitride, etc., and preferably, the material of the low-resistance metal layer 207 is selected to be titanium nitride material, which is easy to etch and not easy to diffuse.

[0095] As an example, the first hard mask layer 208 is selected as a single-layer structure of a silicon nitride layer or a silicon oxide layer or a stacked-layer structure of a silicon nitride layer and a silicon oxide layer, and the silicon nitride layer is located at the lower layer and the silicon oxide layer is located at the upper layer.

[0096] As shown in Figure 9 , Figure 10 and Figure 13 , then step S2 is performed to etch and pattern the first hard mask layer 208 based on the modified HiR mask to obtain a patterned first hard mask layer 211, and the area where the patterned first hard mask layer 211 is located defines a subsequent CT contact hole forming area; wherein the modified HiR mask pattern 224 is obtained by performing a Boolean NOT operation on the original HiR mask pattern 222 and the original SAB mask pattern 223.

[0097] Wherein, Figure 9 is a schematic diagram of the superposition of the original HiR mask pattern 222 and the original SAB mask pattern 223 on the relatively low resistance metal layer 207 in the silicon-based high resistance resistor process, Figure 10 shows the modified HiR mask pattern 224 of the relatively low resistance metal layer 207 obtained by performing a Boolean NOT operation on the original HiR mask pattern 222 and the original SAB mask pattern 223. It should be noted that the mask pattern mentioned in this embodiment only shows the mask pattern related to the process of preparing a metal thin film resistor, and in actual production, the entire mask pattern also includes the mask pattern for preparing the structure of other areas of the device. In this embodiment, the mask pattern of this part is not changed, so it is not shown here. For example, the original HiR mask pattern 222 refers to the mask pattern used in the HiR process, which includes not only the mask pattern shown in Figure 9 for preparing on the shallow trench isolation structure, but also the mask pattern for preparing on other areas of the device (not shown in the figure). Similarly, the original SAB mask pattern 223 refers to the mask pattern used in the SAB process, which includes not only the mask pattern shown in Figure 9 for preparing on the shallow trench isolation structure, but also the mask pattern for preparing on other areas of the device (not shown in the figure).

[0098] As shown in Figures 11 to 13 , as a specific example, the method for forming the patterned first hard mask layer 211 includes the following steps:

[0099] S21, as shown in Figure 11 , a first photoresist layer 209 is formed on the first hard mask layer 208;

[0100] S22, as shown in Figure 10 and Figure 12As shown, the first photoresist layer 209 is patterned by using the modified HiR mask 224 to obtain a patterned first photoresist layer 210.

[0101] S23, as shown, the first hard mask layer 208 is etched based on the patterned first photoresist layer 210 to obtain a patterned first hard mask layer 211. Figure 13

[0102] S24, as shown, the patterned first photoresist layer 210 is removed. Figure 13

[0103] As shown, step S3 is then performed, the low-resistance metal layer 207 is etched based on the patterned first hard mask layer 211 to form a patterned low-resistance metal layer 212 and remove the patterned first hard mask layer 211. Figure 14 Figure 15 As shown, step S4 is then performed, a high-resistance metal layer 213 and a second hard mask layer 214 are sequentially formed on the substrate 200 and the patterned low-resistance metal layer 212.

[0104] As shown, step S4 is then performed, a high-resistance metal layer 213 and a second hard mask layer 214 are sequentially formed on the substrate 200 and the patterned low-resistance metal layer 212. Figure 15 As shown, step S4 is then performed, a high-resistance metal layer 213 and a second hard mask layer 214 are sequentially formed on the substrate 200 and the patterned low-resistance metal layer 212.

[0105] As shown, step S4 is then performed, a high-resistance metal layer 213 and a second hard mask layer 214 are sequentially formed on the substrate 200 and the patterned low-resistance metal layer 212. Figure 16 As an example, the material of the high-resistance metal layer 213 can be selected from any metal material suitable for high-resistance resistance in a device, such as titanium nitride, tantalum nitride, etc. Preferably, when the material of the low-resistance metal layer 207 is titanium nitride, the material of the high-resistance metal layer 213 is also titanium nitride, which is easy to etch and not easy to diffuse. In addition, titanium nitride can adjust the resistance value by thickness, and the thicker the resistance value is smaller. In the present embodiment, the materials of the low-resistance metal layer 207 and the high-resistance metal layer 213 are both titanium nitride, and the thickness of the low-resistance metal layer 207 is more than ten times the thickness of the high-resistance metal layer 213.

[0106] As an example, the second hard mask layer 214 is selected as a single-layer structure of a silicon nitride layer or a silicon oxide layer or a stacked structure of a silicon nitride layer and a silicon oxide layer, and the silicon nitride layer is located in the lower layer and the silicon oxide layer is located in the upper layer.

[0107] As shown, step S4 is then performed, a high-resistance metal layer 213 and a second hard mask layer 214 are sequentially formed on the substrate 200 and the patterned low-resistance metal layer 212.

[0108] Figure 17 Figure 18 Figure 22 ​​​​​​As shown, step S5 is then performed, where the second hard mask layer 214 is etched and patterned based on the modified SAB mask to obtain a patterned second hard mask layer 217. The area where the patterned second hard mask layer 217 is located defines the subsequent metal thin film resistor formation area. The modified SAB mask pattern 225 is obtained by performing Boolean operations on the original SAB mask pattern 223 to obtain the metal thin film resistor mask pattern.

[0109] in, Figure 17 This is a schematic diagram of the original SAB mask pattern 223 relative to the high-resistivity metal layer 213 in a silicon-based high-resistivity resistive process. Figure 18 This is a comparative schematic diagram showing the modified SAB mask pattern 225, obtained by performing Boolean operations on the original SAB mask pattern 223, relative to the high-resistivity metal layer 213.

[0110] like Figures 19 to 22 As shown, as a specific example, the method for forming the graphical second hard mask layer 217 includes the following steps:

[0111] S51, such as Figure 19 As shown, a second photoresist layer 215 is formed on the second hard mask layer 214;

[0112] S52, such as Figure 18 and Figure 20 As shown, the modified SAB mask is used to pattern the second photoresist layer 215 to obtain a patterned second photoresist layer 216.

[0113] S53, such as Figure 21 As shown, the second hard mask layer 214 is etched based on the patterned second photoresist layer 216 to obtain the patterned second hard mask layer 217.

[0114] S54, such as Figure 22 As shown, the patterned second photoresist layer 216 is removed.

[0115] like Figure 22 and Figure 23 As shown, step S6 is then performed, whereby the high-resistivity metal layer 213 is etched based on the patterned second hard mask layer 217 to form the metal thin film resistor 218.

[0116] like Figure 26 As shown, step S7 is performed to form a CT contact hole 221 on the patterned low-resistivity metal layer 212, which penetrates the metal thin film resistor 218 and the patterned second hard mask layer 217.

[0117] like Figures 24 to 26As shown, as a specific example, the method for forming the CT contact hole 221 includes the following steps:

[0118] S71, such as Figure 24 As shown, a flat dielectric layer 219 is formed on the substrate 200 and the patterned second hard mask layer 217. That is, the dielectric layer 219 covers the entire structure on the insulating layer 206 and its surface is flat. The surface of the dielectric layer 219 can be planarized by CMP process after the dielectric layer 219 is formed.

[0119] S72, such as Figure 25 As shown, the dielectric layer 219, the patterned second hard mask layer 217 and the metal thin film resistor 218 are etched sequentially to form a CT hole 220, that is, the CT hole 220 exposes the surface of the patterned low-resistivity metal layer 212.

[0120] S73, such as Figure 26 As shown, the CT hole 220 is filled with a conductive metallic material to obtain the CT contact hole 221. For example, the CT hole 220 can be filled with PVD process and the metal material outside the CT hole 220 can be ground with CMP process, leaving only the metal material of the CT hole 220 to obtain the CT contact hole 221.

[0121] This embodiment also provides a metal thin film resistor, which is prepared using the metal thin film resistor preparation method of this embodiment.

[0122] In summary, the present application provides a metal thin film resistor and a preparation method thereof. The original HiR mask pattern in the silicon-based high resistance resistor process is subjected to Boolean operation NOT the original SAB mask pattern to obtain a modified HiR mask pattern as the area for subsequent CT contact hole ohmic contact, i.e. the patterned low resistance metal layer area. Then the original SAB mask pattern in the silicon-based high resistance resistor process is subjected to Boolean operation to obtain a modified SAB mask pattern, so that the modified SAB mask pattern defines a metal thin film resistor mask pattern. Then, based on the metal thin film resistor mask pattern, a metal thin film resistor is formed on the patterned low resistance metal layer. Finally, a CT contact hole is formed on the patterned low resistance metal layer. Since the area between the patterned low resistance metal layers is actually the original SAB mask pattern, and the metal thin film resistor is formed on the patterned low resistance metal layer, the design resistance length of the finally formed metal thin film resistor can be defined by the boundary of the original SAB mask pattern, and the boundary of the original SAB mask pattern is also the resistance length definition method of the silicon-based high resistance resistor in the silicon-based high resistance resistor process. Therefore, in the process of port migration from the silicon-based high resistance resistor process to the metal thin film resistor process, the mask pattern in the silicon-based high resistance resistor process does not need to be changed, and only the required Boolean operation of the mask pattern in the silicon-based high resistance resistor process is needed to realize the consistency of the resistance length definition method between the two ports. It is avoided to change the layout of the back-end CT process to make the design resistance lengths of the two ports have consistent definition, thereby avoiding the risk of complex operation and poor CT and MET1 contact caused by changing the layout of the back-end CT process. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0123] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating a metal thin film resistor, characterized by, The preparation method comprises the following steps: A substrate is provided, and a low-resistance metal layer and a first hard mask layer are sequentially formed on the substrate; The first hard mask layer is etched and patterned based on a modified high-resistance metal mask, to obtain a patterned first hard mask layer, and a region where the patterned first hard mask layer is located defines a subsequent CT contact hole forming region; wherein the modified high-resistance metal mask pattern is obtained by performing a Boolean operation of an original high-resistance metal mask pattern and a NOT original SAB mask pattern; The low-resistance metal layer is etched based on the patterned first hard mask layer, to form a patterned low-resistance metal layer and remove the patterned first hard mask layer; A high-resistance metal layer and a second hard mask layer are sequentially formed on the substrate and the patterned low-resistance metal layer; The second hard mask layer is etched and patterned based on a modified SAB mask, to obtain a patterned second hard mask layer, and a region where the patterned second hard mask layer is located defines a subsequent metal thin film resistor forming region; wherein the modified SAB mask pattern is obtained by performing a Boolean operation of the original SAB mask pattern to obtain a metal thin film resistor mask pattern; The high-resistance metal layer is etched based on the patterned second hard mask layer, to form the metal thin film resistor; The CT contact hole is formed on the patterned low-resistance metal layer, penetrating through the metal thin film resistor and the patterned second hard mask layer.

2. The method of claim 1, wherein: The substrate is a silicon substrate.

3. The method of claim 1, wherein: The substrate has a shallow trench isolation structure formed therein, and the metal thin film resistor is formed above the shallow trench isolation structure.

4. The method of claim 3, wherein: A metal gate structure is formed on the shallow trench isolation structure, and the metal gate structure and the metal thin film resistor are isolated by an insulating layer.

5. The method of claim 1, wherein: The material of the low-resistance metal layer is titanium nitride material, and the material of the high-resistance metal layer is titanium nitride material.

6. The method of claim 5, wherein: The thickness of the low-resistance metal layer is more than ten times the thickness of the high-resistance metal layer.

7. The method of claim 1, wherein: The first hard mask layer is a silicon nitride layer and / or a silicon oxide layer, and the second hard mask layer is a silicon nitride layer and / or a silicon oxide layer.

8. The method of claim 1, wherein the metal thin film resistor is formed on a substrate. The method for forming the CT contact hole comprises: A surface flat medium layer is formed on the substrate and the patterned second hard mask layer; A CT hole is formed by sequentially etching the medium layer, the patterned second hard mask layer and the metal thin film resistor; The CT hole is filled with a metal conductive material, to obtain the CT contact hole.

9. The preparation method of the metal thin film resistor according to claim 1, wherein: The method for obtaining the patterned first hard mask layer comprises: A first photoresist layer is formed on the first hard mask layer; The first photoresist layer is patterned by using the modified high-resistance metal mask, to obtain a patterned first photoresist layer; The first hard mask layer is etched based on the patterned first photoresist layer, to obtain the patterned first hard mask layer; The patterned first photoresist layer is removed; The method for obtaining the patterned second hard mask layer comprises: A second photoresist layer is formed on the second hard mask layer; The second photoresist layer is patterned by using the modified SAB mask to obtain a patterned second photoresist layer; The second hard mask layer is etched based on the patterned second photoresist layer to obtain a patterned second hard mask layer; The patterned second photoresist layer is removed.

10. A thin film metal resistor characterized by: The metal thin film resistor is prepared by using the preparation method of the metal thin film resistor according to any one of claims 1-9.

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