Memory device and operating method thereof

Abstract

The invention relates to a storage device. An example storage device includes a non-volatile memory device including a plurality of memory blocks, and a memory controller that controls the non-volatile memory device. The memory controller performs a soft erase operation on a first memory block among the plurality of memory blocks, measures a first cell count by applying a first reference voltage to a plurality of first memory cells pre-selected from a plurality of memory cells of the first memory block after performing the soft erase operation, a first health index associated with a retention characteristic of the first memory block is generated based on the first cell count, and a reliability management operation is performed on the first memory block based on the first health index.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0085855 filed on July 3, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to the field of memory devices, and more particularly, to memory devices and methods of operating the same. Background Art

[0004] Flash memory devices are widely used as high-capacity storage for computing systems. Flash memory devices can store data based on the threshold voltage of a memory cell. However, the threshold voltage of a memory cell may change due to various factors. Thus, errors may occur in the data stored in the memory cell.

[0005] A memory block including memory cells storing data may remain alone for a long time. In this case, the memory block may be determined as a runtime bad block (RTBB) due to an error caused by a threshold voltage variation.

[0006] A storage device may perform a reliability management operation for managing the reliability of data stored in a memory block. A flash memory device may include a memory block. Due to process deviations of the memory blocks, the memory blocks may have different retention characteristics. Therefore, when the reliability management operation is performed on all memory blocks under the same conditions, the performance of the storage device may be reduced. Summary of the invention

[0007] The present disclosure relates to a storage device, including a storage device having improved performance and improved reliability by individually managing memory blocks and an operating method thereof.

[0008] In general, according to some aspects, a storage device includes: a nonvolatile memory device and a memory controller, the nonvolatile memory device including a plurality of memory blocks, the memory controller controlling the nonvolatile memory device. The memory controller performs a soft erase operation on a first memory block among the plurality of memory blocks, after performing the soft erase operation, measures a first cell count by applying a first reference voltage to a predetermined plurality of first memory cells among a plurality of memory cells from the first memory block, generates a first health index associated with a retention characteristic of the first memory block based on the first cell count, and performs a reliability management operation on the first memory block based on the first health index.

[0009] Generally, according to some other aspects, a method for operating a storage device, the storage device including a memory controller that controls a non-volatile memory device, the non-volatile memory device including multiple memory blocks, the method including: performing a pre-programming operation on a first memory block among the multiple memory blocks; performing a soft erase operation on the first memory block; applying a first reference voltage to a first memory cell predetermined from among multiple memory cells of the first memory block to measure a first cell count; based on the first cell count, generating a first health index associated with a retention characteristic of the first memory block; and based on the first health index, performing a reliability management operation on the first memory block.

[0010] In general, according to some other aspects, a memory device includes a nonvolatile memory device and a memory controller, the nonvolatile memory device including a plurality of memory blocks, and the memory controller controls the nonvolatile memory device. The memory controller includes a health index table and a health index lookup table, the health index table includes reference health indexes corresponding to the plurality of memory blocks, and the health index lookup table includes reference values. The memory controller performs a pre-programming operation on a first memory block from among the plurality of memory blocks, performs a soft erase operation on the first memory block after performing the pre-programming operation, measures a first cell count by applying a first reference voltage to a first memory cell predetermined from among first memory cells of the first memory block after performing the soft erase operation, generates a first health index associated with a retention characteristic of the first memory block based on the first cell count and the reference value, compares the first health index with a first reference health index corresponding to the first memory block from among the reference health indexes, updates the first reference health index to the first health index based on the comparison result, and performs a reliability management operation on the first memory block based on the first health index. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating an example of a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown in detail Figure 1 A block diagram of an example of a memory controller.

[0014] Figure 3 It is shown in detail Figure 1 A block diagram of an example of a non-volatile memory device.

[0015] Figure 4 It is shown Figure 3 A circuit diagram of an example of one memory block among a plurality of memory blocks included in a memory cell array.

[0016] Figure 5 It is shown Figure 4 Graph of example threshold voltage distributions for the memory cells shown in .

[0017] Figure 6 is a diagram for describing example retention characteristic differences of memory blocks.

[0018] Figure 7 It is shown Figure 1 A flowchart of an example method of operating a storage device.

[0019] Figure 8 and Fig. 9 Is used to describe Figure 7 FIG. 1 is a diagram of operation S110 .

[0020] Fig.10 It is shown Figure 1 A flowchart of an example method for generating a health index of a storage device.

[0021] Fig.11 Is used to describe Fig.10 FIG. 1 is a diagram of an example of a pre-program operation and a soft erase operation.

[0022] Fig.12 Is used to describe Fig.10 FIG. 10 is a diagram of operation S240 .

[0023] Fig.13 It is shown in detail Fig.10 Flow chart of operation S250.

[0024] Fig.14 Is used to describe Fig.10 FIG. 1 is a diagram of operation S250 .

[0025] Fig.15 It is shown Figure 1 A flowchart of another example of a method for generating a health index of a storage device.

[0026] Fig.16 Is used to describe Fig.15 Figure 2. Example of a dummy close operation.

[0027] Fig.17 It is shown Fig.16 A distribution plot of an example of dummy data.

[0028] Fig.18 is a diagram showing an example of a change in threshold voltage distribution of each memory block in which a virtual shut-down operation is performed.

[0029] Fig.19 Is used to describe Fig.15 FIG. 1 is a diagram of operation S350 .

[0030] Fig. 20 It is shown in detail Fig.15 Flow chart of operation S360.

[0031] Fig.21 is a diagram for describing an example of a health index generating method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Hereinafter, the embodiments of the present disclosure will be described in detail and clearly so that those skilled in the art can easily perform the present disclosure. Details such as detailed components and structures are provided only for a comprehensive understanding of the embodiments of the present disclosure. Therefore, without departing from the spirit and scope of the technology described herein, those skilled in the art may modify the embodiments disclosed herein. In addition, for clarity and conciseness, the description of known functions and structures is omitted. In the following figures or in the specific embodiments, in addition to the components shown in the figures or described in the specific embodiments, the components may be connected to any other components. The terms used in the specification are defined in view of the functions of the present disclosure and are not limited thereto. The definition of the term should be determined based on the content in the entire specification.

[0033] In the detailed description, components described with reference to terms such as "drivers", "blocks", "units", etc. will be implemented in software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, or application software. For example, hardware may include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components, or a combination thereof.

[0034] Figure 1 is a block diagram showing an example of a storage device according to an embodiment of the present disclosure. Figure 1 , the storage device 100 includes a nonvolatile memory device 110 and a memory controller 120 .

[0035] The memory controller 120 may store the data “DATA” in the nonvolatile memory device 110, or may read the data “DATA” stored in the nonvolatile memory device 110. For example, the memory controller 120 may transmit a command CMD, an address ADDR, and a control signal CTRL to the nonvolatile memory device 110, and may read the data “DATA” stored in the nonvolatile memory device 110; alternatively, the memory controller 120 may send a command CMD, an address ADDR, a control signal CTRL, and the data “DATA” to the nonvolatile memory device 110 so that the data “DATA” is stored in the nonvolatile memory device 110.

[0036] The nonvolatile memory device 110 may receive a command CMD and an address ADDR from the memory controller 120. The nonvolatile memory device 110 may operate in response to the received signals. For example, when the command CMD received from the memory controller 120 is a read command, the nonvolatile memory device 110 may return data "DATA" to the memory controller 120. When the command CMD received from the memory controller 120 is a program command, the nonvolatile memory device 110 may store the data "DATA" received from the memory controller 120.

[0037] Hereinafter, an embodiment in which the nonvolatile memory device 110 is a flash memory device and the storage device 100 is a solid state drive (SSD) will be representatively described. However, the present disclosure is not limited thereto.

[0038] The nonvolatile memory device 110 may include a plurality of memory blocks BLK1 to BLKn. Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of memory cells. A read or program operation of the plurality of memory cells may be performed based on a word line. In detail, a read or program operation of the plurality of memory cells may be performed in units of pages. Each of the plurality of memory blocks may be erased in units of blocks. In some embodiments, each of the memory cells may be implemented with a charge trap flash (CTF) memory cell.

[0039] For example, the threshold voltage of a memory cell may change due to various factors. As the threshold voltage of a memory cell changes, an error may occur in data stored in the memory cell.

[0040] For example, the change in the threshold voltage of the memory cell may be determined based on the retention characteristic. The retention characteristic may be associated with how long the data is maintained without loss after being stored in the memory cell. Due to the process characteristics of the nonvolatile memory device 110, the retention characteristic of the first memory block BLK1 may be different from the retention characteristic of the second memory block BLK2.

[0041] For example, when a charge loss phenomenon occurs, the threshold voltage of a programmed memory cell may decrease. The charge loss phenomenon may mean that the threshold voltage of a memory cell decreases as the charge stored in the memory cell leaks over time from a programming time point. The retention characteristic may be determined based on how much charge is lost in a memory block within a specific time (i.e., based on the charge loss amount).

[0042] For example, the retention characteristics of the second memory block BLK2 may be better than the retention characteristics of the first memory block BLK1. In this case, the amount of charge lost in the memory cells of the first memory block BLK1 may be greater than the amount of charge lost in the memory cells of the second memory block BLK2 over time from the programming time point. In this way, the decrement of the threshold voltage of the memory cells in the first memory block BLK1 may be greater than the decrement of the threshold voltage of the memory cells in the second memory block BLK2. Therefore, after the same time has passed from the programming time point, the data error rate of the first memory block BLK1 may be greater than the data error rate of the second memory block BLK2.

[0043] For the purpose of managing the reliability of the data "DATA" stored in the non-volatile memory device 110, the memory controller 120 may perform various reliability management operations. For example, the reliability management operations may include garbage collection operations, read reclaim operations, patrol read operations, etc. However, the present disclosure is not limited thereto.

[0044] The garbage collection operation refers to an operation of protecting free blocks in the nonvolatile memory device 110 by copying valid data of a first memory block to a second memory block as a new block and then invalidating the data existing in the first memory block. For example, a free block may mean a memory block including only invalid data.

[0045] The read reclaim operation refers to an operation of moving valid data present in a first memory block to a second memory block before an uncorrectable error occurs in data stored in the first memory block.

[0046] The patrol read operation refers to an operation of searching for a read recovery target block target for a read recovery operation in a memory block. For example, the patrol read operation may include performing a read operation on a preset memory cell among memory cells of a specific memory block, measuring a data error rate, and determining whether the specific memory block is a read recovery target block based on the error rate.

[0047] In order to minimize unnecessary operations so that the performance of the memory device 100 is improved, for example, the memory controller 120 may need to perform a patrol read operation at a point in time close to a point in time when an uncorrectable error occurs in data stored in a memory block.

[0048] For example, the memory controller 120 may periodically (or in the same cycle) perform a patrol read operation on each of the memory blocks BLK1 to BLKn. For example, when a reference time has passed since the time point when the storage device 100 is powered on, the memory controller 120 may perform a patrol read operation on the memory blocks BLK1 to BLKn. However, as described above, the retention characteristics of the second memory block BLK2 may be superior to the retention characteristics of the first memory block BLK1. In this case, when a reference time has passed since the time point when the storage device 100 is powered on, the data error rate of the first memory block BLK1 may be at a level that requires read recovery, and the data error rate of the second memory block BLK2 may be at a level that does not require read recovery. Even if the error rate of the second memory block BLK2 is low, the memory controller 120 may also unnecessarily perform a patrol read operation on the second memory block BLK2. In this case, the performance of the storage device 100 may be reduced.

[0049] In some embodiments, the memory controller 120 may include a health index manager 121 , a health index table 122 , and a health index lookup table (hereinafter, referred to as “LUT”) 123 .

[0050] The health index manager 121 may generate health indexes corresponding to the memory blocks BLK1 to BLKn. The health indexes may be associated with retention characteristics of the memory blocks.

[0051] The health index manager 121 may measure a cell count of a memory block based on a reference voltage. The health index manager 121 may generate a health index corresponding to the memory block based on the measured cell count and the LUT 123. The health index manager 121 may compare a current health index and a past health index of each memory block, and may update the health index table 122 based on the comparison result.

[0052] In some embodiments, the health index manager 121 may measure the cell count of the memory block performing the soft erase operation. For example, the soft erase operation may mean an operation of releasing only some of the charges stored in the memory block. Compared to the case of performing the normal erase operation, the memory cells of the memory block performing the soft erase operation may form a relatively high threshold voltage distribution. The soft erase operation will be described in detail with reference to the following drawings.

[0053] In some embodiments, the health index manager 121 may measure a cell count of a memory block performing a virtual shutdown operation. The virtual shutdown operation may mean an operation of programming dummy data in an unprogrammed memory cell. The virtual shutdown operation will be described in detail with reference to the following drawings.

[0054] The health index table 122 may include health indexes corresponding to the memory blocks BLK1 to BLKn of the nonvolatile memory device 110 .

[0055] LUT 123 may include multiple reference values. For example, LUT 123 may include information about the relationship between the health index and the cell count and information about the relationship between the reliability management operating condition and the health index. In some embodiments, the reliability management operating condition may include a patrol read execution condition and / or a read reclaim entry condition.

[0056] Reference Figure 8 and Fig. 9 The health index table 122 and the LUT 123 are described in detail.

[0057] In some embodiments, the memory controller 120 may perform reliability management operations on each memory block based on the health index. For example, the retention characteristics of the second memory block BLK2 may be better than the retention characteristics of the first memory block BLK1. The memory controller 120 may check the retention characteristics of the first memory block BLK1 and the second memory block BLK2 with reference to the health index table 122 and the LUT 123.

[0058] For example, the memory controller 120 may determine the patrol read cycle of the first memory block BLK1 and the second memory block BLK2 with reference to the health index table 122 and the LUT 123. The memory controller 120 may perform a patrol read operation on the first memory block BLK1 and the second memory block BLK2 based on the determined patrol read cycle. In this case, the patrol read cycle of the second memory block BLK2 may be longer than the patrol read cycle of the first memory block BLK1.

[0059] In other words, in some embodiments, the storage device 100 may check the retention characteristics of each of the memory blocks BLK1 to BLKn, and may perform reliability management operations on each memory block based on the retention characteristics of each of the memory blocks BLK1 to BLKn. That is, the storage device 100 may manage the memory blocks BLK1 to BLKn individually based on the health index table 122 and the LUT 123. In this case, the performance of the storage device 100 may be prevented from being degraded. Therefore, in some embodiments, a storage device 100 having improved reliability and improved performance may be provided.

[0060] Figure 2 It is shown in detail Figure 1 The memory controller 120 includes a health index manager 121, a health index table 122, a LUT 123, a processor 124, a volatile memory 125, an ECC engine 126, a flash translation layer (FTL) 127, a host interface 128, and a non-volatile memory (NVM) interface 129.

[0061] The health index manager 121 , the health index table 122 , the LUT 123 , the processor 124 , the volatile memory 125 , the ECC engine 126 , the flash translation layer 127 , the host interface 128 , and the non-volatile memory interface 129 may be connected to each other through a bus.

[0062] refer to Figure 1 The health index manager 121 , the health index table 122 , and the LUT 123 are described, and therefore, additional description will be omitted to avoid redundancy.

[0063] The processor 124 may control the overall operation of the memory controller 120. For example, the health index manager 121 and the FTL 127 may be provided in the form of software and may be driven by the processor 124.

[0064] The volatile memory 125 may be used as a main memory, a buffer memory, or a cache memory of the memory controller 120. The volatile memory 125 may temporarily store read data and a cell count read from the nonvolatile memory device 110. In addition, the volatile memory 125 may include information for managing a memory space of the nonvolatile memory device 110 and information about program / erase cycles, erase counts (ECs), and cycle counts (LCs) for each memory block. In some embodiments, the health index table 122 and the LUT 123 may be stored in the volatile memory 125.

[0065] The ECC engine 126 may detect and correct errors of data obtained from the non-volatile memory device 110. For example, the ECC engine 126 may have a given level of error correction capability. The ECC engine 126 may process data having an error level (e.g., the number of flipped bits) that exceeds the error correction capability as an uncorrectable error.

[0066] The FTL 127 may perform a role of converting a logical address received from an external device (eg, a host) into a physical address used in the nonvolatile memory device 110. In addition, the FTL 127 may perform reliability management operations for the nonvolatile memory device 110. Figure 1 As described, reliability management operations may include garbage collection operations, read reclaim operations, patrol read operations, and the like.

[0067] In some embodiments, the health index manager 121 and the FTL 127 may be implemented in the form of firmware. For example, the processor 124 may implement the health index manager 121 and the FTL 127 by loading instructions stored in the non-volatile memory device 110 into the volatile memory 125 and executing the loaded instructions. However, the present disclosure is not limited thereto. For example, the health index manager 121 and the FTL 127 may be implemented with separate hardware, or may be implemented with a combination of hardware and software.

[0068] In some implementations, the FTL 127 may implement the functionality of the health index manager 121. In this case, the above-described operations of the health index manager 121 may be performed by the FTL 127.

[0069] The memory controller 120 may communicate with the host through the host interface 128. In some implementations, the host interface 128 may be implemented based on at least one of various interfaces, such as a Serial ATA (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Serial Attached SCSI (SAS), a Non-Volatile Memory Express (NVMe) interface, a Universal Flash Storage (UFS) interface.

[0070] The memory controller 120 may communicate with the nonvolatile memory device 110 through the nonvolatile memory interface 129. For example, the nonvolatile memory interface 129 may be implemented based on a NAND interface.

[0071] Figure 3 It is shown in detail Figure 1 A block diagram of an example of a nonvolatile memory device. Figure 3, the nonvolatile memory device 110 includes a memory cell array 111 , an address decoder 112 , a control logic 113 , an input / output (I / O) circuit 114 , and a voltage generator 115 .

[0072] The memory cell array 111 may include a plurality of memory blocks BLK1 to BLKn. Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of cell strings connected to a plurality of bit lines BL. Each of the plurality of cell strings may include a plurality of cell transistors connected in series. The plurality of cell transistors may be connected to a string selection line SSL, a word line WL, and a ground selection line GSL.

[0073] The address decoder 112 may be connected to the memory cell array 111 through the string selection lines SSL, the word lines WL, and the ground selection lines GSL. The address decoder 112 may control or drive the string selection lines SSL, the word lines WL, and the ground selection lines GSL.

[0074] The control logic 113 may control the operation of the nonvolatile memory device 110 in response to the command CMD, the control logic CTRL, and the address ADDR from the memory controller 120. For example, the control logic 113 may control the address decoder 112, the input / output circuit 114, and the voltage generator 115 in response to the command CMD so that an operation (e.g., a program operation, a read operation, an erase operation, or a soft erase operation) corresponding to the command CMD is performed. The control logic 113 may provide a row address to the address decoder 112, and may provide a voltage control signal CTRL_Vol to the voltage generator 115.

[0075] The input / output circuit 114 may exchange data “DATA” with the memory controller 120 . The input / output circuit 114 may write data “DATA” received from the memory controller 120 into the memory cell array 111 , or may transfer data “DATA” read from the memory cell array 111 to the memory controller 120 .

[0076] The voltage generator 115 may generate various voltages for performing write, read, normal erase, and soft erase operations on the memory cell array 111 based on the voltage control signal CTRL_vol. In detail, the voltage generator 115 may be configured to generate word line voltages VWL, for example, a plurality of program voltages, a plurality of program verification voltages, a plurality of pass voltages, a plurality of read voltages, and a soft erase voltage, etc.

[0077] The soft erase voltage may mean a voltage applied to the word line WL connected to the memory cell of the memory block when performing a soft erase operation. For example, the soft erase voltage may be higher than a voltage applied to the word line WL connected to the memory cell of the memory block when performing a normal erase operation.

[0078] Figure 4 It is shown Figure 3 A circuit diagram of an example of a memory block among a plurality of memory blocks included in a memory cell array of FIG. Figure 4 One memory block BLK is described, but the present disclosure is not limited thereto. The plurality of memory blocks BLK1 to BLKn included in the memory cell array 111 may also have the same Figure 4 The memory block BLK has the same or similar structure. Figure 3 and Figure 4 , the memory block BLK includes a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22 are arranged along row directions and column directions.

[0079] Cell strings located in the same column among a plurality of cell strings CS11, CS12, CS21, and CS22 may be connected to the same bit line. For example, cell strings CS11 and CS21 may be connected to a first bit line BL1, and cell strings CS12 and CS22 may be connected to a second bit line BL2. Each of a plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. Each of a plurality of cell transistors may be a charge trap flash memory (CTF) memory cell transistor, but the present disclosure is not limited thereto. A plurality of cell transistors may be stacked on a plane (e.g., a semiconductor substrate (not shown)) defined by a row direction and a column direction.

[0080] A plurality of cell transistors may be connected in series between a corresponding bit line (e.g., BL1 or BL2) and a common source line CSL. For example, a plurality of cell transistors may include string selection transistors SSTa and SSTb, dummy memory cells DMC1 and DMC2, memory cells MC1 to MC8, and ground selection transistors GSTa and GSTb. String selection transistors SSTa and SSTb connected in series may be disposed or connected between memory cells MC1 to MC8 connected in series and corresponding bit lines (e.g., BL1 and BL2). Ground selection transistors GSTa and GSTb connected in series may be disposed or connected between memory cells MC1 to MC8 connected in series and a common source line CSL.

[0081] Memory cells located at the same height among memory cells MC1 to MC8 from a plurality of cell strings CS11 , CS12 , CS21 , and CS22 may share the same word line.

[0082] Dummy memory cells located at the same height among the dummy memory cells DMC1 and DMC2 of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may share the same dummy word line.

[0083] String selection transistors located at the same height and the same row among string selection transistors SSTa and SSTb from the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may share the same string selection line.

[0084] Although not shown, string selection transistors located at the same row among string selection transistors SSTa and SSTb from a plurality of cell strings CS11 , CS12 , CS21 , and CS22 may share the same string selection line.

[0085] Ground selection transistors placed at the same height and the same row among the ground selection transistors GSTa and GSTb from the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may be connected to the same ground selection line.

[0086] Although not shown, the ground selection transistors GSTa and GSTb of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line. Alternatively, the ground selection transistors located at the same height among the ground selection transistors GSTa and GSTb from the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line. Alternatively, the ground selection transistors located at the same row among the ground selection transistors GSTa and GSTb from the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line.

[0087] Figure 5 It is shown Figure 4 A diagram of example threshold voltage distributions for the memory cells shown in FIG. Figure 5 In the distribution diagram, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. For ease of description, it is assumed that each memory cell is a three-level cell configured to store 3-bit data. However, the present disclosure is not limited thereto. For example, each memory cell is implemented in the form of a single-level cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), a four-level cell (QLC), or a five-level cell (PLC).

[0088] refer to Figures 1 to 5 , the memory controller 120 stores data in the memory cells by controlling the threshold voltages of the memory cells of the memory block BLK. For example, each of the memory cells is programmed to have a normal erase state NE and one of a plurality of program states P1 to P7.

[0089] The memory controller 120 may read data stored in memory cells by sensing program states (ie, threshold voltages) of the memory cells using a plurality of read voltages Vrd1 to Vrd7 .

[0090] In some implementations, the threshold voltage of a memory cell may change due to various factors, such as elapsed time, read disturb, program disturb, and word line coupling. For example, as described above, as charge loss occurs in a memory cell, the threshold voltage of a memory cell may decrease.

[0091] In this case, if Figure 5 As shown, there may be a period in which the programming states P1' to P7' of the memory cells overlap with each other. In the overlapping period (e.g., Figure 5 An error may occur in a memory cell in area A); in this case, the reliability of data stored in the memory cell may be reduced.

[0092] When the charge stored in the memory cell leaks, that is, when charge loss occurs, the threshold voltage of the memory cell may be reduced. In this case, the higher the threshold voltage distribution (or programming state) of the memory cell, the greater the charge loss. In detail, for example, when the memory cell belongs to the highest programming state P7, the memory cell in the highest programming state P7 may experience a relatively large charge loss during the same time period compared to the memory cells belonging to the remaining programming states P1 to P6.

[0093] Figure 6 is a diagram for describing example retention characteristic differences of memory blocks. Figures 1 to 5 describe Figure 6 .exist Figure 6 In the distribution diagram of , the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. Figure 6 , the first distribution graph G1 shows a change in threshold voltage distribution of memory cells included in the first memory block BLK1, and the second distribution graph G2 shows a change in threshold voltage distribution of memory cells included in the second memory block BLK2.

[0094] Due to the difference between the degradation levels of memory blocks with different process deviations or their program / erase (P / E) cycle counts, the first memory block BLK1 and the second memory block BLK2 may have different retention characteristics. In this case, the amount of charge loss that occurs over time from the programming time point may be determined differently for each memory block.

[0095] For example, at a first time point, a programming operation may be performed on the first memory block BLK1 and the second memory block BLK2. For example, at a first time point, a lower limit of a threshold voltage distribution of a highest program state P7 of memory cells of the first memory block BLK1 and the second memory block BLK2 may correspond to a first voltage V1.

[0096] After a first time has passed from the first time point, a lower limit of a highest program state P7' of memory cells of the first memory block BLK1 may correspond to a second voltage V2. In addition, a lower limit of a highest program state P7' of memory cells of the second memory block BLK2 may correspond to a third voltage V3.

[0097] The difference "V1-V2" between the first voltage V1 and the second voltage V2 may be greater than the difference "V1-V3" between the first voltage V1 and the third voltage V3. That is, although the same time has passed from the programming time point, the amount of charge loss that occurs in the first memory block BLK1 may be greater than the amount of charge loss that occurs in the second memory block BLK2. In this way, after the same time has passed from the programming time point, the error rate of the data stored in the first memory block BLK1 may be higher than the error rate of the data stored in the second memory block BLK2. This situation may be referred to as "a situation in which the retention characteristics of the second memory block BLK2 are superior to the retention characteristics of the first memory block BLK1".

[0098] Because the memory blocks have different retention characteristics, the memory controller 120 should set the execution conditions of the reliability management operation (e.g., the patrol read operation and the read reclaim operation) for each memory block differently based on the retention characteristics of the memory blocks. That is, the memory controller 120 can manage the memory blocks individually to improve the performance of the storage device 100.

[0099] Figure 7 It is shown Figure 1 A flowchart of an example of a method of operating a storage device. Figures 1 to 6 describe Figure 7 . refer to Figure 7 , in operation S110, the storage device 100 determines the reliability management operation condition of the first memory block BLK1 with reference to the health index table 122 and the LUT 123. For example, the storage device 100 checks the health index of the first memory block BLK1 with reference to the health index table 122. The storage device 100 determines the reliability management operation condition of the first memory block BLK1 with reference to the LUT 123. In some embodiments, the reliability management operation condition includes a patrol read cycle. In this case, the storage device 100 determines the reliability management operation condition of the first memory block BLK1 with reference to the health index table 122 and the LUT 123.

[0100] In operation S120, the memory device 100 determines whether the reliability management operation condition of the first memory block BLK1 is satisfied. When the reliability management operation condition of the first memory block BLK1 is satisfied, the memory device 100 performs operation S130.

[0101] In some embodiments, as described above, when the reliability management operation condition means a patrol read cycle, the storage device 100 determines whether the patrol read cycle of the first memory block BLK1 passes. For example, the storage device 100 determines whether the patrol read cycle corresponding to the health index of the first memory block BLK1 passes. When the patrol read cycle of the first memory block BLK1 passes, the storage device 100 performs operation S130.

[0102] In operation S130 , the memory device 100 performs a reliability management operation of the first memory block BLK1 .

[0103] In some embodiments, as described above, when the reliability management operation condition means a patrol read cycle, in operation S130 , the memory device 100 may perform a patrol read operation on the first memory block BLK1 .

[0104] For example, the storage device 100 may read data of a preset memory cell among the memory cells included in the first memory block BLK1, and may measure an error rate. For example, the preset memory cell may refer to a memory cell connected to at least one of the plurality of word lines included in the first memory block BLK1. In addition, the storage device 100 may determine whether the measured error rate exceeds a recovery threshold. When the measured error rate exceeds the recovery threshold, the storage device 100 may designate the first memory block BLK1 as a read recovery target block.

[0105] As described above, in some embodiments, the storage device 100 may check the retention characteristics of the memory blocks with reference to the health index table 122 and the LUT 123. In addition, the storage device 100 may perform reliability management operations optimized for each memory block in consideration of the retention characteristics of the memory blocks.

[0106] In other words, the storage device 100 can manage the memory blocks individually based on the health index. In this way, the time point at which the storage device 100 performs reliability management operations can be optimized for each memory block. Therefore, the storage device 100 can manage the reliability of the data of the memory blocks without unnecessary operations.

[0107] In some embodiments, when the storage device 100 enters an idle mode, the above operations S110 to S130 may be performed. That is, when the storage device 100 operates in the idle mode, the storage device 100 may perform operations S110 to S130. The idle mode may refer to a mode in which the storage device 100 is in an available state but does not actually perform any work.

[0108] Figure 8 and Fig. 9 Is used to describe Figure 7 Reference will be made to an example diagram of operation S110. Figures 1 to 7 describe Figure 8 and Fig. 9 . Figure 8 An example of a health index table 122 is shown, and Fig. 9 An example of LUT 123 is shown. Figure 8 and Fig. 9 An example of the health index table 122 and an example of the LUT 123 are shown in FIG. 1 , but the present disclosure is not limited thereto. For example, in some embodiments, the health index table 122 and the LUT 123 may be changed or modified in various forms.

[0109] refer to Figure 8 , the health index table 122 includes health indexes respectively corresponding to the memory blocks BLK1 to BLKn of the nonvolatile memory device 110 .

[0110] In some embodiments, Figure 8 Unlike the example illustrated in , the health index table 122 may include information on reliability management operation conditions corresponding to the health indexes as well as the health indexes.

[0111] refer to Fig. 9 , LUT 123 includes a plurality of reference values. The reference values ​​may include a cell count corresponding to a health index and a reliability management operating condition (eg, a patrol read cycle) corresponding to the health index. Fig. 9 , the cell count may represent an on-cell count. However, the present disclosure is not limited thereto. The cell count may represent an off-cell count of a specific memory block, and the LUT 123 may include various information about reliability management operations of the specific memory block. In some embodiments, the LUT 123 may include information about a read recovery operation condition corresponding to the health index. The cell count will be described in detail with reference to the following drawings.

[0112] For example, refer to Fig. 9In the LUT 123 implemented as shown, when the on-cell count of the memory block is 0 or more and less than 100, the health index of the memory block may be "A", and the patrol read cycle of the memory block may be "14 days". When the on-cell count of the memory block is 100 or more and less than 200, the health index of the memory block may be "B", and the patrol read cycle of the memory block may be "10 days". When the on-cell count of the memory block is 200 or more and less than 300, or when there is no measured on-cell count of the memory block in the LUT 123, the health index of the memory block may be "C", and the patrol read cycle of the memory block may be "7 days". That is, the default value of the health index of the memory block may be "C". When the on-cell count of the memory block is 300 or more and less than 400, the health index of the memory block may be "D", and the patrol read cycle of the memory block may be "4 days". When the on-cell count of the memory block is 400 or more and less than 500, the health index of the memory block may be "E", and the patrol read cycle of the memory block may be "1 day". When the on-cell count of the memory block is 500 or more, the health index of the memory block may be "F", and the memory block may be regarded as a runtime bad block (RTBB).

[0113] For example, the memory controller 120 may check the health indexes of the memory blocks BLK1 to BLKn with reference to the health index table 122. The memory controller 120 may determine the reliability management operation condition of each of the memory blocks BLK1 to BLKn based on the checked health index and the LUT 123.

[0114] The health index table 122 and the LUT 123 may be like Figure 8 and Fig. 9. In this case, the memory controller 120 may refer to the health index table 122 to check that the health index of the first memory block BLK1 is "A". In addition, the memory controller 120 may refer to the LUT 123 to determine that the patrol read cycle of the first memory block BLK1 is "14 days". Therefore, the memory controller 120 may perform a patrol read operation on the first memory block BLK1 every 14 days from the time point when the storage device 100 is powered on. In addition, the memory controller 120 may refer to the health index table 122 to check that the health index of the second memory block BLK2 is "C". The memory controller 120 may refer to the LUT 123 to determine that the patrol read cycle of the second memory block BLK2 is "7 days". Therefore, the memory controller 120 may perform a patrol read operation on the second memory block BLK2 every 7 days from the time point when the storage device 100 is powered on. In addition, because the health index of the nth memory block BLKn is "D", the memory controller 120 may perform a patrol read operation on the nth memory block BLKn every 4 days from the time point when the storage device 100 is powered on.

[0115] That is, the memory controller 120 may perform a reliability management operation in consideration of a retention characteristic of each of the memory blocks BLK1 to BLKn, and may individually manage the reliability of data of the memory blocks BLK1 to BLKn without unnecessary operations.

[0116] Fig.10 It is shown Figure 1 A flowchart of an example of a method for generating a health index of a storage device. Figures 1 to 9 describe Fig.10 In operation S210, the memory device 100 determines whether the first memory block BLK1 satisfies the soft erase operation condition. When the first memory block BLK1 satisfies the soft erase operation condition, the memory device 100 performs operation S220.

[0117] In some embodiments, the first memory block BLK1 may be a free block. In this case, the first memory block BLK1 may satisfy a soft erase operation condition. As described above, a free block may mean a memory block including only invalid data.

[0118] For example, the first memory block BLK1 can be designated as a victim block for garbage collection. In this case, the storage device 100 can designate the first memory block BLK1 as a free block. Alternatively, when a programming operation is performed on the memory cell of the first memory block BLK1, a sudden power-off event may occur. In this case, the storage device 100 can designate the first memory block BLK1 as a free block. The memory controller 120 can allow the first memory block BLK1 designated as a free block to store only invalid data. In this way, the first memory block BLK1 can be set to a free block.

[0119] In some embodiments, the first memory block BLK1 may be a free block, and the number of P / E cycles (or P / E cycle count) of the first memory block BLK1 may be a reference value or greater. In this case, the first memory block BLK1 may satisfy the soft erase operation condition.

[0120] In some embodiments, the first memory block BLK1 may be an idle block, the number of P / E cycles (or P / E cycle count) of the first memory block BLK1 may be less than a reference value, and a first health index indicating a health index of the first memory block BLK1 included in the health index table 122 may be included in the soft erase health index. In this case, the first memory block BLK1 may satisfy the soft erase operation condition.

[0121] For example, the health index table 122 may be as follows: Figure 8 , and LUT 123 can be implemented as Fig. 9 Implementation shown. In addition, the soft erase health index may include "D", "E", and "F"; the first memory block BLK1, the second memory block BLK2, and the nth memory block BLKn may be free blocks; the P / E cycle count of each of the first memory block BLK1, the second memory block BLK2, and the nth memory block BLKn may be less than a reference value. In this case, the first memory block BLK1 and the second memory block BLK2 may be memory blocks that do not meet the soft erase operation conditions, and the nth memory block BLKn may be a memory block that meets the soft erase operation conditions.

[0122] In operation S220, the memory device 100 performs a pre-programming operation on the first memory block BLK1. Fig.11 Describes the pre-programming operation.

[0123] In operation S230, the memory device 100 performs a soft erase operation on the first memory block BLK1. The soft erase operation may be one of operations of erasing data stored in the memory block. The soft erase operation will be described in detail with reference to the following drawings.

[0124] In operation S240, the memory device 100 measures a cell count of the first memory block BLK1. In some embodiments, the cell count may be an on-cell count or an off-cell count calculated based on a soft erase reference voltage.

[0125] In operation S250, the memory device 100 generates a first health index corresponding to the first memory block BLK1. In detail, the memory device 100 may generate the first health index with reference to the cell count and the LUT 123. The first health index may be associated with a retention characteristic of the first memory block BLK1.

[0126] For example, the cell count may refer to the on-cell count, and the LUT 123 may be like Fig. 9 The example shown is implemented as above. In addition, the cell count may be 120. In this case, the first health index generated thereby may be "B".

[0127] In some embodiments, when the storage device 100 enters the idle mode, the above operations S210 to S250 may be performed. That is, when the storage device 100 operates in the idle mode, the storage device 100 may perform operations S210 to S250.

[0128] In some embodiments, the storage device 100 may perform a soft erase operation only when the memory block is a free block. That is, the storage device 100 may check the retention characteristics of the memory block that does not store valid data by performing a soft erase operation on the memory block, then measuring the cell count, and then generating a health index. In this way, the storage device 100 can check the retention characteristics of the memory block without losing valid data.

[0129] Fig.11 Is used to describe Fig.10 Reference will be made to the diagram of an example of a pre-programming operation and a soft erase operation. Fig.10 describe Fig.11 .exist Fig.11 In the distribution diagram of , the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. Fig.11 , the first distribution graph G1 shows the threshold voltage distribution of the memory cells of the first memory block BLK1 after the pre-programming operation and the soft erasing operation are performed on the first memory block BLK1. The second distribution graph G2 shows the threshold voltage distribution of the memory cells of the second memory block BLK2 after the pre-programming operation and the soft erasing operation are performed on the second memory block BLK2.

[0130] For example, the first memory block BLK1 may be a defective memory block degraded due to a process defect or a plurality of operations (e.g., read, write, and erase operations). In contrast, the second memory block BLK2 may be a normal memory block that does not include defects and is not degraded. In this case, the second memory block BLK2 may be referred to as having a normal retention characteristic.

[0131] In this case, immediately after performing a soft erase operation on the first and second memory blocks BLK1 and BLK2 undergoing a pre-program operation, memory cells of the first memory block BLK1 may have a defective soft erase state dSE and memory cells of the second memory block BLK2 may have a normal soft erase state nSE.

[0132] For example, the lower limit value nVL of the threshold voltage distribution of the normal soft erase state nSE may be higher than the upper limit value VNH of the threshold voltage distribution of the normal erase state NE. For example, the lower limit value nVL of the threshold voltage distribution of the normal soft erase state nSE may be higher than the lower limit value of the threshold voltage distribution of the first programming state P1. In addition, the upper limit value nVH of the threshold voltage distribution of the normal soft erase state nSE may be lower than the lower limit value of the threshold voltage distribution of the third programming state P3. However, the present disclosure is not limited thereto. For example, the lower limit value nVL of the threshold voltage distribution of the normal soft erase state nSE may represent any state in which the lower limit value nVL of the threshold voltage distribution is higher than the upper limit value VNH of the threshold voltage distribution of the normal erase state NE.

[0133] refer to Fig.10 and Fig.11 , the memory controller 120 may perform a pre-programming operation before performing a soft erase operation. In some embodiments, the pre-programming operation may mean an operation of controlling a threshold voltage of a memory cell having a programming state lower than a normal soft erase state nSE among memory cells from a memory block. Through the pre-programming operation, a memory cell having a programming state lower than a normal soft erase state nSE may be programmed to have a programming state higher than a normal soft erase state nSE.

[0134] For example, the lower limit value of the threshold voltage distribution of the programming state of the memory cell may be lower than the lower limit value nVL of the threshold voltage distribution of the normal soft erase state nSE. In this case, the memory cell may be referred to as having a programming state lower than the normal soft erase state nSE. Fig.11 In the example, memory cells having the normal erase state NE or the first programming state P1 may be referred to as having a programming state lower than the normal soft erase state nSE, and memory cells having the second programming state P2 to the seventh programming state P7 may be referred to as having a programming state higher than the normal soft erase state nSE.

[0135] After performing the pre-programming operation, the memory controller 120 may perform a soft erase operation. The soft erase operation may be one of the operations that releases the charges stored in the memory block so that the data is erased. Unlike a normal erase operation, the soft erase operation may refer to an operation that releases only some charges stored in the memory cells of the memory block.

[0136] In detail, when the memory controller 120 performs a soft erase operation on a memory block, as in a normal erase operation, a high-voltage erase voltage may be applied to the body of the memory cell of the memory block. However, the soft erase voltage may be applied to the word line connected to the memory cell. In some embodiments, the soft erase voltage may be 3V, and the voltage applied to the word line connected to the memory cell in a normal erase operation may be 0V. Therefore, when a soft erase operation is performed on a memory block, the charge stored in the memory block may be released less than when a normal erase operation is performed. In other words, unlike the case of performing a normal erase operation, some charge may remain at the memory cell of the memory block performing the soft erase operation.

[0137] As described above, the first memory block BLK1 may be a defective memory block, and the second memory block BLK2 may be a normal memory block. In this case, charge loss is more likely to occur in the first memory block BLK1 than in the second memory block BLK2. That is, the charge stored in the first memory block BLK1 may be released more easily than the charge stored in the second memory block BLK2. In other words, the retention characteristics of the second memory block BLK2 may be better than the retention characteristics of the first memory block BLK1.

[0138] As described above, even after performing a soft erase operation, some of the charges stored in the memory blocks may remain. When performing a soft erase operation, the same soft erase voltage may be applied to the word lines of the first memory block BLK1 and the word lines of the second memory block BLK2. However, due to the difference in retention characteristics between the first memory block BLK1 and the second memory block BLK2, the charges stored in the first memory block BLK1 may be released more easily than the charges stored in the second memory block BLK2. Therefore, when performing a soft erase operation, the amount of charge released from the memory cells of the first memory block BLK1 may be greater than the amount of charge released from the memory cells of the second memory block BLK2.

[0139] Therefore, after performing the soft erase operation, the memory cells of the first memory block BLK1 as the defective memory block may have the defective soft erase state dSE, and the memory cells of the second memory block BLK2 as the normal memory block may have the normal soft erase state nSE. In this case, the lower limit value dVL of the threshold voltage distribution of the defective soft erase state dSE may be lower than the lower limit value nVL of the threshold voltage distribution of the normal soft erase state nSE.

[0140] In some embodiments, the memory controller 120 may check the retention characteristics of each memory block based on the difference between the lower limit value (e.g., nVL) of the threshold voltage distribution of the normal soft erase state nSE and the lower limit value (e.g., dVL) of the threshold voltage distribution of the defective soft erase state dSE. In addition, the memory controller 120 may determine whether the memory block is a defective memory block based on the above-mentioned lower limit value difference of the threshold voltage distribution. Below, how to check the retention characteristics will be described in detail.

[0141] In other words, in some embodiments, since a soft erase operation is used instead of a normal erase operation, a difference in threshold voltage distributions of a normal memory block and a defective memory block may be checked immediately after the soft erase operation is performed.

[0142] Meanwhile, in some embodiments, unlike the above description, the pre-programming operation may mean an operation of controlling the threshold voltage of a specific memory cell having a programming state lower than the normal soft erase state nSE among the memory cells of the memory block. For example, the specific memory cell may be a memory cell connected to a predetermined word line. For example, the predetermined word line may mean a word line sensitive to degradation. For example, the number of predetermined word lines may be one or more. Through the pre-programming operation, the specific memory cell may be programmed to have a programming state higher than the normal soft erase state nSE. For example, after performing the pre-programming operation on the first memory block BLK1 and the second memory block BLK2, the memory controller 120 may perform a soft erase operation. In this case, after performing the soft erase operation, the first memory cell connected to the predetermined word line from the memory cell of the first memory block BLK1 may have a normal soft erase state nSE. On the contrary, the memory cell connected to the predetermined word line from the memory cell of the second memory block BLK2 may have a defective soft erase state dSE.

[0143] For convenience, a description will be given below based on a case where the pre-program operation is an operation of controlling the threshold voltages of all memory cells having a program state lower than a normal soft erase state nSE among memory cells from a memory block.

[0144] Fig.12Is used to describe Fig.10 Reference will be made to an example diagram of operation S240. Figures 1 to 11 describe Fig.12 . refer to Fig.12 , the first memory block BLK1 includes a plurality of pages PG1 to PGn. The plurality of pages PG1 to PGn are connected to word lines WL1 to WLn. Each of the plurality of pages PG1 to PGn includes a plurality of memory cells. For example, the first page PG1 includes memory cells connected to the first word line WL1, the second page PG2 includes memory cells connected to the second word line WL2, the third page PG3 includes memory cells connected to the third word line WL3, and the nth page PGn includes memory cells connected to the nth word line WLn.

[0145] For example, as referenced Fig.11 As described, the first memory block BLK1 may be a defective memory block. Therefore, after performing a soft erase operation with respect to the first memory block BLK1, the memory cells of the pages PG1 to PGn may have a defective soft erase state dSE. The memory controller 120 may measure a cell count by applying a soft erase reference voltage to a predetermined specific word line (e.g., WL2) from among the word lines WL1 to WLn.

[0146] In some embodiments, a specific word line (eg, WL2) may be a word line connected to memory cells undergoing a pre-programming operation.

[0147] For example, the cell count may be a turn-on cell count or a turn-off cell count. For example, the memory controller 120 may perform a read operation once on a first memory cell (e.g., a first memory cell connected to the second word line WL2) predetermined by using a soft erase reference voltage. The soft erase reference voltage refers to a read voltage used to perform a turn-on cell / turn-off cell count operation. The memory controller 120 may detect the number of memory cells (i.e., turn-on cells) whose threshold voltage is lower than the soft erase reference voltage. Alternatively, the memory controller 120 may detect the number of memory cells (i.e., turn-off cells) whose threshold voltage is higher than the soft erase reference voltage. For example, as the turn-on cell count increases, the charge loss may become greater. Similarly, as the turn-off cell count decreases, the charge loss may become greater.

[0148] For example, the soft erase reference voltage may be a normal soft erase state (eg, Fig.11 The lower limit value of the threshold voltage distribution of nSE) (for example, Fig.11 of nVL).

[0149] For example, since the program operation is used to store charges in memory cells, a defective memory block and a normal memory block may have the same threshold voltage distribution immediately after performing the program operation. Therefore, the memory controller 120 may determine whether a memory block is a defective memory block only when a separate retention time has passed after performing the program operation. At the same time, since the soft erase operation is used to release charges existing in the memory cells, such as Fig.11 As shown, after performing a soft erase operation, the threshold voltage distributions of the defective memory block and the normal memory block can be different from each other immediately. In some embodiments, the memory controller 120 can check the retention characteristics of the memory block by measuring the cell count without waiting for a separate retention time after performing a soft erase operation.

[0150] Fig.13 It is shown in detail Fig.10 An example flow chart of operation S250 of FIG. Fig.13 In operation S251, the storage device 100 compares the cell count with the LUT 123. In detail, the storage device 100 generates a first health index corresponding to the cell count based on the reference value of the LUT 123. For example, the cell count refers to the through cell count, and the cell count is 120. In addition, the LUT 123 is as follows: Fig. 9 In this case, the first health index generated by the storage device 100 is "B".

[0151] In operation S252, the storage device 100 compares the first health index with the first reference health index. For example, the health index table 122 includes health indexes generated in the past. The health index generated in the past is referred to as a "reference health index". The first reference health index is a reference health index corresponding to the first memory block BLK1 from among the reference health indexes. That is, the first reference health index means a past health index corresponding to the first memory block BLK1.

[0152] When the first reference health index is the same as the first health index, the storage device 100 performs operation S253. In operation S253, the storage device 100 maintains the health index table 122.

[0153] When the first reference health index is different from the first health index, the storage device 100 performs operation S254. In operation S254, the storage device 100 updates the health index table 122. In detail, the storage device 100 changes the first reference health index of the health index table 122 to the first health index.

[0154] In some embodiments, the storage device 100 may compare the current health index value and the past health index value of each memory block. When the current health index value and the past health index value are different, the storage device 100 may update the health index table 122. In this way, the storage device 100 may check the retention characteristics of the memory blocks that change over time, and may manage the memory blocks based on the retention characteristics.

[0155] Fig.14 Is used to describe Fig.10 In detail, Fig.14 An example of the operation of the memory controller 120 to manage the health index table 122 is shown in FIG. Figures 1 to 13 describe Fig.14 The following description will be based on the case where the memory controller 120 generates the health index of each memory block based on the on-cell count. Fig.14 However, the present disclosure is not limited thereto.

[0156] refer to Fig.14 , at the first time point T1, the first memory block BLK1 and the second memory block BLK2 may be memory blocks in which no data is stored. In addition, before the first time point T1, the soft erase operation may not be performed on the first memory block BLK1 and the second memory block BLK2. In this case, the health indexes of the first memory block BLK1 and the second memory block BLK2 included in the health index table 122 may be a default value "C".

[0157] For example, in the time period from T1 to T2, the memory controller 120 may designate the first memory block BLK1 as a free block. In this way, the first memory block BLK1 may be set as a free block. In this case, the memory controller 120 may determine that the first memory block BLK1 satisfies the soft erase operation condition, may perform a pre-programming operation on the first memory block BLK1, may perform a soft erase operation on the first memory block BLK1, and may measure the first conduction cell count of the first memory block BLK1. In some embodiments, the first conduction cell count may be 300 or greater than 300 and less than 400.

[0158] For example, in the time period from T1 to T2, the memory controller 120 may generate a first health index based on the first on-cell count and the LUT 123. The first health index thus generated may be "D". The memory controller 120 may compare the first health index with a first reference health index. The first reference health index may be a health index (e.g., "C") included in the health index table 122 and corresponding to the first memory block BLK1 before the first health index (e.g., "D") is generated. Because the first reference health index "C" and the first health index "D" are different, the memory controller 120 may update the health index table 122. In this way, at the second time point T2, the health index of the first memory block BLK1 included in the health index table 122 may be set to "D".

[0159] At the same time, for example, in the time period from T1 to T2, the memory controller 120 may designate the second memory block BLK2 as a free block. In this way, the second memory block BLK2 may be set as a free block. The memory controller 120 may determine that the second memory block BLK2 satisfies the soft erase operation condition, may perform a pre-programming operation on the second memory block BLK2, may perform a soft erase operation on the second memory block BLK2, and may measure the second conduction cell count of the second memory block BLK2. In some embodiments, the second conduction cell count may be 0 or greater than 0 and less than 100.

[0160] For example, in the time period from T1 to T2, the memory controller 120 may generate a second health index based on the second on-cell count and the LUT 123. The second health index thus generated may be "A". The memory controller 120 may compare the second health index with a second reference health index. The second reference health index may be a health index (e.g., "C") included in the health index table 122 and corresponding to the second memory block BLK2 before the second health index (e.g., "A") is generated. Because the second reference health index "C" is different from the second health index "A", the memory controller 120 may update the health index table 122. In this way, at the second time point T2, the health index of the second memory block BLK2 included in the health index table 122 may be set to "A".

[0161] In the time period from T2 to T3, the memory controller 120 may again designate the first memory block BLK1 as a free block. In this way, the memory controller 120 may determine that the first memory block BLK1 satisfies the soft erase operation condition, may perform a pre-programming operation on the first memory block BLK1, may perform a soft erase operation on the first memory block BLK1, and may again measure the first on-cell count of the first memory block BLK1. In some embodiments, the first on-cell count may be 400 or greater than 400 and less than 500.

[0162] In the time period from T2 to T3, the memory controller 120 may again generate a first health index based on the first on-cell count and the LUT 123. The first health index thus generated may be "E". The memory controller 120 may compare the first health index with the first reference health index. The first reference health index may be a health index (e.g., "D") included in the health index table 122 and corresponding to the first memory block BLK1 before the first health index (e.g., "E") is generated. Because the first reference health index "D" and the first health index "E" are different, the memory controller 120 may update the health index table 122. In this way, after the third time point T3, the health index of the first memory block BLK1 may be set to "E".

[0163] In addition, in the time period from T2 to T3, the memory controller 120 may again designate the second memory block BLK2 as a free block. The memory controller 120 may determine that the second memory block BLK2 satisfies the soft erase operation condition, may perform a pre-programming operation on the second memory block BLK2, may perform a soft erase operation on the second memory block BLK2, and may again measure the second conduction cell count of the second memory block BLK2. In some embodiments, the second conduction cell count may be 0 or greater than 0 and less than 100. The memory controller 120 may again generate a second health index based on the second conduction cell count and the LUT 123. The second health index thus generated may be "A".

[0164] In the time period from T2 to T3, the memory controller 120 may compare the second reference health index with the second health index. The second reference health index may be a health index (e.g., "A") included in the health index table 122 and corresponding to the second memory block BLK2 before the second health index (e.g., "A") is generated. Because the second reference health index of "A" is the same as the second health index of "A", the memory controller 120 may maintain the health index table 122. In this way, after the third time point T3, the health index of the second memory block BLK2 may still be "A".

[0165] As described above, in some embodiments, the memory controller 120 can generate a health index by measuring the cell count after performing a pre-programming operation and a soft erase operation on a memory block that meets the soft erase operation condition. When the memory controller 120 operates, the memory block designated as the free block can be continuously changed. In this way, the memory controller 120 can generate health indexes corresponding to the memory blocks respectively. The memory controller 120 can manage the memory blocks individually based on the health index table 122 and the LUT 123. For example, the memory controller 120 can perform a patrol read operation on each memory block based on the health index table 122 and the LUT 123 at each optimal cycle.

[0166] Fig.15 It is shown Figure 1 A flowchart of another example of a method for generating a health index of a storage device. Figures 1 to 14 describe Fig.15 In operation S310, the memory device 100 performs a program operation on the first memory block BLK1. The program operation is performed on at least one of the pages included in the first memory block BLK1.

[0167] In operation S320, the storage device 100 determines whether a virtual event occurs. The virtual event may include 1) a sudden power-off event and 2) an event in which an idle reference time of the first memory block BLK1 including at least one unprogrammed page has passed since the time point at which operation S310 ends. When the virtual event occurs, the storage device 100 performs operation S330.

[0168] In operation S330, the memory device 100 performs a dummy power-off operation on the first memory block BLK1. In detail, the memory device 100 programs dummy data at an unprogrammed page among pages of the first memory block BLK1.

[0169] In operation S340, the storage device 100 determines whether the retention reference time has passed. When the retention reference time has passed from the time point when the virtual power-off operation is performed, the storage device 100 performs operation S350.

[0170] In operation S350, the memory device 100 measures a cell count of the first memory block BLK1. The cell count is an on-cell count or an off-cell count based on a virtual off reference voltage.

[0171] In operation S360 , the memory device 100 generates a first health index corresponding to the first memory block BLK1 .

[0172] In some implementations, when the storage device 100 enters the idle mode, operations S320 to S360 are performed.

[0173] Fig.16 Is used to describe Fig.15 Figure 1. Example of a virtual close operation. Fig.16 , the first memory block BLK1 includes a first memory region R1 and a second memory region R2. The first memory region R1 and the second memory region R2 include a plurality of memory cells.

[0174] For example, at a first time point, the memory controller 120 may perform a normal erase operation on the first memory block BLK1. In this case, the memory cells of the first storage area R1 and the second storage area R2 may have a normal erase state NE. Thereafter, the memory controller 120 may perform a program operation on the first storage area R1. For example, at a second time point, the program operation of the first storage area R1 may end. In this case, each memory cell of the first storage area R1 may have one of the first programming state P1 to the seventh programming state P7. That is, valid data may be stored in the first storage area R1.

[0175] For example, until the idle reference time passes from the second time point, no additional programming operation may be performed on the memory cells of the second storage region R2. In this case, the memory controller 120 may determine that a virtual event occurs. In this way, the memory controller 120 may perform a virtual shutdown operation on the first memory block BLK1. That is, the memory controller 120 may program the virtual data DT_d at the memory cells of the second storage region R2.

[0176] For example, when performing a programming operation of the first storage area R1, a sudden power-off event may occur. In this case, the memory controller 120 may determine that a virtual event has occurred. In this way, the memory controller 120 may perform a virtual shutdown operation on the first memory block BLK1. That is, the memory controller 120 may program the virtual data DT_d at the memory cell of the second storage area R2.

[0177] For example, memory cells included in a storage area (e.g., the first storage area R1) in which valid data is stored may be referred to as "data storage cells", and memory cells in a storage area (e.g., the second storage area R2) in which data is not programmed from the time point when an erase operation or a soft erase operation is performed until an idle reference time passes may be referred to as "open memory cells".

[0178] For example, when the second storage area R2 is left alone without performing a programming operation, the threshold voltage distribution of the memory cells of the second storage area R2 may increase due to interference. When the threshold voltage distribution of the memory cells increases excessively, the threshold voltage distribution of the memory cells having the erased state may overlap with the first programming state P1. In this case, a read error may occur in the first memory block BLK1.

[0179] In order to prevent the above-mentioned problem due to the memory cells not being programmed, the memory controller 120 may perform a virtual shutdown operation.

[0180] Fig.17 It is shown Fig.16 When a virtual event occurs in a memory block, the memory device 100 opens a memory cell (e.g., Figure 2 The dummy data DT_d is programmed at the memory cells of the second storage region R2).

[0181] For example, the dummy data DT_d may represent the highest programming state among a plurality of programming states (in other words, the programming state corresponding to the highest threshold voltage distribution). Fig.16 In the embodiment, the memory cells of the second storage region R2 may be programmed to the seventh program state P7 through a virtual shut-down operation.

[0182] As described above, as the threshold voltage distribution corresponding to the programming state of the memory cell becomes higher, the charge loss of the memory cell may become faster. In some embodiments, the memory controller 120 may perform a virtual shutdown operation based on the highest programming state of multiple programming states. In this case, the charge loss of the memory cell undergoing the virtual shutdown operation may become faster. The memory controller 120 may generate a health index of the memory block based on the change in the threshold voltage distribution of the memory cell performing the virtual shutdown operation.

[0183] Fig.18 is a diagram showing an example of a change in the threshold voltage distribution of each memory block in which a virtual shutdown operation is performed. Fig.18 In the example, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. For example, a virtual shutdown operation is performed on the first memory block BLK1 and the second memory block BLK2. For example, at a first time point, the virtual shutdown operation of the first memory block BLK1 and the second memory block BLK2 ends. In this case, at a first time point, as shown in the first distribution graph G1, a threshold voltage distribution of the memory cell undergoing the virtual shutdown operation is formed. That is, at the first time point, the lower limit value of the threshold voltage distribution of the memory cell undergoing the virtual shutdown operation corresponds to the initial value Vin.

[0184] As described above, the retention characteristics of the first memory block BLK1 and the retention characteristics of the second memory block BLK2 may be different from each other. For example, the retention characteristics of the second memory block BLK2 may be superior to the retention characteristics of the first memory block BLK1. In this case, after the retention reference time has passed from the first time point, the threshold voltage distribution of the memory cells of the first memory block BLK1 that performs the virtual shutdown operation may be formed, as shown in the second distribution graph G2. In addition, after the retention reference time has passed from the first time point, the threshold voltage distribution of the memory cells of the second memory block BLK2 that performs the virtual shutdown operation may be formed, as shown in the third distribution graph G3.

[0185] That is, the lower limit value of the threshold voltage distribution of the memory cells included in the first memory block BLK1 may correspond to the first voltage V1, and the lower limit value of the threshold voltage distribution of the memory cells included in the second memory block BLK2 may correspond to the second voltage V2. In this case, the difference "Vin-V1" between the initial voltage Vin and the first voltage V1 may be greater than the difference "Vin-V2" between the initial voltage Vin and the second voltage V2. That is, during the same time period, the amount of charge loss occurring in the first memory block BLK1 may be greater than the amount of charge loss occurring in the second memory block BLK2.

[0186] The memory controller 120 may check the retention characteristics of the memory block based on how much the lower limit value of the threshold voltage distribution of the memory cells subjected to the virtual shut-down operation decreases when the retention reference time elapses.

[0187] In some embodiments, the memory controller 120 can accelerate the charge loss of the memory cells by programming the memory cells to the highest programming state (eg, P7) in the virtual shutdown operation. As the charge loss of the memory cells undergoing the virtual shutdown operation is accelerated, the retention reference time can be minimized.

[0188] Fig.19 Is used to describe Fig.15 In detail, Fig.19 is a diagram for describing a method of measuring a cell count of a first memory block BLK1 after a retention reference time has elapsed from a time point when a virtual power-off operation is performed. Fig.19 , the first memory block BLK1 includes a plurality of pages PG1 to PGn connected to word lines WL1 to WLn. For example, a virtual shutdown operation is performed after valid data is programmed at memory cells of the first and second pages PG1 and PG2. When the virtual shutdown operation is performed, memory cells of the third to nth pages PG3 to PGn have the highest program state P7.

[0189] For example, after a retention reference time has passed from the time point when a virtual shutdown operation is performed, the memory controller 120 may measure a cell count by applying a virtual shutdown reference voltage to a predetermined specific word line (e.g., WL3) from among word lines WL3 to WLn connected to pages PG3 to PGn where virtual data is programmed.

[0190] For example, the cell count may be a turn-on cell count or a turn-off cell count. For example, the memory controller 120 may perform a read operation on a specific memory cell predetermined by using a virtual turn-off reference voltage. The virtual turn-off reference voltage refers to a read voltage used to perform a turn-on cell / turn-off cell count operation. The memory controller 120 may detect the number of memory cells (i.e., turn-on cells) whose threshold voltages are lower than the virtual turn-off reference voltage. Alternatively, the memory controller 120 may detect the number of memory cells (i.e., turn-off cells) whose threshold voltages are higher than the virtual turn-off reference voltage. For example, as the turn-on cell count increases, the charge loss may become greater. Similarly, as the turn-off cell count decreases, the charge loss may become greater.

[0191] For example, the virtual turn-off reference voltage may correspond to a lower limit value (eg, Fig.18 The initial voltage Vin).

[0192] Fig. 20 It is shown in detail Fig.15 An example flow chart of operation S360 of FIG. Fig. 20 In operation S361, the storage device 100 compares the cell count with the LUT 123. In detail, the storage device 100 generates a first health index corresponding to the cell count based on the reference value of the LUT 123. For example, the cell count means a pass cell count, and the cell count is 50. In addition, the LUT 123 is as follows: Fig. 9 In this case, the first health index generated by the storage device 100 is "A".

[0193] In operation S362, the storage device 100 compares the first health index with the first reference health index. For example, the health index table 122 may include health indexes generated in the past. The health index generated in the past may be referred to as a "reference health index". The first reference health index may be a reference health index corresponding to the first memory block BLK1 from among the reference health indexes. That is, the first reference health index may represent a past health index corresponding to the first memory block BLK1.

[0194] When the first reference health index is the same as the first health index, the storage device 100 performs operation S363. In operation S363, the storage device 100 maintains the health index table 122.

[0195] When the first reference health index is different from the first health index, the storage device 100 performs operation S364. In operation S364, the storage device 100 updates the health index table 122. In detail, the storage device 100 changes the first reference health index of the health index table 122 to the first health index.

[0196] In some embodiments, the storage device 100 may compare the current health index value and the past health index value of each memory block. When the current health index value and the past health index value are different, the storage device 100 may update the health index table 122.

[0197] Fig.21 FIG. 1 is a diagram for describing an example of a method for generating a health index according to an embodiment of the present disclosure. Figures 1 to 20 describe Fig.21 . refer to Fig.21 , the nonvolatile memory device 110 includes a first memory block BLK1 and a second memory block BLK2. The first memory block BLK1 includes a first memory region R1 and a second memory region R2, and the second memory block BLK2 includes a third memory region R3 and a fourth memory region R4.

[0198] For example, before the first time point, a normal erase operation may be performed on the first memory block BLK1 and the second memory block BLK2. In this case, after the first time point, the memory cells of the first memory block BLK1 and the second memory block BLK2 may have a normal erase state NE. That is, the first memory block BLK1 and the second memory block BLK2 may be in a state where no data is stored and new data can be written. In addition, the health index of each of the first memory block BLK1 and the second memory block BLK2 may be set to a default value (e.g., "C"). In other words, the health index table 122 may include information indicating that the health index of the first memory block BLK1 is "C" and the health index of the second memory block BLK2 is "C".

[0199] Afterwards, at a second time point, valid data may exist in the first storage area R1 of the first memory block BLK1, and invalid data may exist in the second storage area R2 of the first memory block BLK1. In some embodiments, in the first memory block BLK1, the ratio of invalid data to valid data may be large. The memory controller 120 may designate the first memory block BLK1 as a sacrificial block for garbage collection. The memory controller 120 may designate the first memory block BLK1 as a free block. Meanwhile, at a second time point, the programming operation of the second memory block BLK2 may be completed. In this case, for example, valid data may exist in the third storage area R3 of the second memory block BLK2, and there may be no programmed data in the fourth storage area R4. Therefore, the fourth storage area may still be in a normal erase state NE.

[0200] Afterwards, at a third time point, the memory controller 120 may perform migration so that valid data of the first storage region R1 of the first memory block BLK1 is migrated to a free block. Migration may include writing original data (e.g., data of the first storage region R1) into a target region and then invalidating the original data (e.g., data of the first storage region R1). In this way, the first memory block BLK1 may be set as a free block.

[0201] Meanwhile, the third time point may be a time point after the idle reference time from the second time point. In this case, the memory controller 120 may perform a virtual shutdown operation on the second memory block BLK2. Through the virtual shutdown operation, virtual data may be stored in the fourth storage region R4 of the second memory block BLK2. That is, the memory cells of the fourth storage region R4 may have the highest programming state (e.g., P7).

[0202] For example, at the fourth time point, the memory controller 120 may perform a soft erase operation on the first memory block BLK1. In this case, the memory cells of the first memory region R1 and the second memory region R2 may have a soft erase state nSE. After performing the soft erase operation, the memory controller 120 may measure the cell count of the first memory block BLK1. For example, the cell count may refer to a turn-on cell count, the cell count may be 300, and the LUT 123 may be like Fig. 9 In this case, the storage device 100 may generate a first health index of the first memory block BLK1 and may update the health index table 122. Thus, in the health index table 122, the health index of the first memory block BLK1 may be set to "D".

[0203] Meanwhile, the fourth time point may be a time point at which the retention reference time has passed since the time point at which the virtual shutdown operation is completed. The storage device 100 may measure the cell count of the second memory block BLK2. For example, the cell count may refer to the on-cell count, the cell count may be 110, and the LUT 123 may be like Fig. 9 In this case, the memory controller 120 may generate a second health index of the second memory block BLK2 and may update the health index table 122. Thus, in the health index table 122, the health index of the second memory block BLK2 may be set to "B".

[0204] For example, when something like Fig. 9 When LUT 123 is implemented as in the example shown, memory controller 120 can perform patrol read operation on first memory block BLK1 every 4 days from the time when memory device 100 is powered on. In addition, memory controller 120 can perform patrol read operation on second memory block BLK2 every 10 days from the time when memory device 100 is powered on.

[0205] In some embodiments, with respect to a memory block designated as a free block (e.g., the first memory block BLK1), the storage device 100 may generate a health index based on a soft erase operation; with respect to a memory block where a virtual event occurs (e.g., the second memory block BLK2), the storage device 100 may generate a health index based on a virtual shutdown operation.

[0206] The storage device 100 can check the retention characteristics of each memory block based on the health index corresponding to each memory block and the LUT 123. Considering the retention characteristics of the memory blocks, the storage device 100 can perform the best reliability management operation for each memory block. In other words, the storage device 100 can manage the memory blocks individually without performing unnecessary operations. Therefore, according to the present disclosure, a storage device with improved performance and improved reliability and an operating method thereof are provided.

[0207] In some embodiments, the storage device may measure the cell count of the memory block after performing a soft erase operation. The storage device may generate a health index associated with the retention characteristics of the memory block based on the cell count. The storage device may manage the memory blocks individually based on the health index of each of the memory blocks. Therefore, a storage device having improved performance and improved reliability and an operating method thereof are provided.

[0208] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope that can be claimed, but rather as descriptions of features that can be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0209] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: a non-volatile memory device comprising a plurality of memory blocks; as well as a memory controller configured to control the nonvolatile memory device, Wherein, the memory controller is configured as: performing a soft erase operation on a first memory block among the plurality of memory blocks; applying a first reference voltage to a plurality of first memory cells to measure a first cell count after performing the soft erase operation, wherein the plurality of first memory cells are preselected from a plurality of memory cells of a first memory block; generating a first health index associated with a retention characteristic of the first memory block based on the first cell count; and Based on the first health index, a reliability management operation is performed on the first memory block.

2. The storage device according to claim 1, wherein: The memory controller comprises: a health index lookup table including information regarding a relationship between a plurality of health indexes and a plurality of cell counts, and The memory controller is configured to generate a first health index based on a first cell count and the health index lookup table.

3. The storage device according to claim 2, wherein: The health index lookup table includes: information about the relationship between multiple execution conditions of reliability management operations and multiple health indices, Wherein, the memory controller is configured as: Based on the first health index and the health index lookup table, an execution condition of a reliability management operation associated with the first memory block is determined.

4. The storage device according to claim 1, wherein: The memory controller comprises: Health index table, including multiple reference health indexes, Wherein, the memory controller is configured as: comparing the first health index with a first reference health index corresponding to the first memory block from among the plurality of reference health indexes to obtain a comparison result; and Based on the comparison result, the first reference health index is updated to the first health index, and The multiple reference health indexes indicate multiple health indexes generated before the first health index is generated.

5. The storage device according to claim 1, wherein: The memory controller is configured to operate in an idle mode.

6. The storage device according to claim 1, wherein: The first memory block is a spare block, and wherein the memory controller is configured to: Before performing the soft erase operation, a pre-program operation is performed on the first memory block.

7. The storage device according to claim 6, wherein: After performing the pre-program operation, the pre-selected plurality of first memory cells have a programmed state higher than a normal soft erased state.

8. The storage device according to claim 7, wherein: When the memory controller is configured to perform a soft erase operation on a normal memory block among the plurality of memory blocks, a plurality of memory cells of the normal memory block have a normal soft erase state immediately after the soft erase operation is performed on the normal memory block, wherein the lower limit value of the threshold voltage distribution in the normal soft erase state is a first value, and the first value is higher than the upper limit value of the threshold voltage distribution in the normal erase state, and The first reference voltage corresponds to a first value.

9. The storage device according to claim 8, wherein: The first cell count is an on-cell count or an off-cell count of a preselected plurality of first memory cells, wherein the on-cell count indicates the number of first memory cells that are turned on when a first reference voltage is applied thereto from a plurality of pre-selected first memory cells, and The turn-off cell count indicates the number of first memory cells that are turned off when a first reference voltage is applied thereto from a plurality of pre-selected first memory cells.

10. The storage device according to claim 1, wherein: The memory controller is configured to: performing a virtual shutdown operation on a second memory block from the plurality of memory blocks that is different from the first memory block; applying a second reference voltage to a plurality of second memory cells to measure a second cell count after performing the virtual shutdown operation, wherein the plurality of second memory cells are preselected from a plurality of memory cells of a second memory block; generating a second health index associated with a retention characteristic of the second memory block based on the second cell count; and Based on the second health index, a reliability management operation is performed on the second memory block.

11. The storage device according to claim 10, wherein: The plurality of second memory cells include: at least one data memory cell having one of a plurality of programming states; and at least one open memory cell having a normally erased state, wherein the virtual shutdown operation includes programming the at least one open memory cell to have a highest programming state among the plurality of programming states, and The highest programming state is a programming state having a highest lower limit value, and the highest lower limit value is a highest lower limit value among multiple lower limit values ​​of multiple threshold voltage distributions of the multiple programming states.

12. The storage device according to claim 11, wherein: The first cell count indicates the number of first memory cells that are turned on when the first reference voltage is applied thereto from the preselected plurality of first memory cells, and wherein the second cell count indicates the number of second memory cells that are turned on when a second reference voltage is applied to a preselected plurality of second memory cells after a retention reference time has passed since a time point when the memory controller completes a virtual shutdown operation on the second memory block, and The first reference voltage is a lower limit value of the threshold voltage distribution in a normal soft erase state, and the second reference voltage is the highest lower limit value.

13. The storage device according to claim 11, wherein: When the first cell count is greater than the second cell count, the memory controller is configured to: performing a reliability management operation on a first memory block during a first period of time; and A reliability management operation is performed on the second memory block for a second period of time that is longer than the first period of time.

14. A method for operating a storage device, wherein: The storage device includes a memory controller and a non-volatile memory device, the non-volatile memory device includes a plurality of memory blocks, and the memory controller controls the non-volatile memory device, the method includes: performing a pre-programming operation on a first memory block among the plurality of memory blocks; performing a soft erase operation on the first memory block; applying a first reference voltage to a first plurality of memory cells to measure a first cell count, wherein the first plurality of memory cells are preselected from a plurality of memory cells of a first memory block; generating a first health index associated with a retention characteristic of the first memory block based on the first cell count; and Based on the first health index, a reliability management operation is performed on the first memory block.

15. The method according to claim 14, wherein: The first memory block is a free block, and wherein performing the pre-programming operation comprises: A plurality of threshold voltages of the preselected plurality of first memory cells are adjusted so that the preselected plurality of first memory cells have a programmed state higher than a normal soft erased state.

16. The method according to claim 15, wherein: The lower limit value of the threshold voltage distribution in the normal soft erase state is a first value, The first value is higher than the upper limit of the threshold voltage distribution in the normal erase state, and The first reference voltage corresponds to a first value.

17. The method according to claim 14, wherein: Generating the first health index includes: comparing the first cell count to a plurality of reference values; comparing the first health index with a first reference health index corresponding to the first memory block from a plurality of reference health indexes indicating a plurality of health indexes generated before the first health index is generated to obtain a comparison result; and Based on the comparison result, the first reference health index is updated to the first health index.

18. The method according to claim 14, wherein: Performing reliability management operations includes: determining, based on the first health index, an execution condition of a reliability management operation of the first memory block; and It is determined whether the first memory block satisfies the execution condition.

19. The method according to claim 14, wherein: The soft erase operation includes an operation of releasing some of the charges stored in the memory block.

20. A storage device comprising: a non-volatile memory device comprising a plurality of memory blocks; as well as a memory controller configured to control the nonvolatile memory device, Wherein, the memory controller comprises: a health index table including a plurality of reference health indexes corresponding to a plurality of memory blocks; and Health index lookup table, including multiple reference values, Wherein, the memory controller is configured as: performing a pre-programming operation on a first memory block among the plurality of memory blocks; After performing the pre-programming operation, performing a soft erase operation on the first memory block; applying a first reference voltage to a plurality of first memory cells to measure a first cell count after performing the soft erase operation, wherein the plurality of first memory cells are preselected from a plurality of memory cells of a first memory block; generating a first health index associated with a retention characteristic of the first memory block based on the first cell count and a plurality of reference values; comparing the first health index with a first reference health index corresponding to the first memory block from among the plurality of reference health indexes to obtain a comparison result; Based on the comparison result, updating the first reference health index to the first health index; and Based on the first health index, a reliability management operation is performed on the first memory block.

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