Data storage device for wave control system

Abstract

The invention provides a data storage device for a wave control system. The data storage device comprises a FLASH data read-write module, a DDR3 data read-write module, a data scheduling module and a wave control calculation module. According to the invention, the FLASH is used as a data storage chip, the storage capacity reaches Gbit, and the FLASH has a non-volatile characteristic; a DDR3 is used as a dynamic storage chip, and the storage capacity reaches Gbit and is far greater than the internal storage capacity (generally dozens of Mbits) of the FPGA; and the dynamic read-write rate of the data can reach 1Gbit.

Description

Technical Field

[0001] The invention belongs to the field of antenna wave control, and in particular relates to a data storage device used in a wave control system. Background Art

[0002] The October 2017 issue of Ship Electronic Countermeasures, Volume 40, Issue 5, entitled "A Design of Miniaturized Beam Control Equipment for Airborne Radars", describes a wave control design method that can be widely used in small and medium-sized ground, airborne, and satellite-borne phased array radars. This design method achieves the phase arrangement and timing control requirements of 256 antenna units, and has the characteristics of small size, high speed, high reliability, and high flexibility. However, the system has a dynamic storage capacity of only 13Mb, and when the storage capacity required by the system increases, the system is no longer applicable. Summary of the invention

[0003] The present invention proposes a data storage device for a centralized wave control system, which solves the problem of insufficient dynamic storage capacity of the wave control system. Specifically, it includes four parts: FLASH data reading and writing module, DDR3 data reading and writing module, data scheduling module, and wave control calculation module.

[0004] 1. Data scheduling module

[0005] The data scheduling module receives external control instructions and mainly completes the following functions:

[0006] 1) Write the data contained in the instruction to the FLASH address specified by the instruction.

[0007] 2) Read the data specified by the instruction from FLASH and write it to DDR3.

[0008] 3) Read the data required for wave control calculation from DDR3 and output it to the wave control calculation.

[0009] 2. FLASH read and write control module

[0010] The data scheduling module receives external instructions, parses the address and data information in the instructions, and sends them to the FLASH read-write control module, which writes the data into the corresponding address of the FLASH as solid-state storage data. The data will not be lost after each power-on and power-off.

[0011] 3. DDR3 read and write control module

[0012] The data scheduling module receives external instructions, parses the data information that needs to be read in the instructions, reads the data from the FLASH read-write control module in turn, and then writes the data into the DDR3 read-write control module as dynamic data for wave control calculation. The data will be lost after each power on and off.

[0013] 4. Wave control calculation module

[0014] The wave control calculation module receives external instructions and performs corresponding calculations. During the calculation process, it controls data scheduling to read required data from the DDR3 read-write control module for calculation.

[0015] The beneficial effects of the present invention are

[0016] 1. Use FLASH as the data storage chip, the storage capacity reaches Gbit, and it has the characteristics of non-volatility.

[0017] 2. Use DDR3 as the dynamic memory chip, with a storage capacity of Gbit, which is much larger than the internal storage capacity of FPGA (usually tens of Mbit).

[0018] 3. The dynamic data read and write rate reaches 1Gbit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a block diagram of the data storage device architecture of the present invention.

[0020] Figure 2 A block diagram of an embodiment. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The present invention is applied to a beam control module, which realizes the beam control of an antenna array unit, which is an important component of a phased array radar. Figure 2 shown.

[0023] Take the antenna array unit as 256 channels, 64 frequencies, 8 bits of receiving amplitude (AR) compensation data, 8 bits of receiving phase (PR) compensation data, 8 bits of transmitting amplitude (AT) compensation data, and 8 bits of transmitting phase (PT) compensation data. The minimum FLASH erasure area (sector) is 8KB as an example. The storage address allocation scheme is shown in Table 1.

[0024] Table 1 Storage address allocation

[0025]

[0026]

[0027] When FPGA writes compensation data into FLASH, the address allocation is shown in Table 1. The storage address of the 256-channel data of frequency point 1 is 0x0000~0x03FF, and the sector number is 1. The storage address of the 256-channel data of frequency point 2 is 0x2000~0x23FF, and the sector number is 2, and so on.

[0028] If you need to rewrite the data of frequency point 1, you only need to erase sector 1 of FLASH and then write the data of frequency point 1. The same is true for other frequency points. Therefore, to change the compensation data of any frequency point, you only need to erase the sector to which the compensation data belongs, and the compensation data of other frequency points will not be affected.

[0029] The present invention is not limited to the above specific implementations, and the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made to the above implementations based on the technical essence of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data storage device for a wave control system, characterized in that: include: FLASH data reading and writing module, DDR3 data reading and writing module, data scheduling module and wave control calculation module; The data scheduling module receives external control instructions and completes the following functions: 1) Write the data contained in the instruction to the FLASH address specified by the instruction; 2) Read the data specified by the instruction from the FLASH and write it into the DDR3 data read / write module; 3) Read the data required for wave control calculation from the DDR3 data read-write module and output it to the wave control calculation; The FLASH read-write control module implements the storage and reading of instruction data; The DDR3 data reading and writing module uses the data written by the data scheduling module as dynamic data for wave control calculation; The wave control calculation module receives external instructions and performs corresponding calculations. During the calculation process, the data scheduling module is controlled to read required data from the DDR3 data read-write module for calculation.

2. A data storage device for a wave control system according to claim 1, characterized in that: The FLASH data reading and writing module includes a FLASH control interface.

3. A data storage device for a wave control system according to claim 1, characterized in that: The DDR3 data read-write module includes a DDR3 interface controller.

4. A data storage device for a wave control system according to claim 1, characterized in that: The functions of FLASH data reading and writing module, DDR3 data reading and writing module, data scheduling module and wave control calculation module are implemented in FPGA.

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