A probe processor

Abstract

The present invention discloses a probe processor, based on the RISC-V processor architecture, comprising: a probe operation dedicated instruction set and a probe processor micro-architecture; wherein the probe operation dedicated instruction set is used to implement basic operations related to the probe; and the probe processor micro-architecture is used to implement probe operations according to the probe operation dedicated instruction set. The technical solution of the present invention is adopted to effectively improve the computing efficiency of the probe operation.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a probe processor. Background Art

[0002] Solving NP-complete problems is one of the major challenges facing society today, and it requires breaking through the limitations of the Turing model. The concept of the probe machine is a new computing model that has been proposed for the first time in recent years and can effectively solve this NP-complete problem. It is an important frontier of global academic exploration.

[0003] The mathematical model of the von Neumann processor is the Turing machine, which is a typical serial computing model, which makes it "incapable" of handling large-scale NP-complete problems. NP-complete problems are generally regarded as one of the biggest challenges facing the development of human society today, because the computational complexity of such problems grows exponentially with the increase of the problem size.

[0004] Taking the 3-coloring problem of a 100-point computational graph as an example, the feasible solution space required is 3 100 , about 5.15×10 47 . Using a traditional Turing machine large server, it takes dozens of days to solve. The difficulty of solving such NP-complete problems is widely present in real life. For example: 1. Integer programming problems, including train scheduling, aerospace on-orbit aircraft planning, logistics warehousing unmanned vehicle planning, etc. 2. Communication protocol encryption and decryption problems, such as the RSA algorithm, a public key encryption algorithm, which is widely used in the financial field for inter-bank data transmission.

[0005] Professor Xu Jin and his team proposed a low-level fully parallel computing model called "probe machine" in 2016. This model theoretically surpassed the traditional Turing machine model for the first time, aiming to solve NP-complete problems that current electronic computers cannot efficiently handle, such as the Hamiltonian problem and the vertex coloring problem of graphs.

[0006] Based on the above probe machine model, Professor Xu Jin's team proposed two ideas for biological realization: one is a nano-DNA computer that uses nanoparticles and DNA molecules as data and DNA molecules as probes; the other is a model that uses neurotransmitters such as acetylcholine as information in data fibers, similar to the "action potential" in the biological nervous system as a probe.

[0007] Although biologically implemented computing models are innovative and promising, they also have some significant disadvantages: (1) Complexity and controllability: The complexity of biological systems is much higher than that of electronic systems, especially when it comes to operations at the molecular and cellular levels. Controlling and precisely managing the behavior of these systems is an extremely challenging task; (2) Stability and reliability: Biological materials (such as DNA, proteins, etc.) may exhibit instability or degradation under different environmental conditions, which poses a major threat to the reliability and stability of computing; (3) Speed ​​and efficiency: Although biological computing may perform well on certain specific problems, it is still at a disadvantage compared to modern electronic computers in terms of overall speed and efficiency. The time scale of biological reactions is generally long and cannot be compared with the nanosecond speed of electronic computing; (4) Scale and scalability: Biological computing systems are currently difficult to expand to large-scale applications. The manufacture and maintenance of large-scale biological computers is not only technically complex but also costly. Professor Xu Jin's team proposed a fully parallel computing model from the bottom up - the probe machine; (5) Environmental dependence: Biological systems are extremely sensitive to environmental conditions (such as temperature, pH value, nutrient supply, etc.), and slight changes may cause large fluctuations in system performance. This dependence on the environment increases the difficulty of practical application. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a probe processor to effectively improve the computing efficiency of probe operations.

[0009] To achieve the above object, the present invention adopts the following technical solution:

[0010] A probe processor, based on the RISC-V processor architecture, includes: a probe operation dedicated instruction set and a probe processor microarchitecture; wherein,

[0011] The probe operation dedicated instruction set is used to implement basic operations related to the probe;

[0012] The probe processor micro-architecture is used to implement probe operations according to a probe operation-specific instruction set.

[0013] Preferably, the probe operation-specific instruction set includes: gset instruction, gpre instruction, gclear instruction, ginfer instruction, gprobe instruction, and gfill instruction; wherein, the gset instruction is used to set the number of shading and points; the gpre instruction is used to set the point color set; the gclear instruction is used to clear the temp_sol, temp_fresh_point, temp_sign or true_sol, true_fresh_point, true_sign registers; the ginfer instruction is used to start the inference operation; the gprobe instruction is used to specify the address of the adjacency matrix and start the probe operation; the gfill instruction is used to fill the temp_fresh_point and true_fresh_point registers.

[0014] Preferably, the probe processor micro-architecture comprises: an instruction fetch unit, an execution unit and a probe unit; wherein,

[0015] The instruction fetch unit is used to fetch the correct instruction from the specified memory, and perform branch prediction and decoding. If the prediction is successful, the corresponding instruction PC and corresponding instruction information are obtained; if the prediction fails, the instruction pipeline is cleared to continue to execute the corresponding instruction, obtain the instruction information, and send the information to the execution unit;

[0016] The execution unit is used to receive instructions, distribute them to corresponding computing units for execution according to different instruction types, and maintain the data relevance of the instructions;

[0017] The probe unit is used to implement a dedicated instruction set for probe operations.

[0018] Preferably, the probe unit includes a probe decoding module, a data interface module, a database module, a probe control module, a probe write-back module, an inference module and a probe module; wherein,

[0019] The probe decoding module is used to fully decode the custom instruction, obtain instruction information, and pass it to the probe control module. The instruction information includes: probe operation configuration information, processing data address, operation type and read and write operation information;

[0020] The probe control module is used to schedule, configure and execute the probe internal function modules according to the probe operation configuration information, processing data address, operation type and read / write operation information;

[0021] The database module is used to store multiple bits of intermediate temporary data and input and output data during the probe operation;

[0022] The reasoning module is used to perform reasoning operations;

[0023] The probe module is used to perform probe operations according to instruction configuration information and operation types;

[0024] The probe write-back module is used to save the calculation results and write them back to the correct location in the RISC-V processor through arbitration.

[0025] Preferably, the database module comprises: three register groups of true_sol, true_fresh_point and true_sign with a width of N and a depth of M, and three register groups of temp_sol, temp_fresh_point and temp_sign with a width of N and a depth of 2M-1.

[0026] Preferably, the inference module is composed of a plurality of inverters and AND gates, the input of the inference module is Able_list and true_fresh_point register data, and after inference calculation, the output result is stored in temp_fresh_point and temp_sol.

[0027] Preferably, the input of the probe module is the temp_sol register data and the adjacency matrix, and the output result is stored in temp_sign.

[0028] Preferably, the instruction fetch unit generates the address required for the instruction through the address generation module; the address generation module is connected to the pre-branch prediction module and the bus control module; the bus control module is connected to the bus interface unit and the instruction memory, and the bus control module also establishes a connection with the pre-decoding module and the instruction fetch distribution unit in the execution unit through a selector; the instruction fetch distribution unit distributes the instruction to the control instruction judgment module, the arithmetic operation unit, the long instruction unit, the load storage unit and the probe decoder; the probe decoder is connected to the data interface and the probe control module; the data interface module is connected to the database module and the probe write back module, and is also connected to the inference module and the probe module; the execution unit is connected to the delivery module through the write back arbitration selector, and is finally connected to the write back register module.

[0029] Preferably, the instruction execution process is as follows: the instruction execution process starts when the instruction is stored in the instruction memory, and the address generation module generates the address of the instruction, that is, the program counter PC, and passes this address to the bus control module; the bus control module takes out the corresponding instruction according to the PC and passes it to the pre-decoding module and the instruction fetch distribution unit; if the instruction is a jump instruction, it will directly generate a new jump address through the pre-branch prediction module; if the instruction is not a jump instruction, the instruction fetch distribution unit distributes it to the arithmetic operation unit, the long instruction unit, the load storage unit or the policy calculation execution unit according to the different types of instructions; for the probe instruction, the probe decoder is used to perform full decoding to obtain complete instruction information, the data interface module receives the decoded data information, and obtains the required data from the external data memory; at the same time, the probe control module receives the calculation information, and schedules and configures the reasoning module and the probe module according to the calculation information; the reasoning module and the probe module also receive the calculation data from the data pool, and pass it to the write-back arbitration selector through the probe write-back module; the write-back arbitration selector cooperates with the delivery module to ensure that the calculation result is correctly written back to the register.

[0030] The probe processor of the present invention adopts a two-level pipeline structure consisting of instruction fetch and execution, and implements probe operations by designing a probe processing unit and expanding custom probe instructions. Accordingly, the probe processor modifies the decoding logic of the instruction fetch part so that the processor can recognize custom instructions, configure and schedule the probe unit of the storage-computation integrated structure to support the implementation of probe operations with different numbers of points and different coloring numbers. The probe processor makes full use of the disassembly of the probe operation and the extensibility of the RISC-V architecture to effectively improve the computing efficiency of the probe operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0032] Figure 1 This is a schematic diagram of the structure of a probe processor according to an embodiment of the present invention;

[0033] Figure 2 Hardware implementation diagram of gclear and gfill instructions in the instruction set dedicated for custom probe operations;

[0034] Figure 3 The hardware implementation diagram of the ginfer instruction in the dedicated instruction set for custom probe operations;

[0035] Figure 4Hardware implementation diagram of gprobe instruction in the instruction set dedicated for custom probe operation;

[0036] Figure 5 A schematic diagram of a probe processor microarchitecture according to an embodiment of the present invention;

[0037] Figure 6 A schematic diagram of a probe processor register according to an embodiment of the present invention;

[0038] Figure 7 This is the implementation process diagram of the instruction layer for the 12-point coloring situation. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Embodiment 1:

[0042] like Figure 1 As shown, an embodiment of the present invention provides a probe processor based on the RISC-V processor architecture, including: a probe operation dedicated instruction set and a probe processor microarchitecture; wherein,

[0043] The probe operation dedicated instruction set is used to implement basic operations related to the probe;

[0044] The probe processor microarchitecture is used to implement probe operations according to the probe operation dedicated instruction set.

[0045] As an implementation method of an embodiment of the present invention, the design of a dedicated instruction set for probe operations is shown in Table 1, which is divided into three instruction types. Gr type instructions represent instructions that require two source registers, Gi type instructions represent instructions that require immediate numbers, and G type instructions represent instructions that require both immediate numbers and two source operands. There are a total of 6 custom instructions for probe-related operations, and the dedicated instruction set for probe operations includes: gset instructions, gpre instructions, gclear instructions, ginfer instructions, gprobe instructions, and gfill instructions.

[0046] Table 1

[0047]

[0048]

[0049] The gset instruction is used to set the shading number and the number of points. It belongs to the Gr type instruction. The instruction structure is shown in Table 2. The opcode field is the operation code of the Gr type instruction. Funct3 and funct7 are the function codes of the gset instruction. The values ​​in the rs1 and rs2 registers represent the shading number and the number of points of this graph shading operation respectively.

[0050] Table 2

[0051]

[0052] The gpre instruction is used to set the point color set. It belongs to the Gi type instruction. The instruction structure is shown in Table 3. The opcode field is the operation code of the Gi type instruction, the funct3 field is the function code of the gpre instruction, and the rs1 field and the imm field are the base address and offset address of the point color set respectively. This instruction is used to specify the location of the point color set corresponding to the current graph coloring operation in memory.

[0053] Table 3

[0054]

[0055] The gclear instruction is used to clear the temp_sol, temp_fresh_point, temp_sign or true_sol, true_fresh_point, true_sign registers. It belongs to the Gi type instruction, and the instruction structure is shown in Table 3. The opcode field is the operation code of the Gi type instruction, funct3 is the function code of the gclear instruction, rs1 is the register to be cleared, and imm is the offset of the register to be cleared.

[0056] The ginfer instruction is used to start the inference operation and belongs to the G-type instruction. The instruction structure is shown in Table 4. The opcode field is the operation code of the G-type instruction, funct3 is the function code of the ginfer instruction, the rs1 source register is the true_fresh_point register, the rs2 source register and imm are the base address and offset address of the point color set respectively, and the rd destination register is the temp_fresh_point register to which the inference operation result is returned.

[0057] Table 4

[0058]

[0059] The gprobe instruction is used to specify the address of the adjacency matrix and start the probe operation. It belongs to the G-type instruction. The instruction structure is shown in Table 4. The opcode field is the operation code of the G-type instruction, funct3 is the function code of the gprobe instruction, the rs1 source register is the temp_sol register, the rs2 source register and imm are the base address and offset address of the adjacency matrix respectively, and the rd destination register is the temp_sign register to which the probe operation result is returned.

[0060] The gfill instruction is used to fill the temp_fresh_point and true_fresh_point registers. It belongs to the Gi type instruction, and the instruction structure is shown in Table 3. The opcode field is the operation code of the Gi type instruction, funct3 is the function code of the gfill instruction, rs1 is the register to be filled, and imm is the offset of the fill register.

[0061] gset and gpre are configuration instructions used to set the data required for graph coloring operations. Therefore, the hardware implementation is integrated into the Probe Control module. gclear and gfill are register-related instructions. The hardware implementation is as follows: Figure 2 shown.

[0062] The hardware implementation of the ginfer instruction is as follows Figure 3 The input of the module is the true_fresh_point register and the able_list point color set. The value in the true_fresh_point register is inverted and then ANDed with each value in the abli_list point color set. The result is judged by the truth table and finally output to the temp_fresh_point and temp_sol registers to complete the reasoning operation.

[0063] The hardware implementation of the gprobe instruction is as follows Figure 4 As shown. The input of the module is the temp_sol register and the adjacency matrix. The adjacency matrix consists of 0 and 1, representing whether the two points at the corresponding coordinate positions are connected or disconnected. When the temp_sol register and the adjacency matrix are calculated, since the probe operation needs to be calculated point by point, in order to prevent redundant calculation operations from affecting the calculation efficiency, the MASK matrix is ​​introduced. The MASK matrix is ​​a matrix of all 0s. When the target point is probed, the states of the remaining points in the adjacency matrix are ANDed with the MASK matrix to reduce unnecessary calculations. The probe operation is performed by performing an XOR operation on the values ​​in the temp_sol register, and then performing an AND operation with the connection relationship of the corresponding position in the adjacency matrix, and finally outputting the probe operation result.

[0064] As an implementation method of the embodiment of the present invention, Figure 5As shown, the probe processor micro-architecture includes: an instruction fetch unit, an execution unit and a probe unit.

[0065] Furthermore, the instruction fetch unit is composed of an instruction address generation module, a bus control module, a pre-branch prediction module, and a pre-decoding module. The instruction fetch unit is used to fetch the correct instruction from the specified memory, perform simple branch prediction and decoding functions, and send the processed instruction to the execution unit. The address generation module is a crucial component of the processor. It is responsible for generating the value of the program counter (PC), which is the address of the executed instruction. The address generation module uses advanced branch prediction technology, which can predict the execution flow of the program and calculate the possible jump address in advance. When the branch prediction is successful, the address generation module will receive the jump result and update the PC value accordingly to ensure a smooth transition of the instruction flow.

[0066] The updated PC value is then sent to the bus control module, which decides whether to fetch instructions from the internal instruction memory (such as the instruction cache or ITCM) or from the external memory through the bus based on the PC value provided by the address generation module and the current configuration information. This flexible configuration allows the processor to choose the most appropriate instruction fetching method based on different application scenarios and performance requirements. If the configuration points to the internal instruction memory, the bus control module will read the instructions directly from the ITCM. ITCM (Instruction Trace Cache Memory) is a dedicated high-speed cache used to store frequently accessed instruction sequences to reduce the number of accesses to the external memory and reduce latency. On the contrary, if instructions need to be fetched from the external memory, the bus control module will issue a read request through the system bus to exchange data with the external memory. After the instruction is successfully fetched, it will be sent to the next level of execution unit.

[0067] Furthermore, the execution unit includes an instruction fetch and dispatch unit, an arithmetic logic unit ALU, a long instruction unit Long Pipes, an access execution unit LSU, an instruction delivery module Commit, a write back arbitration module WB Arb, and a data consistency module OITF. The execution unit receives instructions and distributes them to the corresponding operation units for execution according to different instruction types. It is also responsible for maintaining the data relevance of the instructions. The execution unit is mainly responsible for implementing the instruction function. By judging the type of instruction, it distributes it to different operation units such as ALU, LongPipes, LSU for function implementation. The Probe probe unit is also one of the operation units. The execution unit also includes the processor's register group, such as Figure 6 As shown, it includes 32 64-bit general registers and 6 probe registers.

[0068] Furthermore, the probe unit is a computing unit specifically used to implement probe instructions, including a probe decoder ProbeDecoder, a data interface Data Interface, a database module Data Library, a probe controller ProbeControl, a probe write back module Probe Write Back, an inference module Infer, and a probe module Probe. The probe decoder receives the probe instruction and determines the specific instruction through decoding. If it is a configuration instruction, it is directly distributed to the probe controller module. If it is a calculation instruction, it is distributed to the corresponding functional module according to the instruction. The final result is arbitrated by the probe write back module to determine the write back position.

[0069] like Figure 5 As shown, the instruction fetch unit IFU generates the address required for the instruction through the address generation module Pc_Gen. The address generation module is further connected to the pre-branch prediction module SimpleBPU and the bus control module Bus_Ctrl. The bus control module Bus_Ctrl is not only connected to the bus interface unit BIU and the instruction memory ITCM, but also establishes a connection with the pre-decoding module MiniDecode and the instruction fetch distribution unit Decode&Dispatch in the execution unit through the selector. The instruction fetch distribution unit distributes the instruction to the control instruction judgment module OITF, the arithmetic operation unit ALU, the long instruction unit Long Pipes, the load storage unit LSU, and the probe decoder Probe Decoder, which process different types of instructions respectively. The probe decoder Probe Decoder is connected to the data interface Data Interface and the probe control module Probe Control, and is responsible for allocating different probe instructions to the corresponding modules. The data interface module Data Interface is connected to the database module DataLibrary module and the probe write back module Probe Write Back module, and is also connected to the inference module Infer and the probe module Probe. The execution units are connected to the delivery modules through write-back arbitration selectors, and finally to the write-back register modules.

[0070] The instruction execution process is as follows: The instruction execution process starts when the instruction is stored in the instruction memory. The address generation module generates the address of the instruction, namely the program counter (PC), and passes this address to the bus control module. The bus control module fetches the corresponding instruction according to the PC and passes it to the pre-decoding module and the instruction fetch distribution unit. If the instruction is a jump instruction, it will directly generate a new jump address through the pre-branch prediction module. If the instruction is not a jump instruction, the instruction fetch distribution unit will distribute it to the arithmetic operation unit, long instruction unit, load storage unit or policy calculation execution unit according to the different types of instructions. For probe instructions, they will be fully decoded through the probe decoder to obtain complete instruction information. The data interface module receives the decoded data information and obtains the required data from the external data memory. At the same time, the probe control module receives the calculation information and schedules and configures the reasoning module and the probe module according to this information. The reasoning module and the probe module also receive the calculation data from the data pool. After the calculation is completed, the result is passed to the write-back arbitration selector through the probe write-back module. The write-back arbitration selector cooperates with the delivery module to ensure that the calculation result is correctly written back to the register.

[0071] Take the 12-point coloring as an example. Figure 7 This is the implementation process of the instruction layer. First, configure the bit width of each element to 8, the number of elements to 12, and the number of colors to 3. Use the gset instruction to set the number of elements and colors of the probe module, then set the base address of the point color set to 0x10040000, set the base address of the adjacency matrix to 0x10050000, and use the gpre instruction to set the point color set address. The point color set requires a 96-bit size, so the offset address is 0x60, and the point color set address is 0x10040060. Then use the gclear instruction to clear the temp_sol register. Then use the ginfer instruction to start the inference operation. After the inference is completed, use the gprobe instruction to configure the adjacency matrix with an offset address of 0x90 to start the probe operation. Use gclear to clear the true_sol register, and then use gfill to fill the probe register. Finally, determine whether the inference is completed. If not, jump to GLoop to continue the operation until all point inferences are completed and the operation ends.

[0072] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A probe processor, characterized in that: Based on RISC-V processor architecture, including: probe operation dedicated instruction set and probe processor microarchitecture; among which, The probe operation dedicated instruction set is used to implement basic operations related to the probe; The probe processor micro-architecture is used to implement probe operations according to a probe operation-specific instruction set; The dedicated instruction set for probe operation includes: gset instruction, gpre instruction, gclear instruction, ginfer instruction, gprobe instruction, and gfill instruction; among them, the gset instruction is used to set the number of shading and points; the gpre instruction is used to set the point color set; the gclear instruction is used to clear the temp_sol, temp_fresh_point, temp_sign or true_sol, true_fresh_point, true_sign registers; the ginfer instruction is used to start the inference operation; the gprobe instruction is used to specify the address of the adjacency matrix and start the probe operation; the gfill instruction is used to fill the temp_fresh_point and true_fresh_point registers.

2. The probe processor according to claim 1, characterized in that The probe processor micro-architecture includes: an instruction fetch unit, an execution unit and a probe unit; wherein, The instruction fetch unit is used to fetch the correct instruction from the specified memory, and perform branch prediction and decoding. If the prediction is successful, the corresponding instruction PC and corresponding instruction information are obtained; if the prediction fails, the instruction pipeline is cleared to continue to execute the corresponding instruction, obtain the instruction information, and send the information to the execution unit; The execution unit is used to receive instructions, distribute them to corresponding computing units for execution according to different instruction types, and maintain the data relevance of the instructions; The probe unit is used to implement a dedicated instruction set for probe operations.

3. The probe processor according to claim 2, characterized in that: The probe unit includes a probe decoding module, a data interface module, a database module, a probe control module, a probe write-back module, an inference module and a probe module; wherein, The probe decoding module is used to fully decode the custom instruction, obtain instruction information, and pass it to the probe control module. The instruction information includes: probe operation configuration information, processing data address, operation type and read and write operation information; The probe control module is used to schedule, configure and execute the probe internal function modules according to the probe operation configuration information, processing data address, operation type and read / write operation information; The database module is used to store multiple bits of intermediate temporary data and input and output data during the probe operation; The reasoning module is used to perform reasoning operations; The probe module is used to perform probe operations according to instruction configuration information and operation types; The probe write-back module is used to save the calculation results and write them back to the correct location in the RISC-V processor through arbitration.

4. The probe processor according to claim 3, characterized in that: The database module includes: three register groups of true_sol, true_fresh_point and true_sign with a width of N and a depth of M, and three register groups of temp_sol, temp_fresh_point and temp_sign with a width of N and a depth of 2M-1.

5. The probe processor according to claim 4, characterized in that: The inference module is composed of several inverters and AND gates. The input of the inference module is the Able_list and true_fresh_point register data. After inference calculation, the output result is stored in temp_fresh_point and temp_sol.

6. The probe processor according to claim 5, characterized in that: The input of the probe module is the temp_sol register data and the adjacency matrix, and the output result is stored in temp_sign.

7. The probe processor according to claim 6, characterized in that: The instruction fetch unit generates the address required for the instruction through the address generation module; the address generation module is connected to the pre-branch prediction module and the bus control module; the bus control module is connected to the bus interface unit and the instruction memory, and the bus control module also establishes a connection with the pre-decoding module and the instruction fetch distribution unit in the execution unit through a selector; the instruction fetch distribution unit distributes the instruction to the control instruction judgment module, the arithmetic operation unit, the long instruction unit, the load storage unit and the probe decoder; the probe decoder is connected to the data interface and the probe control module; the data interface module is connected to the database module and the probe write back module, and is also connected to the inference module and the probe module; the execution unit is connected to the delivery module through the write back arbitration selector, and finally connected to the write back register module.

8. The probe processor according to claim 7, characterized in that: The instruction execution process is as follows: the instruction execution process starts when the instruction is stored in the instruction memory, the address generation module generates the address of the instruction, that is, the program counter PC, and passes this address to the bus control module; The bus control module takes out the corresponding instruction according to the PC and passes it to the pre-decoding module and the instruction fetch distribution unit; if the instruction is a jump instruction, it will directly generate a new jump address through the pre-branch prediction module; if the instruction is not a jump instruction, the instruction fetch distribution unit distributes it to the arithmetic operation unit, the long instruction unit, the load storage unit or the policy calculation execution unit according to the different types of instructions; for the probe instruction, the probe decoder performs full decoding to obtain the complete instruction information, the data interface module receives the decoded data information, and obtains the required data from the external data storage; at the same time, the probe control module receives the calculation information, and schedules and configures the reasoning module and the probe module according to the calculation information; the reasoning module and the probe module also receive the calculation data from the data pool, and pass it to the write-back arbitration selector through the probe write-back module; the write-back arbitration selector cooperates with the delivery module to ensure that the calculation result is correctly written back to the register.

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