System starting method, data transmission system, electronic equipment and chip system

Abstract

The invention provides a system starting method, a data transmission system, electronic equipment and a chip system. Relates to the technical field of computers. In order to solve the problems that when a system is started, due to the fact that an SOC memory is small, function implementation is limited, the system starting method is provided and comprises the steps that an FPGA chip loads FPGA firmware in a storage medium for starting; after the FPGA chip is started, the FPGA chip loads FPGA software in the FPGA firmware, and SOC firmware in the FPGA software is stored in a running memory; the SOC chip obtains the SOC firmware in the running memory on the basis of a configuration interface connected with the FPGA chip, and starting is completed; according to the embodiment of the invention, for a system with a relatively small SOC memory, the problem of high demand on the memory in an SOC dominant control structure can be avoided, the memory advantages of the FPGA are fully utilized, and the functionality, the stability, the reliability and the portability of the system are improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a system startup method, a data transmission system, an electronic device and a chip system. Background Art

[0002] Universal Serial Bus (USB) 3.0 (U3V for short) data transmission system, as a new generation of connection technology, is widely used in modern electronic devices due to its high speed and high efficiency. The system usually includes Field Programmable Gate Array (FPGA) chip and System-on-a-Chip (SOC); FPGA is responsible for data processing, and SOC is responsible for USB transmission with the host computer. In actual application, SOC usually takes the lead in controlling the storage medium; when the system starts, the requirements for the SOC interface, software functions and memory are relatively high. For some systems with small SOC memory, the function implementation is limited. Summary of the invention

[0003] According to various embodiments of the present application, a system startup method, a data transmission system, an electronic device and a chip system are provided. For systems with a small SOC memory, the high demand for memory in the SOC-dominated control structure can be avoided, thereby improving the functionality of the system.

[0004] In a first aspect, the present application provides a system startup method, which is applied to a data transmission system, wherein the data transmission system includes an FPGA chip, a SOC chip, and a storage medium; the method includes:

[0005] The FPGA chip loads the FPGA firmware in the storage medium to start up; after the FPGA chip completes the startup, the FPGA chip loads the FPGA software in the FPGA firmware and stores the SOC firmware in the FPGA software in the running memory; the SOC chip obtains the SOC firmware in the running memory based on the configuration interface connected to the FPGA chip to complete the startup.

[0006] Through the above method, the data transmission system is autonomously started by the FPGA chip by loading the FPGA firmware in the storage medium, without the need for SOC chip configuration, and thus there is no need for the SOC chip configuration to connect to the interface for FPGA chip burning, thus avoiding the high demand for memory in the SOC-dominated control structure and improving the functionality of the system; it has strong ease of use and practicality.

[0007] In a possible implementation of the first aspect, the FPGA chip loads the FPGA firmware in the storage medium to start up, including: the FPGA chip loads the bit stream in the FPGA firmware and is configured as a programmable system on chip; the FPGA chip loads the FPGA software in the FPGA firmware based on the programmable system on chip to complete the startup.

[0008] In a possible implementation manner of the first aspect, the method further includes: after the FPGA chip completes startup, controlling the SOC chip to be in a reset state.

[0009] In a possible implementation of the first aspect, the method further includes: the FPGA chip loads the FPGA software in the FPGA firmware and configures an analog storage medium interface; the analog storage medium interface is used to provide the SOC firmware to the SOC chip when the SOC chip starts, and the FPGA software includes the SOC firmware.

[0010] In a possible implementation manner of the first aspect, the method further includes: after the SOC chip completes startup, feeding back a startup completion signal to the FPGA chip through the configuration interface.

[0011] In a possible implementation manner of the first aspect, the method further includes: after the SOC chip fails to start, the FPGA chip controls the SOC chip to be in a reset state; and the SOC chip re-acquires the SOC firmware for startup.

[0012] In a possible implementation of the first aspect, the method includes: the SOC chip receives a firmware update request sent by a host computer, and receives the firmware to be updated; the SOC chip sends the firmware to be updated to the FPGA chip through the configuration interface; the FPGA chip transfers the firmware to be updated to the running memory.

[0013] In a possible implementation of the first aspect, the method further includes: the FPGA chip verifies the firmware to be updated in the running memory; after the verification passes, the FPGA chip stores the firmware to be updated to the storage medium; the firmware to be updated is loaded by the FPGA chip at the next startup.

[0014] In a second aspect, the present application provides a data transmission system, which includes an FPGA chip, a SOC chip and a storage medium; the FPGA chip is communicatively connected to the storage medium, and the SOC chip is communicatively connected to the FPGA chip via a configuration interface;

[0015] The FPGA chip is used to load the FPGA firmware in the storage medium for startup;

[0016] The FPGA chip is further used to load the FPGA software in the FPGA firmware after the startup is completed, and store the SOC firmware in the FPGA software in the running memory;

[0017] The SOC chip is used to obtain the SOC firmware in the running memory based on the configuration interface connected to the FPGA chip to complete the startup.

[0018] In a third aspect, the present application provides an electronic device, comprising at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute any one of the methods described in the first aspect.

[0019] In a fourth aspect, the present application provides a chip system, which is applied to an electronic device, and the chip system includes one or more processors, and the one or more processors are used to call computer instructions so that the electronic device executes the method described in the first aspect.

[0020] In a fifth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in the first aspect is implemented.

[0021] In a sixth aspect, the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device executes the method described in the first aspect above.

[0022] It can be understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the data transmission system architecture provided in an embodiment of the present application;

[0025] Figure 2A schematic diagram of the improved data transmission system architecture provided in an embodiment of the present application;

[0026] Figure 3 A flowchart of a system startup method provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of the firmware architecture provided for an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the system startup process provided in the embodiment of the present application;

[0029] Figure 6 A schematic diagram of a system firmware update process provided in an embodiment of the present application;

[0030] Figure 7 A structural schematic diagram of an electronic device is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0033] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0036] Due to the complexity of the USB3.0 protocol, the U3V data transmission system combines the advantages of FPGA chips and SOC chips; the FPGA chip is responsible for data processing, and the SOC chip is responsible for USB data transmission. In practical applications, the reasonable storage and efficient management of the firmware of the FPGA chip and the SOC chip are of vital importance, so that the U3V data transmission system can start stably and reliably, run continuously and stably, and update the firmware conveniently.

[0037] Currently, if Figure 1 As shown in Figure (a), the data transmission system corresponding to the electronic device is usually dominated by the SOC chip to control the storage medium. When the system starts, the SOC chip configures the FPGA chip through the burning interface of the FPGA chip; when the firmware is updated, the SOC chip dominates the entire process of firmware data transmission between the electronic device and the host computer. In this way, there are requirements for the physical interface of the SOC chip, and the SOC is required to provide an interface that can be connected to the FPGA chip for burning; and the software functions and memory requirements on the SOC chip are also high. The dedicated SOC chip used for USB transmission usually has a small memory and limited memory resources, so that the software functions that the SOC chip can support will also be subject to corresponding restrictions; therefore, the lack of memory resources will make it difficult for the SOC chip to meet the actual application scenario requirements with increasing and changing functional requirements.

[0038] In order to reduce the demand for SOC chip memory and improve the functionality of SOC chips, such as Figure 1 As shown in Figure (b), the FPGA chip takes the lead and the FPGA chip and the SOC chip can access the storage medium in time-sharing manner by rationally planning the internal content partition of the storage medium. However, the separation of the two chips' access to the storage medium has a potential risk of conflict. Coordination between the two chips requires more specialized designs. When the model of the FPGA chip or SOC chip is replaced, the coordination plan must be redesigned, which is inconvenient.

[0039] In response to the above problems, an embodiment of the present application proposes a system startup method, which mounts the storage medium through the FPGA chip in the system and completes the startup autonomously. The SOC chip no longer needs to be configured through the burning interface, thereby avoiding the high memory demand problem in the SOC-dominated control structure. By making full use of the memory advantages of the FPGA chip, the system functionality, stability, reliability and portability are improved.

[0040] like Figure 2 As shown, the improved data transmission system architecture schematic diagram provided by the embodiment of the present application. In view of the problem that both the SOC chip and the FPGA chip need to load firmware from the storage medium for startup, the interface for loading firmware of the SOC chip is connected to the FPGA chip in a cascade manner, the FPGA chip is connected to the storage medium, and the SOC firmware is included in the firmware of the FPGA chip in the form of software data.

[0041] Among them, the interface for loading firmware on the SOC chip can be a common serial interface, so there is no need for the SOC to provide an interface compatible with the FPGA chip burning. The FPGA has an embedded processor (such as a central processing unit (CPU)) and various functional peripherals, and has its own external running memory (such as double data rate synchronous dynamic random access memory (DDR SDRAM)) and storage media (such as flash memory). The SOC chip serves as an interactive medium between the FPGA chip and the host computer, and is connected to both. The host computer can act as a server to remotely update the firmware of electronic equipment; Figure 2 The electronic device shown may be an embedded device such as a monitoring device or a mobile device.

[0042] Based on the above system architecture, the specific implementation process of the system startup method is further introduced below through embodiments.

[0043] like Figure 3 As shown, a flow chart of the system startup method provided in the embodiment of the present application is shown. The execution subject of the method can be Figure 2 The electronic device shown in , the electronic device may be a data transmission system, the data transmission system may include a cascaded FPGA chip and a SOC chip; wherein the FPGA chip is connected to a storage medium. The method may include the following steps:

[0044] S301, the FPGA chip loads the FPGA firmware in the storage medium to start.

[0045] In the embodiments of the present application, Figure 4 As shown, the storage medium stores FPGA firmware, which includes two files, namely, bit stream (FPGA loading file) and FPGA software; wherein the FPGA software includes the SOC firmware of the SOC chip.

[0046] Exemplarily, FPGA firmware is a software program required for the operation of the SOC chip and the FPGA chip. Figure 2In the system architecture shown, the FPGA chip is connected to the storage medium, and the FPGA firmware can be read from the storage medium and started based on the bit stream and FPGA software in the FPGA firmware.

[0047] In some embodiments, the FPGA chip loads the FPGA firmware in the storage medium to start up, including:

[0048] The FPGA chip loads the bitstream in the FPGA firmware and is configured as a programmable system on chip; based on the programmable system on chip, the FPGA chip loads the FPGA software in the FPGA firmware and completes the startup.

[0049] Exemplarily, the bitstream in the FPGA firmware contains a file of the internal configuration state of the FPGA chip, such as wiring, logic resources, and input / output (I / O) settings, etc. Among them, based on the logic of the SOC chip implemented by the hardware description language Verilog code, the logic is compiled into the FPGA load file, that is, the above-mentioned bitstream, and the bitstream is downloaded to the storage medium (Flash).

[0050] Accordingly, after the FPGA chip is powered on, the FPGA firmware in the storage medium (Flash) is loaded, and according to the logic of the bit stream in the FPGA firmware, it is configured as an editable system on chip (or configured as a temporary SOC chip), so that the FPGA chip has similar functional characteristics as the SOC chip. Among them, the editable system on chip is a system that can run software and has the function of communicating with peripherals.

[0051] Exemplarily, after the FPGA chip is configured as a programmable system on chip, it has the same characteristics as the SOC chip, and needs to further load the FPGA software to complete the startup and work normally. Based on the configured programmable system on chip, the FPGA chip further loads the FPGA software in the FPGA firmware to complete the startup. Among them, after the FPGA chip completes the startup, it can support peripheral communication capabilities such as double data rate DDR, serial peripheral interface (Serial Peripheral Interface, SPI), universal asynchronous receiver / transmitter (Universal Asynchronous Receiver / Transmitter, UART) and integrated circuit bus (Inter-Integrated Circuit, I2C).

[0052] In some embodiments, the method further includes: the FPGA chip loads the FPGA software in the FPGA firmware and configures the simulated storage medium interface; the simulated storage medium interface is used to provide the SOC firmware to the SOC chip when the SOC chip starts, and the FPGA software includes the SOC firmware.

[0053] For example, during the startup process, the FPGA chip can load the FPGA software to implement the logic of the simulated storage medium interface based on the veilog code. The simulated storage medium interface is used to simulate the response of the storage medium (Flash) to the read or write of the SOC chip to meet the timing requirements of the SOC chip for the storage medium during startup loading and firmware update.

[0054] In some embodiments, after the FPGA chip completes startup, the SOC chip is controlled to be in a reset state.

[0055] For example, Figure 2 As shown, after the FPGA chip completes the startup, it controls the reset pin of the SOC chip to put the SOC chip in a reset state. Among them, the general-purpose input / output pin (GPIO) of the FPGA chip is connected to the reset negative signal (RSTN) pin of the SOC chip. The FPGA chip configuration software sends a reset signal to the RSTN pin of the SOC chip through the GPIO pin to put the SOC chip in a reset state, that is, the initial state. For example, when the reset signal is at a low level, the SOC chip is controlled to be in a reset state; otherwise, the control of the RSTN pin is released (that is, the reset control of the SOC chip is released).

[0056] It can be understood that the reset operation of the SOC chip can ensure that the registers, memory and other components of the SOC chip are initialized to a preset initial state (the initial state is determined and known) to wait for startup; thereby ensuring the stability of the system during the startup process and reducing the probability of system startup failure; and through the reset process, it can ensure that the SOC chip is in the best state before startup, reducing the probability of internal parameter drift; while improving system stability, it can also prepare the necessary environment and resources when the SOC chip starts.

[0057] S302, after the FPGA chip is started up, the FPGA chip loads the FPGA software in the FPGA firmware, and stores the SOC firmware in the FPGA software in the running memory.

[0058] In the embodiment of the present application, the startup firmware of the SOC chip (i.e., SOC firmware) is the data part of the FPGA software when compiled; the SOC firmware contains the configuration information required for the startup and operation of the SOC chip, such as clock settings, memory mapping, and peripheral initialization. These configuration information exist in the form of data in the FPGA software. During the compilation process, the SOC firmware is converted into machine-readable binary codes, which are stored and processed as data in the FPGA software to control the startup behavior and functions of the SOC chip.

[0059] Exemplarily, the SOC firmware includes components such as the SOC chip's startup code, operating system, and driver; the FPGA chip loads the FPGA software through the storage medium, extracts the SOC firmware therein, and stores the extracted SOC firmware in the running memory for subsequent loading when the SOC chip is started.

[0060] Among them, after the FPGA chip is started, it has the function of communicating with the running memory. Figure 2 As shown, the FPGA chip has an external running memory (such as DDR). As a high-speed running memory, its data access speed is much faster than that of storage media (such as Flash).

[0061] In this way, the FPGA chip extracts the SOC chip from the storage medium and stores it in the running memory. When the SOC chip is started later, the time required to read the SOC firmware from the storage medium can be significantly reduced, thereby improving the overall system startup speed. It can also meet the system startup with high real-time requirements, ensure system stability and reliability, and be suitable for more complex application scenarios.

[0062] It should be noted that after the FPGA chip stores the SOC firmware in the running memory, the control of the reset pin of the SOC chip can be released, so that the SOC chip starts loading the firmware for startup.

[0063] S303, the SOC chip obtains the SOC firmware in the running memory based on the configuration interface connected to the FPGA chip to complete the startup.

[0064] In the embodiment of the present application, the FPGA chip is configured as an editable system on chip during the startup process, and has functional characteristics similar to those of the SOC chip, that is, it can realize external communication based on the SPI / I2C serial communication interface. Figure 2 As shown, the SOC chip starts the configuration interface, and the configuration interface can be a communication interface such as SPI or I2C between the SOC chip and the FPGA chip.

[0065] Exemplarily, during the startup process of the SOC chip, the SOC chip needs to read the SOC firmware in the running memory; based on the configuration of the simulated storage medium interface of the FPGA chip, the configuration interface on the FPGA chip connected to the SOC chip simulates the behavior of the storage medium returning the storage content when the SOC chip reads the storage medium, and transfers the SOC firmware stored in the running memory to the SOC chip.

[0066] As a result, during the startup process, the SOC chip can flexibly interact with different storage units (such as running memory DDR or storage medium Flash) to obtain the SOC firmware without changing the storage location of the SOC firmware; and based on the editability of the FPGA chip, different versions of SOC firmware can also be matched to improve the compatibility and flexibility of the system, and there is no need to connect the SOC chip to the storage medium, reducing the design complexity and cost; and the data transmission speed between the FPGA chip and the running memory and the data transmission speed between the FPGA chip and the SOC chip are both fast, which can shorten the startup time of the SOC chip and improve the system startup efficiency.

[0067] Among them, for the configuration interface on the FPGA chip, the interface logic of the simulated storage medium is implemented through the Register Transfer Level (RTL) code, that is, the communication protocol between the storage medium and the SOC is simulated; for example, how to receive the read request of the SOC chip, how to obtain the content of the SOC firmware from the software of the FPGA chip, and how to return the content of the SOC firmware to the SOC chip in the correct format.

[0068] As a possible implementation method, the analog storage medium is composed of RTL code, FPGA software and running memory; the FPGA software transfers the content of the SOC firmware from the running memory to the logic implemented by the RTL code; the RTL code implements the analog storage medium interface logic, directly responds to the SOC chip, transfers the SOC firmware to the SOC chip, and the FPGA chip assists the SOC chip to complete the startup.

[0069] Since the SOC chip startup process relies on the analog storage medium interface inside the FPGA chip, the analog storage medium interface cannot work when the FPGA has not completed startup (the FPGA software has not been loaded), so the SOC chip needs to be kept in a reset state to wait for startup.

[0070] In some embodiments, the method further includes: after the SOC chip completes startup, feeding back a startup completion signal to the FPGA chip through a configuration interface.

[0071] For example, Figure 2 As shown, after the SOC chip completes the startup, it can feedback the startup completion status to the FPGA chip based on the serial communication interface, and notify the FPGA chip that the startup is completed; the FPGA chip can also send a status request to the SOC chip to request to obtain the startup status of the SOC chip. After the SOC chip completes the startup, it can feedback the startup completion status to the FPGA chip based on the status request.

[0072] In some embodiments, the method further includes: after the SOC chip fails to start, the FPGA chip controls the SOC chip to be in a reset state; and the SOC chip re-acquires the SOC firmware for startup.

[0073] For example, when the SOC chip fails to start, it will also feedback the startup failure status to the FPGA chip to notify the FPGA chip to control the reset pin of the SOC chip to put the SOC chip in a reset state; based on the analog storage medium interface of the FPGA chip, after the SOC chip reloads the SOC firmware from the running memory of the FPGA chip, it will start again until the startup is successful.

[0074] like Figure 5 As shown, the schematic diagram of the system startup process provided in the embodiment of the present application is based on the same implementation principle as the above embodiment, which will not be repeated here. The process includes the following steps:

[0075] S51, the FPGA chip loads the bitstream.

[0076] S52, the FPGA chip loads the FPGA software.

[0077] S53, the FPGA chip resets the SOC chip.

[0078] S54, the SOC chip loads the SOC firmware from the FPGA chip.

[0079] S55, whether the SOC chip has completed startup; if not, execute S53 and subsequent steps; if yes, end.

[0080] In some embodiments, the method also includes: the SOC chip receives a firmware update request sent by the host computer and receives the firmware to be updated; the SOC chip sends the firmware to be updated to the FPGA chip through the configuration interface; the FPGA chip transfers the firmware to be updated to the running memory.

[0081] Exemplarily, the SOC chip serves as the interaction medium between the FPGA chip and the host computer, and is responsible for receiving the firmware update request sent by the host computer, as well as the firmware to be updated sent by the host computer, i.e., the new FPGA firmware. The SOC chip transmits the firmware to be updated to the analog storage medium interface of the FPGA chip through the configuration interface (such as SPI / I2C); the FPGA software transfers the firmware to be updated received by the analog storage medium interface to the running memory, and the SOC chip completes the firmware distribution.

[0082] In some embodiments, the method further includes: the FPGA chip verifies the firmware to be updated in the running memory; after the verification is passed, the FPGA chip stores the firmware to be updated to the storage medium; the firmware to be updated is loaded by the FPGA chip at the next startup.

[0083] Exemplarily, the FPGA chip runs the update program and starts to update the FPGA firmware of the storage medium, that is, the FPGA chip solidifies the firmware to be updated (new FPGA firmware) stored in the running memory into the storage medium by running the update program, and refreshes the FPGA firmware in the storage medium. The next time the system starts, the new FPGA firmware is loaded, the system starts, and the new FPGA firmware takes effect.

[0084] The new FPGA firmware (ie, the firmware to be updated) also includes a bit stream and FPGA software, and the data content of the SOC firmware is embedded in the FPGA software.

[0085] Exemplarily, after the firmware to be updated is temporarily stored in the running memory, the firmware to be updated is verified using the MD5 verification method, and after the verification passes, the FPGA firmware of the storage medium is refreshed. The MD5 value of the firmware to be updated is calculated based on the MD5 verification method, and compared with the MD5 value sent by the SOC chip to complete the verification.

[0086] like Figure 6 As shown, a schematic diagram of a firmware update process provided in an embodiment of the present application is provided, and the process includes the following steps:

[0087] S61, the SOC chip receives the firmware data of the host computer and transparently transmits the firmware data to the FPGA chip. The firmware data is the firmware to be updated, that is, the new FPGA firmware.

[0088] S62, the FPGA chip temporarily stores the firmware data and verifies it. The FPGA chip temporarily stores the firmware data in the running memory and verifies the firmware data. After the verification passes, the FPGA firmware in the storage medium is refreshed based on the firmware data.

[0089] S63, check whether it passes. If yes, execute S64; if no, execute S61.

[0090] S64, the FPGA chip refreshes the firmware data in the storage medium. The FPGA chip solidifies the firmware data into the storage medium, that is, deletes the old FPGA firmware in the storage medium, saves the new FPGA firmware, and completes the firmware update. The new FPGA firmware can be loaded when the system is started next time.

[0091] Through the embodiment of the present application, when the system is started and the firmware is updated, the entire system is controlled by the FPGA chip to read and write the storage medium, and there will be no access conflict; and when the system is started, the SOC chip can automatically retry when the startup fails, the SOC chip feedbacks the startup failure to the FPGA chip, the FPGA chip resets the SOC chip, and the SOC chip reloads the SOC firmware to complete the startup, thereby ensuring the complete startup of the entire electronic device and ensuring the stability of the system startup. When the firmware is updated, the firmware to be updated can be stored based on the external DDR of the FPGA chip, and the storage medium flash is written only after the verification is normal, thereby reducing the possibility of damage to the original firmware file due to firmware transmission errors, firmware transmission interruptions, or errors when erasing the storage medium. In addition, when the model of the FPGA chip or SOC chip is updated based on the product iteration requirements, the system startup and firmware update method in the embodiment of the present application can be transplanted, that is, there is no need to consider the differences in the requirements of different FPGA chips or SOC chips for the relative position and storage format of the firmware in the storage medium. The present application can be applied to FPGA chips and SOC chips of different versions and models, and has strong ease of use and applicability.

[0092] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0093] Corresponding to the system startup method provided in the above embodiment, the embodiment of the present application provides a data transmission system. For the sake of convenience of explanation, only the parts related to the embodiment of the present application are shown.

[0094] The data transmission system includes: an FPGA chip, a SOC chip and a storage medium; the FPGA chip is connected to the storage medium for communication, and the SOC chip is connected to the FPGA chip for communication through a configuration interface;

[0095] The FPGA chip is used to load the FPGA firmware in the storage medium for startup;

[0096] The FPGA chip is further used to load the FPGA software in the FPGA firmware after the startup is completed, and store the SOC firmware in the FPGA software in the running memory;

[0097] The SOC chip is used to obtain the SOC firmware in the running memory based on the configuration interface connected to the FPGA chip to complete the startup.

[0098] In one possible implementation, the FPGA chip is also used to load the bit stream in the FPGA firmware and is configured as a programmable system on chip; the FPGA chip is also used to load the FPGA software in the FPGA firmware based on the programmable system on chip to complete startup.

[0099] In a possible implementation, the FPGA chip is further used to control the SOC chip to be in a reset state after completing startup.

[0100] In a possible implementation, the SOC chip is further configured to feed back a startup completion signal to the FPGA chip through the configuration interface after the startup is completed.

[0101] In a possible implementation, the SOC chip is further used to control the SOC chip to be in a reset state after a startup failure by the FPGA chip; the SOC chip is further used to re-acquire the SOC firmware for startup.

[0102] In a possible implementation, the SOC chip is also used to receive a firmware update request sent by a host computer and receive the firmware to be updated; the SOC chip is also used to send the firmware to be updated to the FPGA chip through the configuration interface; the FPGA chip is also used to transfer the firmware to be updated to the running memory.

[0103] In one possible implementation, the FPGA chip is also used to verify the firmware to be updated in the running memory; the FPGA chip is also used to store the firmware to be updated to the storage medium after the verification is passed; the firmware to be updated is loaded by the FPGA chip at the next startup.

[0104] Through the embodiment of the present application, when the system is started and the firmware is updated, the entire system is controlled by the FPGA chip to read and write the storage medium, and there will be no access conflict; and when the system is started, the SOC chip can automatically retry when the startup fails, the SOC chip feedbacks the startup failure to the FPGA chip, the FPGA chip resets the SOC chip, and the SOC chip reloads the SOC firmware to complete the startup, thereby ensuring the complete startup of the entire electronic device and ensuring the stability of the system startup. When the firmware is updated, the firmware to be updated can be stored based on the external DDR of the FPGA chip, and the storage medium flash is written only after the verification is normal, thereby reducing the possibility of damage to the original firmware file due to firmware transmission errors, firmware transmission interruptions, or errors when erasing the storage medium. In addition, when the model of the FPGA chip or SOC chip is updated based on the product iteration requirements, the system startup and firmware update method in the embodiment of the present application can be transplanted, that is, there is no need to consider the differences in the requirements of different FPGA chips or SOC chips for the relative position and storage format of the firmware in the storage medium. The present application can be applied to FPGA chips and SOC chips of different versions and models, and has strong ease of use and applicability.

[0105] Figure 7 A schematic diagram of the hardware structure of the electronic device 7 is shown.

[0106] like Figure 7 As shown, the electronic device 7 of this embodiment includes: at least one processor 70 ( Figure 7 Only one is shown in the figure), a memory 71, in which a computer program 72 that can be run on the processor 70 is stored. When the processor 70 executes the computer program 72, the steps in the above method embodiment are implemented, such as Figure 3 Alternatively, when the processor 70 executes the computer program 72, the functions of the modules / units in the above-mentioned device embodiments are realized.

[0107] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 7. In other embodiments of the present application, the electronic device 7 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0108] The electronic device 7 may include, but is not limited to, a processor 70 and a memory 71. Those skilled in the art will appreciate that Figure 7 It is only an example of the electronic device 7 and does not constitute a limitation of the electronic device 7. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device may also include an input sending device, a network access device, a bus, etc.

[0109] The processor 70 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0110] The processor 70 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 70 is a cache memory. The memory may store instructions or data that the processor 70 has just used or cyclically used. If the processor 70 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 70, and thus improves the efficiency of the system.

[0111] In some embodiments, the memory 71 may be an internal storage unit of the electronic device 7, such as a hard disk or memory of the electronic device 7. The memory 71 may also be an external storage device of the electronic device 7, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 7. Further, the memory 71 may include both an internal storage unit and an external storage device of the electronic device 7. The memory 71 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as program codes of computer programs. The memory 71 may also be used to temporarily store data that has been sent or is to be sent.

[0112] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0113] It should be noted that the structure of the above-mentioned electronic device is only illustrative, and based on different application scenarios, it may also include other physical structures, and the physical structure of the electronic device is not limited here.

[0114] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0115] An embodiment of the present application also provides a chip system, which is applied to an electronic device. The chip system includes one or more processors, and the one or more processors are used to call computer instructions so that the electronic device implements the steps in the above-mentioned method embodiments.

[0116] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0117] An embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0118] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. Computer-readable media may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0119] The devices, electronic devices, chip systems, computer storage media, and computer program products provided in the above-mentioned embodiments of the present application are all used to execute the methods provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding beneficial effects of the methods provided above, and will not be repeated here.

[0120] It should be understood that the above is only to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the embodiments of the present application. According to the above examples given, those skilled in the art can obviously make various equivalent modifications or changes. For example, some steps in each embodiment of the above detection method may be unnecessary, or some steps may be newly added. Or a combination of any two or any multiple embodiments of the above. Such modifications, changes or combined schemes also fall within the scope of the embodiments of the present application.

[0121] It should also be understood that the division of the methods, situations, categories and embodiments in the embodiments of the present application is only for the convenience of description and should not constitute a special limitation. The features of various methods, categories, situations and embodiments can be combined without contradiction.

[0122] It should also be understood that in the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0123] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0124] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0125] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0126] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

[0127] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A system startup method, characterized in that: Applied to a data transmission system, the data transmission system includes an FPGA chip, a SOC chip and a storage medium; the method includes: The FPGA chip loads the FPGA firmware in the storage medium to start up; After the FPGA chip is started up, the FPGA chip loads the FPGA software in the FPGA firmware and stores the SOC firmware in the FPGA software in the running memory; The SOC chip obtains the SOC firmware in the running memory based on the configuration interface connected to the FPGA chip to complete the startup.

2. The method according to claim 1, characterized in that The FPGA chip loads the FPGA firmware in the storage medium to start up, including: The FPGA chip is loaded with the bit stream in the FPGA firmware and configured as a programmable system on chip; The FPGA chip loads the FPGA software in the FPGA firmware based on the programmable system on chip to complete startup.

3. The method according to claim 2, characterized in that The method further comprises: After the FPGA chip is started up, the SOC chip is controlled to be in a reset state.

4. The method according to claim 2, characterized in that: The method further comprises: The FPGA chip loads the FPGA software in the FPGA firmware and configures an analog storage medium interface; the analog storage medium interface is used to provide the SOC firmware to the SOC chip when the SOC chip is started, and the FPGA software includes the SOC firmware.

5. The method according to claim 1, characterized in that The method further comprises: After the SOC chip completes startup, a startup completion signal is fed back to the FPGA chip through the configuration interface.

6. The method according to claim 5, characterized in that The method further comprises: After the SOC chip fails to start, the FPGA chip controls the SOC chip to be in a reset state; The SOC chip re-acquires the SOC firmware for startup.

7. The method according to any one of claims 1 to 6, characterized in that: The method comprises: The SOC chip receives a firmware update request sent by the host computer, and receives the firmware to be updated; The SOC chip sends the firmware to be updated to the FPGA chip through the configuration interface; The FPGA chip transfers the firmware to be updated to the running memory.

8. The method according to claim 7, characterized in that The method further comprises: The FPGA chip verifies the firmware to be updated in the running memory; After the verification is passed, the FPGA chip stores the firmware to be updated in the storage medium; the firmware to be updated is loaded by the FPGA chip at the next startup.

9. A data transmission system, characterized in that: It includes an FPGA chip, a SOC chip and a storage medium; the FPGA chip is connected to the storage medium for communication, and the SOC chip is connected to the FPGA chip for communication via a configuration interface; The FPGA chip is used to load the FPGA firmware in the storage medium for startup; The FPGA chip is further used to load the FPGA software in the FPGA firmware after the startup is completed, and store the SOC firmware in the FPGA software in the running memory; The SOC chip is used to obtain the SOC firmware in the running memory based on the configuration interface connected to the FPGA chip to complete the startup.

10. An electronic device, characterized in that: The electronic device includes at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method described in any one of claims 1 to 8.

11. A chip system, characterized in that: The chip system is applied to an electronic device, and the chip system includes one or more processors, and the one or more processors are used to call computer instructions so that the electronic device executes the method as described in any one of claims 1 to 8.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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