Method and system for processing tasks based on multiple threads

Abstract

The invention discloses a method and a system for processing a task based on multithreading, the method comprises the following steps of: issuing the task to a task queue corresponding to each thread in parallel through multithreading for arbitration, and accurately updating a control register in combination with configuration queue data in a memory, so that the task processing efficiency is improved. All tasks are serially sent to the execution unit for time-sharing processing, so that the occurrence condition of task gaps caused by untimely interrupt response of the processor can be reduced, the performance loss of the processor caused by null and the like is reduced, the resource utilization rate of arithmetic logic is improved, and the performance of the processor is further improved; the register configuration queue data of the tasks are stored in the memory in advance, so that the execution unit can reach the upper limit of hardware performance under the condition of not increasing hardware resources, and the cost is saved while the performance utilization rate of the execution unit is improved; and the coupling degree of the system and the hardware processor is effectively reduced, and the software scheduling overhead of the processor is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a method and system for processing tasks based on multithreading. Background Art

[0002] In common consumer electronics, such as tablets, projectors, and dashcams, there are usually various data processing requirements involved, such as layer overlay, zooming, and rotation. For the main control chip, this type of data processing requirement is generally handed over to the dedicated data processor inside the SoC for execution, and the CPU schedules the data processor to meet the real-time data processing requirements of the operating system. When the SoC chip is performing data processing tasks, it may be unable to respond to the interrupt signal of the data processor in time due to excessive CPU load, resulting in gaps between tasks, causing the performance of the data processor to decline, and ultimately failing to meet the real-time data processing requirements of the operating system.

[0003] In order to reduce the gap between tasks, the current mainstream technical solutions in the industry include using dual control registers (ping-pong registers) to enable software to configure the next task in advance to reduce the gap between tasks, or Figure 1 A schematic diagram of the structure of a synchronous multi-threaded processor disclosed, such as Figure 1 As shown, the first pipeline control unit and the second pipeline control unit, i.e., two sets of pipeline control units, are instantiated to schedule the first dedicated execution unit, the second dedicated execution unit, i.e., two sets of dedicated execution units and an independent shared execution unit to reduce task gaps.

[0004] However, practice has found that both of these technical solutions will increase hardware resource overhead and the degree of coupling between the system and hardware, and the increased cost does not bring about an increase in the upper limit of hardware performance. Therefore, it is urgent to propose a technical solution on how to save hardware resources (such as area and cost) while reducing task gaps. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a method and system for processing tasks based on multithreading, which can reduce task gaps and save hardware resources at the same time.

[0006] In order to solve the above technical problems, the first aspect of the embodiment of the present invention discloses a method for processing tasks based on multi-threading, the method is applied to a data processing system, the data processing system includes a thread control register and a task manager, the number of threads between the thread control register and the task manager is greater than 1, all the threads do not interfere with each other, each thread has a unique corresponding command queue and a unique corresponding task queue, the method includes:

[0007] The task manager obtains the target task in the command queue corresponding to the thread from the thread control register through each of the threads, and stores each of the target tasks in the task queue matching the thread corresponding to the target task;

[0008] The task manager arbitrates all target tasks in all the task queues to obtain an arbitration result, and determines the configuration parameters corresponding to each of the target tasks according to the arbitration result and the configuration queue data stored in the predetermined storage space;

[0009] The configuration parameters of each target task are used as a basis for executing processing on the data corresponding to the target task.

[0010] As an optional implementation, in the first aspect of the present invention, the task manager determines the configuration parameters corresponding to each of the target tasks according to the arbitration result and the configuration queue data stored in the predetermined storage space, including:

[0011] The task manager determines the header information corresponding to each of the target tasks according to the arbitration result;

[0012] The task manager analyzes the header information corresponding to each of the target tasks and the configuration queue data stored in a predetermined storage space to obtain configuration parameters that match the header information, and determines that the configuration parameters that match the header information are the configuration parameters corresponding to the target task that matches the header information.

[0013] As an optional implementation, in the first aspect of the present invention, the data processing system further includes a command queue parser;

[0014] The task manager determines the header information corresponding to each of the target tasks according to the arbitration result, including:

[0015] The task manager selects, according to the arbitration result, a target task from all target tasks in all the task queues that have not executed data processing operations as the current target task;

[0016] The task manager generates a task start signal according to the current target task, and sends the task start signal to the command queue parser, wherein the task start signal carries the current target task;

[0017] The command queue parser determines the header information corresponding to the current target task according to the task start signal.

[0018] As an optional implementation, in the first aspect of the present invention, each of the target tasks includes at least one command, and the header information corresponding to each of the target tasks includes the header address of the command ranked first among all the commands of the target task and the header length of the next command corresponding to each of the commands;

[0019] The command queue parser determines the header information corresponding to the current target task according to the task start signal, including:

[0020] For any of the current target tasks, for the command ranked first in the current target task, the command queue parser parses the task start signal to obtain the header address corresponding to the command and the header length of the next command corresponding to each of the commands; for the commands not ranked first in the current target task, the header address corresponding to the command is determined based on the header length address corresponding to the previous command and the header length of the next command corresponding to the previous command.

[0021] As an optional implementation, in the first aspect of the present invention, the data processing system further includes a data processor;

[0022] The method further comprises:

[0023] The command queue parser performs a configuration operation on a control register of the data processor according to a configuration parameter corresponding to each of the target tasks;

[0024] After the control registers of the data processor are configured, the command queue parser controls the execution unit of the data processor to execute the data processing operation matching the target task according to the configuration parameters corresponding to each target task.

[0025] As an optional implementation, in the first aspect of the present invention, the command queue parser controls the execution unit of the data processor to perform a data processing operation matching the target task according to the configuration parameters corresponding to each target task, including:

[0026] The command queue parser sends a start signal of the current command of the current target task to the execution unit of the data processor;

[0027] The execution unit receives a start signal of the current command, switches the current state to a working state according to the start signal of the current command, and processes data corresponding to the current command according to current configuration parameters configured by the control register; when the data corresponding to the current command is processed, sends a processing completion signal of the current command to the command queue parser;

[0028] The command queue parser receives a processing completion signal of the current command, and switches the current state to a working state according to the processing completion signal of the current command. After switching to the working state, it determines whether the current command is the last command in the current target task according to the header length of the next command of the current command. When the judgment result is no, the next command is updated to the current command, and the operation of sending the start signal of the current command to the execution unit of the data processor is repeated until the data corresponding to the last command in the current target task is processed.

[0029] As an optional embodiment, in the first aspect of the present invention, the method further comprises:

[0030] When the data corresponding to the last command in the current target task is processed, the command queue parser sends a task end signal of the current target task to the task manager;

[0031] The task manager receives a task end signal of the current target task, and selects the target task that is currently ranked first from all target tasks that have not executed data processing operations in all the task queues according to the arbitration result as the next target task;

[0032] The task manager updates the next target task to the current target task, and re-executes the operation of generating a task start signal according to the current target task until the data corresponding to the last target task in all target tasks in the command queue corresponding to the task manager is processed.

[0033] As an optional implementation, in the first aspect of the present invention, the data processing system further includes an interrupt manager;

[0034] The method further comprises:

[0035] The interrupt manager determines whether there is a thread among all the threads that has completed the execution of all the target tasks, and when the determination result is yes, the interrupt flag bit of the thread is raised;

[0036] Each of the threads has a unique corresponding register command queue head address and a unique corresponding interrupt flag bit.

[0037] A second aspect of an embodiment of the present invention discloses a system for processing tasks based on multithreading, the system comprising a thread control register and a task manager, the number of threads between the thread control register and the task manager is greater than 1, all the threads do not interfere with each other, each thread has a unique corresponding command queue and a unique corresponding task queue, wherein:

[0038] The task manager is used to obtain, through each of the threads, a target task in a command queue corresponding to the thread from the thread control register, and store each of the target tasks in a task queue matching the thread corresponding to the target task;

[0039] The task manager is further used to arbitrate all target tasks in all the task queues to obtain an arbitration result, and determine the configuration parameters corresponding to each of the target tasks according to the arbitration result and the configuration queue data stored in the predetermined storage space;

[0040] The configuration parameters of each target task are used as a basis for executing processing on the data corresponding to the target task.

[0041] As an optional implementation, in the second aspect of the present invention, the task manager determines the configuration parameters corresponding to each of the target tasks according to the arbitration result and the configuration queue data stored in the predetermined storage space in a specific manner including:

[0042] Determine the header information corresponding to each target task according to the arbitration result;

[0043] The header information corresponding to each of the target tasks and the configuration queue data stored in the predetermined storage space are analyzed to obtain configuration parameters matching the header information, and the configuration parameters matching the header information are determined to be the configuration parameters corresponding to the target task matching the header information.

[0044] As an optional implementation, in the second aspect of the present invention, the data processing system further includes a command queue parser;

[0045] The specific manner in which the task manager determines the header information corresponding to each target task according to the arbitration result includes:

[0046] According to the arbitration result, a target task from all target tasks that have not performed data processing operations in all the task queues is selected as the current target task, and a task start signal is generated based on the current target task, and the task start signal is sent to the command queue parser. The task start signal carries the current target task to trigger the command queue parser to determine the header information corresponding to the current target task according to the task start signal.

[0047] As an optional implementation, in the second aspect of the present invention, each of the target tasks includes at least one command, and the header information corresponding to each of the target tasks includes the header address of the command ranked first among all the commands of the target task and the header length of the next command corresponding to each of the commands;

[0048] The specific manner in which the command queue parser determines the header information corresponding to the current target task according to the task start signal includes:

[0049] For any of the current target tasks, for the command ranked first in the current target task, the task start signal is parsed to obtain the header address corresponding to the command and the header length of the next command corresponding to each of the commands; for the commands not ranked first in the current target task, the header address corresponding to the command is determined based on the header length address corresponding to the previous command and the header length of the next command corresponding to the previous command.

[0050] As an optional implementation, in the second aspect of the present invention, the data processing system further includes a data processor;

[0051] The command queue parser is further used to perform configuration operations on the control register of the data processor according to the configuration parameters corresponding to each of the target tasks;

[0052] The command queue parser is further used to control the execution unit of the data processor to perform data processing operations matching the target task according to the configuration parameters corresponding to each target task after the control register of the data processor is configured.

[0053] As an optional implementation, in the second aspect of the present invention, the command queue parser controls the execution unit of the data processor to perform the data processing operation matching the target task according to the configuration parameters corresponding to each target task, including:

[0054] Sending a start signal of the current command of the current target task to the execution unit of the data processor to trigger the execution unit to receive the start signal of the current command, and switching the current state to the working state according to the start signal of the current command, and processing the data corresponding to the current command according to the current configuration parameters configured by the control register; when the data corresponding to the current command is processed, sending a processing completion signal of the current command to the command queue parser;

[0055] Receive a processing completion signal of the current command, and switch the current state to a working state according to the processing completion signal of the current command; after switching to the working state, determine whether the current command is the last command in the current target task according to the header length of the next command of the current command; when the determination result is no, update the next command to the current command, and repeat the operation of sending the start signal of the current command to the execution unit of the data processor until the data corresponding to the last command in the current target task is processed.

[0056] As an optional implementation, in the second aspect of the present invention, the command queue parser is further used to send a task end signal of the current target task to the task manager after the data corresponding to the last command in the current target task is processed;

[0057] The task manager is further used to receive a task end signal of the current target task, and select the target task that is currently ranked first from all target tasks that have not performed data processing operations in all the task queues according to the arbitration result as the next target task;

[0058] The task manager is also used to update the next target task to the current target task, and re-execute the operation of generating a task start signal based on the current target task until the data corresponding to the last target task in all target tasks in the command queue corresponding to the task manager is processed.

[0059] As an optional implementation, in the second aspect of the present invention, the data processing system further includes an interrupt manager;

[0060] The interrupt manager is used to determine whether there is a thread among all the threads that has completed the execution of all the target tasks, and when the determination result is yes, the interrupt flag bit of the thread is raised;

[0061] Each of the threads has a unique corresponding register command queue head address and a unique corresponding interrupt flag bit.

[0062] The third aspect of the present invention discloses another system for processing tasks based on multithreading, the system comprising:

[0063] A memory storing executable program code;

[0064] a processor coupled to the memory;

[0065] The processor calls the executable program code stored in the memory to execute part or all of the steps in any one of the methods for processing tasks based on multi-threading disclosed in the first aspect of the present invention.

[0066] The fourth aspect of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute some or all of the steps in any method for processing tasks based on multi-threading disclosed in the first aspect of the present invention.

[0067] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0068] In an embodiment of the present invention, a method and system for processing tasks based on multi-threading are disclosed. The method is applied to a data processing system, and the data processing system includes a thread control register and a task manager. The number of threads between the thread control register and the task manager is greater than 1, and all threads do not interfere with each other. Each thread has a unique corresponding command queue and a unique corresponding task queue. The method includes: the task manager obtains the target task in the command queue corresponding to the thread from the thread control register through each thread, and stores each target task in the task queue matching the thread corresponding to the target task; the task manager arbitrates all target tasks in all task queues to obtain an arbitration result, and determines the configuration parameters corresponding to each target task according to the arbitration result and the configuration queue data stored in the predetermined storage space; wherein the configuration parameters of each target task are used as the basis for executing processing on the data corresponding to the target task. It can be seen that the embodiment of the present invention obtains corresponding tasks from the thread control register through multiple threads, that is, multiple threads send tasks to the task queue corresponding to each thread in parallel, arbitrates the tasks in the task queue corresponding to each thread, and then accurately determines the configuration parameters of the corresponding control register according to the arbitration result and the configuration queue data in the memory storage space to update the control register, that is, all tasks are sent serially to the execution unit for time-sharing processing, which can reduce the occurrence of task gaps caused by untimely processor interrupt response, thereby reducing the performance loss of the processor due to idle waiting, improving the resource utilization of the operation logic, and thus improving the processor performance; and by providing By storing the register configuration parameters of multiple tasks in the internal storage space, the execution unit of the data processor can reach the upper limit of hardware performance without increasing hardware resources (such as hardware area), thereby improving the performance utilization of the execution unit and saving costs; and reducing the inability to respond to interrupts due to the processor CPU being busy at a certain moment or the processor CPU being idle at a certain moment, but the previous level of hardware has not yet completed processing, resulting in the next target task having no input source data, reducing the waiting time of the execution unit in a single thread, improving the processing performance of the execution unit, effectively reducing the coupling degree between the operating system and the hardware processor, and reducing the software scheduling overhead of the CPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0070] Figure 1 It is a structural diagram of a synchronous multi-threaded processor disclosed in the prior art;

[0071] Figure 2 It is a schematic diagram of a system architecture for processing tasks based on multithreading disclosed in an embodiment of the present invention;

[0072] Figure 3 It is a flowchart of a method for processing tasks based on multithreading disclosed in an embodiment of the present invention;

[0073] Figure 4 It is a schematic diagram of a structure for configuring queue data in a storage space disclosed in an embodiment of the present invention;

[0074] Figure 5 It is a structural diagram of a thread instantiation disclosed in an embodiment of the present invention;

[0075] Figure 6 It is a processing timing diagram of sending subtasks to execution units in parallel through multiple threads disclosed in an embodiment of the present invention;

[0076] Figure 7 It is a structural diagram of configuration queue data of a chain structure disclosed in an embodiment of the present invention;

[0077] Figure 8 It is a schematic diagram of the architecture of a task manager and a thread control register disclosed in an embodiment of the present invention;

[0078] Fig. 9 It is a flow chart of a control state machine of a task manager disclosed in an embodiment of the present invention;

[0079] Fig.10 It is a working sequence diagram of a command queue parser disclosed in an embodiment of the present invention;

[0080] Fig.11 It is a schematic diagram of the architecture of a multi-threaded multi-tasking structure disclosed in an embodiment of the present invention;

[0081] Fig.12 It is a schematic diagram of the architecture of another multi-threaded multi-tasking structure disclosed in an embodiment of the present invention;

[0082] Fig.13It is a structural diagram of a system for processing tasks based on multithreading disclosed in an embodiment of the present invention;

[0083] Fig.14 It is a structural diagram of another system for processing tasks based on multithreading disclosed in an embodiment of the present invention;

[0084] Fig.15 It is a structural diagram of another system for processing tasks based on multithreading disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0085] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0086] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or equipment that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or equipment.

[0087] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0088] The present invention discloses a method and system for processing tasks based on multi-threading, which can obtain corresponding tasks from thread control registers through multiple threads, that is, multiple threads send tasks to the task queue corresponding to each thread in parallel, arbitrate the tasks in the task queue corresponding to each thread, and then accurately determine the configuration parameters of the corresponding control register according to the arbitration result and the configuration queue data in the memory storage space to update the control register, that is, send all tasks serially to the execution unit for time-sharing processing, which can reduce the occurrence of task gaps caused by untimely processor interrupt response, thereby reducing the performance loss of the processor due to idle waiting, improving the resource utilization of the operation logic, and thus improving the processing The invention improves the processor performance; and by storing the register configuration parameters of multiple tasks in the internal storage space in advance, the execution unit of the data processor can reach the upper limit of the hardware performance without increasing the hardware resources (such as the hardware area), thereby improving the performance utilization of the execution unit and saving costs; and reduces the inability to respond to interrupts due to the processor CPU being busy at a certain moment or the processor CPU being idle at a certain moment, but the previous level of hardware has not yet completed the processing, resulting in the next target task having no input source data, reducing the waiting time of the execution unit in a single thread to improve the processing performance of the execution unit, effectively reducing the coupling degree between the operating system and the hardware processor, and reducing the software scheduling overhead of the CPU.

[0089] In order to better understand the method and system for processing tasks based on multithreading described in the present invention, firstly, the system architecture applicable to the method for processing tasks based on multithreading is described. Specifically, the system architecture can be as follows Figure 2 As shown, Figure 2 Schematic diagram of a system architecture for processing tasks based on multithreading disclosed in an embodiment of the present invention. Figure 2As shown, the system architecture may include a thread control register, a task manager, a command queue parser and a data processor, wherein the data processor includes a control register and an execution unit, and the storage space is used to store configuration queue data, and the configuration queue data is used to configure the data processor, specifically to configure the control register of the data processor. Furthermore, the storage space is also used to store data to be processed (such as images) and processed data. The command queue parser and the execution unit interact with the storage space through the memory bus, and the thread control register obtains tasks from the processor CPU through the register configuration bus, and sends the corresponding tasks to the task queue of the task manager in parallel through 4 threads. The task manager arbitrates all tasks in all task queues, obtains arbitration results, and selects a task from all tasks that have not performed data processing operations in all task queues as the current task according to the arbitration results; and generates a task start signal according to the current task, and sends the task start signal to the command queue parser, and the task start signal carries the current task; for any current task, for the command ranked first in the current task, the command queue parser parses the task start signal, Get the header address corresponding to the command and the header length of the next command corresponding to each command; for the command that is not ranked first in the current target task, determine the header address corresponding to the command according to the header length address corresponding to the previous command and the header length of the next command corresponding to the previous command, and search the corresponding configuration parameters from the storage space according to the header address corresponding to the command, and perform configuration operations on the control register of the data processor; after the control register of the data processor is configured, the execution unit of the data processor performs data processing operations that match the command of the current task, and after processing the data corresponding to the current task, continue to determine the next task as the current task according to the arbitration result, and repeat the above operations until the data corresponding to all tasks are processed. Among them, if there is a thread whose data of all tasks has been processed, an interrupt signal will be sent to the processor CPU to pull up the flag bit of the thread.

[0090] It should be noted that Figure 2 The system architecture shown is only for the purpose of representing a system applicable to the method of processing tasks based on multithreading. All units involved are only schematically presented. The specific structure / size / shape / location / installation method can be adaptively adjusted according to the actual system. Figure 2 The system architecture shown is not limiting in this regard.

[0091] The above describes a system to which the method for processing tasks based on multithreading is applicable. The following describes in detail the method and system for processing tasks based on multithreading.

[0092] Embodiment 1

[0093] See also Figure 3 , Figure 3 The present invention discloses a method for processing tasks based on multithreading. The method can be applied to a data processing system, and the data processing system includes a thread control register and a task manager. The number of threads between the thread control register and the task manager is greater than 1. All threads do not interfere with each other. Each thread has a unique corresponding command queue Cmd-queue and a unique corresponding task queue. Figure 3 As shown, the method for processing tasks based on multithreading may include the following operations:

[0094] 101. The task manager obtains the target task in the command queue corresponding to each thread from the thread control register through each thread, and stores each target task in the task queue matching the thread corresponding to the target task.

[0095] In the embodiment of the present invention, the thread control register obtains the target task from the processor and stores it in the corresponding command queue, and then sends the target task to the task queue of the task manager through the thread corresponding to the command queue. Each task queue can store at least one target task.

[0096] 102. The task manager arbitrates all target tasks in all task queues, obtains an arbitration result, and determines the configuration parameters corresponding to each target task based on the arbitration result and the configuration queue data stored in a predetermined storage space; wherein the configuration parameters of each target task are used as a basis for executing processing on the data corresponding to the target task.

[0097] In an embodiment of the present invention, optionally, all target tasks in all task queues are arbitrated, which can be understood as arbitrating all target tasks in all task queues. For example, when target tasks from different task queues come out of the corresponding task queues at the same time, all target tasks coming out at the same time are arbitrated, which can also be understood as arbitrating all task queues. For example, after arbitration, all target tasks in task queue 1 are processed first, and when the processing is completed, all target tasks in task queue 2 are processed.

[0098] In an embodiment of the present invention, optionally, the configuration queue data is composed of the data of each header among multiple headers and the data of the main block uniquely corresponding to the header; for any header, the data of the header includes the starting address of the main block uniquely corresponding to the header, the length of the main block, the base address offset of the control register that needs to be updated corresponding to the main block, the header length of the next command and the update flag of the control register; the data of each main block includes the address offset of the control register that needs to be updated and the data in all main blocks are continuous; each header is used to address and parse the main block uniquely corresponding to the header, and the data of each main block is used to perform an update operation on the address offset of the control register, and the storage space occupied by all main blocks in the storage space includes continuous storage space and / or non-continuous storage space. Figure 4 As shown, Figure 4 is a schematic diagram of a structure for configuring queue data in a storage space disclosed in an embodiment of the present invention, such as Figure 4As shown, each header consists of the starting address Body_Block_Start_Address of the body block that the header uniquely corresponds to, the length of the body block Body_Block_Length, in bytes, the base address offset Register_Offset of the control register that needs to be updated corresponding to the body block, the header length Next_Cmd_Head_Length of the next command, and the update flag Dirty of the control register. Each header occupies 128 bits, 4 32 bits, of which the starting address is used for the header to address in the storage space, the header length of the next command, the high 24 bits of the 4th 32 bits, when this value is equal to 0, it means that there is no next command, and the command is the last one in the queue, and when this value is greater than 0, it means that there is a next command. The update flag, bit0 of the 4th 32 bits, is 1, indicating that the control register corresponding to Register_Offset needs to be updated to the value in body_block, that is, the value of the control register Register Value; if it is 0, it means that no update is required. The address offsets stored in the body block body_block are each 32 bits, and the memory address and length of the body block are obtained from the corresponding header, and the control register of the corresponding offset address in the data processor is incrementally and continuously updated according to the base address offset in the header, and the updated value is the data in the body block body_block, and Body_Block_Length is continuously updated, each time updating 32 bits. In this way, by storing the configuration data of the control register in blocks and configuring the corresponding address for addressing analysis, the control register can skip the register address segment that does not need to be updated, and realize non-continuous update, which ensures the accuracy of the control register update while improving the update efficiency of the control register, which is conducive to further reducing the occurrence of task gaps. Among them, the storage space can be integrated in the data processing system or independent of the data processing system.

[0099] In the embodiment of the present invention, further, the head address Head_address and the head length Head_length of the corresponding register command queue are instantiated for each thread in the top-level thread control register, and are configured by the processor. Figure 5 As shown, Figure 5 is a schematic diagram of a thread instantiation structure disclosed in an embodiment of the present invention, such as Figure 5As shown, there are four threads, Cmdline0, Cmdline1, Cmdline2, and Cmdline3. Each thread instantiates the head address Head_address and head length Head_length of the corresponding register command queue. Each thread points to a different address segment in the storage space. Each target task carries the address segment of the corresponding thread. The hardware retrieves the corresponding configuration parameter, namely Register Value, through the address segment. And Figure 6 is a processing timing diagram of sending subtasks to execution units in parallel through multiple threads disclosed in an embodiment of the present invention, such as Figure 6 As shown, there are 4 threads in total, namely, thread Cmdline0, thread Cmdline1, thread Cmdline2, and thread Cmdline3. Among them, thread Cmdline0 issues 3 subtasks, namely, subtask 1 (including 3 commands, Cmd0, Cmd1, and Cmd3), subtask 2 (including 2 commands, Cmd3 and Cmd4), and subtask 3 (including 2 commands, Cmd5 and Cmd6); thread Cmdline1 issues 4 subtasks, namely, subtask 4 (including 2 commands, Cmd7 and Cmd8), subtask 5 (including 1 command, Cmd9), subtask 6 (including 1 command, Cmd10), and subtask 7 (including 2 commands, Cmd11 and Cmd12); thread Cmdline2 issues 3 subtasks, namely, subtask 8 (including 2 commands, Cmd13 1 command), subtask nine (including 2 commands Cmd14 and Cmd15) and subtask ten (including 3 commands Cmd16, Cmd17 and Cmd18); thread Cmdline3 issues 3 subtasks, namely subtask eleven (including 2 commands Cmd19 and Cmd20), subtask twelve (including 3 commands Cmd21, Cmd22 and Cmd23) and subtask thirteen (including 2 commands Cmd24 and Cmd25). The subtasks issued by each thread will first enter the corresponding task queue for queueing. After arbitration, an arbitration queue sequence is formed: subtask one, subtask four, subtask eight, subtask eleven, subtask two, subtask five, subtask nine, subtask twelve... Then it is sent to the execution unit for processing. The execution unit continuously processes tasks from different threads. From the perspective of a single processor, the time points at which each thread issues tasks are scattered, and the task gaps still exist. However, after the arbitrator of the task manager interweaves the tasks of different threads, the task gaps disappear for the execution unit. It can be seen that using a multi-threaded architecture to balance the load to the processor CPU effectively reduces the task gaps of the execution unit, reduces the performance loss caused by the execution unit waiting in vain, and maximizes the hardware performance of the execution unit.

[0100] It can be seen that implementation Figure 3The described method for processing tasks based on multi-threading obtains corresponding tasks from thread control registers through multiple threads, that is, multiple threads send tasks to the task queue corresponding to each thread in parallel, arbitrates the tasks in the task queue corresponding to each thread, and then accurately determines the configuration parameters of the corresponding control register according to the arbitration result and the configuration queue data in the memory storage space to update the control register, that is, all tasks are sent serially to the execution unit for time-sharing processing, which can reduce the occurrence of task gaps caused by untimely processor interrupt response, thereby reducing the performance loss of the processor due to idle waiting, improving the resource utilization of the operation logic, and thus improving the processor performance; By storing the register configuration parameters of multiple tasks in the internal storage space in advance, the execution unit of the data processor can reach the upper limit of hardware performance without increasing hardware resources (such as hardware area), thereby improving the performance utilization of the execution unit and saving costs; and reducing the inability to respond to interrupts due to the processor CPU being busy at a certain moment or the processor CPU being idle at a certain moment, but the previous level of hardware has not yet completed processing, resulting in the next target task having no input source data, reducing the waiting time of the execution unit in a single thread to improve the processing performance of the execution unit, effectively reducing the degree of coupling between the operating system and the hardware processor, and reducing the software scheduling overhead of the CPU.

[0101] In the embodiment of the present invention, optionally, the task manager determines the configuration parameters corresponding to each target task according to the arbitration result and the configuration queue data stored in the predetermined storage space, including:

[0102] The task manager determines the header information corresponding to each target task based on the arbitration result;

[0103] The task manager analyzes the header information corresponding to each target task and the configuration queue data stored in the predetermined storage space to obtain the configuration parameters matching the header information, and determines the configuration parameters matching the header information as the configuration parameters corresponding to the target task matching the header information.

[0104] In the embodiment of the present invention, further optionally, the data processing system further includes a command queue parser; and the task manager determines the header information corresponding to each target task according to the arbitration result, including:

[0105] The task manager selects a target task from all target tasks that have not executed data processing operations in all task queues as the current target task according to the arbitration result;

[0106] The task manager generates a task start signal according to the current target task, and sends the task start signal to the command queue parser, where the task start signal carries the current target task;

[0107] The command queue parser determines the header information corresponding to the current target task based on the task start signal.

[0108] It can be seen that the embodiment of the present invention can accurately determine the configuration parameters corresponding to the task by analyzing the arbitration result and the configuration queue data stored in the storage space; and by analyzing the arbitration result of the task to generate a task start signal for the current task, thereby analyzing it to achieve efficient and accurate determination of the header information corresponding to the current task; and after the data corresponding to all commands of the current task are processed, the self-starting task manager determines the next task from the existing task queue as soon as possible for processing, without waiting for the interrupt response of the processor CPU, thereby reducing the task gap and improving the execution performance of the execution unit; and according to the arbitration result of the task, selecting the next task can improve the accuracy and efficiency of determining the next task, which is conducive to further reducing the gap between tasks and further improving the execution performance of the execution unit.

[0109] In the embodiment of the present invention, further optionally, each target task includes at least one command, and the header information corresponding to each target task includes the header address of the command ranked first among all commands of the target task and the header length of the next command corresponding to each command;

[0110] The command queue parser determines the header information corresponding to the current target task based on the task start signal, including:

[0111] For any current target task, for the command ranked first in the current target task, the command queue parser parses the task start signal to obtain the header address corresponding to the command and the header length of the next command corresponding to each command; for the command not ranked first in the current target task, the header address corresponding to the command is determined based on the header length address corresponding to the previous command and the header length of the next command corresponding to the previous command.

[0112] In the embodiment of the present invention, optionally, the header of each command includes the header length Next_Cmd_Head_Length (NCHL) of the next command. This information is used to indicate the number of Head_blocks of the next command. When the NCHL information is 0, it indicates that the current command is the last one. When the NCHL information is greater than 0, it indicates that the current command is not the last one. Thanks to the addition of the NCHL information, the Head_block of the next command can be addressed at the end of the previous command. Therefore, the Head_block can be made into a chain structure to realize the function of the command queue, such as Figure 7 As shown, Figure 7 is a schematic diagram of a chain-structured configuration queue data disclosed in an embodiment of the present invention, such as Figure 7 As shown in the figure, the Head_address and Head_length of command Cmd0 come from the top-level thread control register and are initialized and configured by the processor CPU. Since the Head data is stored continuously in the memory, the Head_address corresponding to each command can be calculated, and the Head_length is recorded in the NCHL information of the previous command. Therefore, the calculation formula of the Head_address of each command is as follows:

[0113] cmd1_Head_address=cmd0_Head_address+cmd0_Head_length;

[0114] cmd2_Head_address=cmd1_Head_address+cmd1_Head_length(cmd0_NCHL);

[0115] cmd3_Head_address=cmd2_Head_address+cmd2_Head_length(cmd1_NCHL);

[0116] …

[0117] And so on.

[0118] Since the memory address of the body_block is recorded in the Head_block information, multiple body_blocks can use a continuous piece of memory or multiple scattered pieces of memory in the storage space, such as Figure 7 As shown, by storing the main block in a continuous or fragmented manner, the storage flexibility of the main block data is improved, and the utilization rate of the fragmented memory of the storage space is improved.

[0119] It can be seen that this optional embodiment determines the header information of the next command by combining the header information of the previous command, that is, through the header information relationship between two adjacent commands, the header information of each command is accurately and efficiently determined.

[0120] In an optional embodiment, the data processing system further includes a data processor; and the method may further include the following steps:

[0121] The command queue parser performs configuration operations on the control registers of the data processor according to the configuration parameters corresponding to each target task;

[0122] After the control registers of the data processor are configured, the command queue parser controls the execution unit of the data processor to execute the data processing operation matching the target task according to the configuration parameters corresponding to each target task.

[0123] In the embodiment of the present invention, the data processing operation corresponds to the type of the data processor. When the data processor is an image processor, the data processing operation includes an image processing operation, and further, may also include a data processing operation; when the data processor is a non-image processor, the data processing operation includes a non-image processing operation.

[0124] In an embodiment of the present invention, the command queue parser performs configuration operations on the control registers of the data processor according to the configuration parameters corresponding to each command of each target task, and after the configuration is completed, controls the execution unit of the data processor to perform data processing operations matching the command according to the configuration parameters corresponding to the command.

[0125] In this optional embodiment, optionally, the command queue parser controls the execution unit of the data processor to perform a data processing operation matching the target task according to the configuration parameters corresponding to each target task, including:

[0126] The command queue parser sends a start signal of the current command of the current target task to the execution unit of the data processor;

[0127] The execution unit receives the start signal of the current command, switches the current state to the working state according to the start signal of the current command, and processes the data corresponding to the current command according to the current configuration parameters configured by the control register; when the data corresponding to the current command is processed, a processing completion signal of the current command is sent to the command queue parser;

[0128] The command queue parser receives a signal indicating that the current command has been processed, and switches the current state to a working state based on the signal indicating that the current command has been processed. After switching to the working state, it determines whether the current command is the last command in the current target task based on the header length of the next command of the current command. When the result of the determination is no, the next command is updated to the current command, and the above-mentioned operation of sending a start signal of the current command to the execution unit of the data processor is performed again until the data corresponding to the last command in the current target task is processed.

[0129] In the embodiment of the present invention, Figure 8 is a schematic diagram of the architecture of a task manager and a thread control register disclosed in an embodiment of the present invention, Fig. 9 is a flow chart of a control state machine of a task manager disclosed in an embodiment of the present invention, Figure 8 , 9As shown, the thread control register includes command queues, specifically 4 command queues, each command queue corresponds to a thread and is connected to the task queue in the task manager through the thread, and each task queue can store multiple tasks. The arbitrator of the task manager arbitrates all tasks in all task queues to determine the current task. If the control state machine of the task manager is in the idle IDLE state, it continuously detects the current task output of the arbitrator, generates a task start signal Task_start, and starts the command queue parser at the same time. The command queue parser analyzes the task start signal to obtain the header information of the task, and queries the offset address of the corresponding main block to configure the parameters of the control register. After the configuration is completed, a start signal Cmd_start is generated to start the execution unit. When the execution unit processes the data corresponding to the current command, it sends a processing completion signal Cmd_end to the command queue parser to determine whether the NCHL (Next_Cmd_Head_Length) information at the end of the current command chain is equal to 0. If the NCHL information is not equal to 0, the head address Head_address and head length Head_length of the next command are calculated according to the value of NCHL, and then the command queue parser is started to repeat the above process to execute the next command. If the NCHL information is equal to 0, it means that the last command in the command queue has been processed and a task end signal Task_end is generated. At this time, the state of the control state machine jumps back to IDLE and continues to detect the task output of the task queue.

[0130] It can be seen that after obtaining the configuration parameters corresponding to the task, this optional embodiment updates the control register, thereby controlling the execution unit to perform the corresponding data processing operation on the task. Without increasing the control register, it can reduce the occurrence of task gaps caused by the untimely response of the processor interrupt, thereby reducing the performance loss of the processor due to waiting, improving the resource utilization of the operation logic, and thus improving the processor performance; and through the self-starting hardware, the data between two adjacent commands is processed without the need for the processor CPU to schedule, so that no command gaps will be generated due to the untimely response of the processor CPU to the interrupt, thereby effectively improving the utilization of the execution unit.

[0131] In another optional embodiment, the method may further include the following steps:

[0132] When the data corresponding to the last command in the current target task is processed, the command queue parser sends a task end signal of the current target task to the task manager;

[0133] The task manager receives the task end signal of the current target task, and according to the arbitration result, selects the target task that is currently ranked first from all target tasks that have not executed data processing operations in all task queues as the next target task;

[0134] The task manager updates the next target task as the current target task, and re-executes the above operation of generating a task start signal according to the current target task, until the data corresponding to the last target task in all target tasks in the command queue corresponding to the task manager is processed.

[0135] In this optional embodiment, Fig.10 is a working sequence of a command queue parser disclosed in an embodiment of the present invention, such as Fig.10As shown, at time T0, the task manager sends a task to the command queue parser, and sends the task start signal Task_start and the command queue head address Head_address and head length Head_length. At this time, the command queue parser enters the working state, retrieves the data of the head Head and the data of the body block body from the storage space to configure the control register. At time T1, when the configuration of the control memory corresponding to the command Cmd0 is completed, the command queue parser sends a start signal Cmd_statr to the execution unit, and then the execution unit enters the working state from the idle state, processes the data of the command Cmd0 according to the address offset of the current control register, repeatedly reads and writes data input data from the storage space and inputs the written data output data into the memory space; at time T2, after the data processing corresponding to the command Cmd0 is completed, the execution unit outputs the processing completion signal Cmd_end to start the command queue parser, and the command queue parser retrieves the data of the header Head of the command Cmd1 and the data of the body block body according to the NCHL information at the end of the command Cmd0 chain to configure the control register; at time T3, after the configuration of the command Cmd1 is completed, the start signal Cmd_s is output. At time T4, the execution unit starts the data processing of command Cmd1; at time T4, after the processing of command Cmd1 is completed, the execution unit outputs the processing completion signal Cmd_end, and the command queue parser starts again, and according to the NCHL information at the end of the command Cmd1 chain, retrieves the data of the header Head and the body of the command Cmd2, and configures the control register; at time T5, the command queue parser sends the start signal Cmd_start, and the execution unit starts the data processing of command Cmd2; at time T6, after the execution of command Cmd2 is completed, the processing completion signal Cmd_end is output. At this time, the NCHL information at the end of the Cmd2 chain in the command queue parser is 0, indicating that command Cmd2 is the last command in the command queue, and then the task end signal Task_end is output to notify the task manager that the task it has issued has been completed.

[0136] It should be noted that the time taken by the command queue parser to configure the control registers is very short and negligible compared to the time taken by the execution unit to process a command. Fig.10 In order to allow technicians in this field to more clearly understand the various processes of task processing, the proportion of the working time of the command queue parser is lengthened. In actual hardware, Cmd0, Cmd1, and Cmd2 can be considered to work continuously.

[0137] It can be seen that after the optional embodiment completes processing of the data corresponding to all commands of the current task, the self-starting task manager determines the next task from the existing task queue as soon as possible for processing, without waiting for the interrupt response of the processor CPU, thereby reducing the task gap and improving the execution performance of the execution unit; and selecting the next task based on the arbitration result of the task can improve the accuracy and efficiency of determining the next task, which is conducive to further reducing the gap between tasks and improving the execution performance of the execution unit.

[0138] In yet another optional embodiment, the data processing system further includes an interrupt manager; and the method may further include the following steps:

[0139] The interrupt manager determines whether there is a thread among all threads that has completed all target tasks. If the result of the determination is yes, the interrupt flag of the thread is pulled high.

[0140] Each thread has a unique corresponding register command queue head address and a unique corresponding interrupt flag bit.

[0141] In this optional embodiment, multiple threads can be connected to different systems and heterogeneous CPUs, such as Fig.11 As shown, Fig.11 is a schematic diagram of a multi-threaded multi-tasking structure disclosed in an embodiment of the present invention. Fig.11 As shown in the figure, there are 4 threads, namely thread 0 (Android), thread 1 (Liunx), thread 2 (ARM) and thread 3 (RiskV). The tasks issued by each thread are sent to the execution unit for processing after polling arbitration by the task manager. After the task processing is completed, the interrupt manager judges and outputs the interrupt flag of the corresponding thread, such as thread 0 interrupt, thread 1 interrupt, thread 2 interrupt and thread 3 interrupt. It can be seen that the 4 threads correspond to the first address of 4 register command queues and 4 interrupt flags. From the system level, the subtasks of the 4 threads are processed "in parallel" by 4 independent execution units (actually processed serially by a single execution unit), which simplifies the interaction logic between the system and the heterogeneous processor CPU, and can be applied to multi-screen heterogeneous display and multi-system SoC. Multithreading is a technology that allows a processor to execute multiple control flows. Its principle is: use 1 processor as 4, and turn 1 "physical" processor with multi-threading function into 4 "logical" processors. For the system, the logical processor is no different from the physical processor. Therefore, the system will dispatch the working threads to these four logical processors for execution, so that multiple threads of (single or multiple) applications can be executed on the same physical processor at the same time, and the four logical processors share all the execution resources of a single physical processor. Therefore, multithreading technology can be considered as the virtualization of the processor.

[0142] In the embodiment of the present invention, optionally, Fig.11 The multi-threaded multi-tasking architecture shown can effectively reduce the task gap and make the called execution unit close to its performance limit. However, from the perspective of the entire system, the total performance of the data processor is limited by the performance of a single execution unit. Therefore, two independent execution units can be instantiated internally to improve the total performance of the data processor. Fig.12 is a schematic diagram of another multi-threaded multi-tasking structure disclosed in an embodiment of the present invention. Fig.12 As shown, by instantiating two execution units 0 and 1, a 4-thread 2-core architecture can be implemented. From a system level, 4 logical execution units still process the tasks of 4 threads in parallel, and the software scheduling logic of the CPU will not change.

[0143] It can be seen that in this optional embodiment, if the task corresponding to the corresponding thread has been processed, the interrupt flag of the thread can be raised so that other tasks can be issued in parallel through the thread, thereby improving the utilization rate of the thread, thereby further reducing the task gap, and further improving the execution performance of the execution unit and the system.

[0144] Embodiment 2

[0145] See also Fig.13 , Fig.13 The structure diagram of a system for processing tasks based on multithreading disclosed in an embodiment of the present invention. The data processing system includes a thread control register and a task manager. The number of threads between the thread control register and the task manager is greater than 1. All threads do not interfere with each other. Each thread has a unique corresponding command queue and a unique corresponding task queue. Fig.12 As shown, the system for processing tasks based on multi-threading may include:

[0146] The task manager is used to obtain the target task in the command queue corresponding to each thread from the thread control register through each thread, and store each target task in the task queue matching the thread corresponding to the target task;

[0147] The task manager is also used to arbitrate all target tasks in all task queues, obtain arbitration results, and determine the configuration parameters corresponding to each target task based on the arbitration results and the configuration queue data stored in the predetermined storage space; wherein the configuration parameters of each target task are used as the basis for executing processing on the data corresponding to the target task.

[0148] It can be seen that implementation Fig.13The described system for processing tasks based on multi-threading obtains corresponding tasks from thread control registers through multiple threads, that is, multiple threads send tasks to the task queue corresponding to each thread in parallel, arbitrates the tasks in the task queue corresponding to each thread, and then accurately determines the configuration parameters of the corresponding control register based on the arbitration result and the configuration queue data in the memory storage space to update the control register, that is, all tasks are sent serially to the execution unit for time-sharing processing, which can reduce the occurrence of task gaps caused by untimely processor interrupt response, thereby reducing the performance loss of the processor due to idle waiting, improving the resource utilization of the operation logic, and thus improving the processor performance; By storing the register configuration parameters of multiple tasks in the internal storage space in advance, the execution unit of the data processor can reach the upper limit of hardware performance without increasing hardware resources (such as hardware area), thereby improving the performance utilization of the execution unit and saving costs; and reducing the inability to respond to interrupts due to the processor CPU being busy at a certain moment or the processor CPU being idle at a certain moment, but the previous level of hardware has not yet completed processing, resulting in the next target task having no input source data, reducing the waiting time of the execution unit in a single thread to improve the processing performance of the execution unit, effectively reducing the degree of coupling between the operating system and the hardware processor, and reducing the software scheduling overhead of the CPU.

[0149] In an optional embodiment, the task manager determines the configuration parameters corresponding to each target task according to the arbitration result and the configuration queue data stored in the predetermined storage space in a specific manner including:

[0150] The task manager determines the header information corresponding to each target task based on the arbitration result;

[0151] The task manager analyzes the header information corresponding to each target task and the configuration queue data stored in the predetermined storage space to obtain the configuration parameters matching the header information, and determines the configuration parameters matching the header information as the configuration parameters corresponding to the target task matching the header information.

[0152] It can be seen that implementation Fig.13 The described system for processing tasks based on multi-threading can also save pixel storage resource space and improve the search accuracy and reliability of macroblocks used for final macroblock search by first performing macroblock matching on the current block of the downsampled current frame with the macroblock of the downsampled pixel area and by performing macroblock matching on the current block of the downsampled current frame with the macroblock of the downsampled integer pixel area, and then comparing the macroblocks obtained by matching the two. This can further improve the search efficiency, accuracy and reliability of the final macroblock.

[0153] In another alternative embodiment, Fig.14 is a schematic diagram of the structure of another system for processing tasks based on multithreading disclosed in an embodiment of the present invention, such as Fig.14 As shown, the above data processing system also includes a command queue parser;

[0154] The task manager determines the specific method of header information corresponding to each target task based on the arbitration result, including:

[0155] Based on the arbitration result, the task manager selects a target task from all target tasks that have not performed data processing operations in all task queues as the current target task, and generates a task start signal based on the current target task. The task start signal carries the current target task, and sends the task start signal to the command queue parser to trigger the command queue parser to determine the header information corresponding to the current target task based on the task start signal.

[0156] It can be seen that implementation Fig.14 The described system for processing tasks based on multi-threading can accurately determine the configuration parameters corresponding to the task by analyzing the arbitration result with the configuration queue data stored in the storage space; and by analyzing the arbitration result of the task to generate a task start signal for the current task, thereby analyzing it to achieve efficient and accurate determination of the header information corresponding to the current task; and after the data corresponding to all commands of the current task are processed, the self-starting task manager determines the next task from the existing task queue as soon as possible for processing, without waiting for the interrupt response of the processor CPU, reducing the task gap and improving the execution performance of the execution unit; and selecting the next task based on the arbitration result of the task can improve the accuracy and efficiency of determining the next task, which is conducive to further reducing the gap between tasks and further improving the execution performance of the execution unit.

[0157] In yet another optional embodiment, each target task includes at least one command, and the header information corresponding to each target task includes the header address of the command ranked first among all commands of the target task and the header length of the next command corresponding to each command;

[0158] The specific method by which the command queue parser determines the header information corresponding to the current target task according to the task start signal includes:

[0159] For any current target task, for the command ranked first in the current target task, the command queue parser parses the task start signal to obtain the header address corresponding to the command and the header length of the next command corresponding to each command; for the command not ranked first in the current target task, the header address corresponding to the command is determined based on the header length address corresponding to the previous command and the header length of the next command corresponding to the previous command.

[0160] It can be seen that implementation Fig.14 The described system for processing tasks based on multithreading determines the header information of the next command by combining the header information of the previous command, that is, through the relationship between the header information of two adjacent commands, the header information of each command is accurately and efficiently determined.

[0161] In yet another optional embodiment, Fig.14 As shown, the data processing system also includes a data processor;

[0162] The command queue parser is further used to perform configuration operations on the control registers of the data processor according to the configuration parameters corresponding to each target task;

[0163] The command queue parser is also used to control the execution unit of the data processor to perform data processing operations matching the target task according to the configuration parameters corresponding to each target task after the control register of the data processor is configured.

[0164] In this optional embodiment, the specific manner in which the command queue parser controls the execution unit of the data processor to perform the data processing operation matching the target task according to the configuration parameters corresponding to each target task includes:

[0165] Sending a start signal of a current command of a current target task to an execution unit of a data processor to trigger the execution unit to receive the start signal of the current command, and switching the current state to a working state according to the start signal of the current command, and processing the data corresponding to the current command according to the current configuration parameters configured by the control register; when the data corresponding to the current command is processed, sending a processing completion signal of the current command to a command queue parser;

[0166] Receive a signal indicating that the current command has been processed, and switch the current state to a working state based on the signal indicating that the current command has been processed. After switching to the working state, determine whether the current command is the last command in the current target task based on the header length of the next command of the current command. When the determination result is no, update the next command to the current command, and re-send the above-mentioned operation of sending a start signal for the current command to the execution unit of the data processor until the data corresponding to the last command in the current target task is processed.

[0167] It can be seen that implementation Fig.14The described system for processing tasks based on multi-threading updates the control register after obtaining the configuration parameters corresponding to the task, thereby controlling the execution unit to perform the corresponding data processing operation on the task. Without increasing the control register, it can reduce the occurrence of task gaps caused by the untimely response of the processor interrupt, thereby reducing the performance loss caused by the processor waiting in vain, improving the resource utilization of the operation logic, and thus improving the processor performance; and through the self-starting hardware, the data between two adjacent commands is processed without the need for the processor CPU to schedule, so that no command gap will be generated due to the untimely response of the processor CPU to the interrupt, effectively improving the utilization of the execution unit.

[0168] In yet another optional embodiment, Fig.14 As shown, the command queue parser is also used to send a task end signal of the current target task to the task manager after the data corresponding to the last command in the current target task is processed;

[0169] The task manager is further used to receive a task end signal of the current target task, and select the target task that is currently ranked first from all target tasks that have not performed data processing operations in all task queues according to the arbitration result as the next target task;

[0170] The task manager is also used to update the next target task to the current target task, and re-execute the above-mentioned operation of generating a task start signal based on the current target task until the data corresponding to the last target task in all target tasks in the command queue corresponding to the task manager is processed.

[0171] It can be seen that implementation Fig.14 The described system for processing tasks based on multi-threading, after processing the data corresponding to all commands of the current task, the self-starting task manager determines the next task from the existing task queue as soon as possible for processing, without waiting for the interrupt response of the processor CPU, thereby reducing the task gap and improving the execution performance of the execution unit; and selecting the next task based on the arbitration result of the task can improve the accuracy and efficiency of determining the next task, which is conducive to further reducing the gap between tasks and improving the execution performance of the execution unit.

[0172] In yet another optional embodiment, Fig.14 As shown, the data processing system further includes an interrupt manager;

[0173] The interrupt manager is used to determine whether there is a thread among all threads that has completed all target tasks. If the result of the determination is yes, the interrupt flag of the thread is pulled high.

[0174] Each thread has a unique corresponding register command queue head address and a unique corresponding interrupt flag bit.

[0175] It can be seen that implementation Fig.14 In the described system for processing tasks based on multi-threading, if a corresponding thread has completed processing of a task, the interrupt flag of the thread can be raised so that other tasks can be issued in parallel through the thread, thereby improving the utilization rate of the thread, thereby further reducing the task gap, and further improving the execution performance of the execution unit and the system.

[0176] Embodiment 3

[0177] See also Fig.15 , Fig.15 FIG. 1 is a schematic diagram of another system for processing tasks based on multithreading disclosed in an embodiment of the present invention. Fig.15 As shown, the device may include:

[0178] A memory 301 storing executable program codes;

[0179] a processor 302 coupled to the memory 301;

[0180] Furthermore, it may also include an input interface 303 and an output interface 304 coupled to the processor 302;

[0181] The processor 302 calls the executable program code stored in the memory 301 to execute the steps of the method for processing tasks based on multi-threading described in the first embodiment.

[0182] Embodiment 4

[0183] An embodiment of the present invention discloses a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute the steps of the method for processing tasks based on multithreading described in the first embodiment.

[0184] Embodiment 5

[0185] An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute the steps in the method for processing tasks based on multithreading described in the first embodiment.

[0186] The device embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, i.e., they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0187] Through the specific description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or partly contributed to the prior art in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0188] Finally, it should be noted that the method and system for processing tasks based on multi-threading disclosed in the embodiments of the present invention are only the preferred embodiments of the present invention, which are only used to illustrate the technical scheme of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical schemes described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical schemes from the spirit and scope of the technical schemes of the embodiments of the present invention.

Claims

1. A method for processing tasks based on multithreading, characterized in that: The method is applied to a data processing system, the data processing system includes a thread control register and a task manager, the number of threads between the thread control register and the task manager is greater than 1, all the threads do not interfere with each other, each thread has a unique corresponding command queue and a unique corresponding task queue, the method includes: The task manager obtains the target task in the command queue corresponding to the thread from the thread control register through each of the threads, and stores each of the target tasks in the task queue matching the thread corresponding to the target task; The task manager arbitrates all the target tasks in all the task queues to obtain an arbitration result, and determines the configuration parameters corresponding to each of the target tasks according to the arbitration result and the configuration queue data stored in the predetermined storage space; The configuration parameters of each target task are used as a basis for executing processing on the data corresponding to the target task.

2. The method for processing tasks based on multithreading according to claim 1, characterized in that: The task manager determines the configuration parameters corresponding to each of the target tasks according to the arbitration result and the configuration queue data stored in the predetermined storage space, including: The task manager determines the header information corresponding to each of the target tasks according to the arbitration result; The task manager analyzes the header information corresponding to each of the target tasks and the configuration queue data stored in a predetermined storage space to obtain configuration parameters that match the header information, and determines that the configuration parameters that match the header information are the configuration parameters corresponding to the target task that matches the header information.

3. The method for processing tasks based on multithreading according to claim 2, characterized in that: The data processing system also includes a command queue parser; The task manager determines the header information corresponding to each of the target tasks according to the arbitration result, including: The task manager selects, according to the arbitration result, a target task from all target tasks in all the task queues that have not executed data processing operations as the current target task; The task manager generates a task start signal according to the current target task, and sends the task start signal to the command queue parser, wherein the task start signal carries the current target task; The command queue parser determines the header information corresponding to the current target task according to the task start signal.

4. The method for processing tasks based on multithreading according to claim 3, characterized in that: Each of the target tasks includes at least one command, and the header information corresponding to each of the target tasks includes the header address of the command that is ranked first among all the commands of the target task and the header length of the next command corresponding to each of the commands; The command queue parser determines the header information corresponding to the current target task according to the task start signal, including: For any of the current target tasks, for the command ranked first in the current target task, the command queue parser parses the task start signal to obtain the header address corresponding to the command and the header length of the next command corresponding to each of the commands; For a command that is not ranked first in the current target task, the header address corresponding to the command is determined according to the header length address corresponding to the previous command and the header length of the next command corresponding to the previous command.

5. The method for processing tasks based on multithreading according to claim 3 or 4, characterized in that: The data processing system also includes a data processor; The method further comprises: The command queue parser performs a configuration operation on a control register of the data processor according to a configuration parameter corresponding to each of the target tasks; After the control registers of the data processor are configured, the command queue parser controls the execution unit of the data processor to execute the data processing operation matching the target task according to the configuration parameters corresponding to each target task.

6. The method for processing tasks based on multithreading according to claim 5, characterized in that: The command queue parser controls the execution unit of the data processor to perform a data processing operation matching the target task according to the configuration parameters corresponding to each target task, including: The command queue parser sends a start signal of the current command of the current target task to the execution unit of the data processor; The execution unit receives a start signal of the current command, switches the current state to a working state according to the start signal of the current command, and processes data corresponding to the current command according to current configuration parameters configured by the control register; when the data corresponding to the current command is processed, sends a processing completion signal of the current command to the command queue parser; The command queue parser receives a processing completion signal of the current command, and switches the current state to a working state according to the processing completion signal of the current command. After switching to the working state, it determines whether the current command is the last command in the current target task according to the header length of the next command of the current command. When the judgment result is no, the next command is updated to the current command, and the operation of sending the start signal of the current command to the execution unit of the data processor is repeated until the data corresponding to the last command in the current target task is processed.

7. The method for processing tasks based on multithreading according to claim 6, characterized in that: The method further comprises: When the data corresponding to the last command in the current target task is processed, the command queue parser sends a task end signal of the current target task to the task manager; The task manager receives a task end signal of the current target task, and selects the target task that is currently ranked first from all target tasks that have not executed data processing operations in all the task queues according to the arbitration result as the next target task; The task manager updates the next target task to the current target task, and re-executes the operation of generating a task start signal according to the current target task until the data corresponding to the last target task in all target tasks in the command queue corresponding to the task manager is processed.

8. The method for processing tasks based on multithreading according to any one of claims 1 to 7, characterized in that: The data processing system also includes an interrupt manager; The method further comprises: The interrupt manager determines whether there is a thread among all the threads that has completed the execution of all the target tasks, and when the determination result is yes, the interrupt flag bit of the thread is raised; Each of the threads has a unique corresponding register command queue head address and a unique corresponding interrupt flag bit.

9. A system for processing tasks based on multithreading, characterized in that: The system includes a thread control register and a task manager, the number of threads between the thread control register and the task manager is greater than 1, all the threads do not interfere with each other, and each thread has a unique corresponding command queue and a unique corresponding task queue, wherein: The task manager is used to obtain, through each of the threads, a target task in a command queue corresponding to the thread from the thread control register, and store each of the target tasks in a task queue matching the thread corresponding to the target task; The task manager is further used to arbitrate all the target tasks in all the task queues to obtain an arbitration result, and determine the configuration parameters corresponding to each of the target tasks according to the arbitration result and the configuration queue data stored in the predetermined storage space; The configuration parameters of each target task are used as a basis for executing processing on the data corresponding to the target task.

10. A system for processing tasks based on multithreading, characterized in that: The device is applied to a data processing system, and the device comprises: A memory storing executable program code; a processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the method for processing tasks based on multi-threading as described in any one of claims 1-8.

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