FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform

Abstract

The application belongs to the field of coherent synthesis, and discloses a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA, which is used for solving the problem that the MATALAB software simulation SPGD algorithm is not accurate, and the simulation system of the application combines software and hardware, first, the SPGD algorithm and related simulation modules are deployed into the FPGA board card; then, the software simulation light path is established in the computer; subsequently, the FPGA is connected with the computer through the gigabit Ethernet interface to establish the data interaction channel; then, the internal parameters of the SPGD algorithm are set by sending instructions from the computer to the FPGA, and the SPGD algorithm simulation is started; after that, the positive and negative voltage values calculated by the SPGD algorithm are sent to the computer, and after the positive and negative voltage data are received by the computer software simulation light path, the ADC data are calculated and sent to the FPGA; finally, the simulation of the SPGD algorithm is realized through the cyclic data interaction between the FPGA and the computer. The method of the application can simulate the simulation of the SPGD algorithm under complex experimental environment, improve the accuracy of the simulation, and increase the success rate of the experiment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of laser coherent synthesis, and particularly relates to a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA. BACKGROUND

[0002] High-energy laser is widely used in industry, aerospace, military and many other fields. However, due to its own physical characteristics, the output power of a single laser is also limited. Through laser synthesis technology, multiple lasers can be coherently synthesized to effectively improve the output power of the laser.

[0003] The main methods of laser coherent synthesis include heterodyne method, multi-dithering method, particle swarm algorithm, genetic algorithm, stochastic parallel gradient descent (SPGD) algorithm, and machine learning method. Among them, the SPGD algorithm was proposed by the US Army Research Institute Vorontsov in 1997. Due to the simple logical structure of the algorithm, it is easy to implement, and therefore widely improved and applied in laser coherent synthesis systems. In the process of improving these algorithms, the algorithm is mainly simulated based on MATALAB. However, this simulation method cannot well simulate the real experimental system, resulting in a large error between the simulation results and the experimental results. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art and provide a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA. Compared with the traditional idealized simulation based on MATALB, the verification platform can simulate a simulation environment close to the experimental system, improve the accuracy of the simulation, and facilitate the discovery of the shortcomings in the improvement of the SPGD algorithm, thereby improving the success rate of further conversion of the simulation algorithm to experiments.

[0005] The technical solution of the present application to solve the above technical problems is:

[0006] A multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA, comprising the following steps:

[0007] (S1), before the Ethernet module sends data or after the Ethernet module receives data, the data passes through a cross-clock domain module, and the cross-clock domain module buffers the data according to different clock frequencies of the SPGD;

[0008] (S2), after the instructions sent by the computer pass through the cross-clock domain module, the instruction parsing module parses the instructions according to the self-defined instruction set format to obtain the SPGD algorithm parameters;

[0009] (S3), the random sequence module generates multiple groups of pseudo-random sequences R n by a linear feedback register;

[0010] (S4), the SPGD algorithm module obtains the perturbation voltage δu n , the forward voltage dv + , the negative voltage dv - , the update voltage U n ;

[0011] (S5), the DAC data conversion module in the DAC and ADC data conversion module, converts the forward voltage dv + , the negative voltage dv - value calculated by the SPGD algorithm module into DAC data, and sends the DAC data to the computer through the Ethernet module;

[0012] (S6), the ADC data conversion module in the DAC and ADC data conversion module, converts the ADC data received by the cross-clock domain module into voltage values available for the SPGD algorithm module to calculate;

[0013] (S7), the computer end simulation light path obtains the forward voltage dv + , the negative voltage dv - , and then calculates the ADC data corresponding to the evaluation functions J + , J - respectively, and sends the ADC data to the FPGA.

[0014] Preferably, in step (S1), the cross-clock domain module uses an asynchronous FIFO to establish a data cache area, writes data from the end with a slower clock frequency into the FIFO for caching, and judges whether to read out from the end with a faster clock frequency through a non-empty flag signal of the data output by the FIFO.

[0015] Preferably, in step (S2), the instruction analysis module uses a custom instruction format to receive instructions sent by the computer, and the instructions are divided into three modes: SPGD start mode, SPGD reset mode, and SPGD parameter adjustment mode.

[0016] Preferably, in step (S2), the SPGD start mode is 1 byte long, the SPGD reset mode is 1 byte long, and the SPGD parameter adjustment mode is 9 bytes.

[0017] Preferably, in step (S2), the 9 bytes of the SPGD parameter adjustment mode include: 1 byte of mode instruction, 3 bytes of update voltage coefficient instruction, 2 bytes of perturbation voltage coefficient instruction, 2 bytes of system delay instruction, and 1 byte of ADC average sampling number instruction.

[0018] Preferably, in step (S4), the perturbation voltage δu n, forward voltage dv + , negative voltage dv - , update voltage U n The calculation steps are as follows:

[0019] (S4-1), if the pseudo-random sequence R n equals 1, the disturbance voltage δu n = b, if the pseudo-random sequence R n equals 0, the disturbance voltage δu n = -b, wherein b is a disturbance voltage coefficient;

[0020] (S4-2), the forward voltage dv + = U n + δu n , the negative voltage dv - = U n - δu n ;

[0021] (S4-3), the update voltage U n+1 = U n + a * δu n * ΔJ, wherein the change amount ΔJ of the performance evaluation function = J + - J - .

[0022] Preferably, in step (S5), the DAC in the DAC and ADC data conversion module converts the forward and negative voltage values calculated by the SPGD algorithm module into corresponding DAC input data according to the mapping relationship between the input data and the output voltage of different DAC modules.

[0023] Preferably, in step (S6), the ADC in the DAC and ADC data conversion module converts the ADC data input by the cross-clock domain module into corresponding voltage values according to the mapping relationship between the input voltage and the output data of different ADC modules.

[0024] Compared with the prior art, the application has the following beneficial effects:

[0025] 1. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the application combines FPGA hardware and computer software simulation environment, realizes data interaction between FPGA and computer through Ethernet UDP protocol, runs SPGD algorithm in FPGA, and simulates experimental environment in the software simulation environment in the computer. The simulation system established by this method can more accurately simulate the experimental environment, thereby improving the accuracy of the simulation result.

[0026] 2、The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the application can switch different modes by sending different instructions in the data interaction between the FPGA and the computer through the Ethernet UDP protocol: the SPGD start mode, the SPGD reset mode and the SPGD parameter adjustment mode. The SPGD start mode can start the SPGD algorithm for operation, the SPGD reset mode can reset various parameters in the SPGD algorithm, and the SPGD parameter adjustment mode can change the update voltage coefficient, the disturbance voltage coefficient, the system delay and the ADC average sampling number. This is conducive to the adjustment of the parameters in the SPGD algorithm and improves the convenience of the simulation system. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A structure block diagram of the FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the application.

[0028] Figure 2 A flow chart of the FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the application. DETAILED DESCRIPTION

[0029] The application will be described in further detail below with reference to the embodiments and the accompanying drawings, but the embodiments of the application are not limited thereto.

[0030] Referring to Figure 1 The relationship between the various modules in the FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the application is shown in the figure. The Ethernet module serves as the communication interface between the FPGA and the computer; the cross-clock domain module establishes a data buffer area to ensure that the data is not lost when the DAC and ADC data conversion module, the instruction analysis module and the Ethernet module interact with each other; the instruction analysis module analyzes the instructions sent by the computer and provides calculation parameters for the SPGD algorithm; the DAC and ADC data conversion module converts the positive and negative voltages calculated by the SPGD into DAC data and converts the ADC data sent by the computer into voltage values; the random sequence module and the SPGD algorithm module jointly implement the SPGD algorithm; and the analog optical path simulates the operation of the optical path on the computer.

[0031] Referring to Figure 2 The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the application includes the following steps:

[0032] (S1), the computer sends instructions to the FPGA to set the parameters in the SPGD algorithm; the FPGA uses the xc7z020clg400-2 chip of the Xilinx company;

[0033] (S2), the Ethernet module receives instructions, through the cross-clock domain module, and then through the instruction analysis module to obtain the SPGD algorithm parameters, and sends the parsed parameters to the SPGD algorithm module;

[0034] (S3), the SPGD algorithm module sets the internal parameters and starts the SPGD algorithm simulation;

[0035] (S4), the SPGD algorithm module calculates the perturbation voltage δu n , the forward voltage dv + , the negative voltage dv - , the update voltage U n , and sends the forward voltage and the negative voltage to the DAC and ADC data conversion module;

[0036] (S5), the DAC conversion module in the DAC and ADC data conversion module converts the forward voltage and the negative voltage into DAC data, and sends them to the Ethernet module through the cross-clock domain module;

[0037] (S6), the Ethernet module sends the DAC data to the computer's analog optical path;

[0038] (S7), the computer's analog optical path calculates the evaluation function J + , J - , respectively, by receiving the forward voltage and the negative voltage, and sends the ADC data to the FPGA Ethernet module;

[0039] (S8), the Ethernet module sends the received ADC data to the DAC and ADC data conversion module through the cross-clock domain module;

[0040] (S9), the ADC conversion module in the DAC and ADC data conversion module converts the ADC data into voltage values and sends them to the SPGD algorithm module.

[0041] Referring to Figure 2 , in step (S2), the Ethernet module, the cross-clock domain module, and the instruction analysis module are constructed as follows:

[0042] (S2-1) the Ethernet module uses UDP protocol to interact with the computer;

[0043] (S2-2) the cross-clock domain module uses asynchronous FIFO to establish a data buffer area, writes data from the end with slower clock frequency into the FIFO for buffering, and judges whether to read out from the end with faster clock frequency through the non-empty flag signal output by the FIFO;

[0044] (S2-3) Instruction analysis module, using custom instruction format to receive instructions sent by computer, instructions are divided into three modes: SPGD start mode, SPGD reset mode, SPGD parameter adjustment mode. Among them, the SPGD start mode is 1 byte length (instruction is AF); the SPGD reset instruction is 1 byte length (instruction is A0); the SPGD parameter adjustment mode is 9 bytes, wherein the 9 bytes of the SPGD parameter adjustment mode include: 1 byte mode instruction (instruction is: AA), 3 bytes update voltage coefficient instruction, 2 bytes perturbation voltage coefficient instruction, 2 bytes system delay instruction, 1 byte ADC average sampling number instruction, voltage coefficient instruction, perturbation voltage coefficient instruction, system delay instruction, ADC average sampling number instruction all use fixed-point number Q10 format.

[0045] Referring to Figure 2 In step (S4), the construction of the SPGD algorithm module is as follows:

[0046] (S4-1), random sequence module, generating random sequence R through linear shift feedback register n And sending the generated random sequence to the SPGD algorithm module;

[0047] (S4-2), if the pseudo-random sequence R n is equal to 1, the perturbation voltage δu n = b, if the pseudo-random sequence R n is equal to 0, the perturbation voltage δu n = -b, wherein b is the perturbation voltage coefficient;

[0048] (S4-3), the positive voltage dv + = U n + δu n , the negative voltage dv - = U n - δu n ;

[0049] (S4-4), update voltage U n+1 = U n + a*δu n *ΔJ, wherein the change amount ΔJ of the performance evaluation function = J + -J - .

[0050] Referring to Figure 2In step (S5), the construction of the DAC conversion module in the DAC and ADC data conversion module includes the following steps: the length of the DAC module input data is set to 16 bits, the output voltage range is set to 0-5V, and the DAC module input data and the output voltage are in a linear mapping relationship; the DAC conversion module converts the positive and negative voltage values calculated by the SPGD algorithm module into the input data corresponding to the DAC module.

[0051] Referring to Figure 2 In step (S9), the construction of the ADC conversion module in the DAC and ADC data conversion module includes the following steps: the input voltage range of the ADC module is set to 0-5V, the length of the output data is set to 12 bits, and the input voltage of the ADC module and the output data are in a linear mapping relationship; the ADC conversion module converts the input ADC data into a corresponding voltage value.

Claims

1. An FPGA-based multi-laser coherent synthesis SPGD algorithm verification platform, characterized in that, The simulation system comprises The following steps are included: (S1) Before the Ethernet module sends data or after the Ethernet module receives data, the data passes through a cross-clock domain module, and the cross-clock domain module buffers the data according to different clock frequencies of the SPGD; (S2) After the instruction sent by the computer passes through the cross-clock domain module, an instruction analysis module, the instruction is analyzed according to a self-defined instruction set format, and SPGD algorithm parameters are obtained; (S3) The random sequence module generates multiple sets of pseudo-random sequences R through a linear feedback register n ; (S4), the SPGD algorithm module obtains the disturbance voltage δu through calculation n , forward voltage dv + , negative voltage dv - , update voltage U n ; (S5), the DAC data conversion module in the DAC and ADC data conversion module, converts the positive voltage dv + value calculated by the SPGD algorithm module into DAC data, and sends the DAC data to the computer through the Ethernet module; - value calculated by the SPGD algorithm module into DAC data, and sends the DAC data to the computer through the Ethernet module; (S6) An ADC data conversion module in the DAC and ADC data conversion module converts the ADC data received by the cross-clock domain module into voltage values available for the SPGD algorithm module to calculate; (S7), the computer terminal simulation light path obtains the forward voltage dv sent by the FPGA + , the negative voltage dv - After that, the corresponding evaluation function J + , J - ADC data is obtained by calculation, and the ADC data is sent to the FPGA. 2.The FPGA-based multi-laser coherent combination SPGD algorithm verification platform according to claim 1, wherein, In step (S1), the cross-clock domain module uses an asynchronous FIFO to establish a data buffer area, and the data of the end with a slower clock frequency is written into the FIFO for buffering, and whether the data output by the FIFO is empty is judged by a non-empty flag signal of the data output by the FIFO. 3.The FPGA-based multi-laser coherent combination SPGD algorithm verification platform of claim 1, wherein, In step (S2), the instruction analysis module receives the instruction sent by the computer using a self-defined instruction format, and the instruction is divided into three modes: SPGD start mode, SPGD reset mode and SPGD parameter adjustment mode.

4. The FPGA-based multi-laser coherent combining SPGD algorithm verification platform according to claim 3, characterized in that, The SPGD start mode is 1 byte long, the SPGD reset mode is 1 byte long, and the SPGD parameter adjustment mode is 9 bytes.

5. The FPGA-based multi-laser coherent combining SPGD algorithm verification platform according to claim 4, characterized in that, The 9 bytes of the SPGD parameter adjustment mode include: 1 byte of mode instruction, 3 bytes of updated voltage coefficient instruction, 2 bytes of disturbance voltage coefficient instruction, 2 bytes of system delay instruction and 1 byte of ADC average sampling number instruction.

6. The FPGA-based multi-laser coherent combining SPGD algorithm verification platform according to claim 1, wherein, The perturbation voltage δu in step (S4) n The positive voltage dv + The negative voltage dv - The update voltage U n The calculation step is as follows: (S4-1) if the pseudo-random sequence R n = b, if the pseudo-random sequence R n = -b, if the pseudo-random sequence R n = b, if the pseudo-random sequence R n = -b, if the pseudo-random sequence R (S4-2), forward voltage dv + = U n + δu n , negative voltage dv - = U n - δu n ; (S4-3), update the voltage U n+1 = U n + a * δu n * ΔJ, where the change amount ΔJ of the performance evaluation function = J + - J - .

7. The FPGA-based multi-laser coherent combining SPGD algorithm verification platform according to claim 1, characterized in that, In step (S5), the DAC conversion module in the DAC and ADC data conversion module converts the positive and negative voltage values calculated by the SPGD algorithm module into corresponding DAC input data according to the mapping relationship between the input data and the output voltage of different DAC modules.

8. The FPGA-based multi-laser coherent combining SPGD algorithm verification platform according to claim 1, wherein, In step (S6), the ADC conversion module in the DAC and ADC data conversion module converts the ADC data input by the cross-clock domain module into corresponding voltage values according to the mapping relationship between the input voltage and the output data of different ADC modules.

Images