Simulation method and device of digital circuit, equipment, storage medium and product

Abstract

The invention discloses a simulation method and device of a digital circuit, equipment, a storage medium and a product. The simulation method comprises the steps of obtaining hardware design description information of the digital circuit; in a simulation compiling stage of the circuit, according to the hardware design description information and the deep learning framework, generating a simulation execution program and a library file corresponding to the deep learning framework; acquiring boundary signal data input by a user for the digital circuit; and in the simulation operation stage of the circuit, the simulation execution program is operated according to the boundary signal data and the library file, and a simulation result corresponding to the circuit is obtained. According to the technical scheme, on the premise that accuracy is guaranteed, the software simulation process of the large-scale combinational logic circuit is remarkably accelerated, and the development difficulty and maintenance cost of a simulation tool are reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, applicable to hardware description language (HDL) software simulation scenarios, and particularly to a simulation method, apparatus, device, storage medium, and product for digital circuits. Background Technology

[0002] With the continuous expansion of integrated circuit scale and the sharp increase in design complexity, simulation and verification of digital circuits has become a key link and major performance bottleneck in the design process.

[0003] In the existing technology, when simulating and verifying digital circuits, event-driven simulators, statically compiled simulators, and simulation schemes accelerated by graphics processing units (GPUs) are commonly used.

[0004] However, for large-scale, highly active combinational logic circuits, event-driven simulators suffer from significant performance overhead due to extensive event scheduling and context switching, resulting in slow simulation speeds. Static-compiled simulators typically generate code that executes sequentially, failing to fully utilize the parallel computing capabilities of modern multi-core CPUs. Furthermore, developing and maintaining an efficient code generator is extremely difficult. GPU-accelerated simulation solutions are challenging to port, requiring the circuit structure to be transformed into a model suitable for massively parallel GPU computing. Development is complex, and the transmission of input or output signals between the CPU and GPU introduces additional latency. For circuits with complex control logic or low parallelism, the acceleration effect is not significant, resulting in low energy efficiency.

[0005] Therefore, there is an urgent need to provide a new high-speed simulation solution that is both efficient and parallel, and easy to develop and deploy. Summary of the Invention

[0006] This invention provides a digital circuit simulation method, apparatus, device, storage medium, and product that can significantly accelerate the software simulation process of large-scale combinational logic circuits while ensuring accuracy, and reduce the development difficulty and maintenance cost of simulation tools.

[0007] According to one aspect of the present invention, a method for simulating digital circuits is provided, the method comprising:

[0008] Obtain hardware design description information for digital circuits;

[0009] During the simulation compilation stage of the circuit, a simulation execution program and the corresponding library files of the deep learning framework are generated based on the hardware design description information and the deep learning framework.

[0010] Acquire boundary signal data input by the user for the digital circuit;

[0011] During the simulation operation phase of the circuit, the simulation execution program is run based on the boundary signal data and library files to obtain the simulation results corresponding to the circuit.

[0012] Optionally, based on the hardware design description information and the deep learning framework, generate the corresponding library files for the deep learning framework, including:

[0013] The hardware design description information is analyzed, and the hardware design description information is converted into structured intermediate representation information based on the analysis results;

[0014] Based on the description information, the hardware design is divided into multiple sub-designs that are executed serially;

[0015] Based on the intermediate representation information and the input and output information of each sub-design, the execution code corresponding to the deep learning framework PyTorch is generated; the execution code defines the PyTorch computation graph.

[0016] Based on the PyTorch executable code and the pre-built Torch operator library, generate the corresponding PyTorch library files.

[0017] Optionally, based on the hardware design description information and the deep learning framework, the simulation execution program is generated, including:

[0018] Based on the intermediate representation information and the input and output information of each sub-design, the glue code corresponding to the circuit is generated;

[0019] The glue code includes at least one of the following: global variables passed to the runtime phase, simulation control logic code, and scheduling code that interacts with the PyTorch computation graph;

[0020] The glue code is compiled and linked with the runtime library corresponding to the circuit to obtain the simulation execution program.

[0021] Optional, pre-built Torch operator libraries include:

[0022] Multiple artificial intelligence operators are obtained, and the multiple artificial intelligence operators are divided into a first operator and a second operator according to their implementation complexity;

[0023] The implementation complexity of the first operator is less than that of the second operator.

[0024] Map the first operator to a built-in PyTorch tensor operator;

[0025] Generate the Triton kernel code corresponding to the second operator, which is used to control the hardware characteristics of the graphics processing unit (GPU).

[0026] Optionally, the simulation execution program is run based on the boundary signal data and the library files, including:

[0027] The simulation execution program reads boundary signal data corresponding to multiple instruction cycles and converts the boundary signal data into multiple input tensors corresponding to PyTorch.

[0028] The simulation execution program passes the multiple input tensors to the scheduling code, and the scheduling code sequentially passes each input tensor to the computation function in the library file.

[0029] The output tensor is obtained by parallel computation of multiple input tensors using the computation function, and the output tensor is returned to the simulation execution program.

[0030] Optionally, after returning the output tensor to the simulation executor, the method further includes:

[0031] The simulation execution program processes the output tensor using at least one of the following methods to obtain the simulation results corresponding to the circuit:

[0032] Print the output tensor to the console;

[0033] Write the output tensor to a log file;

[0034] Based on the output tensor, a standard format value-variable dump VCD waveform file is generated.

[0035] According to another aspect of the present invention, a digital circuit simulation apparatus is provided, the apparatus comprising:

[0036] The hardware information acquisition module is used to acquire hardware design description information of digital circuits;

[0037] The simulation compilation module is used to generate a simulation execution program and the library files corresponding to the deep learning framework based on the hardware design description information and the deep learning framework during the simulation compilation stage of the circuit.

[0038] A boundary data acquisition module is used to acquire boundary signal data input by the user to the digital circuit;

[0039] The simulation execution module is used to run the simulation execution program based on the boundary signal data and library files during the simulation execution phase of the circuit, and obtain the simulation results corresponding to the circuit.

[0040] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0041] At least one processor; and

[0042] A memory communicatively connected to the at least one processor; wherein,

[0043] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the digital circuit simulation method according to any embodiment of the present invention.

[0044] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the simulation method of the digital circuit described in any embodiment of the present invention.

[0045] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the digital circuit simulation method described in any embodiment of the present invention.

[0046] The technical solution provided by this invention, by acquiring the hardware design description information of a digital circuit, generating a simulation execution program and a library file corresponding to the deep learning framework based on the hardware design description information and the deep learning framework during the simulation compilation stage of the circuit, acquiring the boundary signal data input by the user for the digital circuit, and running the simulation execution program based on the boundary signal data and the library file during the simulation operation stage of the circuit to obtain the simulation result corresponding to the circuit, can significantly accelerate the software simulation process of large-scale combinational logic circuits while ensuring accuracy, and reduce the development difficulty and maintenance cost of simulation tools.

[0047] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart of a digital circuit simulation method provided according to an embodiment of the present invention;

[0050] Figure 2 This is a flowchart of another digital circuit simulation method provided according to an embodiment of the present invention;

[0051] Figure 3 This is a flowchart of another digital circuit simulation method provided according to an embodiment of the present invention;

[0052] Figure 4a This is a flowchart of a simulation method for digital circuits during the compilation stage according to an embodiment of the present invention;

[0053] Figure 4b This is a flowchart of a simulation method for a digital circuit during the operation phase according to an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of the structure of a digital circuit simulation device according to an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of the structure of an electronic device that implements the digital circuit simulation method of the present invention. Detailed Implementation

[0056] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0057] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0058] Figure 1 This is a flowchart illustrating a digital circuit simulation method provided by an embodiment of the present invention. This embodiment is applicable to the simulation and verification of digital circuits, especially combinational logic circuits. The method can be executed by a digital circuit simulation device, which can be implemented in hardware and / or software and configured in an electronic device, such as... Figure 1 As shown, the method includes:

[0059] Step 110: Obtain the hardware design description information of the digital circuit.

[0060] In this step, the digital circuit can be a combinational logic circuit to be simulated. The hardware design description information can be the Verilog code of the combinational logic circuit. The Verilog code is essentially a hardware description language, whose core functions include behavioral-level description, structural-level description, and register-transfer-level (RTL) description.

[0061] Step 120: During the simulation and compilation stage of the circuit, a simulation execution program and the corresponding library files of the deep learning framework are generated based on the hardware design description information and the deep learning framework.

[0062] In this embodiment, the deep learning framework can be PyTorch. During the simulation and compilation stage of the circuit, the Verilog code of the digital circuit can be read, and PyTorch can be used to generate the executable program sim and the corresponding .pt2 library file.

[0063] Specifically, in the field of Verilog simulation of digital circuits, RTL code and test bench need to be compiled and linked into a binary executable program using simulation tools. This executable program is called "sim," and running it initiates the simulation process for the digital circuit. The .pt2 library file is a compressed file used in PyTorch to store models, tensors, or other PyTorch objects.

[0064] Step 130: Obtain the boundary signal data input by the user for the digital circuit.

[0065] In this embodiment, the user can execute the compiled sim executable program in the command line or script, and specify parameters such as the boundary signal data of the digital circuit and the simulation duration.

[0066] Specifically, the boundary signal data can be the input signal state inside the digital circuit or at the interface, including signal value, timing, etc., and is a key parameter to ensure the accuracy of data transmission between circuit modules.

[0067] Step 140: During the simulation operation phase of the circuit, the simulation execution program is run according to the boundary signal data and library files to obtain the simulation results corresponding to the circuit.

[0068] In this embodiment, during the simulation operation phase of the circuit, the sim simulation execution program can read the boundary signal data input by the user and the generated .pt2 library file, perform simulation calculations, and finally output the simulation results corresponding to the digital circuit.

[0069] The technical solution provided by this invention utilizes the high-performance tensor computation and parallel processing capabilities of the PyTorch deep learning framework to significantly accelerate the software simulation process of large-scale combinational logic circuits. By transforming traditional Verilog code into a parallel computation model based on data flow and tensor operations, it can achieve "compile once, execute multiple times" simulation logic, suitable for scenarios requiring repeated simulation, such as regression testing. Furthermore, by leveraging the mature PyTorch ecosystem, it avoids developing a simulation kernel and compiler from scratch, significantly reducing the development difficulty and maintenance cost of simulation tools.

[0070] Figure 2A flowchart of another digital circuit simulation method provided in an embodiment of the present invention is shown below. Figure 2 As shown, the method includes:

[0071] Step 210: Obtain the hardware design description information of the digital circuit. During the simulation and compilation stage of the circuit, analyze the hardware design description information and convert it into structured intermediate representation information based on the analysis results.

[0072] In this embodiment, during the simulation and compilation stage of the circuit, lexical analysis, syntax analysis, and semantic analysis can be performed on the Verilog code of the digital circuit. Based on the analysis results, the Verilog code is converted into a structured intermediate representation. The intermediate representation precisely describes the module hierarchy, signal connection relationships, and combinational logic functions (such as AND, OR, NOT, multiplexers, etc.) in the digital circuit design.

[0073] In addition, the Verilog code of digital circuits can be refined and optimized, such as expanding the module instances in the digital circuits, or optimizing the readability of the Verilog code (clearness of module division, completeness of comments, naming conventions, etc.). This embodiment does not impose any limitations on this.

[0074] Step 220: Based on the description information, divide the hardware design into multiple sub-designs that are executed serially.

[0075] The advantage of this setup is that by dividing the entire hardware design of the digital circuit into multiple serially executed sub-designs, it is easier to use PyTorch to generate independent computation graphs for each sub-design, thereby reducing the size of the generated computation graph and reducing the time consumption during the compilation stage.

[0076] Step 230: Generate the execution code corresponding to the deep learning framework PyTorch based on the intermediate representation information and the input and output information of each sub-design; the execution code defines the PyTorch computation graph.

[0077] In this step, the intermediate representation information and each sub-design can be analyzed to identify all combinational logic paths in the digital circuit and map them into a directed acyclic data flow computation graph.

[0078] Specifically, each logic gate or expression in a digital circuit can be converted into a corresponding custom PyTorch operation (e.g., AND gates and OR gates are converted into torch::sim_and_2s, torch::sim_or_2s, etc.). Thus, the simulation behavior of the entire hardware design can be constructed into one or more PyTorch models or functions, and high-performance Python code (i.e., the corresponding PyTorch execution code) can be generated based on this. This code fully defines the PyTorch computation graph.

[0079] Step 240: Generate the corresponding PyTorch library file based on the PyTorch executable code and the pre-built Torch operator library.

[0080] In this step, the executable code can be pre-compiled using PyTorch's `torch.export` and `torch.aoti_compile` operations based on a custom Torch operator library, generating a highly optimized, hardware-platform-dependent dynamic link library, i.e., a .pt2 library file. This library file encapsulates the core simulation computation kernel, ensuring optimal runtime performance.

[0081] In one embodiment of this example, pre-building a Torch operator library includes: acquiring multiple artificial intelligence operators, dividing the multiple artificial intelligence operators into a first operator and a second operator according to their implementation complexity; the implementation complexity of the first operator is less than that of the second operator; mapping the first operator to a PyTorch built-in tensor operator; generating Triton kernel code corresponding to the second operator, wherein the kernel code is used to control the hardware characteristic information of the graphics processing unit (GPU).

[0082] In this embodiment, a layered, efficient Python-level custom operator library can be built during the simulation compilation phase to implement combinational logic simulation operations. The operator library can intelligently select the optimal implementation path based on the computational complexity of the operators, balancing development efficiency and runtime performance. Specifically, artificial intelligence operators can be divided into basic operators (involving basic bit-level logic operations such as AND, OR, NOT, XOR, etc.) and complex operators (non-standard or computationally intensive combinational logic modules, such as specific encoders, decoders, complex multiplexing trees, custom bit-width arithmetic units, etc.).

[0083] For basic operators, they can be directly mapped to highly optimized PyTorch built-in tensor operators (such as torch.bitwise_and, torch.bitwise_or, etc.), thus leveraging the advantages of deep operator optimization in PyTorch. For complex operators, Triton can be used to develop their computational kernels.

[0084] Triton is a Python GPU programming language that allows for the direct writing and compilation of high-performance GPU kernels within a Python environment. For complex operators, corresponding Triton kernel code can be generated. These kernels enable fine-grained control over GPU hardware characteristics (such as thread hierarchy and memory access), thereby achieving extreme parallel computing performance.

[0085] Furthermore, this embodiment proposes a unified Python interface and encapsulation method for operators. Regardless of whether the underlying implementation uses PyTorch built-in operators or the Triton kernel, all these operations are uniformly abstracted and encapsulated into Python functions within the system. These functions follow the same calling convention, providing a concise and consistent interface to the outside world. This allows for the seamless mixing of two implementations of operators when constructing a computation graph, without needing to concern themselves with their underlying differences.

[0086] Step 250: Generate the C++ glue code corresponding to the circuit based on the intermediate representation information and the input and output information of each sub-design.

[0087] The glue code includes at least one of the following: global variables passed to the runtime phase, simulation control logic code, and scheduling code that interacts with the PyTorch computation graph.

[0088] Specifically, the global variables control information such as loading all .pt2 library files required for runtime, the number of data sets for each round of parallel computation, and the input and output of the scheduling code. The scheduling code controls the execution order of multiple computation graphs in each round of the simulation process and the data transfer between different computation graphs.

[0089] Step 260: Compile and link the glue code with the runtime library corresponding to the circuit to obtain the simulation execution program.

[0090] The advantage of this setup is that by compiling the entire combinational logic circuit into a static, parallelizable computation graph and using PyTorch's AI compiler for deep optimization to generate a highly optimized underlying kernel, the simulation throughput can be significantly improved. Secondly, the simulation executable generated by this embodiment can fully utilize the parallel computing capabilities of multi-core CPUs or the massive parallel computing capabilities of GPUs, without requiring developers to manually handle complex parallelization details.

[0091] Step 270: Obtain the boundary signal data input by the user for the digital circuit; during the simulation operation phase of the circuit, run the simulation execution program according to the boundary signal data and the library file to obtain the simulation results corresponding to the circuit.

[0092] The technical solution provided by this invention obtains the hardware design description information of a digital circuit, analyzes the hardware design description information during the circuit simulation and compilation stage, converts the analysis results into structured intermediate representation information, divides the hardware design into multiple serially executed sub-designs, generates execution code corresponding to the deep learning framework PyTorch based on the intermediate representation information and the input and output information of each sub-design, generates corresponding PyTorch library files based on the PyTorch execution code and Torch operator library, generates glue code corresponding to the circuit, compiles and links the glue code with the corresponding runtime library of the circuit to obtain the simulation execution program, obtains boundary signal data, and runs the simulation execution program based on the boundary signal data and library files during the circuit simulation run stage to obtain the simulation results corresponding to the circuit. This technical means can compile Verilog combinational logic into a PyTorch dataflow graph, utilize PyTorch's parallel tensor computation capabilities, transform traditional serial event-driven simulation into batch signal parallel processing, achieving an order-of-magnitude speed improvement, and by hybrid scheduling of PyTorch built-in operators and Triton... The GPU core maximizes hardware utilization while maintaining bit-level precision, significantly reduces repetitive overhead in regression testing, greatly accelerates the simulation process while ensuring accuracy, and significantly shortens the verification cycle of chip design.

[0093] Figure 3 A flowchart of another digital circuit simulation method provided in an embodiment of the present invention is shown below. Figure 3 As shown, the method includes:

[0094] Step 310: Obtain the hardware design description information of the digital circuit.

[0095] Step 320: In the simulation compilation stage of the circuit, a simulation execution program and the corresponding library files of the deep learning framework are generated based on the hardware design description information and the deep learning framework.

[0096] Step 330: Obtain the boundary signal data input by the user for the digital circuit.

[0097] Step 340: During the simulation operation phase of the circuit, the boundary signal data corresponding to multiple instruction cycles is read through the simulation execution program, and the boundary signal data is converted into multiple input tensors corresponding to PyTorch.

[0098] In this embodiment, after the sim simulation executor starts, it can first perform initialization processing, and then dynamically load the corresponding .pt2 library file into the process space. The sim simulation executor can read boundary signal data of multiple instruction cycles at once and convert them into PyTorch tensor format.

[0099] Step 350: Through the simulation execution program, the multiple input tensors are passed to the scheduling code, and the scheduling code sequentially passes each of the input tensors to the computation function in the library file.

[0100] Step 360: The output tensor is obtained by parallel computation of multiple input tensors using the computation function, and the output tensor is returned to the simulation execution program.

[0101] In this embodiment, driven by the PyTorch backend, the computation function performs multiple cycle operations in parallel on the entire input tensor, and returns the output tensor to the sim simulation execution program after the computation is completed.

[0102] Step 370: The output tensor is parsed by the simulation execution program, and the output tensor is converted into a simulation result based on the parsing result.

[0103] In one embodiment of this example, after returning the output tensor to the simulation execution program, the method further includes: processing the output tensor by the simulation execution program in at least one of the following ways to obtain the simulation result corresponding to the circuit: printing the output tensor to the console; writing the output tensor to a log file; and generating a standard format Value Change Dump (VCD) waveform file based on the output tensor.

[0104] The technical solution provided by this invention, by acquiring the hardware design description information of a digital circuit, generating a simulation execution program and a library file corresponding to the deep learning framework based on the hardware design description information and the deep learning framework during the simulation compilation stage of the circuit, acquiring the boundary signal data input by the user for the digital circuit, and reading the boundary signal data corresponding to multiple instruction cycles through the simulation execution program during the simulation operation stage of the circuit, converting the boundary signal data into multiple input tensors corresponding to PyTorch, passing the multiple input tensors to the scheduling code through the simulation execution program, and sequentially passing each input tensor to the computation function in the library file through the scheduling code, calculating the multiple input tensors in parallel through the computation function to obtain the output tensor, and returning the output tensor to the simulation execution program, parsing the output tensor through the simulation execution program, and converting the output tensor into a simulation result based on the parsing result, can significantly accelerate the software simulation process of large-scale combinational logic circuits while ensuring accuracy, and reduce the development difficulty and maintenance cost of simulation tools.

[0105] Based on the above embodiments, in order to better express the technical solution of the present invention, the following preferred embodiments can be referred to:

[0106] Figure 4a This is a flowchart of a simulation method for a digital circuit during the compilation stage in this embodiment, as shown below. Figure 4a As shown, the method includes:

[0107] Step 1: Obtain the Verilog hardware design description information of the digital circuit input by the user;

[0108] Step 2: Refine and optimize the Verilog hardware design description information;

[0109] Step 3: Divide the hardware design into multiple sub-designs that are executed serially;

[0110] Step 4: Based on the intermediate representation information of the digital circuit and the input and output information of each sub-design, generate PyTorch execution code, and combine it with the custom Torch operator library to generate the PyTorch .pt2 library file;

[0111] Step 5: Generate the C++ glue code corresponding to the circuit, compile and link the glue code with the runtime library to obtain the sim simulation execution program.

[0112] Figure 4b This is a flowchart of a simulation method for a digital circuit during operation in this embodiment, as shown below. Figure 4b As shown, the method includes:

[0113] Step 11: Start the sim simulation execution program and obtain the boundary signal data input by the user;

[0114] Step 12: Dynamically load the .pt2 library file into the process space;

[0115] Step 13: The Sim simulation execution program initializes the input parameters of the Torch computation graph;

[0116] Step 14: Read the boundary signal data of the specified cycle and convert it into a Torch input tensor;

[0117] Step 15: Place the Torch input tensor on the GPU for parallel computation;

[0118] Step 16: Put the calculation results back to the CPU and execute the Dump operation in parallel;

[0119] Step 17: Determine whether the boundary signal data for all cycles has been executed. If yes, confirm the end of the simulation execution. If no, return to step 14 until the boundary signal data for all cycles has been executed.

[0120] This implementation method can significantly accelerate the software simulation process of large-scale combinational logic circuits while ensuring accuracy, and reduce the development difficulty and maintenance cost of simulation tools.

[0121] Figure 5 This is a schematic diagram of a digital circuit simulation device provided in an embodiment of the present invention. The device is applied in electronic devices, such as... Figure 5 As shown, the device includes: a hardware information acquisition module 410, a simulation compilation module 420, a boundary data acquisition module 430, and a simulation execution module 440.

[0122] The hardware information acquisition module 410 is used to acquire hardware design description information of digital circuits;

[0123] The simulation compilation module 420 is used to generate a simulation execution program and the library files corresponding to the deep learning framework based on the hardware design description information and the deep learning framework during the simulation compilation stage of the circuit.

[0124] Boundary data acquisition module 430 is used to acquire boundary signal data input by the user for the digital circuit;

[0125] The simulation execution module 440 is used to run the simulation execution program according to the boundary signal data and library files during the simulation execution phase of the circuit, and obtain the simulation results corresponding to the circuit.

[0126] The technical solution provided by this invention significantly accelerates the software simulation process of large-scale combinational logic circuits by acquiring hardware design description information of digital circuits, generating a simulation execution program and library files corresponding to the deep learning framework based on the hardware design description information and the deep learning framework during the simulation compilation stage of the circuit, acquiring boundary signal data input by the user for the digital circuit, and running the simulation execution program based on the boundary signal data and the library files during the simulation operation stage of the circuit. This approach is suitable for scenarios requiring repeated simulations, such as regression testing, and reduces the development difficulty and maintenance cost of simulation tools.

[0127] Based on the above embodiments, the simulation compilation module 420 includes:

[0128] The library file generation unit is used to analyze the hardware design description information, convert the hardware design description information into structured intermediate representation information based on the analysis results, divide the hardware design into multiple serially executed sub-designs based on the description information, generate the execution code corresponding to the deep learning framework PyTorch based on the intermediate representation information and the input and output information of each sub-design, define the PyTorch computation graph in the execution code, and generate the corresponding PyTorch library file based on the PyTorch execution code and the pre-built Torch operator library.

[0129] The simulation program generation unit is used to generate glue code corresponding to the circuit based on the intermediate representation information and the input and output information of each sub-design; wherein, the glue code includes at least one of the following: global variables passed to the runtime stage, simulation control logic code, and scheduling code that interacts with the PyTorch computation graph; the glue code is compiled and linked with the runtime library corresponding to the circuit to obtain the simulation execution program;

[0130] An operator library construction unit is used to acquire multiple artificial intelligence operators, divide the multiple artificial intelligence operators into a first operator and a second operator according to their implementation complexity; wherein the implementation complexity of the first operator is less than that of the second operator; map the first operator to a PyTorch built-in tensor operator; generate the Triton kernel code corresponding to the second operator, the kernel code being used to control the hardware characteristic information of the graphics processing unit (GPU).

[0131] The simulation execution module 440 includes:

[0132] The program execution unit is used to read boundary signal data corresponding to multiple instruction cycles through the simulation execution program, and convert the boundary signal data into multiple input tensors corresponding to PyTorch; through the simulation execution program, the multiple input tensors are passed to the scheduling code, and the scheduling code sequentially passes each input tensor to the calculation function in the library file; the calculation function performs parallel calculations on the multiple input tensors to obtain an output tensor, and returns the output tensor to the simulation execution program;

[0133] The output tensor processing unit is used to process the output tensor in at least one of the following ways through the simulation execution program to obtain the simulation result corresponding to the circuit: printing the output tensor to the console; writing the output tensor to a log file; and generating a standard format value change dump VCD waveform file based on the output tensor.

[0134] The above-described apparatus can execute the methods provided in all the foregoing embodiments of the present invention, and has the corresponding functional modules and beneficial effects for executing the above methods. Technical details not described in detail in the embodiments of the present invention can be found in the methods provided in all the foregoing embodiments of the present invention.

[0135] Figure 6 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0136] like Figure 6As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0137] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0138] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processing (DSP) processors, and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as digital circuit simulation methods.

[0139] In some embodiments, the digital circuit simulation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the digital circuit simulation method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the digital circuit simulation method by any other suitable means (e.g., by means of firmware).

[0140] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0141] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0142] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0143] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0144] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0145] A computing system can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and Virtual Private Servers (VPS) in terms of management difficulty and weak business scalability.

[0146] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0147] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A simulation method of a digital circuit, characterized by, The method comprises: obtaining hardware design description information of a digital circuit; in the simulation compilation phase of the circuit, generating a simulation execution program and a library file corresponding to the deep learning framework according to the hardware design description information and the deep learning framework; obtaining boundary signal data input by a user for the digital circuit; in the simulation running phase of the circuit, running the simulation execution program according to the boundary signal data and the library file to obtain a simulation result corresponding to the circuit.

2. The method of claim 1, wherein, According to the hardware design description information and the deep learning framework, the library file corresponding to the deep learning framework is generated, comprising: analyzing the hardware design description information, and converting the hardware design description information into structured intermediate representation information according to the analysis result; dividing the hardware design into multiple serially executed sub-designs according to the description information; generating execution code corresponding to the deep learning framework PyTorch according to the intermediate representation information and the input and output information of each sub-design; the execution code defines a PyTorch computation graph; generating a library file corresponding to PyTorch according to the execution code corresponding to PyTorch and a pre-constructed Torch operator library.

3. The method of claim 2, wherein, According to the hardware design description information and the deep learning framework, the simulation execution program is generated, comprising: generating glue code corresponding to the circuit according to the intermediate representation information and the input and output information of each sub-design; wherein the glue code includes at least one of the following: global variables passed to the running phase, simulation control logic code, and scheduling code for interacting with the PyTorch computation graph; compiling and linking the glue code with the runtime library corresponding to the circuit to obtain the simulation execution program.

4. The method of claim 2, wherein, Pre-constructing the Torch operator library comprises: obtaining multiple artificial intelligence operators, and dividing the multiple artificial intelligence operators into first operators and second operators according to implementation complexity; wherein the implementation complexity of the first operator is less than that of the second operator; mapping the first operator to a built-in tensor operator of PyTorch; generating Triton kernel code corresponding to the second operator, which is used to control the hardware characteristic information of a graphics processing unit (GPU).

5. The method of claim 3, wherein, According to the boundary signal data and the library file, the simulation execution program is run, comprising: reading boundary signal data corresponding to multiple instruction cycles through the simulation execution program, and converting the boundary signal data into multiple input tensors corresponding to PyTorch; passing the multiple input tensors to the scheduling code through the simulation execution program, and sequentially passing each input tensor to a calculation function in the library file in the scheduling code; parallel computing output tensors through the calculation function, and returning the output tensors to the simulation execution program.

6. The method of claim 5, wherein, After returning the output tensors to the simulation execution program, further comprising: processing the output tensors through the simulation execution program in at least one of the following ways to obtain a simulation result corresponding to the circuit: printing the output tensors to the console; writing the output tensor into a log file; generating a value change dump (VCD) waveform file in a standard format according to the output tensor.

7. A simulation apparatus of a digital circuit, characterized by comprising: The device comprises: a hardware information acquisition module configured to acquire hardware design description information of the digital circuit; a simulation compilation module configured to generate a simulation execution program and a library file corresponding to the deep learning framework according to the hardware design description information and the deep learning framework in a simulation compilation phase of the circuit; a boundary data acquisition module configured to acquire boundary signal data input by a user for the digital circuit; a simulation running module configured to run the simulation execution program according to the boundary signal data and the library file in a simulation running phase of the circuit to obtain a simulation result corresponding to the circuit.

8. An electronic device, comprising: The electronic device comprises: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the simulation method of the digital circuit according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to execute the simulation method of the digital circuit according to any one of claims 1-6 when executed by the processor.

10. A computer program product, characterised in that, The computer program product comprises a computer program, and the computer program, when executed by the processor, implements the simulation method of the digital circuit according to any one of claims 1-6.

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