Training System and Method for High-Speed Parallel Port IP

Abstract

The present application relates to the field of integrated circuit technologies and provides a training system and method for a high-speed parallel port IP. The system includes: a high-speed transceiver for transmitting and receiving data and command signals; a delay and reference voltage regulator for performing delay adjustment and reference voltage adjustment; a multi-branch generator for separately generating command combinations, data sequences, and adjustment signals; a microprocessor for controlling the generation of the multi-branch generator based on a first instruction combination; and an instruction memory for storing the first instruction combination. The microprocessor is further configured to generate, based on the first instruction combination, a first scanning strategy including a first scanning object, which is determined based on a first high-speed parallel port IP. The microprocessor controls the generation of the multi-branch generator to utilize the delay and reference voltage regulator to implement the first scanning strategy for the first scanning object in the data and command signals so as to complete eye diagram adaptation. In this way, flexibility and compatibility are achieved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a training system and method for a high-speed parallel interface IP. Background Art

[0002] A chip Intellectual Property Core (IP) is also called chip IP, which refers to a mature design of a circuit module with independent functions. By using the circuit module design included in the chip IP and combining the chip IP with the independently designed circuit part, the overall design workload can be reduced and the development cycle can be shortened. With the development of artificial intelligence and high-performance computer technology, high-speed parallel interface IPs with data storage and inter-chip interconnection characteristics face increasingly high performance requirements. In addition to requiring higher overall performance, such as a data transfer rate of up to 3200 megabits per second (Mbps), a large number of read and write eye diagram trainings are also required to increase system stability. In the prior art, several common high-speed parallel interface IPs, such as double data rate synchronous dynamic random access memory (DDR SDRAM), abbreviated as DDR, high bandwidth memory (HBM), low power double data rate SDRAM (LPDDR), die-to-die (D2D), rely on a pure hardware training structure and perform eye diagram training by configuring a hardware state machine. In this way, it is difficult to adapt and solve problems that are beyond the initial design expectations, and it is also difficult to adapt different strategies based on different application scenarios, which is not conducive to meeting customer customization requirements.

[0003] Therefore, this application provides a training system and method for a high-speed parallel interface IP to address the technical problems in the prior art. Summary of the Invention

[0004] In a first aspect, the present application provides a training system for a high-speed parallel port IP. The training system includes: a high-speed transceiver for transmitting and receiving data and command signals; a delay and reference voltage regulator connected to the high-speed transceiver for performing delay adjustment and reference voltage adjustment on the data and command signals; a multi-branch generator connected to the delay and reference voltage regulator for separately generating a command combination for controlling path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training; a microprocessor connected to the multi-branch generator for controlling the generation of the multi-branch generator based on a first instruction combination; an instruction memory connected to the microprocessor for storing the first instruction combination, and the instruction memory is configured to be editable by downloading training firmware. The microprocessor is further configured to generate a first scanning strategy including a first scanning object based on the first instruction combination, where the first scanning object and the first scanning strategy are determined based on a first high-speed parallel port IP. The microprocessor controls the generation of the multi-branch generator to implement the first scanning strategy for the first scanning object in the data and command signals by using the delay and reference voltage regulator, so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP.

[0005] Through the first aspect of the present application, the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software is realized by combining software and hardware. The flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements is achieved. The training scheme is implemented from three aspects: control path, data path, and eye diagram adaptation, which simplifies the overall design complexity. It is beneficial to adapt to actual requirements by downloading different instruction combinations, and the scanning object and scanning strategy are determined by combining the characteristics and requirements of the high-speed parallel port IP. Furthermore, the corresponding command combination, data sequence, and adjustment signal can be generated by controlling the generation of the multi-branch generator, and the real eye diagram is adapted to find the optimal position by adjusting the weights of eye height and eye width, etc., so as to improve the signal transmission quality. It is beneficial to reduce the hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse vendor chips.

[0006] In a possible implementation manner of the first aspect of the present application, the data and command signals include an address signal and a control signal transmitted through an address control bus, a transmit data signal transmitted through a transmit link, and a receive data signal transmitted through a receive link.

[0007] In a possible implementation of the first aspect of the present application, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal, and the first clock active interval, and the first scanning strategy adapts to the data link mode, link overall delay, link voltage, and packaging requirements associated with the bandwidth memory IP.

[0008] In a possible implementation of the first aspect of the present application, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal, and the second clock active interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP.

[0009] In a possible implementation of the first aspect of the present application, the microprocessor controls the generation of the multi-branch generator such that the multi-branch generator generates a first command combination, a first data sequence, and a first adjustment signal corresponding to the first instruction combination.

[0010] In a possible implementation of the first aspect of the present application, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first command combination includes an address coding error correction mechanism, and when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first command combination does not include an address coding error correction mechanism and includes an address error retry mechanism.

[0011] In a possible implementation of the first aspect of the present application, the delay adjustment is used to determine the eye width, and the reference voltage adjustment is used to determine the eye height and signal voltage amplitude.

[0012] In a possible implementation of the first aspect of the present application, the command combination includes a bus command and a command transceiver timing sequence.

[0013] In a possible implementation of the first aspect of the present application, the data sequence includes a pseudo-random binary sequence and a special symbol sequence determined based on the first high-speed parallel port IP.

[0014] In a possible implementation of the first aspect of the present application, the adjustment signal includes an increment / decrement and a polarity, and the increment / decrement and the polarity are used to control the delay chain in the delay and reference voltage regulator.

[0015] In a possible implementation of the first aspect of the present application, the multi-branch generator includes a command generator, a data generator, a data comparator, and a training controller. Among them, the command generator is used to generate the command combination under the control of the microprocessor, the data generator is used to generate the data sequence under the control of the microprocessor, the data comparator is used to generate a comparison result based on the data sequence, and the training controller is used to generate the adjustment signal under the control of the microprocessor.

[0016] In a possible implementation of the first aspect of the present application, the training firmware is a programmable specific state machine, and the microprocessor is a general state machine and is configured to execute the specific state machine based on the training firmware downloaded to the instruction memory.

[0017] In a possible implementation of the first aspect of the present application, the first instruction combination stored in the instruction memory is configured to be editable in real time by downloading the training firmware.

[0018] In a possible implementation of the first aspect of the present application, the training system further includes a data memory, the data memory is connected to the microprocessor, and the microprocessor uses the data memory to execute the first scanning strategy.

[0019] In a second aspect, an embodiment of the present application further provides a training method for a high-speed parallel interface IP. The training method is applied to a training system, and the training system includes a high-speed transceiver, a delay and reference voltage regulator, a multi-branch generator, a microprocessor, and an instruction memory. The training method includes: through the high-speed transceiver, sending and receiving data and command signals; through the delay and reference voltage regulator, performing delay adjustment and reference voltage adjustment on the data and command signals; through the multi-branch generator, respectively generating a command combination for controlling path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training; through the microprocessor, controlling the generation of the multi-branch generator based on the first instruction combination, and generating a first scanning strategy including a first scanning object based on the first instruction combination, where the first scanning object and the first scanning strategy are determined based on the first high-speed parallel interface IP, the instruction memory is used to store the first instruction combination, and the instruction memory is configured to be editable by downloading training firmware; through the microprocessor, controlling the generation of the multi-branch generator to use the delay and reference voltage regulator to implement the first scanning strategy on the first scanning object in the data and command signals so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel interface IP.

[0020] Through the second aspect of the present application, the combination of hardware and software realizes the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software, achieving flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training scheme is implemented from three aspects: the control path, the data path, and the eye diagram adaptation, simplifying the overall design complexity. It is beneficial to adapt to actual requirements by issuing different instruction combinations, and realizes determining the scanning object and scanning strategy by combining the characteristics and requirements of the high-speed parallel IP, and then generating corresponding command combinations, data sequences, and adjustment signals by controlling the generation of the multi-branch generator. It realizes adapting to the real eye diagram to find the optimal position by adjusting the weights of the eye height and eye width, etc., thereby improving the signal transmission quality, reducing the hardware overhead and training complexity, and helping to be compatible with complex application environments and diverse vendor particles.

[0021] In a possible implementation manner of the second aspect of the present application, the data and command signals include an address signal and a control signal transmitted through an address control bus, a transmission data signal transmitted through a transmission link, and a reception data signal transmitted through a reception link.

[0022] In a possible implementation manner of the second aspect of the present application, when the first high-speed parallel IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal, and a first clock valid interval, and the first scanning strategy adapts to the data link mode, link overall delay, link voltage, and packaging requirements associated with the bandwidth memory IP.

[0023] In a possible implementation manner of the second aspect of the present application, when the first high-speed parallel IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal, and a second clock valid interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 Schematic diagram of a training system for a high-speed parallel IP according to the first implementation manner provided by the embodiments of the present application;

[0026] Figure 2 Schematic diagram of a second implementation of a training system for a high-speed parallel port IP provided by an embodiment of the present application;

[0027] Figure 3 Flow schematic diagram of a training method for a high-speed parallel port IP provided by an embodiment of the present application. Specific implementation

[0028] The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0029] It should be understood that in the description of the present application, "at least one" means one or more, and "a plurality" means two or more. In addition, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions unless otherwise specified, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0030] Figure 1 Schematic diagram of a training system for a high-speed parallel port IP according to a first implementation provided by an embodiment of the present application. As Figure 1 shown, the training system A100 includes: a high-speed transceiver A102 for transmitting and receiving data and command signals; a delay and reference voltage regulator A104 connected to the high-speed transceiver A102 for performing delay adjustment and reference voltage adjustment on the data and command signals; a multi-branch generator A110 connected to the delay and reference voltage regulator A104 for separately generating a command combination for controlling path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training; a microprocessor A120 connected to the multi-branch generator A110 for controlling the generation of the multi-branch generator A110 based on a first instruction combination; an instruction memory A130 connected to the microprocessor A120 for storing the first instruction combination, and the instruction memory A130 is configured to be editable by downloading a training firmware A101. The microprocessor A120 is further configured to generate a first scanning strategy including a first scanning object based on the first instruction combination, and the first scanning object and the first scanning strategy are determined based on a first high-speed parallel port IP. Wherein, the microprocessor A120 controls the generation of the multi-branch generator A110 to use the delay and reference voltage regulator A104 to perform the first scanning strategy on the first scanning object in the data and command signals so as to complete the eye diagram adaptation of the high-speed transceiver A102 relative to the first high-speed parallel port IP.

[0031] Figure 1The training system shown is used for eye diagram adaptation training of high-speed parallel IP, which can flexibly adapt to various application scenarios and different strategies, and can be applied to high-speed parallel IP such as double data rate synchronous dynamic random access memory (doubledatarate SDRAM, DDR SDRAM), high bandwidth memory (high bandwidth memory, HBM), low power double data rate memory (low power doubledata rate SDRAM, LPDDR), die-to-die (D2D), etc., and can also be applied to other interface circuit design, circuit module design, chip IP, etc. using high-speed parallel data transmission interface. In the use scenarios of artificial intelligence and high-performance computing, high-speed parallel IP needs to provide higher high-speed interface performance in data storage, inter-chip interconnection, etc., such as providing a data transmission rate of more than 3200 megabits per second (Mbps), and at the same time needs to adapt the real eye diagram so as to find the best position by adjusting the eye height and eye width weights, thereby improving the signal transmission quality. After the design of the high-speed parallel port IP is completed, it needs to be simulated, verified and tested. However, the scenario requirements and algorithm strategies considered during the design may not cover the actual situations encountered in actual applications. For example, the development of high-speed data transmission requirements may cause the increase in data bit width to exceed the upper limit assumed during the design. Another example is the application of new communication protocols and new communication frequency bands, and another example is the customization requirements proposed by customers. In addition, device failures, device aging, and other interference factors may cause the performance of the chip to deviate from the predictions during the design. To this end, eye diagram training is required to improve the overall transceiver performance of the system and increase system stability. However, most of the high-speed parallel port IP is hardware entity solidified on a highly integrated chip, such as integrated into a system-level chip as a chip interface circuit module. Therefore, the training scheme for high-speed parallel port IP needs to consider factors such as hardware overhead and training complexity. It is also necessary to consider the requirements for training accuracy put forward by the development of high-speed data transmission, as well as compatibility requirements including compatibility with complex application environments and diverse supplier particles. The following is combined with Figure 1 It is described in detail how the training system A100 for high-speed parallel port IP provided in the embodiment of the present application copes with these challenges.

[0032] See also Figure 1 , Figure 1The training system A100 shown includes two major parts. The first part is a microprocessor A120, a multi-branch generator A110, and a delay and reference voltage regulator A104 solidified in the hardware circuit. Here, the multi-branch generator A110 generates command combinations for control path training, data sequences for data path training, and adjustment signals for eye diagram adaptation training respectively. In this way, eye diagram adaptation training can be completed through a scanning algorithm using the generation of the multi-branch generator A110, and the delay adjustment and reference voltage adjustment of the delay and reference voltage regulator A104. The multi-branch generator A110 may include multiple branches, corresponding to the training of the control path, the training of the data path, and the eye diagram adaptation training. For example, a branch in the multi-branch generator A110 may be a command generator, which is used to generate various commands required in the training process, including command transmission and reception timing, that is, to generate a command combination for control path training. For another example, another branch in the multi-branch generator A110 can be used for data generation and data comparison, generating various vector sources required by the data path during the training process, such as the commonly used pseudo-random binary sequence (PRBS), etc., and for comparison of sent data and received data, that is, generating a data sequence for data path training. For another example, another branch in the multi-branch generator A110 can be a training controller, which is responsible for configuring the algorithm to execute the delay chain and the increase and decrease amount and polarity of the voltage. For example, the delay chain entity in the delay and reference voltage regulator A104 can be incremented or decremented by the training controller, and the reference voltage level in the delay and reference voltage regulator A104 can be adjusted by the training controller, that is, generating an adjustment signal for eye diagram adaptation training. Generally, the increase and decrease amount processing of the delay chain entity is used to determine the eye width, and the adjustment of the reference voltage level is used to determine the eye height and signal voltage amplitude, so it can be used to adapt the real eye diagram. The microprocessor A120 is used to control the hardware part. The microprocessor A120 controls the generation of the multi-branch generator A110 so as to use the delay and reference voltage regulator A104 to implement the first scanning strategy for the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver A102 relative to the first high-speed parallel port IP. In this way, the hardware part is provided for realizing high-speed timing control and eye diagram adaptation training by using the microprocessor A120, the multi-branch generator A110 and the delay and reference voltage regulator A104 solidified in the hardware circuit.

[0033] Continue reading Figure 1 , Figure 1 The training system A100 shown includes two parts. The second part is the software part, corresponding to Figure 1The training firmware A101 shown in []. The training firmware A101 is used to issue an instruction combination to the instruction memory A130. Then, the microprocessor A120 reads the instruction memory A130 to obtain the issued instruction combination, and the microprocessor A120 interprets, compiles, and executes the instruction combination. The versatility of the microprocessor A120 and the compilability of the instruction set mean that different usage scenarios, protocol coverage ranges, etc. can be covered by issuing different instruction combinations and then executed by the microprocessor A120. Therefore, the high-speed data transmission requirements, changes in communication protocols, and user customization requirements can be flexibly adapted through a combination of software and hardware. Therefore, Figure 1The training system A100 shown can, through the software part mainly composed of the training firmware A101, schedule all resources for the physical layer of the high-speed parallel port IP and downstream devices, etc. through the microprocessor A120 to implement the training algorithm. The training firmware A101 can change the instruction combination in real time as needed, equivalent to a programmable state machine, while the microprocessor A120 executes the instruction combination in the instruction memory A130, equivalent to a general state machine, and executes the loop of a specific state machine according to the instruction combination. Here, by utilizing the characteristics of the multi-branch generator A110 in generation (the multi-branch generator A110 respectively generates a command combination for controlling path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training), the training scheme can be implemented from three aspects: the control path, the data path, and the eye diagram adaptation, simplifying the overall design complexity and facilitating the adaptation to actual requirements by issuing different instruction combinations. The microprocessor A120 is used to control the generation of the multi-branch generator A110 based on the first instruction combination, and the microprocessor A120 is also used to generate a first scanning strategy including a first scanning object based on the first instruction combination, and the first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP. In this way, the scanning object and the scanning strategy are determined in combination with the characteristics and requirements of the specific high-speed parallel port IP, and then the corresponding command combination, data sequence, and adjustment signal can be generated by controlling the generation of the multi-branch generator A110, realizing the combination of high-speed timing control on the hardware and programmability on the software through the combination of software and hardware. The microprocessor A120 controls the generation of the multi-branch generator A110 to utilize the delay and reference voltage regulator A104 to execute the first scanning strategy on the first scanning object in the data and command signals to complete the eye diagram adaptation of the high-speed transceiver A102 relative to the first high-speed parallel port IP. In this way, the real eye diagram is adapted to find the optimal position by adjusting the eye height and eye width weights, etc., thereby improving the signal transmission quality. And through the optimized design of the hardware part (microprocessor A120, multi-branch generator A110, and delay and reference voltage regulator A104), the overall design complexity is simplified, and the design complexity of controlling the hardware through the software part (training firmware A101) is also simplified. Through the update of the training firmware A101, new changes and new requirements encountered in actual applications can be covered, and the eye height and eye width weights can be adjusted through the reverse compensation algorithm or adjustment algorithm, etc. to adapt to the real eye diagram, thereby improving the signal transmission quality, which is beneficial to reducing the hardware cost and training complexity and helps to be compatible with complex application environments and diverse vendor particles.

[0034] In summary, Figure 1The training system A100 shown realizes the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software through the combination of software and hardware, and realizes the flexible adaptation to the high-speed data transmission requirements, communication protocol changes, and user customization requirements. The training solution is implemented from three aspects: the control path, the data path, and the eye diagram adaptation, which simplifies the overall design complexity and is conducive to adapting to actual requirements by issuing different instruction combinations. By combining the characteristics and requirements of the high-speed parallel IP, the scanning object and scanning strategy are determined, and then the corresponding command combination, data sequence, and adjustment signal can be generated by controlling the generation of the multi-branch generator A110. It realizes the adaptation to the real eye diagram, so as to find the best position by adjusting the eye height and eye width weights, etc., thereby improving the signal transmission quality, reducing the hardware overhead and training complexity, and being conducive to compatible with complex application environments and diverse vendor particles.

[0035] In a possible implementation manner, the data and command signals include an address signal and a control signal transmitted through an address control bus, a transmission data signal transmitted through a transmission link, and a reception data signal transmitted through a reception link. The high-speed transceiver A102 is used for the transmission and reception of data and command signals, and the high-speed transceiver A102 can be connected to the address control bus, the transmission link, and the reception link. In this way, the eye diagram adaptation training of the high-speed parallel IP is realized, and the high-speed data transmission requirements, communication protocol changes, and user customization requirements can be flexibly adapted.

[0036] In some embodiments, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmitted data signal, the received data signal, and the first clock active interval, and the first scanning strategy adapts to the data link mode, the overall link delay, the link voltage, and the packaging requirements associated with the bandwidth memory IP. As described above, the combination of software and hardware realizes the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software, realizes the flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements, and realizes the training scheme from three aspects: the control path, the data path, and the eye diagram adaptation, simplifies the overall design complexity, is conducive to adapting to actual requirements by issuing different instruction combinations, realizes determining the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP, and then can generate corresponding command combinations, data sequences, and adjustment signals by controlling the generation of the multi-branch generator A110, realizes adapting to the real eye diagram so as to find the best position by adjusting the weights of the eye height and eye width, etc., thereby improving the signal transmission quality. Here, when the first high-speed parallel port IP is a high-bandwidth memory IP, it is necessary to adapt to the characteristics of the high-bandwidth memory IP to formulate the scanning strategy and determine the scanning object. Therefore, for the high-bandwidth memory IP, the first scanning object includes the address signal, the transmitted data signal, the received data signal, and the first clock active interval, and moreover, the first scanning strategy adapts to the data link mode, the overall link delay (e.g., 20 nanoseconds), the link voltage, and the packaging requirements associated with the bandwidth memory IP. In addition, the communication protocol for the high-bandwidth memory IP generally stipulates a maximum of sixteen channels, so the serial or parallel method can be selected to adapt to the timeliness of multiple channels. Thus, it is conducive to reducing the hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse vendor particles.

[0037] In some embodiments, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmitted data signal, the received data signal, and the second clock active interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. As described above, the combination of hardware and software realizes the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software, realizes flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements, and realizes the training scheme from three aspects: the control path, the data path, and the eye diagram adaptation, simplifies the overall design complexity, is conducive to adapting to actual requirements by issuing different instruction combinations, realizes determining the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP, and then can generate corresponding command combinations, data sequences, and adjustment signals by controlling the generation of the multi-branch generator A110, realizes adapting to the real eye diagram so as to find the optimal position by adjusting the eye height and eye width weights, etc., thereby improving the signal transmission quality. Here, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, it is necessary to adapt to the characteristics of the double data rate synchronous dynamic random access memory IP to formulate the scanning strategy and determine the scanning object. Therefore, for the double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmitted data signal, the received data signal, and the second clock active interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. It should be understood that as mentioned above, the first scanning object for the high-bandwidth memory IP includes the first clock active interval. Here, the first scanning object for the double data rate synchronous dynamic random access memory IP includes the second clock active interval, and the first clock active interval is different from the second clock active interval. In this way, determining the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP is realized.

[0038] In a possible implementation manner, the microprocessor A120 controls the generation of the multi-branch generator A110 so that the multi-branch generator A110 generates a first command combination, a first data sequence, and a first adjustment signal corresponding to the first instruction combination. In this way, determining the scanning object and scanning strategy in combination with the characteristics and requirements of the specific high-speed parallel port IP is realized, and then corresponding command combinations, data sequences, and adjustment signals can be generated by controlling the generation of the multi-branch generator A110. The combination of hardware and software realizes the combination of high-speed timing control on the hardware and programmability on the software.

[0039] In some embodiments, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first command combination includes an address coding error correction mechanism. When the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first command combination does not include an address coding error correction mechanism and includes an address error retry mechanism. As mentioned above, corresponding scan strategies and scan objects are formulated for the high-bandwidth memory IP and the double data rate synchronous dynamic random access memory IP respectively, so that the characteristics and requirements of the specific high-speed parallel port IP can be combined. Here, the protocol for the high-bandwidth memory IP stipulates a sound error correction mechanism in address coding, such as Advanced Error Report (AER). In contrast, the protocol for the double data rate synchronous dynamic random access memory IP has no error correction mechanism in address coding. When the check value goes wrong, no error is reported, but a retry is initiated through the address error retry mechanism. In this way, the scan object and scan strategy are determined in combination with the characteristics and requirements of the high-speed parallel port IP, and then the corresponding command combination, data sequence, and adjustment signal can be generated by controlling the generation of the multi-branch generator A110, realizing the adaptation to the real eye diagram, so as to find the optimal position by adjusting the eye height and eye width weights, etc., thereby improving the signal transmission quality, being beneficial to reducing the hardware overhead and training complexity, and helping to be compatible with complex application environments and diverse vendor particles.

[0040] In a possible implementation manner, the delay adjustment is used to determine the eye width, and the reference voltage adjustment is used to determine the eye height and the signal voltage amplitude. In this way, the adaptation to the real eye diagram is realized, which helps to improve the signal transmission quality.

[0041] In a possible implementation manner, the command combination includes a bus command and a command transceiver timing sequence. In this way, the generation of the command combination for controlling the path training is realized, which is beneficial to implementing the training scheme from the control path aspect, simplifies the overall design complexity, and is beneficial to adapting to the actual requirements by issuing different instruction combinations.

[0042] In a possible implementation manner, the data sequence includes a pseudo-random binary sequence and a special symbol sequence determined based on the first high-speed parallel port IP. In this way, the generation of the data sequence for data path training is realized, which is beneficial to implementing the training scheme from the data path aspect, simplifies the overall design complexity, and is beneficial to adapting to the actual requirements by issuing different instruction combinations.

[0043] In a possible implementation, the adjustment signal includes an increment / decrement amount and a polarity, and the increment / decrement amount and the polarity are used to control the delay chain in the delay and reference voltage regulator. In this way, an adjustment signal for eye diagram adaptation training is generated, which is beneficial to implementing the training scheme from the aspect of eye diagram adaptation, simplifies the overall design complexity, and is beneficial to adapting to actual requirements by issuing different instruction combinations.

[0044] In a possible implementation, the multi-branch generator A110 includes a command generator, a data generator, a data comparator, and a training controller. Among them, the command generator is used to generate the command combination under the control of the microprocessor A120, the data generator is used to generate the data sequence under the control of the microprocessor A120, the data comparator is used to generate a comparison result based on the data sequence, and the training controller is used to generate the adjustment signal under the control of the microprocessor A120. In this way, using the characteristics of the multi-branch generator A110 in terms of generation, the training scheme can be implemented from three aspects: the control path, the data path, and eye diagram adaptation, simplifies the overall design complexity, is beneficial to adapting to actual requirements by issuing different instruction combinations, and provides the hardware part for implementing high-speed timing control and eye diagram adaptation training.

[0045] In a possible implementation, the training firmware A101 is a programmable specific state machine, and the microprocessor A120 is a general state machine and is configured to execute the specific state machine based on the training firmware issued to the instruction memory A130. The training firmware A101 can change the instruction combination in real time according to needs, which is equivalent to a programmable state machine, while the microprocessor A120 executes the instruction combination in the instruction memory A130, which is equivalent to a general state machine, and executes the loop of the specific state machine according to the instruction combination. Here, using the characteristics of the multi-branch generator A110 in terms of generation (the multi-branch generator A110 respectively generates a command combination for control path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training), the training scheme can be implemented from three aspects: the control path, the data path, and eye diagram adaptation, simplifies the overall design complexity, and is beneficial to adapting to actual requirements by issuing different instruction combinations.

[0046] In a possible implementation, the first instruction combination stored in the instruction memory A130 is configured to be editable in real time by issuing the training firmware. In this way, real-time response is achieved.

[0047] In a possible implementation, the training system A100 further includes a data memory connected to the microprocessor A120, and the microprocessor A120 utilizes the data memory to execute the first scanning strategy. In this way, it is realized to determine the scanning object and the scanning strategy in combination with the characteristics and requirements of a specific high-speed parallel port IP.

[0048] Figure 2 FIG. is a schematic diagram of a training system for a high-speed parallel port IP according to a second implementation manner provided by an embodiment of the present application. As Figure 2 shown, the training system B200 includes: a high-speed transceiver B202 for transmitting and receiving data and command signals; a delay and reference voltage regulator B204 connected to the high-speed transceiver B202 for performing delay adjustment and reference voltage adjustment on the data and command signals; a multi-branch generator B210 connected to the delay and reference voltage regulator B204 for respectively generating a command combination for controlling path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training; a microprocessor B220 connected to the multi-branch generator B210 for controlling the generation of the multi-branch generator B210 based on a first instruction combination; an instruction memory B230 connected to the microprocessor B220 for storing the first instruction combination, and the instruction memory B230 is configured to be editable by downloading a training firmware B201. The microprocessor B220 is further configured to generate a first scanning strategy including a first scanning object based on the first instruction combination, where the first scanning object and the first scanning strategy are determined based on a first high-speed parallel port IP. Wherein, the microprocessor B220 controls the generation of the multi-branch generator B210 to utilize the delay and reference voltage regulator B204 to implement the first scanning strategy for the first scanning object in the data and command signals so as to complete the eye diagram adaptation of the high-speed transceiver B202 relative to the first high-speed parallel port IP.

[0049] Figure 2It is also shown that the multi-branch generator B210 includes a command generator B212, a data generator B214, a data comparator B216, and a training controller B218. Among them, the command generator B212 is used to generate the command combination under the control of the microprocessor B220, the data generator B214 is used to generate the data sequence under the control of the microprocessor B220, the data comparator B216 is used to generate a comparison result based on the data sequence, and the training controller B218 is used to generate the adjustment signal under the control of the microprocessor B220. The training system B200 further includes a data memory B232, and the data memory B232 is connected to the microprocessor B220, and the microprocessor B220 uses the data memory B232 to execute the first scan strategy. In this way, by utilizing the characteristics of the multi-branch generator B210 in terms of generation, the training scheme can be implemented from three aspects: the control path, the data path, and the eye diagram adaptation, simplifying the overall design complexity, facilitating the adaptation to actual requirements by issuing different instruction combinations, and providing a hardware part for implementing high-speed timing control and eye diagram adaptation training.

[0050] In summary, Figure 2 The shown training system B200 realizes the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software through the combination of software and hardware, realizes the flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements, implements the training scheme from three aspects: the control path, the data path, and the eye diagram adaptation, simplifies the overall design complexity, facilitates the adaptation to actual requirements by issuing different instruction combinations, realizes the determination of the scan object and scan strategy by combining the characteristics and requirements of the high-speed parallel port IP, and then can generate the corresponding command combination, data sequence, and adjustment signal by controlling the generation of the multi-branch generator B210, realizes the adaptation to the real eye diagram to find the optimal position by adjusting the weights of the eye height and eye width, etc., thereby improving the signal transmission quality, is conducive to reducing the hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse vendor particles.

[0051] Figure 3 It is a schematic flowchart of a training method for a high-speed parallel port IP provided by an embodiment of the present application. The training method is applied to a training system, and the training system includes a high-speed transceiver, a delay and reference voltage regulator, a multi-branch generator, a microprocessor, and an instruction memory. As Figure 3 shown, the training method includes the following steps.

[0052] Step S302: Transceive data and command signals through the high-speed transceiver.

[0053] Step S304: Perform delay adjustment and reference voltage adjustment on the data and command signals through the delay and reference voltage regulator.

[0054] Step S306: Respectively generate a command combination for controlling path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training through the multi-branch generator.

[0055] Step S308: Control the generation of the multi-branch generator by the microprocessor based on the first instruction combination, and generate a first scanning strategy including a first scanning object based on the first instruction combination, where the first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP. The instruction memory is used to store the first instruction combination, and the instruction memory is configured to be editable by downloading training firmware.

[0056] Step S310: Control the generation of the multi-branch generator by the microprocessor to implement the first scanning strategy for the first scanning object in the data and command signals by using the delay and reference voltage regulator, so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP.

[0057] In summary, Figure 3 The training method shown realizes the combination of high-speed timing control and eye diagram adaptation training in hardware and programmability in software by combining software and hardware. It realizes flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training scheme is implemented from three aspects: control path, data path, and eye diagram adaptation, which simplifies the overall design complexity. It is beneficial to adapt to actual requirements by downloading different instruction combinations, realizes determining the scanning object and scanning strategy by combining the characteristics and requirements of the high-speed parallel port IP, and then can generate corresponding command combinations, data sequences, and adjustment signals by controlling the generation of the multi-branch generator, realizes adapting to the real eye diagram to find the best position by adjusting the weights of eye height and eye width, etc., so as to improve the signal transmission quality, is beneficial to reducing hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse vendor chips.

[0058] In a possible implementation manner, the data and command signals include an address signal and a control signal transmitted through an address control bus, a transmitted data signal transmitted through a transmission link, and a received data signal transmitted through a reception link. In this way, the eye diagram adaptation training of the high-speed parallel port IP is realized, and the high-speed data transmission requirements, changes in communication protocols, and user customization requirements can be flexibly adapted.

[0059] In some embodiments, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal, and the first clock active interval, and the first scanning strategy adapts to the data link mode, the overall link delay, the link voltage, and the packaging requirements associated with the bandwidth memory IP. As described above, the combination of software and hardware realizes the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software, realizes the flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements, and realizes the training scheme from three aspects: the control path, the data path, and the eye diagram adaptation, simplifies the overall design complexity, is conducive to adapting to actual requirements by issuing different instruction combinations, realizes determining the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP, and then can generate corresponding command combinations, data sequences, and adjustment signals by controlling the generation of the multi-branch generator, realizes adapting to the real eye diagram so as to find the optimal position by adjusting the eye height and eye width weights, etc., thereby improving the signal transmission quality. Here, when the first high-speed parallel port IP is a high-bandwidth memory IP, it is necessary to adapt to the characteristics of the high-bandwidth memory IP to formulate the scanning strategy and determine the scanning object. Therefore, for the high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal, and the first clock active interval, and moreover, the first scanning strategy adapts to the data link mode, the overall link delay (such as 20 nanoseconds), the link voltage, and the packaging requirements associated with the bandwidth memory IP. In addition, the communication protocol for the high-bandwidth memory IP generally stipulates up to sixteen channels, so a serial or parallel method can be selected to adapt to the timeliness of multiple channels. In this way, it is conducive to reducing the hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse vendor particles.

[0060] In some embodiments, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmitted data signal, the received data signal, and the second clock active interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. As described above, the combination of hardware and software realizes the combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software, realizes the flexible adaptation to the high-speed data transmission requirements, changes in communication protocols, and user customization requirements, and realizes the training scheme from three aspects: the control path, the data path, and the eye diagram adaptation, simplifies the overall design complexity, is conducive to adapting to the actual requirements by issuing different instruction combinations, realizes determining the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP, and then can generate the corresponding command combination, data sequence, and adjustment signal by controlling the generation of the multi-branch generator, realizes adapting to the real eye diagram so as to find the optimal position by adjusting the eye height and eye width weights, etc., thereby improving the signal transmission quality. Here, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, it is necessary to adapt to the characteristics of the double data rate synchronous dynamic random access memory IP to formulate the scanning strategy and determine the scanning object. Therefore, for the double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmitted data signal, the received data signal, and the second clock active interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. It should be understood that as mentioned above, the first scanning object for the high-bandwidth memory IP includes the first clock active interval, and here, the first scanning object for the double data rate synchronous dynamic random access memory IP includes the second clock active interval, and the first clock active interval is different from the second clock active interval. In this way, determining the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP is realized.

[0061] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. The present application can take the form of an all-hardware embodiment, an all-software embodiment, or an embodiment combining software and hardware aspects. The embodiments of the present application can be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The present application can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center containing one or more collections of available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium, or a semiconductor medium. The semiconductor medium can be a solid-state drive, a random access memory, a flash memory, a read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, a register, or any other suitable form of storage medium.

[0062] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction means that implements the functions specified in Figure 1one process or multiple processes and / or blocks Figure 1 the functions specified in one block or multiple blocks. These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 the functions specified in one block or multiple blocks.

[0063] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method embodiments of the present application can be adjusted, combined or deleted according to actual needs; the modules in the system embodiments of the present application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and variations.

Claims

1. A training system for a high-speed parallel port IP, characterized in that The training system includes: A high-speed transceiver for transmitting and receiving data and command signals; A delay and reference voltage regulator connected to the high-speed transceiver for performing delay adjustment and reference voltage adjustment on the data and command signals; A multi-branch generator connected to the delay and reference voltage regulator for respectively generating command combinations for controlling path training, data sequences for data path training, and adjustment signals for eye diagram adaptation training; A microprocessor connected to the multi-branch generator for controlling the generation of the multi-branch generator based on a first instruction combination; An instruction memory connected to the microprocessor for storing the first instruction combination, and the instruction memory is configured to be editable by downloading training firmware; The microprocessor is further configured to generate a first scanning strategy including a first scanning object based on the first instruction combination, and the first scanning object and the first scanning strategy are determined based on a first high-speed parallel port IP; Wherein, the microprocessor controls the generation of the multi-branch generator to implement the first scanning strategy on the first scanning object in the data and command signals by using the delay and reference voltage regulator so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP; The training firmware is a programmable specific state machine, and the microprocessor is a general state machine and is configured to execute the specific state machine based on the training firmware downloaded to the instruction memory; The first instruction combination stored in the instruction memory is configured to be editable in real time by downloading the training firmware; The training system is configured to adapt different first high-speed parallel port IPs by downloading different first instruction combinations.

2. The training system according to claim 1, wherein The data and command signals include address signals and control signals transmitted through an address control bus, transmission data signals transmitted through a transmission link, and reception data signals transmitted through a reception link.

3. The training system according to claim 2, wherein, When the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal, and a first clock valid interval, and the first scanning strategy adapts to the data link mode, link overall delay, link voltage, and package requirements associated with the bandwidth memory IP.

4. The training system according to claim 2, wherein When the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal, and a second clock valid interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP.

5. The training system according to claim 1, wherein The microprocessor controls the generation of the multi-branch generator so that the multi-branch generator generates a first command combination, a first data sequence, and a first adjustment signal corresponding to the first instruction combination.

6. The training system according to claim 5, characterized in that, When the first high-speed parallel port IP is a high-bandwidth memory IP, the first command combination includes an address coding error correction mechanism. When the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first command combination does not include an address coding error correction mechanism and includes an address error retry mechanism.

7. The training system according to claim 1, wherein The delay adjustment is used to determine the eye width, and the reference voltage adjustment is used to determine the eye height and the signal voltage amplitude.

8. The training system according to claim 1, wherein The command combination includes a bus command and a command transceiver timing.

9. The training system according to claim 1, wherein The data sequence includes a pseudo-random binary sequence and a special symbol sequence determined based on the first high-speed parallel port IP.

10. The training system according to claim 1, characterized in that, The adjustment signal includes an increment / decrement and a polarity, and the increment / decrement and the polarity are used to control the delay chain in the delay and reference voltage regulator.

11. The training system according to claim 1, wherein The multi-branch generator includes a command generator, a data generator, a data comparator, and a training controller. Among them, the command generator is used to generate the command combination under the control of the microprocessor, the data generator is used to generate the data sequence under the control of the microprocessor, the data comparator is used to generate a comparison result based on the data sequence, and the training controller is used to generate the adjustment signal under the control of the microprocessor.

12. The training system according to claim 1, characterized in that, The training system further includes a data memory, the data memory is connected to the microprocessor, and the microprocessor uses the data memory to execute the first scanning strategy.

13. A training method for a high-speed parallel port IP, characterized in that, The training method is applied to a training system, the training system includes a high-speed transceiver, a delay and reference voltage regulator, a multi-branch generator, a microprocessor, and an instruction memory, and the training method includes: Transmit and receive data and command signals through the high-speed transceiver; Perform delay adjustment and reference voltage adjustment on the data and command signals through the delay and reference voltage regulator; Respectively generate a command combination for controlling path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training through the multi-branch generator; Control the generation of the multi-branch generator by the microprocessor based on a first instruction combination, and generate a first scanning strategy including a first scanning object based on the first instruction combination. Among them, the first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP. The instruction memory is used to store the first instruction combination, and the instruction memory is configured to be editable by downloading training firmware; Control the generation of the multi-branch generator by the microprocessor to use the delay and reference voltage regulator to implement the first scanning strategy for the first scanning object in the data and command signals to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP. The training firmware is a programmable specific state machine, and the microprocessor is a general state machine and is configured to execute the specific state machine based on the training firmware downloaded to the instruction memory. The first instruction combination stored in the instruction memory is configured to be editable in real time by downloading the training firmware. The training system is configured to adapt to different first high-speed parallel port IPs by issuing different combinations of the first instructions.

14. The training method according to claim 13, wherein The data and command signals include address signals and control signals transmitted through an address control bus, transmission data signals transmitted through a transmission link, and reception data signals transmitted through a reception link.

15. The training method according to claim 14, characterized in that, When the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal, and a first clock valid interval, and the first scanning strategy adapts to the data link mode, overall link delay, link voltage, and packaging requirements associated with the bandwidth memory IP.

16. The training method according to claim 14, wherein When the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal, and a second clock valid interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth, and data transmission rate associated with the double data rate synchronous dynamic random access memory IP.

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