A quantum circuit deep optimization method and computer device based on heuristic SAT scanning

Abstract

This application discloses a method, computer device, and computer-readable storage medium for deep optimization of quantum circuits based on heuristic SAT scanning. The method includes: in response to user input, setting scanning parameters for the quantum circuit, including the number of scans. When the current number of scans for the quantum circuit is less than the total number of scans, processing the quantum circuit according to the scanning parameters, a heuristic sub-circuit scanning method, a cost evaluation method, and a Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit, thereby achieving quantum circuit optimization. The method of this application obtains a Boolean quantum circuit by processing the quantum circuit using a heuristic sub-circuit scanning method, a cost evaluation method, and a Boolean satisfiability solution algorithm. Thus, this method reduces the number of quantum gates without sacrificing circuit functionality, thereby improving the efficiency and performance of the quantum circuit and enhancing its executability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quantum computing, and more particularly, to a quantum circuit depth optimization method based on heuristic SAT scanning, a computer device and a computer readable storage medium. BACKGROUND

[0002] A quantum computer based on the principles of quantum mechanics can represent multiple states simultaneously using superposition and entanglement of quantum bits, thus achieving the ability to process a large amount of data in parallel. However, quantum computers are still in the development stage and face many technical challenges. For example, quantum hardware of quantum computers has specific limitations, and a compilation operation is needed to help the quantum circuit adapt to these limitations to ensure that the algorithm can be correctly executed on specific quantum hardware. In addition, quantum computers are limited by their own performance and have strict restrictions on the depth index of the quantum circuit they execute. During the compilation process of the quantum circuit, a large number of swap gates are usually introduced near the control non-gate, and one swap gate will be decomposed into multiple control non-gates in the subsequent execution process, thereby increasing the number of quantum gates in the quantum circuit and causing the degradation of the depth index of the quantum circuit, affecting the executability of the quantum circuit. SUMMARY

[0003] The present application provides a quantum circuit depth optimization method based on heuristic SAT scanning, a computer device and a computer readable storage medium.

[0004] The present application provides a quantum circuit depth optimization method based on heuristic SAT scanning, a computer device and a computer readable storage medium.

[0005] In response to a user input, set the scanning parameters of the quantum circuit, the scanning parameters including the number of quantum circuit scans;

[0006] In the case where the current number of scans of the quantum circuit is less than the number of quantum circuit scans, process the quantum circuit according to the scanning parameters, a heuristic sub-circuit scanning method, a cost evaluation method and a Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit, so as to realize the optimization of the quantum circuit.

[0007] In this way, the method of the present application processes the quantum circuit to obtain a Boolean quantum circuit through a heuristic sub-circuit scanning method, a cost evaluation method and a Boolean satisfiability solving algorithm. In this way, through this method, the number of quantum gates is reduced without sacrificing the function of the circuit, thereby improving the efficiency and performance of the quantum circuit and improving the executability of the quantum circuit.

[0008] In some embodiments, the step of processing the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method, and the Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit, thereby optimizing the quantum circuit, includes:

[0009] If the current number of scans is less than the number of scans of the quantum circuit, the quantum circuit is scanned and evaluated according to the scan parameters, the heuristic sub-circuit scanning method, and the cost evaluation method to obtain the optimal sub-circuit.

[0010] If the optimal sub-circuit can be obtained, the optimal sub-circuit is optimized according to the Boolean satisfiability solution algorithm to obtain the Boolean sub-circuit;

[0011] The sub-circuit corresponding to the optimal sub-circuit in the quantum circuit is replaced with the Boolean sub-circuit to obtain the Boolean quantum circuit, and the quantum circuit is replaced according to the Boolean quantum circuit.

[0012] Thus, when the number of scans is less than the number of quantum circuit scans, this application performs scan evaluation processing on the quantum circuit based on scan parameters, a heuristic sub-circuit scanning method, and a cost evaluation method to obtain the optimal sub-circuit. Next, if the optimal sub-circuit can be obtained, this application optimizes the optimal sub-circuit using a Boolean satisfiability solution algorithm to obtain a Boolean sub-circuit. Finally, this application replaces the sub-circuit corresponding to the optimal sub-circuit in the quantum circuit with the Boolean sub-circuit to obtain a Boolean quantum circuit, and then replaces the quantum circuit based on the Boolean quantum circuit. This reduces entanglement and operational complexity between qubits, thereby improving the overall execution efficiency of the quantum circuit. Furthermore, by using the obtained Boolean quantum circuit as a new quantum circuit for multiple iterations, the execution efficiency of the quantum circuit can be maximized.

[0013] In some embodiments, the step of performing a scanning evaluation process on the quantum circuit based on the scanning parameters, the heuristic subcircuit scanning method, and the cost evaluation method to obtain the optimal subcircuit includes:

[0014] If the current number of scans is less than the number of scans of the quantum circuit, the maximum evaluation value is set to 0;

[0015] The pre-selected quantum gates in the quantum circuit are scanned and evaluated according to the scanning parameters, the heuristic sub-circuit scanning method, and the cost evaluation method to obtain the optimal sub-circuit. The pre-selected quantum gates are predetermined 2-bit quantum gates.

[0016] Thus, when the current number of scans is less than the number of quantum circuit scans, this application sets the maximum evaluation value to 0. Next, this application performs a scan evaluation process on the pre-selected quantum gates in the quantum circuit based on scan parameters, a heuristic sub-circuit scanning method, and a cost evaluation method to obtain the optimal sub-circuit. The pre-selected quantum gates are predetermined 2-qubit quantum gates. In this way, by evaluating the pre-selected quantum gates, the quantum circuit components that have the greatest impact on the quantum circuit performance can be identified and optimized, thereby improving the overall performance of the quantum circuit. Furthermore, the sub-circuits of the quantum circuit are sorted for deep optimization using the heuristic sub-circuit scanning method, and this sorting is used as the selection criterion for deep optimization by the SAT solver.

[0017] In some implementations, the scanning parameters include a maximum number of bits and a number of test cases. The step of scanning and evaluating pre-selected quantum gates in the quantum circuit according to the scanning parameters, the heuristic sub-circuit scanning method, and the cost evaluation method to obtain the optimal sub-circuit includes:

[0018] Construct a first sub-circuit and a secondary adjacent set, wherein the first sub-circuit includes the preselected quantum gate, and the secondary adjacent set is an empty set;

[0019] Construct a first adjacent set based on the first sub-circuit;

[0020] The first neighbor set is removed based on the second neighbor set to obtain the second neighbor set;

[0021] If the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, a 2-qubit quantum gate from the second adjacent set is added to the first sub-circuit. The second sub-circuit is obtained by adding the 2-qubit quantum gate from the second adjacent set to the first sub-circuit, and each 2-qubit quantum gate includes 2 qubits.

[0022] Determine the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set and the second sub-circuit.

[0023] Thus, this application constructs a first sub-circuit and a secondary neighbor set. The first sub-circuit includes pre-selected quantum gates, and the secondary neighbor set is an empty set. This application then constructs a first neighbor set based on the first sub-circuit. Next, this application removes qubits from the first neighbor set based on the secondary neighbor set to obtain a second neighbor set. Then, if the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, this application adds 2-qubit quantum gates from the second neighbor set to the first sub-circuit. The second sub-circuit is obtained by adding 2-qubit quantum gates from the second neighbor set to the first sub-circuit, with each 2-qubit quantum gate comprising 2 qubits. Finally, this application determines the potential of the second neighbor set to obtain an optimal sub-circuit based on the potential of the second neighbor set and the second sub-circuit. In this way, by progressively expanding the sub-circuit and evaluating the impact of each step, the complexity and performance of the circuit can be controlled.

[0024] In some implementations, determining the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set includes:

[0025] If the potential of the second adjacent set is not zero, construct the next first adjacent set according to the second sub-circuit;

[0026] The next secondary neighbor set is obtained by the union of the second neighbor set and the secondary neighbor set;

[0027] The next first neighbor set is removed based on the next second-order neighbor set to obtain the next second neighbor set;

[0028] If the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, a 2-qubit quantum gate from the next second adjacent set is added to the first sub-circuit. The second sub-circuit is obtained by adding the 2-qubit quantum gate from the next second adjacent set to the first sub-circuit, and each 2-qubit quantum gate includes 2 qubits.

[0029] Determine the potential of the second neighboring set in order to obtain the optimal sub-circuit based on the potential of the second neighboring set.

[0030] Thus, when the potential of the second neighbor set is not zero, this application constructs the next first neighbor set based on the second sub-circuit. This application then obtains the next second-order neighbor set based on the union of the second neighbor set and the second-order neighbor set. Next, this application removes elements from the next first neighbor set based on the next second-order neighbor set to obtain the next second neighbor set. Then, when the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, this application adds 2-qubit quantum gates from the next second neighbor set to the first sub-circuit. The second sub-circuit is obtained by adding 2-qubit quantum gates from the next second neighbor set to the first sub-circuit, with each 2-qubit quantum gate comprising 2 qubits. Finally, this application determines the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set. Thus, if the potential of the second neighbor set is not zero, it indicates that these quantum gates need further optimization to obtain the optimal sub-circuit. Furthermore, by continuously updating the neighbor set, it ensures that the same quantum gates are not repeatedly optimized during the optimization process, improving efficiency. In addition, through this iterative process, the complexity and performance of the circuit can be controlled.

[0031] In some implementations, determining the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set includes:

[0032] When the potential of the second adjacent set is 0, the second sub-circuit and the number of test cases are evaluated according to the cost evaluation method to obtain the optimal sub-circuit.

[0033] Thus, when the potential of the second neighbor set is 0, this application evaluates the second sub-circuit and the number of test cases using a cost evaluation method to obtain the optimal sub-circuit. Therefore, when the potential of the second neighbor set is 0, it means that further iterations may not yield better optimization results. Furthermore, the cost evaluation method can obtain the deep redundancy of the second sub-circuit, quantifying its performance.

[0034] In some implementations, the step of evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the optimal sub-circuit includes:

[0035] The second sub-circuit and the number of test cases are evaluated according to the cost evaluation method to obtain the current evaluation value;

[0036] Compare the current evaluation value with the maximum evaluation value;

[0037] If the current evaluation value is greater than the maximum evaluation value, the current evaluation value is used as the maximum evaluation value to update the maximum evaluation value, and the second sub-circuit is used as the optimal sub-circuit.

[0038] Thus, this application evaluates the second sub-circuit and the number of test cases using a cost evaluation method to obtain a current evaluation value. Next, this application compares the current evaluation value with the maximum evaluation value. Finally, if the current evaluation value is greater than the maximum evaluation value, this application uses the current evaluation value as the maximum evaluation value to update the maximum evaluation value and identifies the second sub-circuit as the optimal sub-circuit. In this way, the deep redundancy of the second sub-circuit is obtained through the cost evaluation method, quantifying the performance of the second sub-circuit. Furthermore, by continuously comparing and updating the maximum evaluation value, the method of this application can ensure the finding of the optimal sub-circuit with the best performance, thereby optimizing the performance of the entire quantum circuit.

[0039] In some implementations, the step of evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the current evaluation value includes:

[0040] The second sub-circuit is decomposed to obtain the test sub-circuit;

[0041] If the current number of tests on the quantum circuit is less than the number of test cases, a test quantum state randomly selected from the calculated ground state is applied to the test sub-circuit to obtain the test inner product, and the maximum test inner product is obtained based on the test inner product.

[0042] The current evaluation value is obtained based on the maximum test inner product.

[0043] Thus, this application decomposes the second sub-circuit to obtain a test sub-circuit. Next, when the current number of tests on the quantum circuit is less than the number of test cases, this application applies a test quantum state randomly selected from the computational ground state to the test sub-circuit to obtain a test inner product, and obtains the maximum test inner product based on the test inner product. Then, this application obtains the current evaluation value based on the maximum test inner product. In this way, the second sub-circuit is simplified or decomposed into smaller parts through decomposition to facilitate testing and evaluation. Furthermore, randomly selecting a test quantum state from the computational ground state can simulate different input conditions. By comparing different test inner products, the best performance of the sub-circuit across all test cases can be found; the test inner product reflects changes in the quantum state.

[0044] In some implementations, when the current number of tests on the quantum circuit is less than the number of test cases, applying a randomly selected test quantum state to the test sub-circuit to obtain a test inner product, and obtaining the maximum test inner product based on the test inner product, includes:

[0045] Construct a test inner product set, which is used to store the test inner products;

[0046] The test quantum state is applied to the test sub-circuit to obtain the test inner product, and the test inner product is stored in the test inner product set;

[0047] The maximum test inner product is obtained from the set of test inner products.

[0048] Thus, this application constructs a set of test inner products, which is used to store the test inner products. Next, this application applies the test quantum state to the test sub-circuit to obtain the test inner product, and stores the test inner product in the set of test inner products. Finally, this application obtains the maximum test inner product from the set of test inner products. In this way, by constructing a set of test inner products and obtaining the maximum test inner product from it, the performance of different sub-circuits in a quantum circuit can be systematically evaluated and compared.

[0049] In some embodiments, applying the test quantum state to the test sub-circuit to obtain the test inner product and storing the test inner product in the test inner product set includes:

[0050] If the current number of tests is less than the number of test cases, increment the number of tests by 1;

[0051] A quantum state is randomly selected from the calculated ground state as the test quantum state;

[0052] The test sub-circuit is applied to the test quantum state to obtain the output quantum state;

[0053] The test inner product is obtained based on the test quantum state and the output quantum state;

[0054] The test inner product is stored in the test inner product set.

[0055] Thus, when the number of tests is less than the number of test cases, this application increments the number of tests by 1. Next, this application randomly selects a quantum state from the calculated ground state as the test quantum state. Then, this application applies the test sub-circuit to the test quantum state to obtain the output quantum state. This application then calculates the test inner product based on the test quantum state and the output quantum state. Finally, this application stores the test inner product in the test inner product set. In this way, when the number of tests is less than the number of test cases, this application performs iterative testing and calculates the test inner product to systematically evaluate the performance of the test sub-circuit.

[0056] In some implementations, obtaining the current evaluation value based on the maximum test inner product includes:

[0057] Calculate the test depth of the test sub-circuit;

[0058] The product of the preset parameters and the average number of times is used as the exponent of the Euler number to obtain the first exponent. The average number of times is the average number of times the quantum gates in the test sub-circuit are recompiled by the SAT solver.

[0059] The current evaluation value is obtained based on the first index, the maximum test inner product, and the test depth.

[0060] Thus, this application calculates the test depth of the test sub-circuit. Next, this application uses the product of preset parameters and the average number of iterations as the exponent of the Euler number to obtain the first exponent, and the average number of iterations is the average number of times the quantum gates in the test sub-circuit are recompiled by the SAT solver. Then, this application obtains the current evaluation value based on the first exponent, the maximum test inner product, and the test depth. In this way, by calculating the test depth and the first exponent, and combining them with the maximum test inner product, a comprehensive and quantitative current evaluation value is obtained, which is used to evaluate and optimize the sub-circuits in the quantum circuit.

[0061] In some implementations, the step of processing the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method, and the Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit, thereby optimizing the quantum circuit, includes:

[0062] If the current scan count is greater than or equal to the quantum circuit scan count, the Boolean quantum circuit is output to optimize the quantum circuit.

[0063] Thus, when the current number of scans is greater than or equal to the number of scans of the quantum circuit, this application outputs a Boolean quantum circuit to optimize the quantum circuit. This Boolean quantum circuit, obtained through multiple iterations, exhibits good execution efficiency.

[0064] This application provides a computer device including a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the above-described deep optimization method is implemented.

[0065] This application provides a computer-readable storage medium that stores a computer program that, when executed by one or more processors, implements the aforementioned deep optimization method.

[0066] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0067] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0068] Figure 1 This is one of the flowcharts illustrating the method of an embodiment of this application;

[0069] Figure 2 This is a schematic diagram of an example quantum circuit according to an embodiment of this application;

[0070] Figure 3 This is a second flowchart illustrating the method of the embodiments of this application;

[0071] Figure 4 This is the third flowchart illustrating the method of this application.

[0072] Figure 5 This is the fourth flowchart illustrating the method of implementing this application;

[0073] Figure 6 This is the fifth flowchart illustrating the method of the embodiments of this application;

[0074] Figure 7 This is the sixth flowchart illustrating the method of this application;

[0075] Figure 8 This is the seventh flowchart illustrating the method of this application.

[0076] Figure 9 This is the eighth flowchart illustrating the method of this application.

[0077] Figure 10 This is the ninth flowchart illustrating the method of implementing this application;

[0078] Figure 11 This is the tenth flowchart illustrating the method of this application;

[0079] Figure 12 This is a flowchart of the method of the present application;

[0080] Figure 13 This is the twelfth flowchart illustrating the method of this application;

[0081] Figure 14 This is a schematic diagram of an example input circuit according to an embodiment of this application;

[0082] Figure 15 This is a schematic diagram of an example output circuit according to an embodiment of this application;

[0083] Figure 16 This is the fifteenth flowchart illustrating the method of the embodiments of this application. Detailed Implementation

[0084] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting the embodiments of this application.

[0085] Quantum computers, based on the principles of quantum mechanics, utilize the superposition and entanglement properties of qubits to simultaneously represent multiple states, thereby enabling them to process large amounts of data in parallel.

[0086] However, quantum computers are still under development and face many technical challenges. For example, due to the complexity of their physical implementation, quantum computers have specific limitations on their quantum hardware. To ensure that quantum algorithms can be executed correctly and efficiently on this specific hardware, quantum compilation is needed to adapt and optimize quantum circuits. Quantum compilation is the process of converting high-level quantum algorithms into low-level physical operations that can be executed on specific quantum hardware. Furthermore, quantum computers are limited by their own physical properties, such as the physical properties of qubits, the implementation precision of quantum gates, the connectivity between qubits, and environmental noise. This imposes strict limitations on the depth of the quantum circuits they execute. The depth of a quantum circuit refers to the length of the sequence of quantum gate operations, which directly affects the execution time and resource consumption of quantum computing.

[0087] However, during the compilation of quantum circuits, a large number of swapping gates are typically introduced near the control-NOT gates. During subsequent execution, a single swapping gate is decomposed into multiple control-NOT gates. Furthermore, in quantum circuits, CNOT gates in certain regions interact more with each other, while interactions with qubit gates in other regions are less frequent. These control-NOT gates cluster together in the quantum circuit, increasing its depth. This not only increases the number of quantum gates in the quantum circuit but also degrades the quantum circuit's depth index, affecting its executability.

[0088] Based on the above issues, please refer to Figure 1 This application provides a quantum circuit depth optimization method based on heuristic SAT scanning, characterized in that the method includes:

[0089] 011: In response to user input, set the scanning parameters of the quantum circuit;

[0090] 012: When the current number of scans of the quantum circuit is less than the number of scans of the quantum circuit, the quantum circuit is processed according to the scan parameters, the heuristic sub-circuit scanning method, the cost evaluation method, and the Boolean satisfiability solution algorithm to obtain the Boolean quantum circuit, so as to achieve the optimization of the quantum circuit.

[0091] This application also provides a computer device, including a memory and a processor. The method of this application can be implemented by the computer device of this application. Specifically, the memory stores a computer program, and the processor is used to set the scanning parameters of the quantum circuit in response to user input. When the current number of scans of the quantum circuit is less than the total number of scans of the quantum circuit, the quantum circuit is processed according to the scanning parameters, a heuristic quantum circuit scanning method, a cost evaluation method, and a Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit, thereby optimizing the quantum circuit.

[0092] This application also provides a deep optimization apparatus. The method of this application can be implemented by the deep optimization apparatus of this application. Specifically, the deep optimization apparatus includes a setting module and a processing module. The setting module is used to set the scanning parameters of the quantum circuit in response to user input. The processing module is used to process the quantum circuit according to the scanning parameters, a heuristic sub-circuit scanning method, a cost evaluation method, and a Boolean satisfiability solution algorithm when the current number of scans of the quantum circuit is less than the total number of scans of the quantum circuit, to obtain a Boolean quantum circuit, thereby achieving optimization of the quantum circuit.

[0093] It should be noted that, in the embodiments of this application, the qubit is the basic unit for storing and processing data in a quantum computer. A quantum program implements a specific computational process by performing corresponding quantum gate operations on the qubit.

[0094] Quantum gates are the fundamental operational units in quantum computing. A quantum gate acts on a qubit by changing its quantum state vector. Based on the number of qubits affected, quantum gates can be divided into single-qubit gates and two-qubit gates. A single-qubit gate acts on only one specific qubit and can only change the state of that qubit. A two-qubit gate acts on two qubits and can change the state of each of the affected qubits. Hereinafter, G(i) represents a general single-qubit gate G acting on the i-th qubit, G(i,j) represents a general two-qubit gate G acting on qubits i and j, and |G| represents the number of qubits affected by gate G. The swap gate used in the embodiments of this application is a special two-qubit gate acting on the i-th and j-th qubits, usually denoted as SWAP(i,j).

[0095] Quantum circuits are a common method of describing quantum programs, typically consisting of qubits and a series of quantum gates. Subcircuits are a component of quantum circuits; they are relatively independent circuit units capable of performing specific quantum operations or algorithms. See also... Figure 2 , Figure 2 This is an example quantum circuit containing two qubits q0 and q1, where each line represents the corresponding qubit, and module A represents G. A (q0), module B represents a two-bit CNOT gate G. B (q0,q1) or CNOT(q0,q1), module C represents SWAP(q0,q1).

[0096] The depth of a quantum circuit is an important indicator, determined by the specific layout of the quantum gates within it. In some implementations, techniques for calculating the depth of a quantum circuit include common methods such as direct counting, hierarchical analysis, and dependency graph methods. This application uses the direct counting method to calculate the depth of the quantum circuit.

[0097] Specifically, the number of quantum circuit scans is determined by the user, representing the number of times the quantum circuit is repeatedly executed when the algorithm is run.

[0098] After compiling the quantum circuit, a quantum circuit with a large number of clustered two-qubit quantum gates is obtained. In response to user input, the computer device sets the scanning parameters of the quantum circuit, including the number of times the quantum circuit is scanned.

[0099] Next, when the current number of scans of the quantum circuit is less than the number of scans of the quantum circuit, the quantum circuit is processed according to the scan parameters, the heuristic sub-circuit scanning method, the cost evaluation method, and the Boolean satisfiability solution algorithm to obtain the Boolean quantum circuit, so as to achieve the optimization of the quantum circuit.

[0100] In summary, in the quantum circuit deep optimization method and computer device based on heuristic SAT scanning of the embodiments of this application, for quantum circuits with a large number of clustered two-qubit quantum gates obtained after compilation, the method of this application processes the quantum circuit through a heuristic sub-circuit scanning method, a cost evaluation method, and a Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit. Thus, this method reduces the number of quantum gates without sacrificing circuit functionality, thereby improving the efficiency and performance of the quantum circuit and enhancing its executability.

[0101] Please see Figure 3In some implementations, step 012 (processing the quantum circuit according to scanning parameters, a heuristic subcircuit scanning method, a cost evaluation method, and a Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit, thereby optimizing the quantum circuit) includes:

[0102] 021: When the current number of scans is less than the number of scans of the quantum circuit, the quantum circuit is scanned and evaluated according to the scan parameters, the heuristic sub-circuit scanning method and the cost evaluation method to obtain the optimal sub-circuit;

[0103] 022: If the optimal sub-circuit can be obtained, the optimal sub-circuit is optimized according to the Boolean satisfiability solution algorithm to obtain the Boolean sub-circuit;

[0104] 023: Replace the sub-circuit corresponding to the optimal sub-circuit in the quantum circuit with a Boolean sub-circuit to obtain a Boolean quantum circuit, and replace the quantum circuit according to the Boolean quantum circuit.

[0105] In some implementations, the scanning evaluation module is used to perform scanning evaluation processing on the quantum circuit according to scanning parameters, a heuristic sub-circuit scanning method, and a cost evaluation method when the current number of scans is less than the number of scans of the quantum circuit, in order to obtain the optimal sub-circuit. The optimization module is used to optimize the optimal sub-circuit according to the Boolean satisfiability solution algorithm to obtain a Boolean sub-circuit, provided that the optimal sub-circuit can be obtained. The replacement module is used to replace the sub-circuit in the quantum circuit corresponding to the optimal sub-circuit with a Boolean sub-circuit to obtain a Boolean quantum circuit, and then replace the quantum circuit according to the Boolean quantum circuit.

[0106] In some implementations, the processor is further configured to perform a scan evaluation process on the quantum circuit based on scan parameters, a heuristic sub-circuit scanning method, and a cost evaluation method to obtain an optimal sub-circuit when the current scan count is less than the quantum circuit scan count. And, if an optimal sub-circuit can be obtained, optimize the optimal sub-circuit using a Boolean satisfiability solution algorithm to obtain a Boolean sub-circuit. Furthermore, replace the sub-circuit in the quantum circuit corresponding to the optimal sub-circuit with a Boolean sub-circuit to obtain a Boolean quantum circuit, and replace the quantum circuit based on the Boolean quantum circuit.

[0107] Specifically, when the number of scans is less than the number of scans required for the quantum circuit, the computer device performs a scan evaluation process on the quantum circuit based on scan parameters, a heuristic sub-circuit scanning method, and a cost evaluation method to obtain the optimal sub-circuit. Next, if the optimal sub-circuit can be obtained, the computer device optimizes the optimal sub-circuit using a Boolean satisfiability solution algorithm to obtain a Boolean sub-circuit. Finally, the computer device replaces the sub-circuit in the quantum circuit corresponding to the optimal sub-circuit with the Boolean sub-circuit to obtain a Boolean quantum circuit, and then replaces the quantum circuit based on the Boolean quantum circuit.

[0108] In this way, advanced computing devices can reduce entanglement and operational complexity between qubits, thereby improving the overall execution efficiency of quantum circuits. Furthermore, by using the resulting Boolean quantum circuit as a new quantum circuit and performing multiple iterations, the execution efficiency of the quantum circuit can be maximized.

[0109] Please see Figure 4 In some embodiments, step 021 (scanning and evaluating the quantum circuit according to scanning parameters, a heuristic sub-circuit scanning method, and a cost evaluation method to obtain the optimal sub-circuit) includes:

[0110] 031: If the current number of scans is less than the number of scans performed by the quantum circuit, set the maximum evaluation value to 0;

[0111] 032: Based on the scanning parameters, heuristic sub-circuit scanning method, and cost evaluation method, the pre-selected quantum gates in the quantum circuit are scanned and evaluated to obtain the optimal sub-circuit.

[0112] In some implementations, the setting module is used to set the maximum evaluation value to 0 and increment the current scan count by 1 if the current scan count is less than the quantum circuit scan count. The scan evaluation module is used to perform scan evaluation processing on the pre-selected quantum gates in the quantum circuit according to the scan parameters, the heuristic sub-circuit scan method, and the cost evaluation method to obtain the optimal sub-circuit.

[0113] In some implementations, the processor is also configured to set a maximum evaluation value of 0 if the current number of scans is less than the number of scans of the quantum circuit. Furthermore, it performs scan evaluation processing on pre-selected quantum gates in the quantum circuit based on scan parameters, a heuristic sub-circuit scanning method, and a cost evaluation method to obtain the optimal sub-circuit.

[0114] Specifically, when the current number of scans is less than the number of scans of the quantum circuit, the computer device sets the maximum evaluation value to 0. Next, the computer device performs scan evaluation on the pre-selected quantum gates in the quantum circuit based on the scan parameters, the heuristic sub-circuit scanning method, and the cost evaluation method to obtain the optimal sub-circuit. The pre-selected quantum gates are predetermined 2-qubit quantum gates.

[0115] In this way, by evaluating pre-selected quantum gates, the computer device can identify the quantum circuit components that have the greatest impact on the performance of the quantum circuit and optimize them, thereby improving the overall performance of the quantum circuit. Furthermore, the computer device uses a heuristic sub-circuit scanning method to perform deep optimization of the sub-circuits of the quantum circuit and uses this ranking as the basis for selecting the SAT solver for deep optimization.

[0116] Please see Figure 5In some implementations, the scanning parameters include the maximum number of bits and the number of test cases. Step 032 (scanning and evaluating the pre-selected quantum gates in the quantum circuit according to the scanning parameters, the heuristic sub-circuit scanning method, and the cost evaluation method to obtain the optimal sub-circuit) includes:

[0117] 041: Construct the first sub-circuit and the secondary adjacent set;

[0118] 042: Construct the first adjacent set based on the first sub-circuit;

[0119] 043: Remove elements from the first adjacent set based on the second adjacent set to obtain the second adjacent set;

[0120] 044: If the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, add 2-qubit quantum gates from the second adjacent set to the first sub-circuit. The second sub-circuit is obtained by adding 2-qubit quantum gates from the next second adjacent set to the first sub-circuit.

[0121] 045: Determine the potential of the second adjacent set in order to obtain the optimal sub-circuit based on the potential of the second adjacent set and the second sub-circuit.

[0122] In some implementations, the construction module is used to construct a first sub-circuit, a secondary neighbor set, and a first neighbor set. The first neighbor set is constructed based on the first sub-circuit. The removal module is used to remove qubits from the first neighbor set based on the secondary neighbor set to obtain a second neighbor set. The addition module is used to add 2-qubit quantum gates from the second neighbor set to the first sub-circuit if the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits. The second sub-circuit is obtained by adding 2-qubit quantum gates from the next second neighbor set to the first sub-circuit. The determination module is used to determine the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set and the second sub-circuit.

[0123] In some implementations, the processor is further configured to construct a first sub-circuit, a secondary neighbor set, and a first neighbor set; construct the first neighbor set based on the first sub-circuit; and remove elements from the first neighbor set based on the secondary neighbor set to obtain a second neighbor set. The processor is also configured to, if the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, add a 2-qubit quantum gate from the second neighbor set to the first sub-circuit, wherein the second sub-circuit is obtained by adding a 2-qubit quantum gate from the next second neighbor set to the first sub-circuit; and determine the potential of the second neighbor set to obtain an optimal sub-circuit based on the potential of the second neighbor set and the second sub-circuit.

[0124] Specifically, the computer device constructs a first sub-circuit and a secondary neighbor set. The first sub-circuit includes pre-selected quantum gates, and the secondary neighbor set is an empty set. This application then constructs a first neighbor set based on the first sub-circuit. Next, the computer device removes qubits from the first neighbor set based on the secondary neighbor set to obtain a second neighbor set. Then, if the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, the computer device adds 2-qubit quantum gates from the second neighbor set to the first sub-circuit. The second sub-circuit is obtained by adding 2-qubit quantum gates from the second neighbor set to the first sub-circuit, with each 2-qubit quantum gate comprising 2 qubits. Finally, the computer device determines the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set and the second sub-circuit.

[0125] In this way, computer devices can control the complexity and performance of circuits by progressively expanding sub-circuits and evaluating the impact of each step.

[0126] Please see Figure 6 In some implementations, step 045 (determining the potential of the second neighboring set to obtain the optimal sub-circuit based on the potential of the second neighboring set) includes:

[0127] 051: If the potential of the second adjacent set is not 0, construct the next first adjacent set according to the second sub-circuit;

[0128] 052: Obtain the next secondary adjacent set by the union of the second adjacent set and the secondary adjacent set;

[0129] 053: Remove the next first adjacent set based on the next second adjacent set to obtain the next second adjacent set;

[0130] 054: If the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, add the 2-qubit quantum gate from the next second adjacent set to the first sub-circuit;

[0131] 055: Determine the potential of the second adjacent set in order to obtain the optimal sub-circuit based on the potential of the second adjacent set.

[0132] In some implementations, the construction module is used to construct the next first neighbor set based on the second sub-circuit. The processing module is used to obtain the next second-order neighbor set based on the union of the second neighbor set and the second-order neighbor set. The removal module is used to remove the next first neighbor set based on the next second-order neighbor set to obtain the next second neighbor set. The addition module is also used to add a 2-qubit quantum gate from the next second neighbor set to the first sub-circuit if the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits. The confirmation module is used to determine the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set.

[0133] In some implementations, the processor is further configured to construct a first neighboring set based on the second sub-circuit when the potential of the second neighboring set is not zero; obtain a next secondary neighboring set based on the union of the second neighboring set and the secondary neighboring set; and remove elements from the first neighboring set based on the next secondary neighboring set to obtain a next second neighboring set. The processor is also configured to add a 2-qubit quantum gate from the next second neighboring set to the first sub-circuit when the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits; and determine the potential of the second neighboring set to obtain an optimal sub-circuit based on the potential of the second neighboring set.

[0134] Specifically, when the potential of the second neighbor set is not zero, the computer device constructs the first neighbor set based on the second sub-circuit. This application then obtains the next secondary neighbor set based on the union of the second neighbor set and the secondary neighbor set. Next, the computer device removes elements from the first neighbor set based on the next secondary neighbor set to obtain the next second neighbor set. Then, when the number of qubits in the second sub-circuit is less than or equal to the maximum number of qubits, the computer device adds 2-qubit quantum gates from the next second neighbor set to the first sub-circuit. The second sub-circuit is obtained by adding 2-qubit quantum gates from the next second neighbor set to the first sub-circuit, with each 2-qubit quantum gate comprising 2 qubits. Finally, the computer device determines the potential of the second neighbor set to obtain the optimal sub-circuit based on the potential of the second neighbor set.

[0135] Thus, if the potential of the second neighboring set is not zero, it means that these quantum gates need to be further optimized to obtain the optimal sub-circuit. Furthermore, by continuously updating the neighboring sets, it is ensured that the same quantum gates are not repeatedly optimized during the optimization process, thus improving efficiency. In addition, through this iterative process, the complexity and performance of the circuit can be controlled.

[0136] Please see Figure 7 In some implementations, step 045 (determining the potential of the second neighboring set to obtain the optimal sub-circuit based on the potential of the second neighboring set) includes:

[0137] 056: When the potential of the second adjacent set is 0, the second sub-circuit and the number of test cases are evaluated according to the cost evaluation method to obtain the optimal sub-circuit.

[0138] In some implementations, the evaluation module is used to evaluate the second sub-circuit and the number of test cases according to a cost evaluation method when the potential of the second adjacent set is 0, so as to obtain the optimal sub-circuit.

[0139] In some implementations, the processor is further configured to evaluate the second sub-circuit and the number of test cases according to a cost evaluation method when the potential of the second adjacent set is 0, so as to obtain the optimal sub-circuit.

[0140] Specifically, when the potential of the second adjacent set is 0, the computer device evaluates the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the optimal sub-circuit.

[0141] Thus, when the potential of the second adjacent set is 0, it means that further iterations may not yield better optimization results. Furthermore, the cost evaluation method can obtain the deep redundancy of the second sub-circuit, quantifying its performance.

[0142] Please see Figure 8 In some implementations, step 056 (evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the optimal sub-circuit) includes:

[0143] 061: Evaluate the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the current evaluation value;

[0144] 062: Compare the current assessment value with the maximum assessment value;

[0145] 063: If the current evaluation value is greater than the maximum evaluation value, the current evaluation value is used as the maximum evaluation value to update the maximum evaluation value, and the second sub-circuit is selected as the optimal sub-circuit.

[0146] In some implementations, the evaluation module evaluates the second sub-circuit and the number of test cases according to a cost evaluation method to obtain a current evaluation value. The comparison module compares the current evaluation value with the maximum evaluation value. The processing module further updates the maximum evaluation value by using the current evaluation value as the maximum evaluation value when the current evaluation value is greater than the maximum evaluation value, and designates the second sub-circuit as the optimal sub-circuit.

[0147] In some implementations, the processor further evaluates the second sub-circuit and the number of test cases according to a cost evaluation method to obtain a current evaluation value. It then compares the current evaluation value with a maximum evaluation value. If the current evaluation value is greater than the maximum evaluation value, the processor uses the current evaluation value as the maximum evaluation value to update the maximum evaluation value and designates the second sub-circuit as the optimal sub-circuit.

[0148] Specifically, the computer device evaluates the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the current evaluation value. Next, the computer device compares the current evaluation value with the maximum evaluation value. Finally, if the current evaluation value is greater than the maximum evaluation value, the computer device updates the maximum evaluation value by using the current evaluation value as the maximum evaluation value and designates the second sub-circuit as the optimal sub-circuit.

[0149] Thus, the computer device obtains the deep redundancy of the second sub-circuit through a cost evaluation method, quantifying the performance of the second sub-circuit. Furthermore, by continuously comparing and updating the maximum evaluation value, the method of this application can ensure the finding of the optimal sub-circuit with the best performance, thereby optimizing the performance of the entire quantum circuit.

[0150] Please see Figure 9 In some implementations, step 061 (evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the current evaluation value) includes:

[0151] 071: The second sub-circuit is decomposed to obtain the test sub-circuit;

[0152] 072: When the current number of tests on the quantum circuit is less than the number of test cases, a test quantum state randomly selected from the self-computed ground state is applied to the test sub-circuit to obtain the test inner product, and the maximum test inner product is obtained based on the test inner product;

[0153] 073: Obtain the current evaluation value based on the maximum test inner product.

[0154] In some implementations, the decomposition module is further configured to decompose the second sub-circuit to obtain a test sub-circuit. The processing module, when the current number of tests on the quantum circuit is less than the number of test cases, applies a test quantum state randomly selected from the calculated ground state to the test sub-circuit to obtain a test inner product, and obtains the maximum test inner product based on the test inner product. The calculation module is configured to obtain the current evaluation value based on the maximum test inner product.

[0155] In some implementations, the processor is further configured to decompose the second sub-circuit to obtain a test sub-circuit. And, if the current number of tests on the quantum circuit is less than the number of test cases, to apply a test quantum state randomly selected from the computed ground state to the test sub-circuit to obtain a test inner product, and to obtain a maximum test inner product based on the test inner product. And to obtain a current evaluation value based on the maximum test inner product.

[0156] Specifically, the computer device decomposes the second sub-circuit to obtain a test sub-circuit. Then, if the current number of tests on the quantum circuit is less than the number of test cases, the computer device applies a test quantum state randomly selected from the computational ground state to the test sub-circuit to obtain a test inner product, and obtains the maximum test inner product based on the test inner product. Finally, the computer device obtains the current evaluation value based on the maximum test inner product.

[0157] In this way, the computer device simplifies or decomposes the second sub-circuit into smaller parts through decomposition processing, making it easier to test and evaluate. Furthermore, randomly selecting test quantum states from the computational ground state can simulate different input conditions. By comparing different test inner products, the best performance of the sub-circuit across all test cases can be determined; the test inner product reflects changes in the quantum states.

[0158] Please see Figure 10 In some implementations, step 072 (when the current number of tests on the quantum circuit is less than the number of test cases, applying a randomly selected test quantum state to the test sub-circuit to obtain the test inner product, and obtaining the maximum test inner product based on the test inner product) includes:

[0159] 081: Construct a test inner product set, which is used to store test inner products;

[0160] 082: Apply the test quantum state to the test sub-circuit to obtain the test inner product, and store the test inner product in the test inner product set;

[0161] 083: Obtain the maximum test inner product from the set of self-test inner products.

[0162] In some implementations, the construction module is further configured to construct a test inner product set, which stores the test inner products. The storage module applies the test quantum state to the test sub-circuit to obtain the test inner product and stores it in the test inner product set. The acquisition module retrieves the maximum test inner product from the test inner product set.

[0163] In some implementations, the processor is also configured to construct a set of test inner products for storing test inner products; apply test quantum states to test sub-circuits to obtain test inner products and store them in the set of test inner products; and obtain the maximum test inner product from the set of test inner products.

[0164] Specifically, the computer device constructs a set of test inner products, which is used to store the test inner products. Next, the computer device applies a test quantum state randomly selected from the computational ground state to the test sub-circuit to obtain the test inner product, and stores this test inner product in the set of test inner products. Finally, the computer device obtains the maximum test inner product from the set of test inner products.

[0165] In this way, by constructing a set of test inner products and obtaining the maximum test inner product from it, computer devices can systematically evaluate and compare the performance of different sub-circuits in quantum circuits.

[0166] Please see Figure 11 In some implementations, step 082 (applying the test quantum state to the test sub-circuit to obtain the test inner product, and storing the test inner product in the test inner product set) includes:

[0167] 091: If the current number of tests is less than the number of test cases, increment the number of tests by 1;

[0168] 092: Randomly select a quantum state from the calculated ground state as the test quantum state;

[0169] 093: Apply the test sub-circuit to the test quantum state to obtain the output quantum state;

[0170] 094: Obtain the test inner product based on the test quantum state and the output quantum state;

[0171] 095: Store the test inner product in the test inner product set.

[0172] In some implementations, the increment module is further configured to increment the test count by 1 if the current test count is less than the number of test cases. The selection module is configured to randomly select a quantum state from the calculated ground states as the test quantum state. The processing module is further configured to apply the test sub-circuit to the test quantum state to obtain the output quantum state, and to obtain the test inner product based on the test quantum state and the output quantum state. The storage module is configured to store the test inner product in the test inner product set.

[0173] In some implementations, the processor is further configured to increment the test count by 1 if the current test count is less than the number of test cases; randomly select a quantum state from the calculated ground states as the test quantum state; and apply the test sub-circuit to the test quantum state to obtain the output quantum state. The processor is also configured to obtain the test inner product based on the test quantum state and the output quantum state, and store the test inner product in a test inner product set.

[0174] Specifically, if the current number of tests is less than the number of test cases, the computer device increments the number of tests by 1. Next, the computer device randomly selects a quantum state from the computational ground state as the test quantum state. Then, the computer device applies the test sub-circuit to the test quantum state to obtain the output quantum state. The computer device then calculates the test inner product based on the test quantum state and the output quantum state. Finally, the computer device stores the test inner product in the test inner product set.

[0175] Thus, when the number of tests is less than the number of test cases, the computer device performs iterative testing and calculates the inner product of the tests to systematically evaluate the performance of the test sub-circuits.

[0176] Please see Figure 12 In some implementations, step 094 (obtaining the current evaluation value based on the maximum test inner product) includes:

[0177] 0101: Calculate the test depth of the test sub-circuit;

[0178] 0102: The product of the preset parameters and the average degree is used as the exponent of the Euler number to obtain the first exponent;

[0179] 0103: The current evaluation value is obtained based on the first index, the maximum test inner product, and the test depth.

[0180] In some implementations, the calculation module is also used to calculate the test depth of the test sub-circuit. The processing module is used to take the product of the preset parameters and the average number of times as the exponent of the Euler number to obtain a first exponent. The processing module is also used to obtain the current evaluation value based on the first exponent, the maximum test inner product, and the test depth.

[0181] In some implementations, the processor is also used to calculate the test depth of the test sub-circuit, and to obtain a first exponent by multiplying a preset parameter and the average number of tests as the exponent of the Euler number. Finally, the processor obtains the current evaluation value based on the first exponent, the maximum test inner product, and the test depth.

[0182] Specifically, the computer device calculates the test depth of the test sub-circuit. Next, the computer device uses the product of preset parameters and the average number of iterations as the exponent of the Euler number to obtain the first exponent. The average number of iterations is the average number of times the quantum gates in the test sub-circuit are recompiled by the SAT solver. Then, the computer device obtains the current evaluation value based on the first exponent, the maximum test inner product, and the test depth.

[0183] In this way, the computer device calculates the test depth and the first exponent, and combines them with the maximum test inner product to obtain a comprehensive, quantitative current evaluation value for evaluating and optimizing sub-circuits in quantum circuits.

[0184] Please see Figure 13 In some implementations, step 012 (processing the quantum circuit according to scanning parameters, a heuristic subcircuit scanning method, a cost evaluation method, and a Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit, thereby optimizing the quantum circuit) includes:

[0185] 024: When the current number of scans is greater than or equal to the number of scans of the quantum circuit, output a Boolean quantum circuit to optimize the quantum circuit.

[0186] In some implementations, the output module is also used to output a Boolean quantum circuit when the current scan count is greater than or equal to the quantum circuit scan count, in order to optimize the quantum circuit.

[0187] In some implementations, the processor is also configured to output a Boolean quantum circuit when the current scan count is greater than or equal to the quantum circuit scan count, in order to optimize the quantum circuit.

[0188] Specifically, when the current number of scans is greater than or equal to the number of scans of the quantum circuit, this application outputs a Boolean quantum circuit to optimize the quantum circuit.

[0189] Thus, the Boolean quantum circuit obtained by iterating the input multiple times has good execution efficiency.

[0190] The following example illustrates the method of this application's implementation. In the embodiments described in this application, the dependency between quantum gates generally refers to the fact that, in a quantum circuit, the execution of some quantum gates depends on the result or state of other quantum gates. The affected qubits refer to those qubits directly operated by the quantum gates. In this application's implementation, the method for determining the dependency between quantum gates is as follows:

[0191] In a quantum circuit C, if two quantum gates simultaneously satisfy the following condition:

[0192] At least one active qubit must be shared;

[0193] Furthermore, no other quantum gates can interact between the two quantum gates within the shared qubits.

[0194] The two quantum gates are said to be interdependent in the quantum circuit C. In this application, the process of determining whether two quantum gates are interdependent using the above conditions is denoted as Dependency(G). i G j C).

[0195] The dependency between quantum gates and sub-circuits generally refers to the situation where, in the design and execution of a quantum circuit, the operation of a quantum gate depends on the state or result of a sub-circuit, or vice versa. In this application, the method for determining the dependency between quantum gates and sub-circuits is as follows:

[0196] In a quantum circuit C, if one of the sub-circuits C i The quantum gate G satisfies the following condition:

[0197] C i It shares at least one active qubit with G;

[0198] And in the shared qubits C i No other quantum gates can exist between G and G.

[0199] Then it is called sub-circuit C i The quantum gate G is interdependent with the sub-circuit C. In this embodiment, the process of determining whether the quantum gate and the sub-circuit are interdependent using the above conditions is denoted as Dependency(G, C). i C).

[0200] The adjacency of quantum gates and subcircuits refers to their adjacent relative positions and execution order within a quantum circuit. Adjacent quantum gates or subcircuits are closely connected in the circuit, and their execution order and interactions have a significant impact on the overall function and performance of the circuit. In this application's embodiment, the method for determining the adjacency of quantum gates and subcircuits is as follows:

[0201] In a quantum circuit C, for a given sub-circuit C 1 And quantum gate G0, if there is no non-empty gate sequence Satisfy [(for all i, G i The location is in G i-1 Previously) ∨(For all i, G i The location is in G i-1 Afterwards)]∧Dependency(G i G i-1 ,C)∧Dependency(G K C 1 If C), then the sub-circuit C is called the sub-circuit. 1 Adjacent to quantum gate G0. In this embodiment, the process of determining the adjacency of a quantum gate and a sub-circuit using the above conditions is denoted as Adjacency(G0, C...). 1 C).

[0202] In quantum circuits, a SWAP gate (i, j) can be decomposed into three CNOT gates: CNOT(i, j), CNOT(j, i), and CNOT(i, j). The process of decomposing a SWAP gate into CNOT gates in this embodiment is denoted as Decompose(C). After decomposing the SWAP gates, a new quantum circuit without SWAP gates is obtained. The number of quantum circuit scans is the number of sub-circuit scans TS, the maximum number of bits is the maximum number of bits TN that the SAT solver can process in a CNOT circuit, and the number of test cases is the number of input-output pairs TP tested in the heuristic evaluation function.

[0203] The potential of a set of quantum gates is the number of different quantum gates in the set.

[0204] Before execution of a quantum circuit, a corresponding compilation operation needs to be performed on the quantum circuit to address the connectivity constraints of the target hardware. This compilation operation introduces a large number of clustered two-qubit quantum swapping gates into the quantum circuit, resulting in a large number of two-qubit quantum gate sub-circuits in the output circuit. Please refer to [link to relevant documentation]. Figure 14 , Figure 15 , Figure 14 This is an input circuit for the quantum circuit compilation process. Figure 15 This is one possible output circuit, which contains two sub-circuits, A and B, each containing a two-bit quantum gate.

[0205] Specifically, after compiling the quantum circuit, the heuristic subcircuit scanning technique is first used to divide the compiled quantum circuit C, which has a large number of CNOT gates, into multiple small-scale CNOT-SWAP circuits. The specific operation method is as follows:

[0206] The user inputs scan parameters according to their needs. The computer device responds to the user's input by setting the scan parameters, including the number of scans (TS) for the algorithm subcircuit, the maximum number of bits (TN) that the SAT solver can handle for the CNOT circuit, and the number of input-output pairs (TP) for the heuristic evaluation function test.

[0207] Please see Figure 16 When the current number of scans n is less than TS, the quantum circuit C with a large number of CNOT gates obtained after compilation is processed as follows:

[0208] The initial value of the maximum evaluation value Z0 is set to 0, and the value of the current scan count n is incremented by 1.

[0209] Next, any two-qubit gate from quantum circuit C is extracted to construct the first sub-circuit C1, and a secondary neighbor set D1 with no elements is constructed for the time being. Then, the two-qubit gates in quantum circuit C adjacent to the first sub-circuit C1 are used to construct the first neighbor set D. Then, all two-qubit gates that exist in both the first neighbor set G and the secondary neighbor set D1 are removed from the first neighbor set D to obtain the second neighbor set D2. That is, the second neighbor set D2 is obtained by removing elements from the union of the first neighbor set D and the secondary neighbor set D1.

[0210] Next, before adding the two qubit gates Mi from the first adjacent set to the first sub-circuit C1, a pre-calculation is performed to determine whether the number of qubits in the first sub-circuit C1 will exceed the maximum number of bits TN input by the user after adding the two qubit gates Mi from the first adjacent set. The two qubit gates Mi from the first adjacent set are added to the first sub-circuit C1 in the order of their positions in the first adjacent set. If the number of qubits in the first sub-circuit does not exceed the maximum number of bits TN input by the user, the two qubit gates Mi are added to the first sub-circuit C1, resulting in the second sub-circuit C2. If the number of qubits in the first sub-circuit exceeds the maximum number of bits TN input by the user, the two qubit gates Mi from the first adjacent set are not added to the first sub-circuit C1, and the second sub-circuit C2 is obtained directly.

[0211] Then, the next secondary neighbor set is obtained by taking the union of the first neighbor set D and the secondary neighbor set D1. Next, the cardinality of the second neighbor set D2 is determined. If the cardinality of the second neighbor set D2 is not 0, the second sub-circuit is taken as the new first sub-circuit, and the first neighbor set is reconstructed based on the new first sub-circuit until the cardinality of the resulting second neighbor set D2 is 0.

[0212] If the potential of the second adjacent set D2 is 0, then the second sub-circuit C2 is evaluated using the cost evaluation method Evaluate to obtain the optimal sub-circuit. (See also...) Figure 1 The method for cost evaluation of the second sub-circuit C2 according to the cost evaluation method Evaluate is as follows:

[0213] First, the second sub-circuit is decomposed according to the SWAP gate decomposition method provided in the above-described embodiment of this application to obtain a test sub-circuit C3 that does not contain a SWAP gate. Then, the depth S of the test sub-circuit C3 is calculated according to the depth calculation method provided in the above-described embodiment of this application. Next, a test count i is set to 0. When the test count i is less than the number of input-output pairs TP of the heuristic evaluation function test input by the user, a test inner product set D3 is constructed to store the test inner product, and a quantum state is randomly selected from the ground state as the test quantum state |x>. The test sub-circuit C3 is applied to the test quantum state |x> to obtain the output quantum state |y>. The test inner product d is obtained based on the test quantum state |x> and the output quantum state |y>, i.e.<x|y> The test inner product d is stored in the test inner product set D3. When the number of tests i is greater than or equal to the number of input-output pairs TP of the heuristic evaluation function test input by the user, the largest test inner product d-max is selected from the test inner product set D3. Then, the average number of times v of the quantum gates in the second sub-circuit being recompiled by the SAT solver is calculated.

[0214] Then, the current evaluation value Z1 is obtained by presetting parameters γ, depth S, and average number of trials v, calculated as follows:

[0215] After calculating the current evaluation value Z1, compare it with the maximum evaluation value Z0. If the current evaluation value Z1 is less than or equal to the maximum evaluation value Z0, do not make any changes to the circuit. If the current evaluation value Z1 is greater than the maximum evaluation value Z0, take the current evaluation value Z1 as the new maximum evaluation value Z0, and take the second sub-circuit C2 as the optimal sub-circuit. After obtaining the optimal sub-circuit, optimize it using the Boolean satisfiability solution algorithm to obtain a Boolean sub-circuit. Then, replace the sub-circuit in quantum circuit C corresponding to the optimal sub-circuit with the Boolean sub-circuit to obtain the Boolean quantum circuit.

[0216] The algorithm compares the current scan count n with the user-input scan count TS of the algorithm sub-circuit. If the current scan count n is less than the algorithm sub-circuit scan count TS, the resulting Boolean quantum circuit is treated as a new quantum circuit and evaluated again. If the current scan count n is not less than the algorithm sub-circuit scan count TS, the Boolean quantum circuit is output. This Boolean quantum circuit reduces entanglement and operational complexity between qubits and improves overall execution efficiency.

[0217] Thus, by extracting sub-circuits containing only CNOT and SWAP gates from the quantum circuit, and then recompiling the heuristic CNOT-SWAP circuit to evaluate the sub-circuit redundancy depth and confirm the optimal sub-circuit, the optimal sub-circuit is optimized and sorted through heuristic sub-circuit scanning. Then, the SAT solver is called to perform deep optimization on the optimized sub-circuit obtained from the optimized sorting to obtain the Boolean sub-circuit. Finally, the sub-circuit corresponding to the optimal sub-circuit in the quantum circuit is replaced with the Boolean sub-circuit to obtain the Boolean quantum circuit. This solves the problem that existing SAT techniques, when solving complex quantum circuits, exhibit an exponential increase in SAT problem complexity with circuit complexity, leading to a sharp increase in solution time.

[0218] This application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, it causes the one or more processors to perform the deep optimization method of this application.

[0219] It is understood that a computer program includes computer program code. Computer program code can be in the form of source code, object code, executable files, or some intermediate form. Computer-readable storage media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, external hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution media, etc.

[0220] In this specification, the terms "specifically," "furthermore," "particularly," "understandably," etc., refer to specific features, structures, materials, or characteristics described in connection with embodiments or examples that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0221] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0222] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for depth optimization of a quantum circuit based on heuristic SAT scan, characterized in that, The method comprises: in response to a user input, setting a scan parameter of a quantum circuit, the scan parameter comprising a quantum circuit scan number, a maximum bit number and a test case number; in a case where a current scan number of the quantum circuit is less than the quantum circuit scan number, setting a maximum evaluation value as 0; constructing a first sub-circuit and a secondary adjacent set, wherein the first sub-circuit comprises a preselected quantum gate, the secondary adjacent set is an empty set, and the preselected quantum gate is a pre-determined 2-bit quantum gate; constructing a first adjacent set according to the first sub-circuit; performing removal processing on the first adjacent set according to the secondary adjacent set to obtain a second adjacent set; in a case where a number of quantum bits in a second sub-circuit is less than or equal to the maximum bit number, adding a 2-bit quantum gate in the second adjacent set to the first sub-circuit, the second sub-circuit being obtained after the 2-bit quantum gate in the second adjacent set is added to the first sub-circuit; in a case where a potential of the second adjacent set is 0, performing decomposition processing on the second sub-circuit to obtain a test sub-circuit; in a case where a current test number of the quantum circuit is less than the test case number, applying a test quantum state randomly selected from a ground state to the test sub-circuit to obtain a test inner product, and obtaining a maximum test inner product according to the test inner product; obtaining a current evaluation value according to the maximum test inner product; comparing the current evaluation value and the maximum evaluation value; in a case where the current evaluation value is greater than the maximum evaluation value, taking the current evaluation value as the maximum evaluation value to update the maximum evaluation value, and taking the second sub-circuit as an optimal sub-circuit; processing the quantum circuit according to the optimal sub-circuit and a Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit, so as to realize optimization of the quantum circuit.

2. The method of claim 1, wherein, The processing of the quantum circuit according to the optimal sub-circuit and the Boolean satisfiability solving algorithm to obtain the Boolean quantum circuit, so as to realize optimization of the quantum circuit, comprises: in a case where the optimal sub-circuit can be obtained, optimizing the optimal sub-circuit according to the Boolean satisfiability solving algorithm to obtain a Boolean sub-circuit; replacing a sub-circuit corresponding to the optimal sub-circuit in the quantum circuit with the Boolean sub-circuit to obtain the Boolean quantum circuit, and replacing the quantum circuit according to the Boolean quantum circuit.

3. The method of claim 1, wherein, The method further comprises: in a case where a potential of the second adjacent set is not 0, constructing a next first adjacent set according to the second sub-circuit; obtaining a next secondary adjacent set according to a union set of the second adjacent set and the secondary adjacent set; performing removal processing on the next first adjacent set according to the next secondary adjacent set to obtain a next second adjacent set; In a case that a number of qubits in the second sub-circuit is less than or equal to the maximum number of bits, adding a 2-bit quantum gate in the next second adjacent set to the first sub-circuit, the second sub-circuit being obtained by adding the 2-bit quantum gate in the next second adjacent set to the first sub-circuit, each of the 2-bit quantum gates including 2 qubits; determining a potential of the second adjacent set to obtain the optimal sub-circuit according to the potential of the second adjacent set.

4. The method of claim 1, wherein, In a case that the current test number of the quantum circuit is less than the number of test cases, applying a test quantum state randomly selected from a computational ground state to the test sub-circuit to obtain a test inner product, and obtaining a maximum test inner product according to the test inner product, including: constructing a test inner product set, the test inner product set being configured to store the test inner product; applying the test quantum state to the test sub-circuit to obtain the test inner product, and storing the test inner product in the test inner product set; obtaining the maximum test inner product from the test inner product set.

5. The method of claim 4, wherein, The applying the test quantum state to the test sub-circuit to obtain the test inner product, and storing the test inner product in the test inner product set, includes: in a case that the current test number is less than the number of test cases, increasing the current test number by 1; randomly selecting a quantum state from a computational ground state as the test quantum state; applying the test sub-circuit to the test quantum state to obtain an output quantum state; obtaining the test inner product according to the test quantum state and the output quantum state; storing the test inner product in the test inner product set.

6. The method of claim 4, wherein, The obtaining the current evaluation value according to the maximum test inner product, includes: calculating a test depth of the test sub-circuit; obtaining a first index by taking a product of a preset parameter and an average number of times as an index of Euler number, the average number of times being an average number of times that a quantum gate in the test sub-circuit is recompiled by a SAT solver; obtaining a current evaluation value according to the first index, the maximum test inner product, and the test depth.

7. The method of claim 1, wherein, The method further includes: in a case that the current scan number is greater than or equal to the number of scans of the quantum circuit, outputting the Boolean quantum circuit to implement optimization of the quantum circuit.

8. A computer device, comprising: The computer device includes a memory and a processor, the memory storing a computer program, in a case that the computer program is executed by the processor, implementing the method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, in a case that the computer program is executed by one or more processors, implementing the method according to any one of claims 1-7.

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