Shift register and driving method thereof, gate driving circuit and display device

Abstract

The invention provides a shift register and a driving method thereof, a gate driving circuit and a display device, and belongs to the field of display. The shift register comprises an input control sub-circuit which is configured to control the potential of a first node in response to an input signal transmitted by a signal input end; controlling the potential of the second node in response to a first clock signal transmitted by a first clock signal end; the cascade transmission sub-circuit is configured to write a signal of a first node into a third node in response to a first control signal transmitted by a first control signal end; in response to a signal of a third node, a second clock signal transmitted by a second clock signal end is output through the cascade transmission end; the output sub-circuit comprises a plurality of output units; the output unit is configured to write the signal of the first node into a fourth node in response to a second control signal transmitted by a second control signal end; and outputting a third clock signal transmitted by a third clock signal end through the first output end in response to the signal of the fourth node.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register and a driving method thereof, a gate driving circuit and a display device. Background Art

[0002] With the increase of display panel resolution (Pixels Per Inch, PPI), the layout of gate array integrated drive (GateDrive on Array, GOA) circuits has become increasingly difficult. In small-sized display panels, the longitudinal dimension of the GOA subcircuit is generally consistent with the longitudinal dimension of a row of pixels. However, with the increase of PPI, in large-sized display panels, the longitudinal dimension of the pixels is reduced, and the longitudinal dimension of the GOA subcircuit (such as a shift register) remains unchanged, so the longitudinal dimension of a row of pixels cannot be aligned with the longitudinal dimension of a GOA subcircuit. In large-sized display panels, with the increase of the number of pixel rows, the number of GOA subcircuits increases, and under the premise of ensuring a narrow frame, the problem of insufficient longitudinal layout space of the GOA subcircuit will arise. If a layout scheme of multiple columns of GOA subcircuits is adopted, the frame will inevitably increase. Therefore, it is impossible to achieve the GOA subcircuit layout of a high PPI display panel under the premise of ensuring a narrow frame in the related art. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register and a driving method thereof, a gate driving circuit and a display device.

[0004] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a shift register, including an input control subcircuit, a cascade transfer subcircuit and an output subcircuit;

[0005] The input control subcircuit is configured to control the potential of the first node in response to the input signal transmitted by the signal input terminal; and to control the potential of the second node in response to the first clock signal transmitted by the first clock signal terminal;

[0006] The cascade transfer subcircuit is configured to write the signal of the first node into the third node in response to the first control signal transmitted by the first control signal terminal; output the second clock signal transmitted by the second clock signal terminal through the cascade transfer terminal in response to the signal of the third node; or output the first power signal transmitted by the first power terminal through the cascade transfer terminal in response to the signal of the second node;

[0007] The output subcircuit includes multiple output units; the output unit is configured to write the signal of the first node to the fourth node in response to the second control signal transmitted by the second control signal terminal; output the third clock signal transmitted by the third clock signal terminal through the first output terminal in response to the signal of the fourth node; or, output the second power signal transmitted by the second power terminal through the first output terminal in response to the signal of the second node.

[0008] In some embodiments, the first output terminals of the output units are different; and different first output terminals are electrically connected to different gate lines.

[0009] In some embodiments, both the first control signal and the second control signal are AC signals.

[0010] In some embodiments, the effective potential of the second clock signal is the first voltage, and the invalid potential is the second voltage; the effective potential of the third clock signal is the first voltage, and the invalid potential is the second voltage; the first voltage is higher than the second voltage;

[0011] The effective potential of the first control signal is a third voltage, and the invalid potential is a fourth voltage; the effective potential of the second control signal is a third voltage, and the invalid potential is a fourth voltage; the third voltage is higher than the fourth voltage;

[0012] The third voltage is equal to the first voltage; and the fourth voltage is higher than the sum of the second voltage and the threshold voltage.

[0013] In some embodiments, the second clock signal terminal is different from the third clock signal terminal; the third clock signal terminal of each of the output units is different.

[0014] In some embodiments, the effective potential of the first clock signal is a first voltage, and the invalid potential is the second voltage; the first voltage is higher than the second voltage;

[0015] The effective potential of the second clock signal is the first voltage, and the invalid potential is the second voltage;

[0016] The effective potential of the third clock signal is the first voltage, and the ineffective potential is the second voltage.

[0017] In some embodiments, the first control signal terminal of the cascade transfer subcircuit and the second control signal terminal of each of the output units are the same.

[0018] In some embodiments, the cascade transfer subcircuit includes a ninth transistor, a third transistor, a fourth transistor, and a first capacitor;

[0019] The control electrode of the ninth transistor is electrically connected to the first control signal terminal, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first node;

[0020] The control electrode of the third transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the cascade transmission terminal;

[0021] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode is electrically connected to the cascade transmission terminal, and the second electrode is electrically connected to the first power supply terminal;

[0022] The first plate of the first capacitor is electrically connected to the third node, and the second plate is electrically connected to the cascade transfer end.

[0023] In some embodiments, the output unit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor;

[0024] The control electrode of the tenth transistor is electrically connected to the second control signal terminal, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first node;

[0025] The control electrode of the eleventh transistor is electrically connected to the fourth node, the first electrode is electrically connected to the third clock signal terminal, and the second electrode is electrically connected to the first output terminal;

[0026] The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode is electrically connected to the first output terminal, and the second electrode is electrically connected to the second power supply terminal;

[0027] The first plate of the second capacitor is electrically connected to the fourth node, and the second plate is electrically connected to the first output terminal.

[0028] In some embodiments, the input control subcircuit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third capacitor;

[0029] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode is electrically connected to the third power supply terminal, and the second electrode is electrically connected to the first node;

[0030] The control electrode of the second transistor is electrically connected to the first reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the fourth power supply terminal;

[0031] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal;

[0032] The control electrode of the sixth transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the first power supply terminal;

[0033] The control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the first clock signal terminal, and the second electrode is electrically connected to the second node;

[0034] The first plate of the third capacitor is electrically connected to the second node, and the second plate is electrically connected to the first power supply terminal.

[0035] In some embodiments, the shift register further includes a frame reset subcircuit; the frame reset subcircuit includes an eighth transistor;

[0036] The control electrode of the eighth transistor is electrically connected to the second reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal.

[0037] In a second aspect, an embodiment of the present disclosure further provides a gate driving circuit, which includes N cascaded shift registers as described in any one of the first aspects;

[0038] In addition to the first-stage shift register, the signal input terminal of the i+1th stage shift register is electrically connected to the cascade transmission terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0039] In some embodiments, the first clock signal terminal of the i-th level shift register is electrically connected to the second clock signal terminal of the i+1-th level shift register; the second clock signal terminal of the i-th level shift register is electrically connected to the first clock signal terminal of the i+1-th level shift register.

[0040] In a third aspect, an embodiment of the present disclosure further provides a method for driving a shift register, wherein the shift register is the shift register as described in any one of the first aspects; the method for driving the shift register comprises:

[0041] In the input stage, the input control subcircuit controls the potential of the first node to be the first voltage in response to the input signal transmitted by the signal input terminal; the cascade transfer subcircuit writes the first voltage of the first node to the third node in response to the third voltage of the first control signal; the output unit writes the first voltage of the first node to the fourth node in response to the third voltage of the second control signal;

[0042] In the output stage, the cascade transfer subcircuit outputs the second clock signal transmitted by the second clock signal terminal through the cascade transfer terminal in response to the first voltage of the third node; the output unit outputs the third clock signal transmitted by the third clock signal terminal through the first output terminal in response to the first voltage of the fourth node;

[0043] In the reset stage, the input control subcircuit controls the potential of the second node to be the first voltage and the potential of the first node to be the second voltage in response to the first clock signal transmitted by the first clock signal terminal; the cascade transfer subcircuit outputs the first power signal transmitted by the first power terminal through the cascade transfer terminal in response to the first voltage of the second node; writes the second voltage of the first node to the third node in response to the third voltage of the first control signal; the output unit outputs the second power signal transmitted by the second power terminal through the first output terminal in response to the first voltage of the second node; writes the second voltage of the first node to the fourth node in response to the third voltage of the second control signal;

[0044] In the holding phase, the cascade transfer subcircuit writes the second voltage of the first node into the third node in response to the fourth voltage of the first control signal; the output unit writes the second voltage of the first node into the fourth node in response to the fourth voltage of the second control signal;

[0045] The first voltage is higher than the second voltage; the third voltage is higher than the fourth voltage; the third voltage is equal to the first voltage; and the fourth voltage is higher than the sum of the second voltage and a threshold voltage.

[0046] In some embodiments, during the output stage, the method further includes:

[0047] The cascade transfer subcircuit, under the control of the first voltage of the third node and the first voltage of the second clock signal, uses the first capacitor to pull up the first voltage of the third node to a fifth voltage;

[0048] The output unit, under the control of the first voltage of the fourth node and the first voltage of the third clock signal, uses the first capacitor to pull up the first voltage of the fourth node to a fifth voltage.

[0049] In some embodiments, the timing of the third clock signal of each of the output units is different.

[0050] In some embodiments, the timings of the third clock signals of some of the output units are the same, and the timings of the third clock signals of the remaining output units are different.

[0051] In some embodiments, both the first control signal and the second control signal are AC signals; and the timing of the first control signal and the second control signal is the same.

[0052] In a fourth aspect, an embodiment of the present disclosure further provides a display device, which includes a gate driving circuit as described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1a A schematic diagram of the corresponding relationship between the shift register and the pixel position layout in a related small-size display panel;

[0054] Figure 1b A schematic diagram of the corresponding relationship between the shift register and the pixel position layout in the related large-size display panel;

[0055] Figure 2 A schematic diagram of a shift register provided in an embodiment of the present disclosure;

[0056] Figure 3 A scanning effect diagram within the range of human eye gaze under the timing control of the third clock signal provided in an embodiment of the present disclosure;

[0057] Figure 4 A schematic diagram of a circuit structure of a shift register provided in an embodiment of the present disclosure;

[0058] Figure 5 A schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0059] Figure 6 Timing diagram of the shift register working phase provided by the embodiment of the present disclosure

[0060] Figure 7 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present disclosure;

[0061] Figure 8 A schematic diagram of the structure of another gate driving circuit provided by an embodiment of the present disclosure;

[0062] Fig. 9 A schematic diagram of a shift register cascade structure provided by an embodiment of the present disclosure;

[0063] Fig.10 for Fig. 9 Timing diagram of the cascade structure shown;

[0064] Fig.11 A schematic diagram of the corresponding relationship between the shift register and the pixel position layout provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0066] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0067] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0068] It should be noted that the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first electrode is the source of the P-type transistor, the second electrode is the drain of the P-type transistor, and when a low-level signal is input to the gate, the source and drain are turned on; when an N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when a high-level signal is input to the gate, the source and drain are turned on.

[0069] In the related art, usually, one GOA sub-circuit is used to drive a row of pixels. Figure 1a As shown in FIG. 1 , in a small-size display panel, the longitudinal dimension Py2 of the GOA subcircuit 01 is substantially consistent with the longitudinal dimension Py1 of a row of pixels 02 (Pixel). However, as the PPI increases, Figure 1b As shown, in a large-size display panel, the longitudinal dimension Py1 of the pixel 02 is reduced and recorded as Py3, and the longitudinal dimension of the GOA subcircuit 01 remains unchanged at the original dimension Py2. Therefore, the longitudinal dimension Py3 of a row of pixels 02 cannot be aligned with the longitudinal dimension Py2 of a GOA subcircuit 01, that is, the longitudinal dimension Py2 of a GOA subcircuit 01 is larger than the longitudinal dimension Py3 of a row of pixels 02. In order to achieve high PPI, it is necessary to expand a part of the frame and adopt a double-row layout scheme to drive the pixels. Therefore, the related art cannot realize the GOA subcircuit layout of a high PPI display panel while ensuring a narrow frame.

[0070] In view of this, the embodiments of the present disclosure provide a shift register, which essentially changes the circuit structure of the original shift register and adds multiple output units to drive multiple rows of pixels respectively. That is, one shift register can be used to drive multiple rows of pixels, thereby achieving a higher PPI while ensuring a narrow frame.

[0071] Figure 2 A schematic diagram of a shift register provided by an embodiment of the present disclosure, such as Figure 2 As shown, the shift register includes an input control subcircuit 1, a cascade transfer subcircuit 2 and an output subcircuit 33. The output subcircuit 33 includes a plurality of output units 31. The input control subcircuit 1 includes a signal input terminal Input and a first clock signal terminal CKB; the cascade transfer subcircuit 2 includes a first control signal terminal VGH_G, a second clock signal terminal CKC, a first power supply terminal L VGLand a cascade transmission terminal OutC; the output unit 31 includes a second control signal terminal VGH_n, a third clock signal terminal CLK_n, a second power supply terminal VGL_G and a first output terminal Out_n. Wherein, n represents the number of output units, that is, the output sub-circuit 33 includes n output units, and n is an integer greater than or equal to 2. For example, when n is 4, it means that the output sub-circuit 3 includes 4 output units. The second control signal terminal of the first output unit 31 is recorded as VGH_1, the third clock signal terminal is recorded as CLK_1, the second power supply terminal is recorded as VGL_1, and the first output terminal Out_1; the second control signal terminal of the second output unit 31 is recorded as VGH_2, the third clock signal terminal is recorded as CLK_2, the second power supply terminal is recorded as VGL_2, and the first output terminal Out_2; the second control signal terminal of the third output unit 31 is recorded as VGH_3, the third clock signal terminal is recorded as CLK_3, the second power supply terminal is recorded as VGL_3, and the first output terminal Out_3; the second control signal terminal of the fourth output unit 31 is recorded as VGH_4, the third clock signal terminal is recorded as CLK_4, the second power supply terminal is recorded as VGL_4, and the first output terminal Out_4. Similarly, the second control signal terminal of the nth output unit 31 is recorded as VGH_n, the third clock signal terminal is recorded as CLK_n, the second power supply terminal is recorded as VGL_n, and the first output terminal Out_n.

[0072] The signal input terminal Input is used to receive an input signal. For the first-stage shift register, the input signal is a start signal (STV). For the second to N-stage shift registers, the input signal is a signal output by the cascade transmission terminal of the previous-stage shift register. The first clock signal terminal CKB is used to receive a first clock signal; the second clock signal terminal CKC is used to receive a second clock signal; and the third clock signal terminal CKL_n is used to receive a third clock signal. The first clock signal terminal CKB, the second clock signal terminal CKC and the third clock signal terminal CKL_n are different, so the first clock signal, the second clock signal and the third clock signal are independently controlled. The first control signal terminal VGH_G is used to receive a first control signal; the second control signal terminal VGH_n is used to receive a second control signal. The first power supply terminal L VGL The first control signal terminal VGH_G, the second control signal terminal VGH_n and the third control signal terminal may be the same or different.

[0073] The input control subcircuit 1 is configured to control the potential of the first node PUCN in response to the input signal transmitted by the signal input terminal Input; and to control the potential of the second node PD in response to the first clock signal transmitted by the first clock signal terminal CKB. Here, the potential of the first node PUCN is opposite to the potential of the second node PD. For example, the potential of the first node PUCN is a valid first voltage V1, and the potential of the second node PD is an invalid second voltage V2; the potential of the first node PUCN is an invalid second voltage V2, and the potential of the second node PD is a valid first voltage V1. Whether the potential of the first node PUCN is valid or invalid, or whether the potential of the second node PD is valid or invalid, determines the output result of the cascade transfer subcircuit 2 and the output result of the output unit 31.

[0074] The cascade transfer subcircuit 2 and each output unit 31 share the same first node PUCN and the same second node PD.

[0075] The cascade transfer sub-circuit 2 is configured to write the signal of the first node PUCN to the third node (not shown in the figure, see PUC in the figure below) in response to the first control signal transmitted by the first control signal terminal VGH_G; output the second clock signal transmitted by the second clock signal terminal CKC through the cascade transfer terminal OutC in response to the signal of the third node; or, in response to the signal of the second node PD, output the second clock signal transmitted by the first power terminal L VGL The transmitted first power signal is output through the cascade transmission terminal OutC. In one case, the potential of the first node PUCN is the first voltage V1, and the potential of the second node PD is the second voltage V2; at this time, the cascade transmission subcircuit 2 responds to the first control signal transmitted by the first control signal terminal VGH_G, and writes the first voltage V1 of the first node PUCN into the third node. At this time, the voltage of the third node is valid, so the second clock signal transmitted by the second clock signal terminal CKC can continue to respond to the first voltage V1 of the third node and output through the cascade transmission terminal OutC. Since the potential of the second node PD is the second voltage V2 at this time, the cascade transmission subcircuit 2 cannot output the first power terminal L VGL In another case, the potential of the first node PUCN is the second voltage V2, and the potential of the second node PD is the first voltage V1. The cascade transfer subcircuit 2 responds to the first control signal transmitted by the first control signal terminal VGH_G, and writes the second voltage V2 of the first node PUCN to the third node. Since the voltage of the third node is invalid at this time, the second clock signal transmitted by the second clock signal terminal CKC cannot be output. However, the voltage of the second node PD is valid at this time, so the cascade transfer subcircuit 2 can respond to the first voltage V1 of the second node PD and output the first power terminal L using the cascade transfer terminal OutC. VGL The first power signal is transmitted.

[0076] Here, the cascade transfer subcircuit 2 mainly utilizes the cascade transfer terminal OutC to output the cascade signal (the second clock signal or the first power supply signal) as the input signal of the next stage (or next several stages) of the shift register.

[0077] For any output unit 31, it is configured to write the signal of the first node PUCN into the fourth node (not shown in the figure, see PUn in the figure below) in response to the second control signal transmitted by the second control signal terminal VGH_n; output the third clock signal transmitted by the third clock signal terminal CKL_n through the first output terminal Out_n in response to the signal of the fourth node; or output the second power signal transmitted by the second power supply terminal VGL_G through the first output terminal Out_n in response to the signal of the second node PD. In one case, the potential of the first node PUCN is the first voltage V1, and the potential of the second node PD is the second voltage V2; at this time, the output unit 31 writes the first voltage V1 of the first node PUCN into the fourth node in response to the second control signal transmitted by the second control signal terminal VGH_n. At this time, the voltage of the fourth node is valid, so the third clock signal transmitted by the third clock signal terminal CKL_n can continue to be output through the first output terminal Out_n in response to the first voltage V1 of the fourth node. Since the potential of the second node PD is the second voltage V2 at this time, the output unit 31 cannot output the second power signal transmitted by the second power supply terminal VGL_G. In another case, the potential of the first node PUCN is the second voltage V2, and the potential of the second node PD is the first voltage V1. The output unit 31 responds to the second control signal transmitted by the second control signal terminal VGH_n, and writes the second voltage V2 of the first node PUCN to the fourth node. Since the voltage of the fourth node is invalid at this time, the third clock signal transmitted by the third clock signal terminal CKL_n cannot be output. However, the voltage of the second node PD is valid at this time, so the output unit 31 can respond to the first voltage V1 of the second node PD and output the second power signal transmitted by the second power terminal VGL_G using the first output terminal Out_n.

[0078] Here, a single output unit 31 mainly uses the signal (third clock signal or second power supply signal) output by the first output terminal Out_n as the gate drive signal of a row of pixels corresponding to the shift register. Optionally, the first output terminals Out_n of each output unit 31 are different; different first output terminals Out_n are electrically connected to different gate lines, that is, electrically connected to different rows of pixels. The same shift register can be connected to multiple rows of pixels through multiple different first output terminals Out_n, and provide gate drive signals to multiple rows of pixels.

[0079] Here, the cascade transmission terminal OutC is different from the first output terminal Out_n.

[0080] In the disclosed embodiment, the cascade transfer subcircuit 2 and the output unit 31 are independently set, so that the signal output by the cascade transfer subcircuit 2 and the signal output by the output unit 31 do not affect each other. At the same time, each output unit 31 is independently set, so that the signals output by each output unit 31 do not affect each other. At the same time, multiple output units 31 can provide gate drive signals to multiple rows of pixels, that is, a shift register can be used to drive multiple rows of pixels, and a higher PPI can be achieved while ensuring a narrow frame.

[0081] In some embodiments, the second clock signal terminal CKC is different from the third clock signal terminal CKL_n; the third clock signal terminal CKL_n of each output unit 31 is different, so that the cascade transmission sub-circuit and each output unit 31 can be independently controlled, so that the output of the cascade signal and each row of gate drive signals, and the output of each row of gate drive signals do not affect each other. At the same time, the different clock signal terminals can realize independent control of each clock signal, so that the output timing of the clock signal can be flexibly adjusted.

[0082] Optionally, the timing of the third clock signal of each output unit 31 is different. It should be noted that the timing in the circuit refers to the switching of the signal between high and low potentials in the order of time. Different timing means that the potential jump time nodes of the compared signals are inconsistent, but it does not mean that the potentials of the two are different at the same time node. Exemplarily, the time when the third clock signal of the previous output unit 31 jumps from an invalid potential to a valid potential is earlier than the time when the third clock signal of the next output unit jumps from an invalid potential to a valid potential. For example, Figure 2 As shown, the time when the third clock signal of the first output unit 31 jumps from the invalid potential to the valid potential is earlier than the time when the third clock signal of the second output unit 31 jumps from the invalid potential to the valid potential; the time when the third clock signal of the second output unit 31 jumps from the invalid potential to the valid potential is earlier than the time when the third clock signal of the third output unit 31 jumps from the invalid potential to the valid potential; and so on, the time when the third clock signal of the n-1th output unit 31 jumps from the invalid potential to the valid potential is earlier than the time when the third clock signal of the nth output unit 31 jumps from the invalid potential to the valid potential. Here, the timing of the third clock signal of each output unit 31 is different, which can realize the line-by-line scanning of pixels, avoid the loss of pixel resolution, and ensure the high-definition display effect.

[0083] Optionally, the timing of the third clock signal of some output units 31 is the same, and the timing of the third clock signal of the remaining output units 31 is different. The same timing means that the potential jump time nodes of the compared signals are consistent, but it does not mean that the potentials of the two signals at the same time node must be the same. The embodiment of the present disclosure takes the same timing, the same potential jump time nodes, and the same potential at the same time node as an example for explanation. This solution can be applied to application scenarios where the pixel resolution is dynamically adjusted, such as when the human eye observes the screen, and its gaze range is limited, such as Figure 3 As shown, for pixels near the human eye's gaze point (such as within the gaze range Q), the timing of the third clock signal of the output unit 31 corresponding to each of them is different, so that the pixels within the gaze range can be scanned line by line to ensure high-definition display effects. For pixels outside the human eye's gaze point (such as outside the gaze range Q), the timing of the third clock signal of the output unit 31 corresponding to each of them is the same, that is, multi-line scanning. At this time, even if some clarity is lost, since the position within this range is not the position where the human eye is looking, the human eye cannot perceive whether the picture is clear, so it will not affect the user's viewing experience. At the same time, since the timing of the third clock signal of some output units 31 is the same, for the same third clock signal, the charging time of the effective level of each third clock signal can be increased, thereby improving a series of problems such as inaccurate grayscale due to insufficient charging of pixels, affecting the display effect, etc. Alternatively, for the same third clock signal, without increasing the charging time of the effective level, the saved charging time can be distributed to the third clock signals with different timings, so as to increase the charging time of the effective level of the third clock signals with different timings, and further improve the clarity of the picture within the gaze range Q. In addition, different third clock signal terminals CKL_n receive the same third clock signal, such as the same clock signal, which can save the transmission amount of the clock signal, thereby saving the power consumption of the clock driver.

[0084] Optionally, the timing of the second clock signal is different from that of the third clock signal. The time s when the second clock signal jumps from an invalid potential to a valid potential is between s1 and s2. Among them, s1 represents the time when the third clock signal of the first output unit 31 jumps from an invalid potential to a valid potential, and s2 represents the time when the third clock signal of the nth output unit 31 jumps from an invalid potential to a valid potential.

[0085] Optionally, the second clock signal has the same timing as the third clock signal of a certain output unit 31. Exemplarily, the time when the second clock signal jumps from an invalid potential to a valid potential is the time when the third clock signal of the kth output unit 31 jumps from an invalid potential to a valid potential; if n is an odd number, k=(n+1) / 2; if n is an even number, k=n / 2+1. If n is 4, k is 3.

[0086] In some embodiments, the first clock signal, the second clock signal and the third clock signal are all square wave signals. Optionally, the effective potentials of the first clock signal, the second clock signal and the third clock signal are all the same; and the invalid potentials of the first clock signal, the second clock signal and the third clock signal are all the same.

[0087] It should be noted that the values ​​of the effective potential and the invalid potential of the clock signal are related to the characteristics of the transistors in the shift register. The transistors in the shift register disclosed in the present invention are described by taking N-type transistors as an example.

[0088] Optionally, the effective potentials of the first clock signal, the second clock signal, and the third clock signal are all the first voltage V1. The invalid potentials of the first clock signal, the second clock signal, and the third clock signal are all the second voltage V2. The first voltage V1 is higher than the second voltage V2. For example, the first voltage V1 is 8V, and the second voltage V2 is -8V.

[0089] In some embodiments, the first control signal and the second control signal are both AC signals. The first control signal is an AC signal, which enables the cascade transfer subcircuit 2 to flexibly control whether the signal of the first node PUCN is written to the third node PUC, and avoid the influence of the signal of the third node PUC on the output unit 31 in a specific stage (for example, the output stage t2 and the holding stage t4). The second control signal is an AC signal, which enables the output unit 31 to flexibly control whether the signal of the first node PUCN is written to the fourth node PUn, and avoid the influence of the signal of the fourth node PUn in a specific stage (for example, the output stage t2 and the holding stage t4) on the cascade transfer subcircuit 2.

[0090] Optionally, the first control signal and the second control signal are both square wave signals. The effective potentials of the first control signal and the second control signal are both the third voltage V3, and the invalid potentials are both the fourth voltage V4. The third voltage V3 is higher than the fourth voltage V4. The effective potential of the first control signal can control the signal of the first node PUCN to be written into the third node PUC. The invalid potential of the first control signal can cut off the writing of the first node PUCN signal into the third node PUC, which also means preventing the signal of the third node PUC from affecting the potential of the first node PUCN. Similarly, the effective potential of the second control signal can control the writing of the signal of the first node PUCN into the fourth node PUn. The invalid potential of the second control signal can cut off the writing of the first node PUCN signal into the fourth node PUn, which also means preventing the signal of the fourth node PUn from affecting the potential of the first node PUCN.

[0091] Optionally, the timing of the first control signal and the second control signal is the same. In this way, the first control signal and the second control signal are valid at the same time and invalid at the same time. When the first control signal and the second control signal are valid at the same time, that is, when both are pulled up from the fourth voltage V4 to the third voltage V3, the cascade transfer subcircuit 2 controls the signal of the first node PUCN to be written into the third node PUC, and at the same time, the output unit 31 controls the signal of the first node PUCN to be written into the fourth node PUn. When the first control signal and the second control signal are invalid at the same time, that is, when both are pulled down from the third voltage V3 to the fourth voltage V4, the electrical connection relationship between the third node PUC and the first node PUCN is disconnected, and the electrical connection relationship between the fourth node PUn and the first node PUCN is disconnected, so that the electrical connection relationship between the third node PUC and the fourth node PUn is disconnected, thereby isolating the third node PUC and the fourth node PUn, so that the potentials of the two do not affect each other, and the cascade transfer subcircuit 2 and the output unit 31 are independently controlled.

[0092] This embodiment is different from the solution in which the first control signal and the second control signal use conventional DC signals, and avoids the situation in which the cascade transfer sub-circuit 2 pulls up the potential of the third node PUC in the output stage t2, affecting the potential of the fourth node PUn of the output unit 31, causing the output unit 31 to output a signal at a stage where it should not output, thereby affecting pixel driving.

[0093] In some embodiments, the third voltage V3 is equal to or lower than the first voltage V1 and higher than the second voltage V2. The fourth voltage V4 is higher than the second voltage V2 and lower than the third voltage V3.

[0094] Optionally, the third voltage V3 is equal to the first voltage V1; the fourth voltage V4 is higher than the sum of the second voltage V2 and the threshold voltage. The threshold voltage refers to the threshold voltage of the transistor in the shift register. Exemplarily, the third voltage V3 is +8V, the fourth voltage V4 is greater than -8V+Vth, and Vth represents the threshold voltage, such as 1V, that is, the fourth voltage V4 is greater than -7V and less than +8V. For example, the fourth voltage V4 is set to -7V, -6V, -5V, -4V, -3V, -2V, -1V or 0V.

[0095] Here, the third voltage V3 is equal to the first voltage V1, such as 8V, which can make the cascade transfer subcircuit 2 effectively control the signal (first voltage V1) of the first node PUCN to be written into the third node PUC in the input stage t1, and make the output unit 31 effectively control the signal (first voltage V1) of the first node PUCN to be written into the fourth node PUn. In the output stage t2, since the third node PUC and the fourth node PUn are both high potentials (first voltage V1) at this time, the fourth voltage V4 is set higher than the sum of the second voltage V2 and the threshold voltage, such as 0V, so that the cascade transfer subcircuit 2 is affected by the transistor switching characteristics (for example, the gate-source voltage Vgs of the ninth transistor T9 and the tenth transistor T10 is V4-V1=0-8=-8V), which is much smaller than the threshold voltage 1V, ensuring that the electrical connection between the first node PUCN and the third node PUC is completely disconnected in the output stage t2, and the electrical connection between the first node PUCN and the fourth node PUn is completely disconnected, so as to avoid the mutual influence between the high potentials of the third node PUC and the fourth node PUn. In the reset phase t3, the cascade transfer subcircuit 2 can effectively control the signal (second voltage V2) of the first node PUCN to be written into the third node PUC, and the output unit 31 can effectively control the signal (second voltage V2) of the first node PUCN to be written into the fourth node PUn. At the same time, in the holding stage t4, since the third node PUC and the fourth node PUn are both at a low potential (the second voltage V2) at this time, on this basis, the fourth voltage V4 is set to be higher than the sum of the second voltage V2 and the threshold voltage, such as 0V, so that the cascade transfer sub-circuit 2 can be affected by the transistor switching characteristics (for example, the gate-source voltage Vgs of the ninth transistor T9 and the tenth transistor T10 is Vgs=V4-V2=0-(-8)=8V), which is much larger than the threshold voltage 1V, ensuring that in the holding stage t4, even if the first control signal and the second control signal are loaded with the fourth voltage V4 (low potential), the first node PUCN and the third node PUC, as well as the first node PUCN and the fourth node PUn can still be turned on, so that the second voltage V2 of the first node PUCN is continuously written into the third node PUC and the fourth node PUn, thereby keeping the cascade transfer terminal OutC continuously outputting the first power supply signal, and keeping the first output terminal Out_n continuously outputting the second power supply signal.

[0096] In some embodiments, based on the same timing of the first control signal and the second control signal, the first control signal terminal VGH_G of the cascade transfer subcircuit 2 and the second control signal terminal VGH_n of each output unit 31 can be set to be the same, which can reduce the layout space and facilitate the realization of a narrow frame.

[0097] In some embodiments, Figure 4 A schematic diagram of a circuit structure of a shift register provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the cascade transfer subcircuit 2 includes a ninth transistor T9, a third transistor T3, a fourth transistor T4 and a first capacitor C1. Among them, the control electrode of the ninth transistor T9 is electrically connected to the first control signal terminal VGH_G, the first electrode is electrically connected to the third node PUC, and the second electrode is electrically connected to the first node PUCN; the control electrode of the third transistor T3 is electrically connected to the third node PUC, the first electrode is electrically connected to the second clock signal terminal CKC, and the second electrode is electrically connected to the cascade transfer terminal OutC; the control electrode of the fourth transistor T4 is electrically connected to the second node PD, the first electrode is electrically connected to the cascade transfer terminal OutC, and the second electrode is electrically connected to the first power supply terminal L VGL ; The first plate of the first capacitor C1 is electrically connected to the third node PUC, and the second plate is electrically connected to the cascade transmission terminal OutC. Specifically, the first control signal transmitted by the first control signal terminal VGH_G can control the on-off of the ninth transistor T9. For example, the ninth transistor T9 is turned on in response to the first control signal being the third voltage V3, and the signal of the first node PUCN can be written into the third node PUC. At the same time, the signal of the third node PUC can control the on-off of the third transistor T3. For example, the third transistor T3 is turned on in response to the potential of the third node PUC being the first voltage V1. The second clock signal transmitted by the second clock signal terminal CKC uses the first capacitor C1 to further couple the first voltage V1 of the third node PUC to the fifth voltage V5, thereby maintaining the on state of the third transistor T3, so that the first voltage V1 of the second clock signal can be stably output through the cascade transmission terminal OutC until the second clock signal jumps to the second voltage V2 and is cut off. For another example, the third transistor T3 is turned off in response to the potential of the third node PUC being the second voltage V2; at this time, the fourth transistor T4 is turned on in response to the first voltage V1 of the second node PD, thereby switching the first power supply terminal L VGL The transmitted first power signal is outputted through the cascade transmission terminal OutC. Here, the first power signal is a low level signal, such as the second voltage V2 (-8V).

[0098] In some embodiments, continuing as Figure 4As shown, the output unit 31 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a second capacitor C2; the control electrode of the tenth transistor T10 is electrically connected to the second control signal terminal VGH_n, the first electrode is electrically connected to the fourth node PUn, and the second electrode is electrically connected to the first node PUCN; the control electrode of the eleventh transistor T11 is electrically connected to the fourth node PUn, the first electrode is electrically connected to the third clock signal terminal CKL_n, and the second electrode is electrically connected to the first output terminal Out_n; the control electrode of the twelfth transistor T12 is electrically connected to the second node PD, the first electrode is electrically connected to the first output terminal Out_n, and the second electrode is electrically connected to the second power supply terminal VGL_G; the first electrode plate of the second capacitor C2 is electrically connected to the fourth node PUn, and the second electrode plate is electrically connected to the first output terminal Out_n. Specifically, the second control signal transmitted by the second control signal terminal VGH_n can control the on and off of the tenth transistor T10, for example, the tenth transistor T10 is turned on in response to the second control signal being the third voltage V3, and the signal of the first node PUCN can be written into the fourth node PUn. At the same time, the signal of the fourth node PUn can control the on-off of the eleventh transistor T11. For example, the eleventh transistor T11 is turned on in response to the potential of the fourth node PUn being the first voltage V1, and the third clock signal transmitted by the third clock signal terminal CKL_n further couples the first voltage V1 of the fourth node PUn to the fifth voltage V5 using the second capacitor C2, thereby maintaining the on state of the eleventh transistor T11, so that the first voltage V1 of the third clock signal can be stably output through the first output terminal Out_n until the third clock signal jumps to the second voltage V2 and is cut off. For another example, the eleventh transistor T11 is disconnected in response to the potential of the fourth node PUn being the second voltage V2; at this time, the twelfth transistor T12 is turned on in response to the first voltage V1 of the second node PD, thereby outputting the second power signal transmitted by the second power supply terminal VGL_G through the first output terminal Out_n. Here, the second power signal is a low-level signal, such as the second voltage V2 (-8V).

[0099] The embodiment of the present disclosure includes multiple output units 31. For any output unit 31, the working principle is the same, but the timing of the third clock signal of each output unit 31 is different, which leads to different timing of the third clock signal output by each output unit 31 through the first output terminal Out_n, that is, different timing of the output gate drive signal, thereby realizing line-by-line scanning.

[0100] In some embodiments, continuing as Figure 4As shown, the input control subcircuit 1 includes a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a third capacitor C3. The control electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the first electrode is electrically connected to the third power supply terminal CN, and the second electrode is electrically connected to the first node PUCN; the control electrode of the second transistor T2 is electrically connected to the first reset control terminal Reset, the first electrode is electrically connected to the first node PUCN, and the second electrode is electrically connected to the fourth power supply terminal CNB; the control electrode of the fifth transistor T5 is electrically connected to the second node PD, the first electrode is electrically connected to the first node PUCN, and the second electrode is electrically connected to the third voltage V3 of the first power supply terminal; the control electrode of the sixth transistor T6 is electrically connected to the first node PUCN, the first electrode is electrically connected to the second node PD, and the second electrode is electrically connected to the third voltage V3 of the first power supply terminal; the control electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CKB, the first electrode is electrically connected to the first clock signal terminal CKB, and the second electrode is electrically connected to the second node PD; the first plate of the third capacitor C3 is electrically connected to the second node PD, and the second plate is electrically connected to the third voltage V3 of the first power supply terminal.

[0101] Specifically, the input signal transmitted by the signal input terminal Input can control the on-off of the first transistor T1, for example, the first transistor T1 is turned on in response to the input signal being the first voltage V1, and the third power signal transmitted by the third power terminal CN is written into the first node PUCN. Here, the third power signal is a high level signal, that is, the first voltage V1 (+8V). The first reset control signal transmitted by the first reset control terminal Reset can control the on-off of the second transistor T2, for example, the second transistor T2 is turned on in response to the first reset control signal being the first voltage V1, and the fourth power signal transmitted by the fourth power terminal CNB is written into the first node PUCN. Here, the effective potential of the first reset control signal is the first voltage V1, and the invalid potential is the second voltage V2. The fourth power signal is a low level signal, for example, the second voltage V2 (-8V). The signal of the second node PD can control the on-off of the fifth transistor T5, for example, the fifth transistor T5 is turned on in response to the second node PD being the first voltage V1, and the first power signal transmitted by the third voltage V3 of the first power terminal is written into the first node PUCN. The signal of the first node PUCN can control the on-off of the sixth transistor T6. For example, the sixth transistor T6 is turned on in response to the first node PUCN being the first voltage V1, and the first power signal provided by the third voltage V3 of the first power terminal is written into the second node PD. The first clock signal provided by the first clock signal terminal CKB is used to control the on-off of the seventh transistor T7. For example, the seventh transistor T7 is turned on in response to the first clock signal being the first voltage V1, and the first clock signal which is the first voltage V1 at this time is written into the second node PD.

[0102] In some embodiments, Figure 5A schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure, such as Figure 5 As shown, Figure 4 Compared with the circuit structure, a frame reset subcircuit is added. The frame reset subcircuit includes an eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the second reset control terminal TRST, the first electrode is electrically connected to the first node PUCN, and the second electrode is electrically connected to the third voltage V3 of the first power supply terminal. Specifically, the second reset signal provided by the second reset control terminal TRST is used to control the on and off of the eighth transistor T8. For example, the eighth transistor T8 is turned on in response to the second reset signal being the first voltage V1, and the first power supply signal is written to the first node PUCN. The first power supply signal is a low-level signal (second voltage V2) to reset the first node PUCN before the frame start stage.

[0103] Exemplarily, in the shift register provided by the embodiment of the present disclosure, the orthographic projections of the output units 31 on the horizontal reference plane are arranged side by side along the extension direction of the gate line. The shift register includes a first conductive layer, a second conductive layer and a semiconductor layer. The control electrode of the ninth transistor T9 and the control electrode of the tenth transistor T10 are both located in the first conductive layer, and the control electrode of the ninth transistor T9 and the control electrode of the tenth transistor T10 are formed by a mask; the first electrode and the second electrode of the ninth transistor T9, and the first electrode and the second electrode of the tenth transistor T10 are both located in the second conductive layer and are formed by a mask, which saves the preparation process to a great extent and is conducive to reducing the preparation cost.

[0104] The above is a detailed description of the circuit structure of the shift register provided by the embodiment of the present disclosure. The working principle of the shift register provided by the embodiment of the present disclosure is further described in detail below.

[0105] The embodiment of the present disclosure also provides a shift register driving method. Figure 6 The timing diagram of the shift register working phase provided by the embodiment of the present disclosure is as follows: Figure 6 As shown, the working phases of the shift register specifically include input phase t1, output phase t2, reset phase t3 and hold phase t4. Here, the timing of the control signal output by the first control signal terminal VGH_G and the second control signal terminals VGH1-n of each output unit 31 is the same as an example for description, that is, VGH'.

[0106] In the input stage t1, the input control subcircuit 1 controls the potential of the first node PUCN to be the first voltage V1 in response to the input signal transmitted by the signal input terminal Input; the cascade transfer subcircuit 2 writes the first voltage V1 of the first node PUCN into the third node PUC in response to the third voltage V3 of the first control signal; the output unit 31 writes the first voltage V1 of the first node PUCN into the fourth node PUn in response to the third voltage V3 of the second control signal.

[0107] by Figure 4 The circuit structure of the shift register shown in FIG. 4, and n is taken as 4 as an example, as Figure 6 As shown, in the input stage t1, the first transistor T1 is turned on in response to the input signal being the first voltage V1, and at this time, the first node PUCN introduces the third power signal (high level signal), that is, the first voltage V1. Afterwards, the first control signal terminal VGH_G and the second control signal terminal VGH_n of each input unit simultaneously transmit the third voltage V3, the ninth transistor T9 and the tenth transistor T10 of each input unit are turned on, and the first voltage V1 is written into the third node PUC and the fourth node PUn. The fourth node PUn can represent any one of PU1~4.

[0108] In the output stage t2, the cascade transfer subcircuit 2 responds to the first voltage V1 of the third node PUC, and outputs the second clock signal transmitted by the second clock signal terminal CKC through the cascade transfer terminal OutC; the output unit 31 responds to the first voltage V1 of the fourth node PUn, and outputs the third clock signal transmitted by the third clock signal terminal CKL_n through the first output terminal Out_n.

[0109] by Figure 4 The circuit structure of the shift register shown in FIG. 4, and n is taken as 4 as an example, as Figure 6As shown, in the output stage t2, the first control signal terminal VGH_G and the second control signal terminal VGH_n of each input unit simultaneously transmit the fourth voltage V4, that is, the control electrode of the ninth transistor T9 and the control electrode of the tenth transistor T10 of each input unit are both the fourth voltage V4, and because the source of the ninth transistor T9 (the third node PUC) and the source of the tenth transistor T10 of each input unit (the fourth node PUn) are respectively written with the first voltage V1 of the previous stage, the gate-source voltage Vgs of the ninth transistor T9 (the tenth transistor T10) is V4-V1 at this time, and since V4>V2+Vth is pre-set, for example, the fourth voltage V4 is set to -7V, -6V, -5V, -4V, -3V, -2V, -1V or 0V. Therefore, the gate-source voltage Vgs of the ninth transistor T9 (the tenth transistor T10) is less than -8V, that is, much less than the threshold voltage 1V, so that the ninth transistor T9 and the tenth transistor T10 can be completely disconnected in the output stage t2, and the ninth transistor T9 and the tenth transistor T10 are prevented from leaking, and the high potential of the third node PUC and the fourth node PUn is prevented from affecting the signal of the first node PUCN. Further, the third transistor T3 is turned on in response to the first voltage V1 of the third node PUC, and the cascade transmission terminal OutC outputs the second clock signal. Since the second clock signal is an AC signal, in the output stage t2, the cascade transmission terminal OutC may output the first voltage V1 or the second voltage V2, but only the output first voltage V1 is used as the effective input signal of the next stage shift register. The eleventh transistor T11 is turned on in response to the first voltage V1 of the fourth node PUn, and the first output terminal Out_n outputs the third clock signal. Since the third clock signal is an AC signal, in the output stage t2, the first output terminal Out_n may output the first voltage V1 or the second voltage V2, but only the output first voltage V1 is used as the effective gate driving signal for a row of pixels.

[0110] In the reset stage t3, the input control subcircuit 1 controls the potential of the second node PD to be the first voltage V1, and controls the potential of the first node PUCN to be the second voltage V2 in response to the first clock signal transmitted by the first clock signal terminal CKB; the cascade transfer subcircuit 2 responds to the first voltage V1 of the second node PD, and outputs the first power signal transmitted by the third voltage V3 of the first power terminal through the cascade transfer terminal OutC; responds to the third voltage V3 of the first control signal, and writes the second voltage V2 of the first node PUCN to the third node PUC; the output unit 31 responds to the first voltage V1 of the second node PD, and outputs the second power signal transmitted by the second power terminal VGL_G through the first output terminal Out_n; responds to the third voltage V3 of the second control signal, and writes the second voltage V2 of the first node PUCN to the fourth node PUn.

[0111] by Figure 4 The circuit structure of the shift register shown in FIG. 4, and n is taken as 4 as an example, as Figure 6 As shown, in the reset phase t3, the seventh transistor T7 is turned on in response to the first voltage V1 of the first clock signal, and the first voltage V1 is written into the second node PD. At the same time, the fifth transistor T5 is turned on in response to the first voltage V1 of the second node PD, and the second voltage V2 of the third power supply signal (low level signal) is written into the first node PUCN to reset the first node PUCN. At the same time, the ninth transistor T9 is turned on in response to the third voltage V3 of the first control signal, and the second voltage V2 of the first node PUCN is written into the third node PUC, and the third transistor T3 is turned off; similarly, the tenth transistor T10 is turned on in response to the third voltage V3 of the second control signal, and the second voltage V2 of the first node PUCN is written into the fourth node PUn, and the eleventh transistor T11 is turned off. The fourth transistor T4 is turned on in response to the first voltage V1 of the second node PD, and the cascade transfer terminal OutC outputs the second voltage V2 of the first power supply signal (low level signal). The twelfth transistor T12 is turned on in response to the first voltage V1 of the second node PD, and the first output terminal Out_n outputs the second voltage V2 of the second power supply signal (low level signal).

[0112] In the holding stage t4, the cascade transfer subcircuit 2 writes the second voltage V2 of the first node PUCN into the third node PUC in response to the fourth voltage V4 of the first control signal; the output unit 31 writes the second voltage V2 of the first node PUCN into the fourth node PUn in response to the fourth voltage V4 of the second control signal; the first voltage V1 is higher than the second voltage V2; the third voltage V3 is higher than the fourth voltage V4; the third voltage V3 is equal to the first voltage V1; the fourth voltage V4 is higher than the sum of the second voltage V2 and the threshold voltage.

[0113] by Figure 4 The circuit structure of the shift register shown in FIG. 4, and n is taken as 4 as an example, as Figure 6As shown, in the holding stage t4, the voltage of the control electrode of the ninth transistor T9 is the fourth voltage V4, and the voltage of the first electrode of the ninth transistor T9 (that is, the voltage of the third node PUC) is the second voltage V2 written in the previous stage (reset stage t3). At this time, the gate-source voltage Vgs of the ninth transistor T9 is V4-V2. Since V4>V2+Vth is pre-set, Vgs>Vth. The ninth transistor T9 is an N-type transistor. Affected by its switching characteristics, Vgs>Vth satisfies the conduction condition. That is, the control electrode of the ninth transistor T9 is still turned on even if it receives the low-level fourth voltage V4, so that the cascade transfer subcircuit 2 continues to write the low-level second voltage V2 to the third node PUC in the holding stage t4, ensuring that the third transistor T3 is completely turned off, and preventing the third transistor T3 from being affected by the AC characteristics of the second clock signal and leaking to the cascade transfer terminal OutC.

[0114] In the holding stage t4, the voltage of the control electrode of the tenth transistor T10 is the fourth voltage V4, and the voltage of the first electrode of the tenth transistor T10 (that is, the voltage of the fourth node PUn) is the second voltage V2 written in the previous stage (reset stage t3). At this time, the gate-source voltage Vgs of the tenth transistor T10 is V4-V2. Since V4>V2+Vth is pre-set, Vgs>Vth. The tenth transistor T10 is an N-type transistor. Affected by its switching characteristics, Vgs>Vth satisfies the conduction condition. That is, the control electrode of the tenth transistor T10 is still turned on even if it receives the low-level fourth voltage V4, so that the output unit 31 continues to write the low-level second voltage V2 to the fourth node PUn in the holding stage t4, ensuring that the eleventh transistor T11 is completely turned off, and preventing the eleventh transistor T11 from being affected by the AC characteristics of the third clock signal and leaking to the first output terminal Out_n.

[0115] In the holding stage t4, the second node PD maintains the first voltage V1 written in the previous stage (reset stage t3), the fourth transistor T4 continues to be turned on, and the cascade transfer terminal OutC continues to output the second voltage V2 of the first power supply signal; the twelfth transistor T12 continues to be turned on, and the first output terminal Out_n continues to output the second voltage V2 of the second power supply signal.

[0116] In some embodiments, in the output stage t2, it also includes: the cascade transfer subcircuit 2, under the control of the first voltage V1 of the third node PUC and the first voltage V1 of the second clock signal, uses the first capacitor C1 to pull up the first voltage V1 of the third node PUC to a fifth voltage V5; the output unit 31, under the control of the first voltage V1 of the fourth node PUn and the first voltage V1 of the third clock signal, uses the first capacitor C1 to pull up the first voltage V1 of the fourth node PUn to a fifth voltage V5.

[0117] by Figure 4The circuit structure of the shift register shown in FIG. 4, and n is taken as 4 as an example, as Figure 6 As shown, the third transistor T3 is turned on under the control of the first voltage V1. At this time, the voltage of the first electrode of the third transistor T3 is the first voltage V1 of the second clock signal, which charges the second plate of the first capacitor C1 through the third transistor T3. The first capacitor C1 is coupled to increase the potential of the first plate, that is, from the first voltage V1 to the fifth voltage V5. The fifth voltage V5 is approximately twice the first voltage V1, so that the gate-source voltage Vgs of the third transistor T3 is V5-V1≈V1>Vth, and it is continuously turned on, thereby ensuring the stable output of the cascade transfer terminal OutC in the output stage t2.

[0118] The eleventh transistor T11 is turned on under the control of the first voltage V1. At this time, the voltage of the first electrode of the eleventh transistor T11 is the first voltage V1 of the third clock signal, which charges the second electrode plate of the second capacitor C2 through the eleventh transistor T11. The second capacitor C2 is coupled to increase the potential of the first electrode plate, that is, from the first voltage V1 to the fifth voltage V5. The fifth voltage V5 is approximately twice the first voltage V1, so that the gate-source voltage Vgs of the eleventh transistor T11 is V5-V1≈V1>Vth, and it is continuously turned on, thereby ensuring the stable output of the first output terminal Out_n in the output stage t2.

[0119] In some embodiments, the timing of the third clock signal of each output unit 31 is different. Figure 6 As shown, the time when the third clock signal transmitted by the third clock signal terminal CLK_1 jumps from the invalid potential to the valid potential is earlier than the time when the third clock signal transmitted by the third clock signal terminal CLK_2 jumps from the invalid potential to the valid potential; the time when the third clock signal transmitted by the third clock signal terminal CLK_2 jumps from the invalid potential to the valid potential is earlier than the time when the third clock signal transmitted by the third clock signal terminal CLK_3 jumps from the invalid potential to the valid potential; the time when the third clock signal transmitted by the third clock signal terminal CLK_3 jumps from the invalid potential to the valid potential is earlier than the time when the third clock signal transmitted by the third clock signal terminal CLK_4 jumps from the invalid potential to the valid potential. Here, the timing of the third clock signals of each output unit 31 is different, which can realize the line-by-line scanning of pixels, avoid the loss of pixel resolution, and ensure the high-definition display effect.

[0120] In some embodiments, the timing of the third clock signals of some output units 31 is the same, and the timing of the third clock signals of the remaining output units 31 is different. This solution can be applied to application scenarios where the pixel resolution is dynamically adjusted, such as when the human eye observes the screen and its gaze range is limited, such as Figure 3As shown, for pixels near the human eye's gaze point (such as within the gaze range Q), the timing of the third clock signal of the output unit 31 corresponding to each of them is different, so that the pixels within the gaze range can be scanned line by line to ensure high-definition display effect. For pixels outside the human eye's gaze point (such as outside the gaze range Q), the timing of the third clock signal of the output unit 31 corresponding to each of them is the same. Even if some clarity is lost, since this range is not the position where the human eye is looking, the human eye cannot perceive whether the picture is clear, so it will not affect the user's viewing experience. At the same time, since the timing of the third clock signal of some output units 31 is the same, for the same third clock signal, the charging time of the effective level of each third clock signal can be increased, so as to improve a series of problems such as inaccurate grayscale caused by insufficient charging of pixels, affecting the display effect, etc. Alternatively, for the same third clock signal, without increasing the charging time of the effective level, the saved charging time can be divided into third clock signals with different timings to increase the charging time of the effective level of the third clock signals with different timings, and further improve the clarity of the picture within the gaze range Q. In addition, different third clock signal terminals CKL_n receive the same third clock signal, for example, the same clock signal, which can save the transmission amount of the clock signal and thus save the power consumption of the clock driver.

[0121] In some embodiments, the first control signal and the second control signal are both AC signals; the timing of the first control signal and the second control signal is the same. In this way, the first control signal and the second control signal are both valid and invalid at the same time. When the first control signal and the second control signal are valid at the same time, that is, when both are pulled up from the fourth voltage V4 to the third voltage V3, the cascade transfer subcircuit 2 controls the signal of the first node PUCN to be written into the third node PUC, and at the same time, the output unit 31 controls the signal of the first node PUCN to be written into the fourth node PUn. When the first control signal and the second control signal are invalid at the same time, that is, when both are pulled down from the third voltage V3 to the fourth voltage V4, the electrical connection relationship between the third node PUC and the first node PUCN is disconnected, and the electrical connection relationship between the fourth node PUn and the first node PUCN is disconnected, so that the electrical connection relationship between the third node PUC and the fourth node PUn is disconnected, thereby isolating the third node PUC and the fourth node PUn, so that the potentials of the two do not affect each other, and the cascade transfer subcircuit 2 and the output unit 31 are independently controlled. This embodiment is different from the solution in which the first control signal and the second control signal use conventional DC signals, and avoids the situation in which the cascade transfer sub-circuit 2 pulls up the potential of the third node PUC in the output stage t2, affecting the potential of the fourth node PUn of the output unit 31, causing the output unit 31 to output a signal at a stage where it should not output, thereby affecting pixel driving.

[0122] In addition, the embodiment of the present disclosure further provides a gate driving circuit. Figure 7 A schematic diagram of a gate drive circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the gate drive circuit includes N cascaded shift registers such as those formed by any of the above embodiments and structures. Specifically, except for the first-stage shift register, the signal input terminal Input of the i+1-stage shift register is electrically connected to the cascade transmission terminal OutC of the i-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0123] In some embodiments, Figure 7 As shown, the gate drive circuit includes a first clock signal line CK1, a second clock signal line CK2, n third clock signal lines CLKn, a first control line VHH11 and a second control line VHH21. The first clock signal line CK1 is electrically connected to the first clock signal terminal CKB, the second clock signal line CK2 is electrically connected to the second clock signal terminal CKC, and a plurality of third clock signal lines CLKn are electrically connected to the third clock signal terminals CKL_n of different output units 31, respectively; for example, the third clock signal line CLK1 is electrically connected to the third clock signal terminal CKL_1, the third clock signal line CLK2 is electrically connected to the third clock signal terminal CKL_2, the third clock signal line CLK3 is electrically connected to the third clock signal terminal CKL_3, and the third clock signal line CLK4 is electrically connected to the third clock signal terminal CKL_4. The first control line VHH11 electrically connects the first control signal terminal VGH_G (also VGH') and the second control signal terminal VGH_n (also VGH') in the shift register with odd bits; the second control line VHH21 electrically connects the first control signal terminal VGH_G (also VGH') and the second control signal terminal VGH_n (also VGH') in the shift register with even bits.

[0124] Optionally, the first control line VGH11 and the second control line VGH2 are a pair of AC signal lines, and the control signals provided by the two are alternately connected to the shift register.

[0125] Optionally, continue as Figure 7 As shown, the cascade transmission terminal OutC of the i+1th stage shift register is multiplexed as the first reset control terminal Reset of the ith stage shift register.

[0126] Optionally, the cascade transmission terminal OutC of the (i+2)th stage shift register is multiplexed as the first reset control terminal Reset of the i-th stage shift register.

[0127] In some embodiments, Figure 8 A schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, it is Figure 7The difference is that the gate drive circuit includes multiple groups of third clock signal lines CLKn, and each group of third clock signal lines CLKn includes n third clock signal lines CLKn. Take two groups of third clock signal lines CLKn as an example. For example, the first group of third clock signal lines 51 includes third clock signal lines CLK1-4; the second group of third clock signal lines 52 includes third clock signal lines CLK5-8. The n third clock signal lines CLKn in the first group of third clock signal lines 51 are respectively used to electrically connect the third clock signal terminals CKL_n in the shift registers with odd bits. The n third clock signal lines CLKn in the second group of third clock signal lines 52 are respectively used to electrically connect the third clock signal terminals CKL_n in the shift registers with even bits.

[0128] Optionally, the cascade transmission terminal OutC of the (i+2)th stage shift register is multiplexed as the first reset control terminal Reset of the i-th stage shift register.

[0129] In some embodiments, Fig. 9 A schematic diagram of a shift register cascade structure provided by an embodiment of the present disclosure, such as Fig. 9 As shown, the first clock signal terminal CKB of the i-th stage shift register is electrically connected to the second clock signal terminal CKC of the i+1-th stage shift register; the second clock signal terminal CKC of the i-th stage shift register is electrically connected to the first clock signal terminal CKB of the i+1-th stage shift register.

[0130] Fig.10 for Fig. 9 The timing diagram of the cascade structure shown in Fig.11 As shown, it includes input stage t1, output stage t2, reset stage t3 and holding stage t4. The timing control of the i-th stage shift register can be found in Figure 6 The timing control principle of the i-th stage shift register is the same as that of the above-mentioned embodiments, and the repeated parts will not be described in detail.

[0131] In addition, the embodiment of the present disclosure also provides a display device, which includes the gate drive circuit as described above. Further, the display device also includes pixels and a pixel drive circuit for driving the pixels; the gate drive circuit is electrically connected to the pixel drive circuit to provide a gate drive signal to the pixel drive circuit.

[0132] Fig.11 A schematic diagram of the corresponding relationship between the shift register and the pixel position layout provided in the embodiment of the present disclosure, such as Fig.11 As shown, the longitudinal size Py2 of a shift register 100 may correspond to multiple rows of pixels 1 (Pixel), for example, Py2=n×Py3, where Py3 represents the longitudinal size of a row of pixels, which can achieve a higher PPI while ensuring a narrow frame.

[0133] For example, the display device can be any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations on the present disclosure.

[0134] The display device provided by the embodiment of the present disclosure can be applied to large-size, high-resolution display scenarios.

[0135] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register comprising an input control subcircuit, a cascade transfer subcircuit and an output subcircuit; The input control subcircuit is configured to control the potential of the first node in response to an input signal transmitted from the signal input terminal; controlling the potential of the second node in response to a first clock signal transmitted by the first clock signal terminal; The cascade transfer subcircuit is configured to write the signal of the first node into a third node in response to the first control signal transmitted by the first control signal terminal; In response to the signal of the third node, outputting the second clock signal transmitted by the second clock signal terminal through the cascade transmission terminal; Alternatively, in response to the signal of the second node, the first power signal transmitted by the first power terminal is output through the cascade transmission terminal; The output subcircuit comprises a plurality of output units; the output unit is configured to write the signal of the first node into the fourth node in response to the second control signal transmitted by the second control signal terminal; In response to the signal of the fourth node, the third clock signal transmitted by the third clock signal terminal is output through the first output terminal; or, in response to the signal of the second node, the second power signal transmitted by the second power terminal is output through the first output terminal.

2. The shift register according to claim 1, wherein: The first output ends of the output units are different; different first output ends are electrically connected to different gate lines.

3. The shift register according to claim 1, wherein: The first control signal and the second control signal are both AC signals.

4. The shift register according to claim 3, wherein: The effective potential of the second clock signal is the first voltage, and the invalid potential is the second voltage; the effective potential of the third clock signal is the first voltage, and the invalid potential is the second voltage; The first voltage is higher than the second voltage; The effective potential of the first control signal is the third voltage, and the invalid potential is the fourth voltage; the effective potential of the second control signal is the third voltage, and the invalid potential is the fourth voltage; the third voltage is higher than the fourth voltage; The third voltage is equal to the first voltage; and the fourth voltage is higher than the sum of the second voltage and a threshold voltage.

5. The shift register according to claim 1, wherein: The second clock signal terminal is different from the third clock signal terminal; the third clock signal terminals of each output unit are different.

6. The shift register according to claim 1, wherein: The effective potential of the first clock signal is a first voltage, and the invalid potential is a second voltage; the first voltage is higher than the second voltage; The effective potential of the second clock signal is the first voltage, and the ineffective potential is the second voltage; The effective potential of the third clock signal is the first voltage, and the ineffective potential is the second voltage.

7. The shift register according to claim 1, wherein: The first control signal terminal of the cascade transfer subcircuit and the second control signal terminal of each of the output units are the same.

8. The shift register according to any one of claims 1 to 7, wherein: The cascade transfer subcircuit includes a ninth transistor, a third transistor, a fourth transistor and a first capacitor; The control electrode of the ninth transistor is electrically connected to the first control signal terminal, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the cascade transmission terminal; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode is electrically connected to the cascade transmission terminal, and the second electrode is electrically connected to the first power supply terminal; The first plate of the first capacitor is electrically connected to the third node, and the second plate is electrically connected to the cascade transfer end.

9. The shift register according to any one of claims 1 to 7, wherein: The output unit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a second capacitor; The control electrode of the tenth transistor is electrically connected to the second control signal terminal, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first node; The control electrode of the eleventh transistor is electrically connected to the fourth node, the first electrode is electrically connected to the third clock signal terminal, and the second electrode is electrically connected to the first output terminal; The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode is electrically connected to the first output terminal, and the second electrode is electrically connected to the second power supply terminal; The first plate of the second capacitor is electrically connected to the fourth node, and the second plate is electrically connected to the first output terminal.

10. The shift register according to any one of claims 1 to 7, wherein: The input control subcircuit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor and a third capacitor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode is electrically connected to the third power supply terminal, and the second electrode is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the fourth power supply terminal; The control electrode of the fifth transistor is electrically connected to the second node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the first power supply terminal; The control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the first clock signal terminal, and the second electrode is electrically connected to the second node; The first plate of the third capacitor is electrically connected to the second node, and the second plate is electrically connected to the first power supply terminal.

11. The shift register according to claim 10, wherein: The shift register further includes a frame reset subcircuit; the frame reset subcircuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the second reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal.

12. A gate drive circuit, comprising N cascaded shift registers according to any one of claims 1 to 11; In addition to the first-stage shift register, the signal input terminal of the i+1th stage shift register is electrically connected to the cascade transmission terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

13. The gate driving circuit according to claim 12, wherein: The first clock signal terminal of the i-th stage shift register is electrically connected to the second clock signal terminal of the i+1-th stage shift register; the second clock signal terminal of the i-th stage shift register is electrically connected to the first clock signal terminal of the i+1-th stage shift register.

14. A method for driving a shift register, wherein: The shift register is a shift register according to any one of claims 1 to 11; the driving method of the shift register comprises: In the input stage, the input control subcircuit controls the potential of the first node to be the first voltage in response to the input signal transmitted by the signal input terminal; the cascade transfer subcircuit writes the first voltage of the first node to the third node in response to the third voltage of the first control signal; the output unit writes the first voltage of the first node to the fourth node in response to the third voltage of the second control signal; In the output stage, the cascade transfer subcircuit outputs the second clock signal transmitted by the second clock signal terminal through the cascade transfer terminal in response to the first voltage of the third node; the output unit outputs the third clock signal transmitted by the third clock signal terminal through the first output terminal in response to the first voltage of the fourth node; In the reset stage, the input control subcircuit controls the potential of the second node to be the first voltage and the potential of the first node to be the second voltage in response to the first clock signal transmitted by the first clock signal terminal; the cascade transfer subcircuit outputs the first power signal transmitted by the first power terminal through the cascade transfer terminal in response to the first voltage of the second node; writes the second voltage of the first node to the third node in response to the third voltage of the first control signal; the output unit outputs the second power signal transmitted by the second power terminal through the first output terminal in response to the first voltage of the second node; writes the second voltage of the first node to the fourth node in response to the third voltage of the second control signal; In the holding phase, the cascade transfer subcircuit writes the second voltage of the first node into the third node in response to the fourth voltage of the first control signal; the output unit writes the second voltage of the first node into the fourth node in response to the fourth voltage of the second control signal; The first voltage is higher than the second voltage; the third voltage is higher than the fourth voltage; the third voltage is equal to the first voltage; and the fourth voltage is higher than the sum of the second voltage and a threshold voltage.

15. The driving method of the shift register according to claim 14, wherein: In the output stage, it also includes: The cascade transfer subcircuit, under the control of the first voltage of the third node and the first voltage of the second clock signal, uses the first capacitor to pull up the first voltage of the third node to a fifth voltage; The output unit, under the control of the first voltage of the fourth node and the first voltage of the third clock signal, uses the first capacitor to pull up the first voltage of the fourth node to a fifth voltage.

16. The driving method of the shift register according to claim 14, wherein: The timing of the third clock signal of each output unit is different.

17. The driving method of the shift register according to claim 14, wherein: The timing sequences of the third clock signals of some of the output units are the same, and the timing sequences of the third clock signals of the remaining output units are different.

18. The driving method of the shift register according to claim 14, wherein: The first control signal and the second control signal are both AC signals; the timing of the first control signal and the second control signal is the same.

19. A display device, wherein: Comprising a gate drive circuit as claimed in claim 12 or 13.

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