Memory device and read method

Abstract

The invention relates to a memory device and a reading method for the same. The memory device can be a stereoscopic AND-OR gate NAND flash memory with high capacity and high performance. The memory device includes first to third memory cell strings. Each memory cell string includes first to third memory cells. A read method includes performing a first read operation of the memory device to the second memory cell in the second memory cell string, the first read operation including applying a first bit line voltage to a first bit line, a second bit line, and a third bit line; in response to the first read operation failing, a second read operation of the memory device is performed, the second read operation including applying a set of second bit line voltages to the first bit line, the second bit line, and the third bit line.

Description

Technical Field

[0001] The present invention relates to a storage unit reading technology applied to a NAND flash, and more particularly to a memory device and a reading method using the same. Background Art

[0002] High-capacity and high-performance integrated circuit memories, including three-dimensional (3D) NAND flash memory, are being developed continuously, hoping to reduce the size of memory cells and increase data storage density by using three-dimensional stacking technology and triple-level cells (MLC).

[0003] At present, the data retention capability of 3D flash memory still has room for improvement. When accessing data in 3D flash memory, the more bits that can be stored in the third-level storage unit, the more likely errors will occur. The increase in the number of program / erase cycles may also affect the reliability of data storage. Even if error correction codes (ECC) are used to maintain the reliability of the stored data, the use of complex error correction codes will lead to a significant increase in layout area and cost. Therefore, how to reduce the raw bit error rate (RBER) of 3D flash memory and improve its reliability is one of the main research directions of 3D flash memory. Summary of the invention

[0004] The invention provides a memory device and a reading method, which increase the success rate of the reading operation by changing the bit line voltage and improve the data reliability of the memory device.

[0005] The reading method for a memory device of the present invention is applicable to a memory device. The memory device includes a first memory cell string, a second memory cell string, and a third memory cell string, wherein the second memory cell string is between the first memory cell string and the third memory cell string, and each of the first memory cell string, the second memory cell string, and the third memory cell string includes a first memory cell, a second memory cell, and a third memory cell connected in series, wherein the second memory cell is arranged between the first memory cell and the third memory cell. The reading method includes: implementing a first reading operation to the memory device, which includes: applying a first bit line voltage to a first bit line, a second bit line and a third bit line, wherein the first bit line, the second bit line and the third bit line are respectively connected to the first memory cell string, the second memory cell string and the third memory cell string; and in response to the failure of the first reading operation, implementing a second reading operation of the memory device, which includes: applying a group of second bit line voltages to the first bit line, the second bit line and the third bit line, respectively, wherein the group of second bit line voltages includes a third bit line voltage, a fourth bit line voltage and a fifth bit line voltage applied to the first bit line, the second bit line and the third bit line, respectively, and the third bit line voltage and the fifth bit line voltage are different from the first bit line voltage.

[0006] The memory device of the present invention includes a memory array and a memory controller. The memory array includes a first memory cell string, a second memory cell string and a third memory cell string, wherein the second memory cell string is between the first memory cell string and the third memory cell string. Each of the first memory cell string, the second memory cell string and the third memory cell string includes a first memory cell, a second memory cell and a third memory cell connected in series, wherein the second memory cell is arranged between the first memory cell and the third memory cell. The memory controller is used to control the memory array. The memory controller is used to perform: a first read operation of the memory device, and the first read operation includes: applying a first bit line voltage to a first bit line, a second bit line and a third bit line, wherein the first bit line, the second bit line and the third bit line are respectively connected to the first memory cell string, the second memory cell string and the third memory cell string; and in response to the failure of the first read operation, implementing a second read operation of the memory device, which includes: applying a group of second bit line voltages to the first bit line, the second bit line and the third bit line, respectively, wherein the group of second bit line voltages includes a third bit line voltage, a fourth bit line voltage and a fifth bit line voltage applied to the first bit line, the second bit line and the third bit line, respectively, and the third bit line voltage and the fifth bit line voltage are different from the first bit line voltage.

[0007] Based on the above, the memory device and reading method described in the embodiment of the present invention use a first reading operation to determine whether the data retention function of the target memory cell is normal, and when the first reading operation fails, a second reading operation is implemented to change the bit line voltages of multiple target memory cells to adjust the threshold voltage distribution curve in the target memory cell, thereby increasing the success rate of the first reading operation, thereby improving the data reliability of a non-volatile memory device (e.g., flash memory). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic structural diagram of a memory device according to an embodiment of the present invention.

[0009] Figure 2 It is a partial schematic diagram of an embodiment of the invention, taking triple-level cells (TLC) as an example to illustrate the shift of the threshold voltage distribution curve.

[0010] Figure 3 is a flow chart of a reading method for a memory device according to an embodiment of the present invention.

[0011] Figure 4 is a schematic diagram of a portion of a memory array in a memory device according to a first embodiment of the present invention.

[0012] Figure 5 1 is a schematic diagram of threshold voltage distribution curves corresponding to the memory cells C12, C22, and C32 according to the first embodiment of the present invention.

[0013] Figure 6 is a schematic diagram of a portion of a memory array in a memory device according to a second embodiment of the present invention.

[0014] Figure 7 1 is a schematic diagram of threshold voltage distribution curves corresponding to memory cells C12, C22, and C32 according to the second embodiment of the present invention.

[0015] Figure 8 is a schematic diagram of a portion of a memory array in a memory device according to a third embodiment of the present invention.

[0016] Fig. 9 1 is a schematic diagram of threshold voltage distribution curves corresponding to memory cells C12, C22, and C32 according to the third embodiment of the present invention.

[0017] Fig.10 is a schematic diagram of a portion of a memory array in a memory device according to a fourth embodiment of the present invention.

[0018] Fig.111 is a schematic diagram of threshold voltage distribution curves corresponding to memory cells C12 , C22 , and C32 according to the fourth embodiment of the present invention.

[0019] Fig.12 is a schematic diagram of a portion of a memory array in a memory device according to a fifth embodiment of the present invention.

[0020] Fig.13 1 is a schematic diagram of threshold voltage distribution curves corresponding to memory cells C12 , C22 , and C32 according to the fifth embodiment of the present invention.

[0021] Fig.14 is a schematic diagram of a portion of a memory array in a memory device according to a sixth embodiment of the present invention.

[0022] Fig.15 1 is a schematic diagram of threshold voltage distribution curves corresponding to memory cells C12 , C22 , and C32 according to the sixth embodiment of the present invention.

[0023] Fig.16 It is a schematic diagram of threshold voltage distribution curves corresponding to the initial threshold voltages of the potential states Er, P1-P7 in the TLC and before and after the threshold voltage distribution curves are adjusted according to an embodiment of the present invention.

[0024] Description of reference numerals:

[0025] 100: Memory device

[0026] 110: Memory controller

[0027] 120: Sensor amplifier

[0028] 150: Stereo Block

[0029] 152: Page

[0030] 154, CS1~CS3: storage cell string

[0031] 156.SSL: string selection line

[0032] 157, C11~C33: Storage unit

[0033] 158. GSL: Ground Select Line

[0034] 159. CSL: Common Source Line

[0035] 210-5~210-7、220-5~220-7、510、520、530-1~530-2、710-2、710-6~710-7、720-2、720-6~720-7、730-6~730-7、910、920、930、1110、1120、1130、1310-0~1310-4、1320-0~1320-4、1330-0~1330-1、1510~1530、1610-0~1610-7、1620-0~1620-7、1630-0~1630-7:Threshold voltage distribution curve

[0036] 290: Arrow

[0037] S310-S325: Steps of the method for reading a memory device

[0038] 950: Block

[0039] Vth: threshold voltage

[0040] Vpass: pass voltage

[0041] Vread: read voltage

[0042] Vr0~Vr7, Vrn, Vrn+1: reference voltage

[0043] SST: string select line transistor

[0044] GST: Ground Select Line Transistor

[0045] BL1, BL2, BL3, BLn, BLn+1: bit lines

[0046] WL0~WL95:Word line

[0047] X, Y, X: coordinate axis

[0048] Er, P0: Erase potential state

[0049] P10~P7: Potential state

[0050] VBL1, VBL3~VBL5: bit line voltage ΔV, ΔV1~ΔV4: voltage difference

[0051] HPS: High-Level Potential State Group

[0052] MPS: Middle level potential state group

[0053] LPS: Low Latent State Group DETAILED DESCRIPTION

[0054] Figure 1FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 of this embodiment may be Figure 1 The illustrated three-dimensional memory is, for example, a NAND type cache memory device. The memory device 100 includes a memory array, a memory controller 110, and a sensing amplifier (SA) 120. A three-dimensional block 150 in a three-dimensional memory chip represents a portion of the memory array. The memory controller 110 is used to control the memory array and corresponding hardware (e.g., voltage driver, sensing amplifier, scan driver, etc.) and implement various steps in the embodiments of the present invention.

[0055] The plurality of memory cells in the three-dimensional block 150 are arranged in three dimensions (e.g., an XYZ coordinate system). Taking the memory cell 157 as an example, the memory cell 157 is coupled to the corresponding word line WL0 and the bit line BLn. The word lines (e.g., word lines WL0-WL95) are formed by corresponding conductor layers. The memory cells in the memory block 150 are divided into a plurality of pages 152. Each page 152 may be, for example, a layer of memory cells in the XY plane. Memory cells on the same layer (same page) may be coupled to the same word line (e.g., word lines WL0-WL95) and obtain corresponding word line voltages. Memory cells on different layers (different pages) may be coupled to different word lines (e.g., word line WL0 and word line WL95) and obtain different corresponding word line voltages. Each page 152 may be connected to a corresponding contact in the driving circuit, for example, to an X decoder (or scan driver). Each word line has a corresponding voltage driver, and these voltage drivers may be controlled by the memory controller 110 or corresponding hardware. The plurality of memory cells in the memory cell string 154 belong to different pages.

[0056] A memory cell string (e.g., string 154) includes a plurality of memory cells connected in series vertically along the Z direction. The memory cell is configured as a string selection transistor SST coupled to a string selection line SSL 156, and the memory cell may also be configured as a ground selection transistor GST coupled to a ground selection line GSL 158. String 154 is connected to one or more drivers, such as a data driver. String 154 including memory cell 157 is connected to a common source line CSL 159 via a ground selection transistor GST. SSL 156 may be a conductive line or conductive layer formed on top of each page 152 (or word line layer). Each memory cell string (e.g., string 154) is connected to a corresponding bit line (e.g., bit line BLn). The sense amplifier 120 is coupled to the corresponding bit line to read the voltage on the bit line, and uses the potential state and threshold voltage value corresponding to the memory cell to be read and located on this bit line to determine the data in this memory cell.

[0057] The block 150 may include a plurality of SSLs 156 disposed on top of each memory cell string 154 or on top of the topmost page 152. The GSL 158 may be a conductive line or conductive layer formed on the bottom of each page 152 (or word line layer). The CSL 159 may be a conductive layer or a plurality of conductive lines formed below the GSL 158 on the substrate of the three-dimensional storage chip. A plurality of virtual lines or corresponding layers (not shown) may also be disposed between the string selection line SSL 156 and the topmost page 152 or between the ground selection line GSL 158 and the bottommost page 152.

[0058] Figure 2 It is a partial schematic diagram of an embodiment using a three-layer storage cell (TLC) as an example to illustrate the shift of the threshold voltage distribution curve. For example, the potential state of TLC can be divided into the erased potential state Er (also known as potential state P0) and potential states P1 to P7. Moreover, it is known through experiments that different potential states in TLC can be shifted by different threshold voltages after programming, and the amount of shift of the threshold voltage distribution curve corresponding to each potential state is also different. In this embodiment, the erased potential state Er (also known as potential state P0) and the potential state P1 are divided into the low-level potential state group LPS. The potential states P2 to P4 are divided into the middle-level potential state group MPS. The potential states P5 to P7 are divided into the high-level potential state group HPS. The low-level potential state group LPS, the middle-level potential state group MPS and the high-level potential state group HPS have different threshold voltages. Figure 2 The potential states P5 to P7 in the high potential state group HPS and their corresponding threshold voltage distribution curves are presented. Figure 2 The X-axis shows the voltage magnitude of the threshold voltage, Figure 2 The Y-axis presents the number of memory cells located in the corresponding potential states P5 to P7. Figure 2 Three threshold voltage distribution curves are formed. Figure 2 The threshold voltage distribution curves 210-5 to 210-7 represented by the solid lines are threshold voltage distribution curves corresponding to potential states P5 to P7 when the memory device is at an initial threshold voltage (e.g., a memory device just shipped). The threshold voltage distribution curves 210-5 to 210-7 can be clearly distinguished based on the reference voltages Vr5 to Vr7. Figure 2The threshold voltage distribution curves 220-5 to 220-7 represented by the dashed lines are the threshold voltage distribution curves corresponding to the potential states P5 to P7 after the threshold voltage of the memory device shifts (which may be caused by a large number of programming / erase cycles (P / E cycles) or other factors). Due to the threshold voltage shift, if the threshold voltage distribution curves 220-5 to 220-7 are still distinguished based on the reference voltages Vr5 to Vr7, there is a probability that data retention errors will occur (such as the three areas indicated by arrows 290), and the higher the level of the potential states P5 to P7 (such as the potential state P7 is a high-level potential state; the potential state P5 is a lower-level potential state relative to the potential state P7), the higher the probability of data errors. On the other hand, the threshold voltage shift does not necessarily only reduce the voltage value of the threshold voltage distribution curve corresponding to the potential state (such as the threshold voltage distribution curve corresponding to the potential state P3 to P7), but also increase the threshold voltage distribution curve corresponding to the potential state (such as the threshold voltage distribution curve corresponding to the potential state Er, P1 to P2).

[0059] The embodiment of the present invention uses the method of changing the bit line voltage in the second read operation to adjust the threshold voltage distribution curve of the target memory cell, thereby increasing the success rate of the target memory cell for the read operation, thereby improving the data reliability of the non-volatile memory device (such as flash memory). In detail, the embodiment of the present invention implements a first read operation on a specific memory cell (which means a memory cell in a specific page or a memory cell in a specific word line), and when the first read operation fails, the second read operation is implemented to adjust at least two bit line (BL) voltages in the flash memory device, thereby correspondingly adjusting the threshold voltage distribution curve of the target memory cell. The second read operation is performed on the target memory cell to adjust the threshold voltage distribution curve (for example, to move the threshold voltage distribution curve to a higher threshold voltage or a lower threshold voltage). In the second read operation, the success rate of the target memory cell is improved. There are multiple embodiments for adjusting the threshold voltage distribution curve of the memory cell by changing the bit line (BL) voltage in the flash memory device, which are described one by one below.

[0060] Figure 3 is a flow chart of a reading method for a memory device according to an embodiment of the present invention. Figure 4 is a schematic diagram of a portion of a memory array in a memory device according to a first embodiment of the present invention. The reading method is applicable to Figure 1 The memory device 100 and Figure 4 For ease of explanation, Figure 4Some elements of the memory array are omitted, and mainly present three memory cell strings CS1-CS3, memory cells C11-C33 in the memory cell strings CS1-CS3, word lines WL1-WL3 and bit lines BL1-BL3. The aforementioned memory cell strings CS1-CS3 can be memory cell strings at any position in the memory array. In other words, the memory device 100 includes a first memory cell string CS1, a second memory cell string CS2 and a third memory cell string CS3 connected in series, and the memory cell string CS2 is between the memory cell string CS1 and the third memory cell string CS3. Each of the first memory cell string CS1, the second memory cell string CS2 and the third memory cell string CS3 includes a first memory cell C11-C31, a second memory cell C12-C32 and a third memory cell C13-C33. The second memory cell (e.g., memory cell C22) in each memory cell string is between the first memory cell (e.g., memory cell C21) and the third memory cell (e.g., memory cell C23).

[0061] Please also refer to Figure 3 and Figure 4 In step S310, Figure 1 The memory controller 110 implements a first read operation of the memory device 100. The first read operation includes step S315: applying a first bit line voltage VBL1 to a first bit line BL1, a second bit line BL2, and a third bit line BL3. The first bit line BL1, the second bit line BL2, and the third bit line BL3 are connected to the first memory cell string CS1, the second memory cell string CS2, and the third memory cell string CS3, respectively.

[0062] The steps of the first reading operation also include: applying a read voltage Vread to the second word line WL_2 connected to the second memory cell (e.g., the second memory cell C12, C22, and C32) in each memory cell string CS1, CS2, and CS3; and applying a pass voltage Vpass to the first word line WL_1 and the third word line WL_3 connected to the first memory cell (e.g., the first memory cell C11, C21, and C31) and the third memory cell (e.g., the third memory cell C13, C23, and C33) in each memory cell string CS1, CS2, and CS3, respectively.

[0063] In step S320, in response to determining that the first read operation fails, the memory controller enters step S320 from step S310, and implements a second read operation of the memory device. In detail, the steps of the second read operation include step S325: In step S325, a set of second bit line voltages are applied to the first bit line BL1, the second bit line BL2, and the third bit line, respectively. The set of second bit line voltages includes a third bit line voltage VBL3, a fourth bit line voltage VBL4, and a fifth bit line voltage VBL5 applied to the first bit line BL1, the second bit line BL2, and the third bit line BL3, respectively. The third bit line voltage VBL3 and the fifth bit line voltage VBL5 are different from the first bit line voltage VBL1 in the first read operation.

[0064] The steps of the second reading operation also include: applying a read voltage Vread to the second word line WL_2 connected to the second storage cell (e.g., the second storage cell C12, C22, and C32) in each storage cell string CS1, CS2, and CS3; and applying a pass voltage Vpass to the first word line WL_1 and the third word line WL_3 connected to the first storage cell (e.g., the first storage cell C11, C21, and C31) and the third storage cell (e.g., the third storage cell C13, C23, and C33) in each storage cell string CS1, CS2, and CS3, respectively.

[0065] After the second read operation of step S320, the threshold voltage distribution curve of the target memory cell (e.g., the second memory cell C12, C22, and C3) is adjusted, thereby improving the success rate of the target memory cell for the read operation and improving the data reliability of the non-volatile memory device (e.g., flash memory). The second read operation of step S320 has various embodiments and is described in detail in the following and corresponding figures.

[0066] Figure 5 This is a schematic diagram of the threshold voltage distribution curve corresponding to the memory cells C12, C22, and C32 according to the first embodiment of the present invention. Figure 4 and Figure 5 , implemented in the first embodiment Figure 3The method of step S320 is that when the second read operation is performed, each voltage in the set of second bit line voltages (i.e., the third bit line voltage VBL3, the fourth bit line voltage VBL4, and the fifth bit line voltage VBL5) uniformly applied to the first bit line BL1, the second bit line BL2, and the third bit line BL3 are all the same. In addition, each voltage in the set of second bit line voltages is lower than the first bit line voltage VBL1. In other words, taking the third bit line voltage VBL3 as an example, the third bit line voltage VBL3 is the first bit line voltage VBL1 minus the voltage difference ΔV. Each voltage in the set of second bit line voltages is not equal to the first bit line voltage VBL1. In the above case, the threshold voltage of the second storage cell C22 in the second storage cell string CS2 is increased due to step S320, and the threshold voltages of the storage cells C12 and C32 are also increased.

[0067] Figure 5 The solid threshold voltage distribution curve 510 used to present the initial threshold voltage is located on the right side of the reference voltage Vrn. Figure 5 The threshold voltage distribution curve 520 which is a dotted line after the threshold voltage shift has a part of the area located on the left side of the reference voltage Vrn. n is a positive integer, and n is used to represent the level of the potential state. For example, the level of the potential state E1 is n=1, the level of the potential state P2 is n=2, and so on. The threshold voltage distribution curve of the potential state Pn is mainly located between the reference voltage Vrn and the reference voltage Vrn+1. In the present embodiment, when the first read operation and the second read operation of step S320 are implemented, the voltage of the word lines WL1 to WL3 is the same as the voltage when the read operation in step S310 is performed, and the bit lines BL1 to BL3 are adjusted, thereby adjusting the threshold voltage of the second storage cells C12, C22, and C32.

[0068] In detail, in the first read operation, a read voltage Vread is applied to the second word line WL2 connected to the second memory cells C12, C22, and C32 in each memory cell string (e.g., the first to third memory cell strings CS1~CS3), and a pass voltage Vpass is applied to the first word line WL1 connected to the first memory cells C11, C21, and C31 in each memory cell string, and a pass voltage Vpass is applied to the third word line WL3 connected to the first memory cells C13, C23, and C33 in each memory cell string. In the second read operation, a read voltage Vread is applied to the second word line WL2 connected to the second memory cells C12, C22, and C32 in each memory cell string (e.g., the first to third memory cell strings CS1~CS3), and a pass voltage Vpass is applied to the first word line WL1 connected to the first memory cells C11, C21, and C31 in each memory cell string, and a pass voltage Vpass is applied to the third word line WL3 connected to the first memory cells C13, C23, and C33 in each memory cell string.

[0069] In this case, the threshold voltage distribution curve (corresponding to Figure 5 The threshold voltage distribution curve 520) will be increased accordingly, for example, gradually from Figure 5 The middle threshold voltage distribution curve 520 is increased to Figure 5 The threshold voltage distribution curve 530-1 is adjusted and can be raised to Figure 5 The threshold voltage distribution curve 530-2 is adjusted. At this time, the threshold voltage distribution curve 530-2 is all located on the right side of the reference voltage Vrn. Step S320 of this embodiment can be performed multiple times to gradually adjust the threshold voltages of the second storage cells C12, C22, and C32 until they approach Figure 5 The threshold voltage distribution curve 530-2 is obtained, and the read operation in the repeatedly implemented step S310 can be successful. The value of the voltage difference ΔV in this embodiment can be obtained based on the experience of the user who uses this embodiment and the data collected through statistics.

[0070] Figure 6 is a schematic diagram of a portion of a memory array in a memory device according to a second embodiment of the present invention. Figure 7 This is a schematic diagram of the threshold voltage distribution curve corresponding to the memory cells C12, C22, and C32 according to the second embodiment of the present invention. Figure 6 and Figure 7 , implemented in the second embodiment Figure 3 The method of step S320 is that when implementing the second read operation, different bit line voltages VBL3 and VBL5 are applied to the first bit line BL1 and the third bit line BL3 respectively based on different groups of potential states corresponding to the memory cells C12, C22, and C32 (i.e., the lower potential state group LPS, the middle potential state group MPS, and the upper potential state group HPS). The third bit line voltage VBL3 and the fifth bit line voltage VBL5 are both lower than the first bit line voltage VBL1 of the first read operation, and the fourth bit line voltage VBL4 applied to the second bit line BL2 is equal to the first bit line voltage VBL1 of the first read operation. In other words, the third bit line voltage VBL3 is the first bit line voltage VBL1 minus the first voltage difference ΔV1; the fifth bit line voltage VBL5 is the first bit line voltage VBL1 minus the second voltage difference ΔV2. The third bit line voltage VBL3 and the fifth bit line voltage VBL5 are not equal to the first bit line voltage VBL1. In the above case, the threshold voltages of the second memory cells C12 and C32 are raised.

[0071] This embodiment uses the memory cells C12, C22 and C32 as examples of potential states P6, P2 and P7, respectively. Experiments show that when different potential states in TLC are subjected to threshold voltage shift, the amount of shift of the threshold voltage distribution curve corresponding to each potential state is also different. According to the amount of shift of the threshold voltage distribution curve corresponding to each potential state when subjected to threshold voltage shift, the threshold voltage distribution curve corresponding to the middle potential state group MPS is shifted the least, and may not even need to be shifted. Figure 3 Step S320 adjusts the threshold voltage distribution curve; the threshold voltage distribution curves corresponding to the low potential state group LPS and the high potential state group HPS are offset by the largest amount, and the direction in which the threshold voltage distribution curve corresponding to the low potential state group LPS is offset is different from the direction in which the threshold voltage distribution curve corresponding to the high potential state group HPS is offset.

[0072] Therefore, the second embodiment applies different bit line voltages VBL3, VBL4 and VBL5 in the set of second bit line voltages to the first bit line BL1, the second bit line BL2 and the third bit line BL3 respectively based on the groups corresponding to the potential states P6, P2 and P7 corresponding to the memory cells C12, C22 and C32 respectively (i.e., the high potential state group HPS, the middle potential state group MPS and the high potential state group HPS). The third bit line voltage VBL3 and the fifth bit line voltage VBL5 are both lower than the first bit line voltage VBL1 of the first read operation. The fourth bit line voltage VBL4 is equal to the first bit line voltage VBL1.

[0073] In the second embodiment, since the potential state P2 corresponding to the memory cell C22 belongs to the aforementioned middle potential state group MPS, and the potential state P6 corresponding to the memory cell C12 and the potential state P7 corresponding to the memory cell C32 belong to the aforementioned high potential state group HPS, the threshold voltage of the potential state group HPS is higher than the threshold voltage of the potential state group MPS, so the third bit line voltage BVL3 and the fifth bit line voltage VBL5 in this group of second bit line voltages applied to the first bit line BL1 and the third bit line BL3 are both lower than the first bit line voltage VBL1, and the fourth bit line voltage VBL4 in this group of second bit line voltages applied to the second bit line BL2 is equal to the first bit line voltage VBL1. In addition, the second memory cell C12 in the first memory cell string CS1 in the potential state group HPS has a lower threshold voltage ( Figure 6In the second embodiment shown in the figure, the third bit line voltage VBL3 is higher than the fifth bit line voltage VBL5, that is, the determination value of the second voltage difference ΔV2 is greater than the absolute value of the first voltage difference ΔV1. In this way, the threshold voltage distribution curve of the second memory cell C12 in the first memory cell string CS1 and the threshold voltage distribution curve of the second memory cell C32 in the third memory cell string CS3 are improved. The values ​​of the voltage differences ΔV1 and ΔV2 in this embodiment can be obtained based on the experience of the user who applies this embodiment and the data after statistical aggregation, and can be obtained by using a lookup table or other corresponding technology. Figure 1 The memory controller 110 is aware of the voltage difference and thus implements Figure 3 Step S320.

[0074] Figure 7 The solid-line threshold voltage distribution curves 710-2, 710-6, and 710-7 used to represent the initial threshold voltage are located on the right side of the reference voltages Vr2, Vr6, and Vr7, respectively. Figure 7 The threshold voltage distribution curves 720-6 and 720-7, which are dotted lines and belong to the high potential state group HPS, have some areas located to the left of the reference voltages Vr6 and Vr7. Figure 7 The threshold voltage distribution curves 720-6 and 720-7) will be increased accordingly, for example, gradually from Figure 7 The middle threshold voltage distribution curves 720-6 and 720-7 are increased to Figure 7 The threshold voltage distribution curves 730-6 and 730-7 are adjusted. At this time, the threshold voltage distribution curves 730-6 and 730-7 are located on the right side of the reference voltages Vr6 and Vr7, respectively. Figure 7 The threshold voltage distribution curve 720 - 2 which belongs to the middle potential state group MPS and is a dotted line is still located on the right side of the reference voltage Vr2 , and therefore does not need to be adjusted.

[0075] Figure 8 is a schematic diagram of a portion of a memory array in a memory device according to a third embodiment of the present invention. Fig. 9 This is a schematic diagram of the threshold voltage distribution curve corresponding to the memory cells C12, C22, and C32 according to the third embodiment of the present invention. Figure 8 and Fig. 9 , implemented in the third embodiment Figure 3The method of step S320 is that when performing the second read operation, different bit line voltages VBL3' and VBL5' are applied to the first bit line BL1 and the third bit line BL3 respectively based on the arrangement pattern of the potential states P0 to P7 corresponding to the first to third memory cells C11 to C33 in the first to third memory cell strings CS1 to CS3. The third bit line voltage VBL3' and the fifth bit line voltage VBL5' are both lower than the first bit line voltage VBL1.

[0076] In detail, in the third embodiment, when the second memory cells C12, C22, and C32 in the first memory cell string CS1 to the third memory cell string CS3 are all located in the high potential state group HPS, and the first memory cells C11, C21, and C31 and the third memory cells C13, C23, and C33 in the first memory cell string CS1 to the third memory cell string CS3 are located in one of the middle potential state group MPS and the low potential state group LPS, the third bit line voltage VBL3' and the fifth bit line voltage VBL5' are both lower than the first bit line voltage VBL1, and the threshold voltages of the second memory cells C12 to C32 in the first memory cell string CS1 to the third memory cell string CS3 will be increased. In other words, the third bit line voltage VBL3' is the first bit line voltage VBL1 minus the third voltage difference ΔV3; the fifth bit line voltage VBL5' is the first bit line voltage VBL1 minus the fourth voltage difference ΔV4. The bit line voltages VBL3' and VBL5' are not equal to the first bit line voltage VBL1. The values ​​of the voltage differences ΔV3 and ΔV4 in this embodiment can be obtained based on the experience of the user who uses this embodiment or the statistically compiled data, and can be obtained by using a lookup table or other corresponding techniques. Figure 1 The memory controller 110 is aware of the voltage difference and thus implements Figure 3 Step S320.

[0077] The third embodiment marks the hierarchical group to which the potential state corresponding to each storage unit belongs. Figure 8, it can be seen that the second storage cells C12, C22, and C32 all belong to the high potential state group HPS. Please see the second storage cell string CS2. Since the storage cells C21, C22, and C23 also belong to the high potential state group HPS, the second storage cell C22, as one of the target storage cells, can have a better data retention capability, because the threshold voltage values ​​of the storage cells C21 and C23 are also high, and the data retained in the second storage cell C22 is easier to preserve. Please see the first storage cell string CS1. Since the storage cell C11 belongs to the low potential state group LPS and the storage cell C13 belongs to the middle potential state group MPS, the second storage cell C12, as one of the target storage cells, has a medium retention loss, because the data retained in the second storage cell C12 may be lost to the storage cells C11 and C13. Please see the third storage cell string CS3. Since the storage cells C31 and C33 both belong to the low potential state group LPS, the second storage cell C32 as one of the target storage cells has a more serious retention loss because the data retained in the second storage cell C32 may be easily lost to the storage cells C31 and C33.

[0078] Fig. 9 The solid line threshold voltage distribution curve 910 used to represent the initial threshold voltage is located on the right side of the reference voltage Vrn. Fig. 9 The threshold voltage distribution curve 920 which is a dotted line after the threshold voltage shift has a portion of the area located on the left side of the reference voltage Vrn. In this embodiment, when the second read operation in step S320 is performed, the threshold voltage distribution curves (corresponding to Fig. 9 The threshold voltage distribution curve 920) will be raised to Fig. 9 The threshold voltage distribution curve 930 is adjusted. In this embodiment, Figure 1 The memory controller 110 can also read the block 950 in the threshold voltage distribution curve 920 and invert the data read from the block 950 to obtain correct data, thereby obtaining correct data of the second memory cell C22 which is one of the target memory cells.

[0079] Fig.10 is a schematic diagram of a portion of a memory array in a memory device according to a fourth embodiment of the present invention. Fig.11Schematic diagram of threshold voltage distribution curve corresponding to memory cells C12, C22, and C32 in the fourth embodiment of the present invention. The fourth embodiment of the present invention is similar to the aforementioned first embodiment, and the difference is that when the threshold voltage distribution curve is adjusted, each voltage in the set of second bit line voltages (i.e., the third bit line voltage VBL3, the fourth bit line voltage VBL4, and the fifth bit line voltage VBL5) uniformly applied to the bit lines B1, BL2, and BL3 are all the same. In addition, each voltage in the set of second bit line voltages is higher than the first bit line voltage VBL1. In other words, taking the third bit line voltage VBL3 as an example, the third bit line voltage VBL3 is the first bit line voltage VBL1 plus the voltage difference ΔV. The third bit line voltage VBL3 is not equal to the first bit line voltage VBL1. In the aforementioned case, the threshold voltage of the second memory cell C22 in the second memory cell string CS2 is lowered due to step S320, and the threshold voltages of the memory cells C12 and C32 are also lowered.

[0080] Fig.11 The solid threshold voltage distribution curve 1110 used to present the initial threshold voltage is located on the left side of the reference voltage Vrn+1. Fig.11 The threshold voltage distribution curve 1120 after the threshold voltage shift and the dotted line has a portion of the area located on the right side of the reference voltage Vrn+1. In the present embodiment, when the second read operation in step S320 is performed, the voltage of the word lines WL1 to WL3 is the same as the voltage when the read operation in step S310 is performed, and the bit lines BL1 to BL3 are adjusted, thereby adjusting the threshold voltage of the second memory cells C12, C22, and C32. In this case, the threshold voltage distribution curves of the second memory cells C12, C22, and C32 (corresponding to Figure 5 The threshold voltage distribution curve 1120) will be lowered, for example, gradually from Fig.11 The threshold voltage distribution curve 1120 is reduced to Figure 5 The threshold voltage distribution curve 1130 is adjusted. At this time, the threshold voltage distribution curve 1130 is all located on the left side of the reference voltage Vrn+1. Step S320 of this embodiment can be performed multiple times to gradually adjust the threshold voltages of the second storage cells C12, C22, and C32 until they approach Figure 5 The threshold voltage distribution curve 1130 is formed, and the read operation in the repeatedly implemented step S310 can be successful. The value of the voltage difference ΔV in this embodiment can be obtained based on the experience of the user who applies this embodiment and the data collected through statistics.

[0081] Fig.12 is a schematic diagram of a portion of a memory array in a memory device according to a fifth embodiment of the present invention. Fig.13Schematic diagram of threshold voltage distribution curve corresponding to memory cells C12, C22, and C32 in the fifth embodiment of the present invention. The fifth embodiment of the present invention is similar to the aforementioned second embodiment, and the difference is that when the threshold voltage distribution curve is adjusted, the bit line voltages VBL3 and VBL5 applied to the bit lines BL1 and BL3 respectively based on the potential states corresponding to the memory cells C12, C22, and C32 are higher than the first bit line voltage VBL1. In other words, the third bit line voltage VBL3 is the first bit line voltage VBL1 plus the voltage difference ΔV1, the fourth bit line voltage VBL4 is equal to the first bit line voltage VBL1, and the fifth bit line voltage VBL5 is the first bit line voltage VBL1 plus the voltage difference ΔV2. The bit line voltages VBL3 and VBL5 are not equal to the first bit line voltage VBL1. In the aforementioned case, the threshold voltages of the second memory cells C12 and C32 are lowered.

[0082] This embodiment is described by taking the memory cells C12, C22 and C32 as the potential states P1, P4 and P0, respectively. In the fifth embodiment, since the potential state P4 corresponding to the memory cell C22 belongs to the aforementioned middle potential state group MPS, and the potential state P0 corresponding to the memory cell C12 and the potential state P1 corresponding to the memory cell C32 belong to the aforementioned low potential state group LPS, the threshold voltage of the potential state group LPS is lower than the threshold voltage of the potential state group MPS, so the third bit line voltage BVL3 and the fifth bit line voltage VBL5 in the group of second bit line voltages applied to the first bit line BL1 and the third bit line BL3 are both higher than the first bit line voltage VBL1, and the fourth bit line voltage VBL4 in the group of second bit line voltages applied to the second bit line BL2 is equal to the first bit line voltage VBL1. As a result, the threshold voltage of the second memory cell C12 in the first memory cell string CS1 and the threshold voltage of the second memory cell C32 in the third memory cell string CS3 are lowered.

[0083] The second memory cell C12 in the first memory cell string CS1 in the potential state group LPS has a higher threshold voltage (i.e., Fig.12 In the fifth embodiment shown in the figure, the third bit line voltage VBL3 is lower than the fifth bit line voltage VBL5, that is, the determination value of the second voltage difference ΔV2 is greater than the absolute value of the first voltage difference ΔV1. In this way, the threshold voltage distribution curve of the second memory cell C12 in the first memory cell string CS1 and the threshold voltage distribution curve of the second memory cell C32 in the third memory cell string CS3 are lowered. The values ​​of the voltage differences ΔV1 and ΔV2 in this embodiment can be obtained based on the experience of the user who applies this embodiment and the data after statistical aggregation, and can be obtained by using a lookup table or other corresponding technology. Figure 1 The memory controller 110 is aware of the voltage difference and thus implements Figure 3Step S320.

[0084] Fig.13 The solid-line threshold voltage distribution curves 1310-0, 1310-1, and 1310-4 used to represent the initial threshold voltage are all located on the left side of the reference voltages Vr1, Vr2, and Vr5, respectively. Fig.13 The threshold voltage distribution curves 1320-0 and 1320-1, which belong to the lower potential state group LPS and are dashed lines, have some areas located to the right of the reference voltages Vr1 and Vr2. Fig.13 The threshold voltage distribution curves 1320-1, 1320-0) will be lowered, for example, gradually from Fig.13 The middle threshold voltage distribution curves 1320-0 and 1320-1 are reduced to Fig.13 The threshold voltage distribution curves 1330-0 and 1330-1 are adjusted. At this time, the threshold voltage distribution curves 1330-0 and 1330-1 are located on the left side of the reference voltages Vr1 and Vr2, respectively. Fig.13 The threshold voltage distribution curve 1320 - 4 which belongs to the middle potential state group MPS and is a dotted line is still located on the left side of the reference voltage Vr5 , and therefore does not need to be adjusted.

[0085] Fig.14 is a schematic diagram of a portion of a memory array in a memory device according to a sixth embodiment of the present invention. Fig.15 Schematic diagram of threshold voltage distribution curve corresponding to memory cells C12, C22, C32 according to the sixth embodiment of the present invention. The sixth embodiment of the present invention is similar to the aforementioned third embodiment, and the difference is that when the threshold voltage distribution curve is adjusted, the bit line voltages VBL3, VBL4, and VBL5 are applied to the bit lines BL1, BL2, and BL3 respectively based on the arrangement patterns of the potential states P0 to P7 corresponding to the first to third memory cells C11 to C33 in the first to third memory cell strings CS1 to CS3, and the bit line voltages VBL3 and VBL5 are higher than the first bit line voltage VBL1. In other words, the third bit line voltage VBL3 is the first bit line voltage VBL1 plus the voltage difference ΔV3, and the fifth bit line voltage VBL5 is the first bit line voltage VBL1 plus the voltage difference ΔV4. The fourth bit line voltage VBL4 is equal to the first bit line voltage VBL1. The bit line voltages VBL3 and VBL5 are not equal to the first bit line voltage VBL1. In the aforementioned case, the threshold voltages of the second memory cells C12 and C32 are lowered.

[0086] In detail, in the sixth embodiment, when the second memory cells C12, C22, and C32 in the first memory cell string CS1 to the third memory cell string CS3 are all located in the low potential state group LPS, and the first memory cells C11, C21, and C31 and the third memory cells C13, C23, and C33 in the first memory cell string CS1 to the third memory cell string CS3 are located in one of the middle potential state group MPS and the high potential state group HPS, the third bit line voltage VBL3 and the fifth bit line voltage VBL5 are both higher than the first bit line voltage VBL1, and the threshold voltages of the second memory cells C12 to C32 in the first memory cell string CS1 to the third memory cell string CS3 will be reduced accordingly. The values ​​of the voltage differences ΔV3 and ΔV4 in this embodiment can be obtained based on the experience of the person applying this embodiment and the statistically aggregated data, and can be obtained by using a lookup table or other corresponding techniques. Figure 1 The memory controller 110 is aware of the voltage difference and thus implements Figure 3 Step S320.

[0087] The sixth embodiment marks the hierarchical group to which the potential state corresponding to each storage unit belongs on Fig.14 , it can be seen that the second storage cells C12, C22, and C32 all belong to the low potential state group LPS. Please see the second storage cell string CS2. Since the storage cells C21 and C23 also belong to the low potential state group LPS, the second storage cell C22, as one of the target storage cells, can have a better data retention capability. Since the threshold voltage values ​​of the storage cells C21 and C23 are also low, the data retained in the second storage cell C22 is easier to preserve. Please see the first storage cell string CS1. Since the storage cell C11 belongs to the high potential state group HPS and the storage cell C13 belongs to the middle and high potential state group MPS, the second storage cell C12, as one of the target storage cells, has a medium retention loss. The data retained in the second storage cell C22 may be affected by the charge lost by the storage cells C21 and C23. Please see the third storage cell string CS3. Since storage cells C31 and C33 both belong to the high potential state group HPS, the second storage cell C32, which is one of the target storage cells, has a more serious retention loss. The data retained in the second storage cell C22 may be seriously affected by the potential states of storage cells C31 and C33.

[0088] Fig.15 The solid threshold voltage distribution curve 1510 used to represent the initial threshold voltage is located on the left side of the reference voltage Vrn+1. Fig.15The threshold voltage distribution curve 1520 which is a dotted line after the threshold voltage shift has a portion of its area located to the right of the reference voltage Vrn+1. In this embodiment, when the second read operation in step S320 is performed, the threshold voltage distribution curves of the second storage cells C12 and C32 (corresponding to Fig.15 The threshold voltage distribution curve 1520) will be raised to Fig.15 The adjusted threshold voltage distribution curve 1530 is shown in FIG.

[0089] Fig.16 1 is a schematic diagram of threshold voltage distribution curves corresponding to the initial threshold voltages of the potential states Er, P1-P7 in TLC according to an embodiment of the present invention and before and after the threshold voltage distribution curves are adjusted. Fig.16 It can be seen that the threshold voltage distribution curves 1610-0 to 1610-7 are the distributions corresponding to the initial threshold voltages; the threshold voltage distribution curves 1620-0 to 1620-7 are the distributions after the threshold voltage shift; and the threshold voltage distribution curves 1630-0 to 1630-7 are the distribution curves after the shift according to the embodiment of the present invention.

[0090] In summary, the memory device and reading method described in the embodiment of the present invention use a first reading operation to determine whether the data retention function of the target memory cell is normal, and when the first reading operation fails, a second reading operation is implemented to change the bit line voltages of multiple target memory cells to adjust the threshold voltage distribution curve in the target memory cell, thereby increasing the success rate of the first reading operation, thereby improving the data reliability of a non-volatile memory device (e.g., flash memory).

Claims

1. A method for reading a memory device, characterized in that: The memory device includes a first memory cell string, a second memory cell string, and a third memory cell string, wherein the second memory cell string is between the first memory cell string and the third memory cell string, each of the first memory cell string, the second memory cell string, and the third memory cell string includes a first memory cell, a second memory cell, and a third memory cell connected in series, wherein the second memory cell is arranged between the first memory cell and the third memory cell, The reading method comprises: Implementing a first read operation on the memory device, comprising: applying a first bit line voltage to a first bit line, a second bit line, and a third bit line, wherein the first bit line, the second bit line, and the third bit line are connected to the first memory cell string, the second memory cell string, and the third memory cell string, respectively; and In response to the first read operation failing, performing a second read operation of the memory device, comprising: A group of second bit line voltages are applied to the first bit line, the second bit line and the third bit line, respectively, wherein the group of second bit line voltages includes a third bit line voltage, a fourth bit line voltage and a fifth bit line voltage applied to the first bit line, the second bit line and the third bit line, respectively, and the third bit line voltage and the fifth bit line voltage are different from the first bit line voltage.

2. The reading method according to claim 1, further comprising: In the first read operation, applying a read voltage to a second word line connected to the second memory cell in each memory cell string; In the first read operation, a pass voltage is applied to a first word line and a third word line respectively connected to the first memory cell and the third memory cell in each memory cell string; In the second reading operation, applying the read voltage to the second word line connected to the second memory cell in each memory cell string; as well as In the second read operation, the pass voltage is applied to the first word line and the third word line respectively connected to the first memory cell and the third memory cell in each memory cell string. 3 . The reading method according to claim 1 , wherein the third bit line voltage, the fourth bit line voltage and the fifth bit line voltage are the same, wherein the third bit line voltage, the fourth bit line voltage and the fifth bit line voltage are all lower or higher than the first bit line voltage.

4. The reading method according to claim 2, wherein the second memory cell in the first memory cell string and the second memory cell in the third memory cell string are both in a first potential state group, The second memory cells in the second memory cell string are in a second potential state group, and the first potential state group and the second potential state group have different threshold voltages.

5. The reading method according to claim 4, wherein the threshold voltage of the first potential state group is higher than the threshold voltage of the second potential state group, the third bit line voltage and the fifth bit line voltage in the group of second bit line voltages respectively applied to the first bit line and the third bit line are both lower than the first bit line voltage, and the fourth bit line voltage in the group of second bit line voltages applied to the second bit line is equal to the first bit line voltage.

6. The reading method according to claim 4, wherein the second memory cell in the first memory cell string of the first potential state group has a lower threshold voltage than the second memory cell in the third memory cell string of the first potential state group, and the third bit line voltage applied to the first bit line is higher than the fifth bit line voltage applied to the third bit line.

7. The reading method according to claim 4, wherein the threshold voltage of the first potential state group is lower than the threshold voltage of the second potential state group, the third bit line voltage and the fifth bit line voltage in the group of second bit line voltages respectively applied to the first bit line and the third bit line are both higher than the first bit line voltage, and the fourth bit line voltage in the group of second bit line voltages applied to the second bit line is equal to the first bit line voltage.

8. The reading method according to claim 7, wherein the second memory cell in the first memory cell string of the first potential state group has a higher threshold voltage than the second memory cell in the third memory cell string of the first potential state group, and the third bit line voltage applied to the first bit line is lower than the fifth bit line voltage applied to the third bit line.

9. The reading method according to claim 2, wherein the second storage cells in the first storage cell string to the third storage cell string are all in a first potential state group, The first memory cell and the third memory cell in the first to third memory cell strings are located in one of a second potential state group and a third potential state group, and the first potential state group, the second potential state group and the third potential state group have different threshold voltages.

10. The reading method according to claim 9, wherein the threshold voltage of the first potential state group is higher than the threshold voltage of the second potential state group, and the threshold voltage of the second potential state group is higher than the threshold voltage of the third potential state group, the third bit line voltage and the fifth bit line voltage in the group of second bit line voltages respectively applied to the first bit line and the third bit line are both lower than the first bit line voltage, and the fourth bit line voltage in the group of second bit line voltages applied to the second bit line is equal to the first bit line voltage.

11. The reading method according to claim 9, wherein the first memory cell in the first memory cell string located in the third potential state group has a lower threshold voltage than the third memory cell in the first memory cell string located in the second potential state group, the first memory cell and the third memory cell in the third memory cell string are located in the third potential state group, and the third bit line voltage applied to the first bit line is higher than the fifth bit line voltage applied to the third bit line.

12. The reading method according to claim 9, wherein the threshold voltage of the first potential state group is lower than the threshold voltage of the second potential state group, and the threshold voltage of the second potential state group is lower than the threshold voltage of the third potential state group, the third bit line voltage and the fifth bit line voltage in the group of second bit line voltages respectively applied to the first bit line and the third bit line are both higher than the first bit line voltage, and the fourth bit line voltage in the group of second bit line voltages applied to the second bit line is equal to the first bit line voltage.

13. The reading method according to claim 9, wherein the first memory cell in the first memory cell string located in the third potential state group has a higher threshold voltage than the third memory cell in the first memory cell string located in the second potential state group, the first memory cell and the third memory cell in the third memory cell string are located in the third potential state group, and the third bit line voltage applied to the first bit line is lower than the fifth bit line voltage applied to the third bit line.

14. A memory device, characterized in that: include: A memory array comprising a first memory cell string, a second memory cell string and a third memory cell string, wherein the second memory cell string is between the first memory cell string and the third memory cell string, each of the first memory cell string, the second memory cell string and the third memory cell string comprises a first memory cell, a second memory cell and a third memory cell connected in series, wherein the second memory cell is arranged between the first memory cell and the third memory cell; as well as A memory controller for controlling the memory array, The memory controller is configured to perform: a first read operation of the memory device, wherein the first read operation comprises: applying a first bit line voltage to a first bit line, a second bit line, and a third bit line, wherein the first bit line, the second bit line, and the third bit line are respectively connected to the first memory cell string, the second memory cell string, and the third memory cell string; and In response to the first read operation failing, performing a second read operation of the memory device, comprising: A group of second bit line voltages are applied to the first bit line, the second bit line and the third bit line, respectively, wherein the group of second bit line voltages includes a third bit line voltage, a fourth bit line voltage and a fifth bit line voltage applied to the first bit line, the second bit line and the third bit line, respectively, and the third bit line voltage and the fifth bit line voltage are different from the first bit line voltage.

15. The memory device of claim 14, wherein the memory controller is further configured to perform: In the first read operation, applying a read voltage to a second word line connected to the second memory cell in each memory cell string; In the first read operation, a pass voltage is applied to a first word line and a third word line respectively connected to the first memory cell and the third memory cell in each memory cell string; In the second read operation, applying the read voltage to the second word line connected to the second memory cell in each memory cell string; and In the second read operation, the pass voltage is applied to the first word line and the third word line respectively connected to the first memory cell and the third memory cell in each memory cell string.

16. The memory device of claim 15, wherein the third bit line voltage, the fourth bit line voltage, and the fifth bit line voltage provided to the first bit line, the second bit line, and the third bit line are the same, wherein the third bit line voltage, the fourth bit line voltage, and the fifth bit line voltage are all lower or higher than the first bit line voltage.

17. The memory device according to claim 14, wherein the second memory cell in the first memory cell string and the second memory cell in the third memory cell string are both in a first potential state group, The second memory cells in the second memory cell string are in a second potential state group, and the first potential state group and the second potential state group have different threshold voltages.

18. A memory device according to claim 17, wherein the threshold voltage of the first potential state group is higher than the threshold voltage of the second potential state group, the third bit line voltage and the fifth bit line voltage in the group of second bit line voltages applied to the first bit line and the third bit line respectively are both lower than the first bit line voltage, and the fourth bit line voltage in the group of second bit line voltages applied to the second bit line is equal to the first bit line voltage.

19. The memory device of claim 14, wherein The second storage cells in the first storage cell string to the third storage cell string are all in the first potential state group, The first memory cell and the third memory cell in the first to third memory cell strings are located in one of a second potential state group and a third potential state group, and the first potential state group, the second potential state group and the third potential state group have different threshold voltages.

20. A memory device according to claim 19, wherein the threshold voltage of the first potential state group is higher than the threshold voltage of the second potential state group, and the threshold voltage of the second potential state group is higher than the threshold voltage of the third potential state group, the third bit line voltage and the fifth bit line voltage in the group of second bit line voltages applied to the first bit line and the third bit line, respectively, are both lower than the first bit line voltage, and the fourth bit line voltage in the group of second bit line voltages applied to the second bit line is equal to the first bit line voltage.

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